1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
|
/*
* Copyright (c) 2012 Sebastian Huber. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBBSP_ARM_STM32F4_STM32F4_H
#define LIBBSP_ARM_STM32F4_STM32F4_H
#include <bsp/utility.h>
#define STM32F4_BASE 0x00
typedef struct {
uint32_t reserved_00 [16];
uint32_t apb1enr;
#define STM32F4_RCC_APB1ENR_DAC_EN BSP_BIT32(29)
#define STM32F4_RCC_APB1ENR_PWR_EN BSP_BIT32(28)
#define STM32F4_RCC_APB1ENR_CAN2_EN BSP_BIT32(26)
#define STM32F4_RCC_APB1ENR_CAN1_EN BSP_BIT32(25)
#define STM32F4_RCC_APB1ENR_I2C3_EN BSP_BIT32(23)
#define STM32F4_RCC_APB1ENR_I2C2_EN BSP_BIT32(22)
#define STM32F4_RCC_APB1ENR_I2C1_EN BSP_BIT32(21)
#define STM32F4_RCC_APB1ENR_UART5_EN BSP_BIT32(20)
#define STM32F4_RCC_APB1ENR_UART4_EN BSP_BIT32(19)
#define STM32F4_RCC_APB1ENR_USART3_EN BSP_BIT32(18)
#define STM32F4_RCC_APB1ENR_USART2_EN BSP_BIT32(17)
#define STM32F4_RCC_APB1ENR_SPI3_EN BSP_BIT32(15)
#define STM32F4_RCC_APB1ENR_SPI2_EN BSP_BIT32(14)
#define STM32F4_RCC_APB1ENR_WWDG_EN BSP_BIT32(11)
#define STM32F4_RCC_APB1ENR_TIM14_EN BSP_BIT32(8)
#define STM32F4_RCC_APB1ENR_TIM13_EN BSP_BIT32(7)
#define STM32F4_RCC_APB1ENR_TIM12_EN BSP_BIT32(6)
#define STM32F4_RCC_APB1ENR_TIM7_EN BSP_BIT32(5)
#define STM32F4_RCC_APB1ENR_TIM6_EN BSP_BIT32(4)
#define STM32F4_RCC_APB1ENR_TIM5_EN BSP_BIT32(3)
#define STM32F4_RCC_APB1ENR_TIM4_EN BSP_BIT32(2)
#define STM32F4_RCC_APB1ENR_TIM3_EN BSP_BIT32(1)
#define STM32F4_RCC_APB1ENR_TIM2_EN BSP_BIT32(0)
uint32_t apb2enr;
#define STM32F4_RCC_APB2ENR_TIM11 BSP_BIT32(18)
#define STM32F4_RCC_APB2ENR_TIM10_EN BSP_BIT32(17)
#define STM32F4_RCC_APB2ENR_TIM9_EN BSP_BIT32(16)
#define STM32F4_RCC_APB2ENR_SYSCFG_EN BSP_BIT32(14)
#define STM32F4_RCC_APB2ENR_SPI1_EN BSP_BIT32(12)
#define STM32F4_RCC_APB2ENR_SDIO_EN BSP_BIT32(11)
#define STM32F4_RCC_APB2ENR_ADC3_EN BSP_BIT32(10)
#define STM32F4_RCC_APB2ENR_ADC2_EN BSP_BIT32(9)
#define STM32F4_RCC_APB2ENR_ADC1_EN BSP_BIT32(8)
#define STM32F4_RCC_APB2ENR_USART6_EN BSP_BIT32(5)
#define STM32F4_RCC_APB2ENR_USART1_EN BSP_BIT32(4)
#define STM32F4_RCC_APB2ENR_TIM8_EN BSP_BIT32(1)
#define STM32F4_RCC_APB2ENR_TIM1_EN BSP_BIT32(0)
} stm32f4_rcc;
#define STM32F4_RCC (*(volatile stm32f4_rcc *) (STM32F4_BASE + 0x40023800))
typedef struct {
uint32_t sr;
#define STM32F4_USART_SR_CTS BSP_BIT32(9)
#define STM32F4_USART_SR_LBD BSP_BIT32(8)
#define STM32F4_USART_SR_TXE BSP_BIT32(7)
#define STM32F4_USART_SR_TC BSP_BIT32(6)
#define STM32F4_USART_SR_RXNE BSP_BIT32(5)
#define STM32F4_USART_SR_IDLE BSP_BIT32(4)
#define STM32F4_USART_SR_ORE BSP_BIT32(3)
#define STM32F4_USART_SR_NF BSP_BIT32(2)
#define STM32F4_USART_SR_FE BSP_BIT32(1)
#define STM32F4_USART_SR_PE BSP_BIT32(0)
uint32_t dr;
#define STM32F4_USART_DR(val) BSP_FLD32(val, 0, 7)
#define STM32F4_USART_DR_GET(reg) BSP_FLD32GET(reg, 0, 7)
#define STM32F4_USART_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
uint32_t bbr;
#define STM32F4_USART_BBR_DIV_MANTISSA(val) BSP_FLD32(val, 4, 15)
#define STM32F4_USART_BBR_DIV_MANTISSA_GET(reg) BSP_FLD32GET(reg, 4, 15)
#define STM32F4_USART_BBR_DIV_MANTISSA_SET(reg, val) BSP_FLD32SET(reg, val, 4, 15)
#define STM32F4_USART_BBR_DIV_FRACTION(val) BSP_FLD32(val, 0, 3)
#define STM32F4_USART_BBR_DIV_FRACTION_GET(reg) BSP_FLD32GET(reg, 0, 3)
#define STM32F4_USART_BBR_DIV_FRACTION_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
uint32_t cr1;
#define STM32F4_USART_CR1_OVER8 BSP_BIT32(15)
#define STM32F4_USART_CR1_UE BSP_BIT32(13)
#define STM32F4_USART_CR1_M BSP_BIT32(12)
#define STM32F4_USART_CR1_WAKE BSP_BIT32(11)
#define STM32F4_USART_CR1_PCE BSP_BIT32(10)
#define STM32F4_USART_CR1_PS BSP_BIT32(9)
#define STM32F4_USART_CR1_PEIE BSP_BIT32(8)
#define STM32F4_USART_CR1_TXEIE BSP_BIT32(7)
#define STM32F4_USART_CR1_TCIE BSP_BIT32(6)
#define STM32F4_USART_CR1_RXNEIE BSP_BIT32(5)
#define STM32F4_USART_CR1_IDLEIE BSP_BIT32(4)
#define STM32F4_USART_CR1_TE BSP_BIT32(3)
#define STM32F4_USART_CR1_RE BSP_BIT32(2)
#define STM32F4_USART_CR1_RWU BSP_BIT32(1)
#define STM32F4_USART_CR1_SBK BSP_BIT32(0)
uint32_t cr2;
#define STM32F4_USART_CR2_LINEN BSP_BIT32(14)
#define STM32F4_USART_CR2_STOP(val) BSP_FLD32(val, 12, 13)
#define STM32F4_USART_CR2_STOP_GET(reg) BSP_FLD32GET(reg, 12, 13)
#define STM32F4_USART_CR2_STOP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
#define STM32F4_USART_CR2_CLKEN BSP_BIT32(11)
#define STM32F4_USART_CR2_CPOL BSP_BIT32(10)
#define STM32F4_USART_CR2_CPHA BSP_BIT32(9)
#define STM32F4_USART_CR2_LBCL BSP_BIT32(8)
#define STM32F4_USART_CR2_LBDIE BSP_BIT32(6)
#define STM32F4_USART_CR2_LBDL BSP_BIT32(5)
#define STM32F4_USART_CR2_ADD(val) BSP_FLD32(val, 0, 3)
#define STM32F4_USART_CR2_ADD_GET(reg) BSP_FLD32GET(reg, 0, 3)
#define STM32F4_USART_CR2_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
uint32_t cr3;
#define STM32F4_USART_CR3_ONEBIT BSP_BIT32(11)
#define STM32F4_USART_CR3_CTSIE BSP_BIT32(10)
#define STM32F4_USART_CR3_CTSE BSP_BIT32(9)
#define STM32F4_USART_CR3_RTSE BSP_BIT32(8)
#define STM32F4_USART_CR3_DMAT BSP_BIT32(7)
#define STM32F4_USART_CR3_DMAR BSP_BIT32(6)
#define STM32F4_USART_CR3_SCEN BSP_BIT32(5)
#define STM32F4_USART_CR3_NACK BSP_BIT32(4)
#define STM32F4_USART_CR3_HDSEL BSP_BIT32(3)
#define STM32F4_USART_CR3_IRLP BSP_BIT32(2)
#define STM32F4_USART_CR3_IREN BSP_BIT32(1)
#define STM32F4_USART_CR3_EIE BSP_BIT32(0)
uint32_t gtpr;
#define STM32F4_USART_GTPR_GT(val) BSP_FLD32(val, 8, 15)
#define STM32F4_USART_GTPR_GT_GET(reg) BSP_FLD32GET(reg, 8, 15)
#define STM32F4_USART_GTPR_GT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
#define STM32F4_USART_GTPR_PSC(val) BSP_FLD32(val, 0, 7)
#define STM32F4_USART_GTPR_PSC_GET(reg) BSP_FLD32GET(reg, 0, 7)
#define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
} stm32f4_usart;
#define STM32F4_USART_1 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40011000))
#define STM32F4_USART_2 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400))
#define STM32F4_USART_3 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800))
#define STM32F4_USART_4 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00))
#define STM32F4_USART_5 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000))
#define STM32F4_USART_6 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400))
typedef struct {
uint32_t reserved_00 [268439808];
stm32f4_usart usart_2;
uint32_t reserved_4000441c [249];
stm32f4_usart usart_3;
uint32_t reserved_4000481c [249];
stm32f4_usart usart_4;
uint32_t reserved_40004c1c [249];
stm32f4_usart usart_5;
uint32_t reserved_4000501c [12281];
stm32f4_usart usart_1;
uint32_t reserved_4001101c [249];
stm32f4_usart usart_6;
uint32_t reserved_4001141c [18681];
stm32f4_rcc rcc;
} stm32f4;
#define STM32F4 (*(volatile stm32f4 *) (STM32F4_BASE))
#endif /* LIBBSP_ARM_STM32F4_STM32F4_H */
|
