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Diffstat (limited to 'c/src/lib/libbsp/arm/altera-cyclone-v/hwlib')
31 files changed, 0 insertions, 88020 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h deleted file mode 100644 index bca6f63e00..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_16550_uart.h +++ /dev/null @@ -1,1555 +0,0 @@ -/* - * Altera - SoC UART Manager - */ - -/***************************************************************************** - * - * Copyright 2013 Altera Corporation. All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - *****************************************************************************/ - -#ifndef __ALT_16550_UART_H__ -#define __ALT_16550_UART_H__ - -#include "hwlib.h" -#include "alt_clock_manager.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! - * \addtogroup UART UART Driver API - * - * This module defines the Universal Asynchronous Receiver/Transmitter (UART) - * API for accessing and using the UART resources. The API allows for general - * control of a 16550 compatible UART controller. - * - * This implementation can control the following UARTs: - * * SoCFPGA On-board UARTs - * * Altera 16550 Compatible Soft IP UART - * - * The following reference materials were used in the design of this API: - * * Synopsys® DesignWare DW_apb_uart Databook v3.10a - * - * @{ - */ - -/*! - * \addtogroup UART_BASIC UART Basic - * - * This group of APIs provides basic access to the UART to initialize, - * uninitialize, read, write, and reset the UART. - * - * @{ - */ - -/*! - * This type definition enumerates the list of UARTs available on the system. - */ -typedef enum ALT_16550_DEVICE_e -{ - /*! - * This option selects UART0 in the SoC FPGA. - */ - ALT_16550_DEVICE_SOCFPGA_UART0 = 0, - - /*! - * This option selects UART1 in the SoC FPGA. - */ - ALT_16550_DEVICE_SOCFPGA_UART1 = 1, - - /*! - * This option selects an Altera 16550 Compatible soft IP UART. The memory - * location of the device must be provided as part of the initialization. - */ - ALT_16550_DEVICE_ALTERA_16550_UART = 0x100 -} -ALT_16550_DEVICE_t; - -/*! - * This structure is used to represent a handle to a specific UART on the - * system. The internal members are undocumented and should be not altered - * outside of this API. - */ -typedef struct ALT_16550_HANDLE_s -{ - ALT_16550_DEVICE_t device; - void * location; - alt_freq_t clock_freq; - uint32_t data; - uint32_t fcr; -} -ALT_16550_HANDLE_t; - -/*! - * Performs the initialization steps needed by the UART. This should be the - * first API call made when accessing a particular UART - * - * The default UART setting is 8 databits, no parity, 1 stopbit, and 57600 - * baud. - * - * For the SoCFPGA UARTs, The ALT_CLK_L4_SP clock needs to be setup before - * initialization. - * - * \param device - * The UART device identifier. - * - * \param location - * The memory of the location for the given UART. For SoCFPGA - * UARTs, this parameter is ignored. - * - * \param clock_freq - * The clock frequency of the serial clock for the given UART. - * For SoCFPGA UARTs, this paramter is ignored. - * - * \param handle - * [out] A pointer to a handle that will represent the UART. This - * handle should subsequently be used when calling other UART - * APIs. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device identifier is invalid. - * \retval ALT_E_BAD_CLK The required clock is not yet setup. - */ -ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device, - void * location, - alt_freq_t clock_freq, - ALT_16550_HANDLE_t * handle); - -/*! - * Performs the uninitialization steps for the UART. This should be the last - * API call made to cleanup the UART. - * - * After calling this function, the handle will need to be initialized again - * before being used by calling alt_16550_init(). - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle); - -/*! - * Resets the UART to the default configuration. The UART will be reset and - * reinitialized. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle); - -/*! - * Starts the UART after all configuration has been completed. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle); - -/*! - * Stops the UART. While UART configuration can be done while enabled, it is - * not recommended. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle); - -/*! - * Reads a single character from the UART receiver buffer. This API should - * only be used when FIFOs are disabled. - * - * \param handle - * The UART device handle. - * - * \param item - * [out] Pointer to an output parameter that contains the in - * receiver buffer of the UART. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle, - char * item); - -/*! - * Writes a single character to the UART transmitter buffer. This API should - * only be used when FIFOs are disabled. - * - * \param handle - * The UART device handle. - * - * \param item - * The character to write to the transmitter buffer of the UART. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle, - char item); - -/*! - * @} - */ - -/*! - * \addtogroup UART_FIFO UART FIFO Interface - * - * This group of APIs provides access, configuration, and control of the UART - * FIFO. The FIFO allows the UART to buffer received data and data to be - * transmitted. - * - * @{ - */ - -/*! - * This type definition enumerates the receiver FIFO level conditions that - * will trigger the receiver FIFO to issue a receiver FIFO full event. - */ -typedef enum ALT_16550_FIFO_TRIGGER_RX_e -{ - /*! - * 1 or more character(s) in the receiver FIFO will trigger an event. - */ - ALT_16550_FIFO_TRIGGER_RX_ANY = 0, - - /*! - * 25% or higher capacity usage in the receiver FIFO will trigger an - * event. - */ - ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL = 1, - - /*! - * 50% or higher capacity usage in the receiver FIFO will trigger an - * event. - */ - ALT_16550_FIFO_TRIGGER_RX_HALF_FULL = 2, - - /*! - * 2 characters less than the receiver FIFO capacity will trigger an - * event. - */ - ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL = 3 -} -ALT_16550_FIFO_TRIGGER_RX_t; - -/*! - * This type definition enumerates the transmitter FIFO level conditions that - * will trigger the transmitter FIFO to issue a transmitter FIFO empty event. - */ -typedef enum ALT_16550_FIFO_TRIGGER_TX_e -{ - /*! - * Transmitter FIFO being completely empty will trigger an event. - */ - ALT_16550_FIFO_TRIGGER_TX_EMPTY = 0, - - /*! - * 2 or less character(s) in the transmitter FIFO will trigger an event. - */ - ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY = 1, - - /*! - * 25% or less capacity usage in the transmitter FIFO will trigger an - * event. - */ - ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL = 2, - - /*! - * 50% or less capacity usage in the transmitter FIFO will trigger an - * event. - */ - ALT_16550_FIFO_TRIGGER_TX_HALF_FULL = 3 -} -ALT_16550_FIFO_TRIGGER_TX_t; - -/*! - * Enables FIFO on the UART. This will enable both the receiver FIFO and - * transmitter FIFO. Both FIFOs will be cleared. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle); - -/*! - * Disables FIFOs on the UART. This will disable both the receiver FIFO and - * transmitter FIFO. Any data left in the FIFOs will be lost. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle); - -/*! - * Reads the given buffer from the receiver FIFO in the UART. - * - * The available characters in the FIFO can be determined by a few ways. Users - * can determine the number of items by calling alt_16550_fifo_level_get_rx(). - * - * Another way is by using the RX trigger and RX interrupt. First determine the - * RX FIFO size by calling alt_16550_fifo_size_get_rx(). Then set the desired - * trigger level by calling alt_16550_fifo_trigger_set_rx(). Calculate the - * triggering point by applying trigger description on the FIFO size. Enable RX - * interrupts by calling alt_16550_int_enable_rx(). When the RX interrupt fires - * due to the ALT_16550_INT_STATUS_RX_DATA condition, the calculated triggering - * point value can be used to determine the RX FIFO level. If the interrupt - * fires due to the ALT_16550_INT_STATUS_RX_TIMEOUT, the RX FIFO can be - * completely emptied by repeatedly polling the Line Status - * ALT_16550_LINE_STATUS_DR condition by calling alt_16550_line_status_get(). - * These steps are necessary if the UART does not implement FIFO level query - * functionality. As of 13.0sp1, this applies to the Altera 16550 Compatible - * Soft UART. - * - * Reading more data than that which is available can result in invalid data - * appearing like valid data. - * - * The FIFO must first be enabled before calling this function by calling - * alt_16550_fifo_enable(). - * - * \param handle - * The UART device handle. - * - * \param buffer - * [out] Pointer to a buffer where the specified count of - * characters from the receiver FIFO will be copied to. - * - * \param count - * The count of characters from the receiver FIFO to be copied. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle, - char * buffer, - size_t count); - -/*! - * Writes the given buffer to the transmitter FIFO in the UART. - * - * The available space in the FIFO can be determined by a few ways. Users can - * determine the number of items by calculating the FIFO capacity minus the - * FIFO level. This can be done by calling alt_16550_fifo_size_get_tx() and - * alt_16550_fifo_level_get_tx() respectively. - * - * Another way is by using the TX trigger and TX interrupt. First determine the - * TX FIFO size by calling alt_16550_fifo_size_get_tx(). The set the desired - * trigger level by calling alt_16550_fifo_trigger_set_tx(). Calculate the - * triggering point by applying the trigger description on the FIFO size. - * Enable TX interrupts by calling alt_16550_int_enable_tx(). When the TX - * interrupt fires, calculate the empty entries in the FIFO by subtracting the - * TX FIFO size and the calculated value. These steps are necessary if the UART - * does not implement FIFO level query functionality. As of 13.0sp1, this - * applies to the Altera 16550 Compatible Soft UART. - * - * Writing more data that there is space can result in data lost due to - * overflowing. - * - * The FIFOs must first be enabled before calling this function by calling - * alt_16550_fifo_enable(). - * - * \param handle - * The UART device handle. - * - * \param buffer - * Pointer to a buffer from where the specified count of - * characters will be copied to the transmitter FIFO. - * - * \param count - * The count of characters from the given buffer to be copied. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle, - const char * buffer, - size_t count); - -/*! - * Clears the contents of the receiver FIFO. Any characters which were - * previously contained in that FIFO will be discarded. - * - * The FIFOs must first be enabled before calling this function by calling - * alt_16550_fifo_enable(). - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle); - -/*! - * Clears the contents of the transmitter FIFO. Any characters which were - * previously contained in that FIFO will be discarded. - * - * The FIFOs must first be enabled before calling this function by calling - * alt_16550_fifo_enable(). - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle); - -/*! - * Clears the contents of the receiver and transmitter FIFO. Any characters - * which were previously contained on those FIFOs will be discarded. - * - * The FIFOs must first be enabled before calling this function by calling - * alt_16550_fifo_enable(). - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle); - -/*! - * Queries the size of the receiver FIFO. - * - * \param handle - * The UART device handle. - * - * \param size - * [out] Pointer to an output parameter that contains the size of - * the receiver FIFO. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle, - uint32_t * size); - -/*! - * Queries the size of the transmitter FIFO. - * - * \param handle - * The UART device handle. - * - * \param size - * [out] Pointer to an output parameter that contains the size of - * the transmitter FIFO. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle, - uint32_t * size); - -/*! - * Queries the current level of the receiver FIFO. - * - * The FIFOs must first be enabled before calling this function by calling - * alt_16550_fifo_enable(). - * - * For the Altera 16550 Compatible UART, it may not be possible to read the - * FIFO level and this function may always report 0. For more information on - * interacting with the FIFO in this situation, see documentation for - * alt_16550_fifo_read(). - * - * \param handle - * The UART device handle. - * - * \param level - * [out] Pointer to an output parameter that contains the level - * or number of characters in the receiver FIFO. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle, - uint32_t * level); - -/*! - * Queries the current level of the transmitter FIFO. - * - * The FIFOs must first be enabled before calling this function by calling - * alt_16550_fifo_enable(). - * - * For the Altera 16550 Compatible UART, it may not be possible to read the - * FIFO level and this function may always report 0. For more information on - * interacting with the FIFO in this situation, see documentation for - * alt_16550_fifo_write(). - * - * \param handle - * The UART device handle. - * - * \param level - * [out] Pointer to an output parameter that contains the level - * or number of characters in the transmitter FIFO. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle, - uint32_t * level); - -/*! - * Sets the receiver FIFO level which will trigger the receiver FIFO to issue - * receiver FIFO full event. For the list of available receiver FIFO trigger - * levels, see the documentation for ALT_16550_FIFO_TRIGGER_RX_t. - * - * The FIFOs must first be enabled before calling this function by calling - * alt_16550_fifo_enable(). - * - * \param handle - * The UART device handle. - * - * \param trigger - * The level of the receiver FIFO which is needed to trigger a - * receiver FIFO full event. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle, - ALT_16550_FIFO_TRIGGER_RX_t trigger); - -/*! - * Sets the transmitter FIFO level which will trigger the transmitter FIFO to - * transmitter FIFO empty event. For the list of available transmitter FIFO - * trigger levels, see the documentation for ALT_16550_FIFO_TRIGGER_TX_t. - * - * The FIFOs must first be enabled before calling this function by calling - * alt_16550_fifo_enable(). - * - * \param handle - * The UART device handle. - * - * \param trigger - * The level of the transmitter FIFO which is needed to trigger a - * transmitter FIFO empty event. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle, - ALT_16550_FIFO_TRIGGER_TX_t trigger); - -/*! - * @} - */ - -/*! - * \addtogroup UART_BAUD UART Baudrate Interface - * - * This group of APIs allows for the configuration of the UART's baudrate - * generation related functions. - * - * The UART baudrate is determined by dividing the ALT_CLK_L4_SP clock with - * the configured divisor. - * - * @{ - */ - -/*! - * This enumeration lists out the common baudrates used with modem and serial - * ports. Not every baudrate is available for the UART due to the limits of - * the serial clock frequency and divisor value. - */ -typedef enum ALT_16550_BAUDRATE_e -{ - ALT_16550_BAUDRATE_50 = 50, /*!< 50 bps baudrate. */ - ALT_16550_BAUDRATE_75 = 75, /*!< 75 bps baudrate. */ - ALT_16550_BAUDRATE_150 = 150, /*!< 150 bps baudrate. */ - ALT_16550_BAUDRATE_300 = 300, /*!< 300 bps baudrate. */ - ALT_16550_BAUDRATE_600 = 600, /*!< 600 bps baudrate. */ - ALT_16550_BAUDRATE_900 = 900, /*!< 900 bps baudrate. */ - ALT_16550_BAUDRATE_1200 = 1200, /*!< 1200 bps baudrate. */ - ALT_16550_BAUDRATE_1800 = 1800, /*!< 1800 bps baudrate. */ - ALT_16550_BAUDRATE_2400 = 2400, /*!< 2400 bps baudrate. */ - ALT_16550_BAUDRATE_3600 = 3600, /*!< 3600 bps baudrate. */ - ALT_16550_BAUDRATE_4800 = 4800, /*!< 4800 bps baudrate. */ - ALT_16550_BAUDRATE_7200 = 7200, /*!< 7200 bps baudrate. */ - ALT_16550_BAUDRATE_9600 = 9600, /*!< 9600 bps baudrate. */ - ALT_16550_BAUDRATE_14400 = 14400, /*!< 14400 bps baudrate. */ - ALT_16550_BAUDRATE_19200 = 19200, /*!< 19200 bps baudrate. */ - ALT_16550_BAUDRATE_28800 = 28800, /*!< 28800 bps baudrate. */ - ALT_16550_BAUDRATE_38400 = 38400, /*!< 38400 bps baudrate. */ - ALT_16550_BAUDRATE_57600 = 57600, /*!< 57600 bps baudrate. */ - ALT_16550_BAUDRATE_115200 = 115200 /*!< 115200 bps baudrate. */ -} -ALT_16550_BAUDRATE_t; - -/*! - * Gets the baudrate for the UART. - * - * This is done by calculating the baudrate from the divisor and the serial - * clock. The reported baudrate may not correspond exactly to the request - * baudrate. - * - * \param handle - * The UART device handle. - * - * \param baudrate - * [out] Pointer to an output paramter that contains the current - * baudrate of the UART. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle, - uint32_t * baudrate); - -/*! - * Sets the baudrate for the UART. This change will take effect when the UART - * moves from disabled to enabled. - * - * This is done by calculating the correct divisor using the request baudrate - * and the known serial clock. - * - * \param handle - * The UART device handle. - * - * \param baudrate - * The requested baudrate for the UART. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - * \retval ALT_E_ARG_RANGE The given baudrate is not possible due to - * limitations of the baudrate divisor and/or - * serial clock. - */ -ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle, - uint32_t baudrate); - -/*! - * Gets the baudrate divisor for the UART. - * - * The baudrate is determined by the following formula: - * * Baudrate = (serial clock frequency) / (16 * divisor) - * - * \param handle - * The UART device handle. - * - * \param divisor - * [out] Pointer to an output parameter that contains the current - * divisor used for baudrate generation. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle, - uint32_t * divisor); - -/*! - * Sets the baudrate divisor for the UART. This change will take effect when - * the UART moves from disabled to enabled. - * - * The baudrate is determined by the following formula: - * * Baudrate = (serial clock frequency) / (16 * divisor) - * - * \param handle - * The UART device handle. - * - * \param divisor - * The specified divisor value to use for baudrate generation. - * Valid values are 1 - 65535. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART identifier is invalid or the - * specified divisor is not supported by the - * UART. - */ -ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle, - uint32_t divisor); - -/*! - * @} - */ - -/*! - * \addtogroup UART_INT UART Interrupt Interface - * - * This group of APIs provides access, configuration, and control of the - * UART interrupts. - * - * @{ - */ - -/*! - * This type definition enumerates the different interrupt conditions that can - * be generated by the UART controller. - * - * Interrupts are listed in highest to lowest priority order. - */ -typedef enum ALT_16550_INT_STATUS_e -{ - /*! - * This interrupt signals that a overrun, parity, or framing error - * occurred, or a break event occured. The interrupt is cleared by reading - * the line status by calling alt_16550_line_status_get() or by disabling - * line status interrupts by calling alt_16550_int_disable_line(). - */ - ALT_16550_INT_STATUS_LINE = 0x6, - - /*! - * This interrupt signals that some data is available to be read from the - * UART. The definition of some depends on whether FIFOs are enabled or - * not. - * - * If FIFOs are disabled, this interrupt signals that the receiver - * contains data. In this case, the interrupt is cleared by reading the - * data from the UART by calling alt_16550_read(). - * - * If FIFOs are enabled, this interrupt signals that the receiver FIFO - * level is above the receiver trigger level specified. In this case, the - * interrupt is cleared by reading a sufficiently large buffer from the - * receiver FIFO such that the FIFO is filled below the receiver trigger - * level specified by calling alt_16550_fifo_read() or by adjusting the - * receiver trigger level appropriately by calling - * alt_16550_fifo_trigger_set_rx(). - * - * In either case, this interrupt can also be cleared by disabling - * receiver interrupts by calling alt_16550_int_disable_rx(). - */ - ALT_16550_INT_STATUS_RX_DATA = 0x4, - - /*! - * This interrupt signals that data is available in the receiver FIFO and - * that there has been no activity with the receiver FIFO for the last 4 - * character frames. In essence, the receiver FIFO has temporarily settled - * thus it may be a good time to empty the receiver FIFO. This interrupt - * is only available if FIFOs are enabled. The interrupt is cleared by - * reading from the receiver FIFO by calling alt_16550_fifo_read() or by - * disabling receiver interrupts by calling alt_16550_int_disable_rx(). - */ - ALT_16550_INT_STATUS_RX_TIMEOUT = 0xC, - - /*! - * This interrupt signals that the transmitter is idling. The definition - * of idling depends on whether FIFOs are enabled or not. - * - * If FIFOs are disabled, this interrupt signals that the transmitter - * shift register is empty. In this case, the interrupt is cleared by - * writing data to the UART by calling alt_16550_write(). - * - * If FIFO are enabled, this interrupt signals that the transmitter FIFO - * level is below the transmitter trigger level specified. In this case, - * the interrupt is cleared by writing a sufficiently large buffer to the - * transmitter FIFO such that the FIFO is filled above the transmitter - * trigger level specified by calling alt_16550_fifo_write() or by - * adjusting the transmitter trigger level appropriately by calling - * alt_16550_fifo_trigger_set_tx(). - * - * In either case, this interrupt can also be cleared by disabling - * transmitter interrupts by calling alt_16550_int_disable_tx(). - */ - ALT_16550_INT_STATUS_TX_IDLE = 0x2, - - /*! - * Modem status interrupt pending. The interrupt is cleared by reading the - * modem status by calling alt_16550_modem_status_get() or by disabling - * modem status interrupts by calling alt_16550_int_disable_modem(). - */ - ALT_16550_INT_STATUS_MODEM = 0x0, - - /*! - * No interrupts pending. - */ - ALT_16550_INT_STATUS_NONE = 0x1 -} -ALT_16550_INT_STATUS_t; - -/*! - * Enables the receiver FIFO to generate interrupts. Enabling this interrupt - * allows for the following interrupt signal(s): - * * ALT_16550_INT_STATUS_RX_DATA - * * ALT_16550_INT_STATUS_RX_TIMEOUT - * - * This interrupt is disabled by default. - * - * The FIFOs must also be enabled for this interrupt to actually be generated. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle); - -/*! - * Disables the receiver FIFO from generating interrupts. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle); - -/*! - * Enables the transmitter FIFO to generate interrupts. Enabling this - * interrupt allows for the following interrupt signal(s): - * * ALT_16550_INT_STATUS_TX_IDLE - * - * This interrupt is disabled by default. - * - * The FIFOs must also be enabled for this interrupt to actually be generated. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle); - -/*! - * Disables the transmitter FIFO from generating interrupts. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle); - -/*! - * Enables the receiver to generate line status interrupts. Enabling this - * interrupt allows for the following interrupt signal(s): - * * ALT_16550_INT_STATUS_LINE - * - * This interrupt is disabled by default. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle); - -/*! - * Disables the receiver from generating line status interrupts. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle); - -/*! - * Enables the UART to generate modem status interrupts. Enabling this - * interrupt allows for the following interrupt signal(s): - * * ALT_16550_INT_STATUS_MODEM - * - * This interrupt is disabled by default. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle); - -/*! - * Disables the UART from generate modem status interrupts. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle); - -/*! - * Disables all interrupts on the UART. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle); - -/*! - * Queries the interrupt status of the UART. This returns the highest priority - * interrupt pending. The appropriate interrupts must be enabled for them be - * generated in the UART. - * - * \param handle - * The UART device handle. - * - * \param status - * [out] Pointer to an output parameter that contains the current - * interrupt status of the UART. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle, - ALT_16550_INT_STATUS_t * status); - -/*! - * @} - */ - -/*! - * \addtogroup UART_MODEM UART Modem Interface - * - * This group of APIs provides access, configuration, and control of the UART - * Modem interface. - * - * @{ - */ - -/*! - * This type definition enumerates the set of UART modem status conditions as - * register mask values. - */ -typedef enum ALT_16550_MODEM_STATUS_e -{ - /*! - * Data Carrier Detect. This status indicates that the carrier has been - * detected by the modem. It corresponds to an inverted dcd_n input. DCD - * is unasserted when dcd_n is logic 1 and asserted when dcd_n is logic 0. - */ - ALT_16550_MODEM_STATUS_DCD = 1 << 7, - - /*! - * Ring Indicator. This status indicates that the telephone ringing signal - * has been redeived by the modem. It corresponds to an inverted ri_n - * input. RI is unasserted when ri_n is logic 1 and asserted when ri_n is - * logic 0. - */ - ALT_16550_MODEM_STATUS_RI = 1 << 6, - - /*! - * Data Set Ready. This status indicates that the modem is ready to - * establish communications with the UART. It corresponds to an inverted - * dsr_n input. DSR is unasserted when dsr_n is logic 1 and asserted when - * dsr_n is logic 0. - */ - ALT_16550_MODEM_STATUS_DSR = 1 << 5, - - /*! - * Clear To Send. This status indicates the current state of the modem - * cts_n line. It corresponds to an inverted cts_n input. CTS is - * unasserted when cts_n is logic 1 and asserted when cts_n is logic 0. - */ - ALT_16550_MODEM_STATUS_CTS = 1 << 4, - - /*! - * Delta Data Carrier Detect. This status condition indicates that the - * Data Carrier Detect has changed since the last time the modem status - * was read. Reading the modem status clears this status. For more - * information about the Data Carrier Detect status, see - * ALT_16550_MODEM_STATUS_DCD. - */ - ALT_16550_MODEM_STATUS_DDCD = 1 << 3, - - /*! - * Trailing Edge of Ring Indicator. This status indicates that the Ring - * Indicator has changed from asserted to unasserted. Reading the modem - * status will clear this status. For more information about the Ring - * Indicator status, reference ALT_16550_MODEM_STATUS_RI. - */ - ALT_16550_MODEM_STATUS_TERI = 1 << 2, - - /*! - * Delta Data Set Ready. This status condition indicates that the Data Set - * Ready has changed since the last time the modem status was read. - * Reading the modem status will clear this status. For more information - * about the Data Set Ready status, see ALT_16550_MODEM_STATUS_DSR. - */ - ALT_16550_MODEM_STATUS_DDSR = 1 << 1, - - /*! - * Delta Clear To Send. This status condition indicates that the Clear To - * Send has changed since the last time the modem status was read. Reading - * the modem status will clear this status. For more information about the - * Clear To Send status, see ALT_16550_MODEM_STATUS_CTS. - */ - ALT_16550_MODEM_STATUS_DCTS = 1 << 0 -} -ALT_16550_MODEM_STATUS_t; - -/*! - * Enables automatic flow control in the UART modem. When in this mode, the - * rts_n is gated with the threshold trigger condition of the receiver FIFO. - * - * The Altera 16550 Compatible Soft IP UART may not have this option enabled. - * - * The FIFOs must be enabled for flow control to be used. - * - * The recommended bring up for flow control is as follows: - * * Enable automatic flow control by calling alt_16550_flowcontrol_enable(). - * This will allow both the receiver FIFO and user RTS to control the rts_n - * output. Because the user RTS is not enabled, the rts_n will be inactive - * high. - * * Enable RTS by calling alt_16550_modem_enable_rts(). This will give the - * receiver FIFO to have full control of the rts_n output. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle); - -/*! - * Disables automatic flow control in the UART modem. - * - * The recommended bring down for flow control is as follows: - * * Disable RTS by calling alt_16550_modem_disable_rts(). This will disable - * generation of the rts_n ouput. - * * Disable automatic flow control by calling - * alt_16550_flowcontrol_disable(). - * - * The receiver FIFO will still be active after these steps. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle); - -/*! - * Puts the UART in loopback mode. This is used for diagnostic and test - * purposes. - * - * The SoCFPGA UARTs does not support automatic flow control when in loopback - * mode. - * - * The Altera 16550 Compatible Soft IP UART implements this in 13.0sp1 and - * later. Setting this has no effect with 13.0. - * - * When in this mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are - * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) - * are held inactive high externally and internally looped back to the inputs. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle); - -/*! - * Takes the UART out of loopback mode. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle); - -/*! - * Asserts the OUT1 output. OUT1 is inverted then driven out to out1_n. - * - * There are special considerations when the UART is in loopback mode. See - * alt_16550_loopback_enable() for more information. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle); - -/*! - * Unasserts the OUT1 output. OUT1 is inverted then driven out to out1_n. - * - * There are special considerations when the UART is in loopback mode. See - * alt_16550_loopback_enable() for more information. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle); - -/*! - * Asserts the OUT2 output. OUT2 is inverted then driven out to out2_n. - * - * There are special considerations when the UART is in loopback mode. See - * alt_16550_loopback_enable() for more information. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle); - -/*! - * Unasserts the OUT2 output. OUT2 is inverted then driven out to out2_n. - * - * There are special considerations when the UART is in loopback mode. See - * alt_16550_loopback_enable() for more information. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle); - -/*! - * Asserts the RTS (Request To Send) output. RTS is inverted then driven out - * to rts_n. RTS is used to inform the modem that the UART is ready to receive - * data. - * - * There are special considerations when the UART is in automatic flow control - * mode. See alt_16550_flowcontrol_enable() for more information. - * - * There are special considerations when the UART is in loopback mode. See - * alt_16550_loopback_enable() for more information. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle); - -/*! - * Deaserts the RTS (Request To Send) output. RTS is inverted then driven out - * to rts_n. - * - * There are special considerations when the UART is in automatic flow control - * mode. See alt_16550_flowcontrol_enable() for more information. - * - * There are special considerations when the UART is in loopback mode. See - * alt_16550_loopback_enable() for more information. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle); - -/*! - * Asserts the DTR (Data Terminal Ready) output. DTR is inverted then driven - * out to dtr_n. DTR is used to inform the modem that UART is ready to - * establish communications. - * - * There are special considerations when the UART is in loopback mode. See - * alt_16550_loopback_enable() for more information. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle); - -/*! - * Deasserts the DTR (Data Terminal Ready) output. DTR is inverted then driven - * out to dtr_n. - * - * There are special considerations when the UART is in loopback mode. See - * alt_16550_loopback_enable() for more information. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle); - -/*! - * Reads the modem status from the UART. - * - * \param handle - * The UART device handle. - * - * \param status - * [out] Pointer to an output parameter that contains the current - * modem status of the UART as a register mask. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle, - uint32_t * status); - -/*! - * @} - */ - -/*! - * \addtogroup UART_LINE UART Line Interface - * - * This group of APIs provides access, configuration, and control of the UART - * Line interface. - * - * @{ - */ - -/*! - * This type definition enumerates the supported databits per frame. - */ -typedef enum ALT_16550_DATABITS_e -{ - /*! - * This option selects 5 databits per frame. - */ - ALT_16550_DATABITS_5 = 0, - - /*! - * This option selects 6 databits per frame. - */ - ALT_16550_DATABITS_6 = 1, - - /*! - * This option selects 7 databits per frame. - */ - ALT_16550_DATABITS_7 = 2, - - /*! - * This option selects 8 databits per frame. - */ - ALT_16550_DATABITS_8 = 3 -} -ALT_16550_DATABITS_t; - -/*! - * This type definition enumerates the supported stopbits per frame. - */ -typedef enum ALT_16550_STOPBITS_e -{ - /*! - * This options specifies 1 stopbit per frame. - */ - ALT_16550_STOPBITS_1 = 0, - - /*! - * This options specifies 2 stopbits per frame. If the frame is - * configured with 5 databits, 1.5 stopbits is used instead. - */ - ALT_16550_STOPBITS_2 = 1 -} -ALT_16550_STOPBITS_t; - -/*! - * This type definition enumerates the possible parity to use per frame. - */ -typedef enum ALT_16550_PARITY_e -{ - /*! - * This option disables the parity error detection bit in the data frame. - */ - ALT_16550_PARITY_DISABLE = 0, - - /*! - * This option enables the odd parity error detection bit in the data - * frame. - */ - ALT_16550_PARITY_ODD = 1, - - /*! - * This option enables the even parity error detection bit in the data - * frame. - */ - ALT_16550_PARITY_EVEN = 2 -} -ALT_16550_PARITY_t; - -/*! - * This type definition enumerates the set of UART line status conditions as - * register mask values. - */ -typedef enum ALT_16550_LINE_STATUS_e -{ - /*! - * Receiver FIFO Error. This status indicates that one or more parity - * error, framing error, or break indication exists in the receiver FIFO. - * It is only set when FIFO is enabled. This status cleared when line - * status is read, the character with the issue is at the top of the FIFO, - * and when no other issues exist in the FIFO. - */ - ALT_16550_LINE_STATUS_RFE = 1 << 7, - - /*! - * Transmitter EMpTy (Empty). This status indicates that transmitter shift - * register is empty. If FIFOs are enabled, the status is set when the - * transmitter FIFO is also empty. This status is cleared when the - * transmitter shift registers is loaded by writing to the UART - * transmitter buffer or transmitter FIFO if FIFOs are enabled. This is - * done by calling alt_16550_write() and alt_16550_fifo_write() - * respectively. - */ - ALT_16550_LINE_STATUS_TEMT = 1 << 6, - - /*! - * Transmitter Holding Register Empty. This status indicates that the - * transmitter will run out of data soon. The definition of soon depends - * on whether the FIFOs are enabled. - * - * If FIFOs are disabled, this status indicates that the transmitter will - * run out of data to send after the current transmit shift register - * completes. In this case, this status is cleared when the data is - * written to the UART. This can be done by calling alt_16550_write(). - * - * If FIFOs are enabled, this status indicates that the transmitter FIFO - * level is below the transmitter trigger level specified. In this case, - * this status is cleared by writing a sufficiently large buffer to the - * transmitter FIFO such that the FIFO is filled above the transmitter - * trigger level specified by calling alt_16550_fifo_write() or by - * adjusting the transmitter trigger level appropriately by calling - * alt_16550_fifo_trigger_set_tx(). - * - * \internal - * The implementation of the UART driver always ensures that IER[7] is - * set. This means that the UART always has Programmable THRE (Transmitter - * Holding Register Empty) Interrupt Mode Enable (PTIME) enabled. - * \endinternal - */ - ALT_16550_LINE_STATUS_THRE = 1 << 5, - - /*! - * Break Interrupt. This status indicates that a break interrupt sequence - * is detected in the incoming serial data. This happens when the the data - * is 0 for longer than a frame would normally be transmitted. The break - * interrupt status is cleared by reading the line status by calling - * alt_16550_line_status_get(). - * - * If FIFOs are enabled, this status will be set when the character with - * the break interrupt status is at the top of the receiver FIFO. - */ - ALT_16550_LINE_STATUS_BI = 1 << 4, - - /*! - * Framing Error. This status indicates that a framing error occurred in - * the receiver. This happens when the receiver detects a missing or - * incorrect number of stopbit(s). - * - * If FIFOs are enabled, this status will be set when the character with - * the framing error is at the top of the FIFO. When a framing error - * occurs, the UART attempts to resynchronize with the transmitting UART. - * This status is also set if break interrupt occurred. - */ - ALT_16550_LINE_STATUS_FE = 1 << 3, - - /*! - * Parity Error. This status indicates that a parity error occurred in the - * receiver. - * - * If FIFOs are enabled, this status will be set when the character with - * the parity error is at the top of the receiver FIFO. This status is - * also set if a break interrupt occurred. - */ - ALT_16550_LINE_STATUS_PE = 1 << 2, - - /*! - * Overrun Error. This status indicates that an overrun occurred in the - * receiver. - * - * If FIFOs are disabled, the arriving character will overwrite the - * existing character in the receiver. Any previously existing - * character(s) will be lost. - * - * If FIFOs are disabled, the arriving character will be discarded. The - * buffer will continue to contain the preexisting characters. - */ - ALT_16550_LINE_STATUS_OE = 1 << 1, - - /*! - * Data Ready. This status indicates that the receiver or receiver FIFO - * contains at least one character. - */ - ALT_16550_LINE_STATUS_DR = 1 << 0 -} -ALT_16550_LINE_STATUS_t; - -/*! - * Sets the configuration for a given character frame. - * - * \param handle - * The UART device handle. - * - * \param databits - * The number of databits for each character frame. - * - * \param parity - * The parity to use for each character frame. - * - * \param stopbits - * The number of stopbits for each character frame. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle, - ALT_16550_DATABITS_t databits, - ALT_16550_PARITY_t parity, - ALT_16550_STOPBITS_t stopbits); - -/*! - * Starts transmitting a break condition by transmitting a logic 0 state - * longer than a frame would normally be transmitted. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle); - -/*! - * Stops transmitting a break condition. - * - * \param handle - * The UART device handle. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle); - -/*! - * Reads the line status from the UART. - * - * \param handle - * The UART device handle. - * - * \param status - * [out] Pointer to an output parameter that contains the current - * line status of the UART. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given UART device handle is invalid. - */ -ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle, - uint32_t * status); - -/*! - * @} - */ - -/*! - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_16550_UART_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h deleted file mode 100644 index 781cc49aa3..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h +++ /dev/null @@ -1,825 +0,0 @@ -/*! \file - * Altera - SoC FPGA Address Space Manager - */ - -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ALT_ADDRESS_SPACE_H__ -#define __ALT_ADDRESS_SPACE_H__ - -#include <stdbool.h> -#include "hwlib.h" -#include "socal/hps.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/******************************************************************************/ -// ARM Level 2 Cache Controller L2C-310 Register Interface - -// Address Filtering Start Register -// The Address Filtering Start Register is a read and write register. -// Bits Field Description -// :-------|:--------------------------|:----------------------------------------- -// [31:20] | address_filtering_start | Address filtering start address for -// | | bits [31:20] of the filtering address. -// [19:1] | Reserved | SBZ/RAZ -// [0] | address_filtering_enable | 0 - address filtering disabled -// | | 1 - address filtering enabled. - -// Address Filtering Start Register Address -#define L2_CACHE_ADDR_FILTERING_START_OFST 0xC00 -#define L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST) -// Address Filtering Start Register - Start Value Mask -#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000 -// Address Filtering Start Register - Reset Start Address Value (1 MB) -#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 -// Address Filtering Start Register - Enable Flag Mask -#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001 -// Address Filtering Start Register - Reset Enable Flag Value (Enabled) -#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1 - -// Address Filtering End Register -// The Address Filtering End Register is a read and write register. -// Bits Field Description -// :-------|:--------------------------|:----------------------------------------- -// [31:20] | address_filtering_end | Address filtering end address for bits -// | | [31:20] of the filtering address. -// [19:0] | Reserved | SBZ/RAZ - -// Address Filtering End Register Address -#define L2_CACHE_ADDR_FILTERING_END_OFST 0xC04 -#define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST) -// Address Filtering End Register - End Value Mask -#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000 -// Address Filtering End Register - Reset End Address Value (3 GiB) -#define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000 - -#ifndef __ASSEMBLY__ - -/******************************************************************************/ -/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager - * - * This module contains group APIs for managing the HPS address space. This - * module contains group APIs to manage: - * * Memory Map Control - * * Memory Coherence - * * Cache Managment - * * MMU Managment - * - * @{ - */ - -/******************************************************************************/ -/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control - * - * This group API provides functions to map and remap selected address ranges - * into the accessible (visible) views of the MPU and non MPU address spaces. - * - * \b Caveats - * - * \b NOTE: Caution should be observed when remapping address 0 to different - * memory. The code performing the remapping operation should not be executing - * in the address range being remapped to different memory. - * - * For example, if address 0 is presently mapped to OCRAM and the code is - * preparing to remap address 0 to SDRAM, then the code must not be executing in - * the range 0 to 64 KB as this address space is about to be remapped to - * different memory. If the code performing the remap operation is executing - * from OCRAM then it needs to be executing from its permanently mapped OCRAM - * address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR). - * - * \b NOTE: The MPU address space view is controlled by two disparate hardware - * control interfaces: the L3 remap register and the L2 cache address filtering - * registers. To complicate matters, the L3 remap register is write-only which - * means not only that current remap register state cannot be read but also that - * a read-modify-write operation cannot be performed on the register. - * - * This should not present a problem in most use case scenarios except for the - * case where a current MPU address space mapping of 0 to SDRAM is being changed - * to to a mapping of 0 to Boot ROM or OCRAM. - * - * In this case, a two step process whereby the L3 remap register is first set - * to the new desired MPU address 0 mapping and then the L2 cache address - * filtering registers have their address ranges adjusted accordingly must be - * followed. An example follows: -\verbatim -// 1 MB reset default value for address filtering start -#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 -uint32_t addr_filt_start; -uint32_t addr_filt_end; - -// Perform L3 remap register programming first by setting the desired new MPU -// address space 0 mapping. Assume OCRAM for the example. -alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...); - -// Next, adjust the L2 cache address filtering range. Set the start address to -// the default reset value and retain the existing end address configuration. -alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end); -if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET) -{ - alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end); -} -\endverbatim - * @{ - */ - -/******************************************************************************/ -/*! - * This type definition enumerates the MPU address space attributes. - * - * The MPU address space consists of the ARM Cortex A9 processors and associated - * processor peripherals (cache, MMU). - */ -typedef enum ALT_ADDR_SPACE_MPU_ATTR_e -{ - ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, /*!< Maps the Boot ROM to address - * 0x0 for the MPU L3 master. Note - * that the Boot ROM is also - * always mapped to address - * 0xfffd_0000 for the MPU L3 - * master independent of - * attribute. - */ - - ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address - * 0x0 for the MPU L3 master. Note - * that the On-chip RAM is also - * always mapped to address - * 0xffff_0000 for the MPU L3 - * master independent of this - * attribute. - */ -} ALT_ADDR_SPACE_MPU_ATTR_t; - -/******************************************************************************/ -/*! - * This type definition enumerates the non-MPU address space attributes. - * - * The non-MPU address space consists of the non-MPU L3 masters including the - * DMA controllers (standalone and those built into peripherals), the F2H AXI - * Bridge, and the DAP. - */ -typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e -{ - ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0 - * for the non-MPU L3 masters. - */ - ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address - * 0x0 for the non-MPU L3 - * masters. Note that the On-chip - * RAM is also always mapped to - * address 0xffff_0000 for the - * non-MPU L3 masters independent - * of this attribute. - */ -} ALT_ADDR_SPACE_NONMPU_ATTR_t; - -/******************************************************************************/ -/*! - * This type definition enumerates the HPS to FPGA bridge accessiblity - * attributes. - */ -typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e -{ - ALT_ADDR_SPACE_H2F_INACCESSIBLE, /*!< The H2F AXI Bridge is not - * visible to L3 masters. Accesses - * to the associated address range - * return an AXI decode error to - * the master. - */ - ALT_ADDR_SPACE_H2F_ACCESSIBLE /*!< The H2F AXI Bridge is visible - * to L3 masters. - */ -} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t; - -/******************************************************************************/ -/*! - * This type definition enumerates the Lightweight HPS to FPGA bridge - * accessiblity attributes. - */ -typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e -{ - ALT_ADDR_SPACE_LWH2F_INACCESSIBLE, /*!< The LWH2F AXI Bridge is not - * visible to L3 masters. Accesses - * to the associated address range - * return an AXI decode error to - * the master. - */ - ALT_ADDR_SPACE_LWH2F_ACCESSIBLE /*!< The LWH2F AXI Bridge is visible - * to L3 masters. - */ -} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t; - -/******************************************************************************/ -/*! - * Configures the mapped and accessible (visible) address ranges for the HPS - * MPU, non-MPU, and Bridge address spaces. - * - * \param mpu_attr - * The MPU address space configuration attributes. - * - * \param nonmpu_attr - * The non-MPU address space configuration attributes. - * - * \param h2f_attr - * The H2F Bridge attribute mapping and accessibility attributes. - * - * \param lwh2f_attr - * The Lightweight H2F Bridge attribute mapping and accessibility - * attributes. - * - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_INV_OPTION One or more invalid attribute options were - * specified. - */ -ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, - ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr, - ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr, - ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr); - -/******************************************************************************/ -/*! - * Maps SDRAM to address 0x0 for the MPU address space view. - * - * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest - * 64KB of the boot region are accessible because the size of the Boot ROM and - * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to - * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to - * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not - * accessible to the MPU unless address 0 is remapped to SDRAM after reset. - * - * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access - * SDRAM. - * - * \internal - * The remap to address 0x0 is achieved by configuring the L2 cache Address - * Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM - * AXI (M1) master port by calling: - * - * alt_l2_addr_filter_cfg_set(0x0, <current_addr_filt_end_value>); - * - * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical - * Reference Manual, Section 3.3.12 Address Filtering </em>. - * \endinternal - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter - * - * The L2 cache address filter controls where physical addresses within certain - * ranges of the MPU address space are directed. - * - * The L2 cache has master port connections to the L3 interconnect and the SDRAM - * controller. A programmable address filter controls which portions of the - * 32-bit physical address space use each master. - * - * When l2 address filtering is configured and enabled, a physical address will - * be redirected to one master or the other based upon the address filter - * configuration. - * - * If \b address_filter_start <= \e physical_address < \b address_filter_end: - * * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller) - * * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect) - * - * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical - * Reference Manual, Section 3.3.12 Address Filtering </em> for more information. - * @{ - */ - -/******************************************************************************/ -/*! - * Get the L2 cache address filtering configuration settings. - * - * \param addr_filt_start - * [out] An output parameter variable for the address filtering - * start address for the range of physical addresses redirected to - * the SDRAM AXI master port. The value returned is always a 1 MiB - * aligned address. - * - * \param addr_filt_end - * [out] An output parameter variable for the address filtering - * end address for the range of physical addresses redirected to - * the SDRAM AXI master port. The value returned is always a 1 MiB - * aligned address. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG An bad argument was passed. Either \e addr_filt_start - * or \e addr_filt_end or both are invalid addresses. - */ -ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start, - uint32_t* addr_filt_end); - -/******************************************************************************/ -/*! - * Set the L2 cache address filtering configuration settings. - * - * Address filtering start and end values must be 1 MiB aligned. - * - * \param addr_filt_start - * The address filtering start address for the range of physical - * addresses redirected to the SDRAM AXI master port. Only bits - * [31:20] of the address are valid. Any bits outside the range - * [31:20] are invalid and will cause an error status to be - * returned. - * - * \param addr_filt_end - * The address filtering end address for the range of physical - * addresses redirected to the SDRAM AXI master port. Only bits - * [31:20] of the address are valid. Any bits outside the range - * [31:20] are invalid and will cause an error status to be - * returned. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or - * more address arguments do not satisfy the argument - * constraints. - */ -ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, - uint32_t addr_filt_end); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping - * - * This API provides management of the ACP ID Mapper that enables data coherent - * access to the MPU address space by external masters. The set of external - * masters include L3 master peripherals and FPGA soft IP. - * - * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA - * based soft IP - to maintain data coherency with the Cortex-A9 MPCore - * processors and the Snoop Control Unit (SCU). - * - * The ACP supports up to six masters. However, soft IP implemented in the FPGA - * fabric can have a larger number of masters that need to access the ACP. The - * ACP ID Mapper expands the number of masters able to access the ACP. The ACP - * ID Mapper is situated between the interconnect and the ACP of the MPU - * subsystem. It has the following characteristics: - * * Support for up to six concurrent ID mappings. - * * 1 GiB coherent window into 4 GiB MPU address space - * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU) - * and L2 cache. - * - * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller - * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input - * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output - * identifiers) required by the ACP slave port. - * - * The ACP ID Mapper supports the two ID mapping modes: - * * Dynamic Mapping - In this mode an input ID is automatically mapped to an - * available output ID. The dynamic mode is more flexible because the hardware - * handles the mapping. The hardware mapping allows an output ID to be used - * for more than one input ID. Output IDs are assigned to input IDs on a - * first-come, first-served basis. - * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs - * to output IDs. - * - * Out of the total of eight ACP output ID values, only six are available to the - * ACP ID Mapper for remapping. The first two output IDs (0 and 1) are - * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the - * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 - * support fixed and dynamic modes of operation while output ID 7 supports - * dynamic mode only. - * - * The following table summarizes the usage of the 3-bit ouput ID values by the - * ACP ID Mapper and their settings at reset. - * - * Output ID | Usage | Reset State - * :-----------|:--------------------------------------------------|:------------ - * 0 | Reserved for Cortex-A9 cores. | - - * 1 | Reserved for Cortex-A9 cores. | - - * 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed - * : | reset. After reset, can be reconfigured to either | DAP Master - * : | fixed or dynamic. |: - * 3 | Configurable fixed or dynamic mode. | Dynamic - * 4 | Configurable fixed or dynamic mode. | Dynamic - * 5 | Configurable fixed or dynamic mode. | Dynamic - * 6 | Configurable fixed or dynamic mode. | Dynamic - * 7 | Dynamic mode only. | Dynamic - * - * Where <em>Output ID</em> is the ACP ID Mapper output value that goes to the ACP. - * - * Additionally, for masters unable to drive the AXI user sideband signals of - * incoming transactions, the ACP ID Mapper allows control of the AXI user - * sideband signal values. Not all masters drive these signals, so the ACP ID - * Mapper makes it possible to drive the 5-bit user sideband signal with either - * a default value (in dynamic mode) or specific values (in fixed mode). - * - * The ACP ID Mapper can also control which 1 GiB coherent window into memory is - * accessed by masters of the L3 interconnect. Each fixed mapping can be - * assigned a different user sideband signal and memory window to allow specific - * settings for different masters. All dynamic mappings share a common user - * sideband signal and memory window setting. One important exception, however, - * is that the ACP ID mapper always allows user sideband signals from the - * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured - * user sideband value associated with the ID. - * - * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which - * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows - * transactions to be routed to different 1 GiB-sized memory views, called pages, - * in both dynamic and fixed modes. - * - * See: <em>Chapter 6: Cortex-A9 Microprocessor Unit Subsystem</em> in - * <em>Volume 3: Hard Processor System Technical Reference Manual</em> of the - * <em>Arria V or Cyclone V Device Handbook</em> for a complete discussion of - * the operation and restrictions on the ACP and the ACP ID Mapper. - * - * @{ - */ - -/******************************************************************************/ -/*! - * \name External Master ID Macros - * - * These macros define the HPS external master identifiers that are 12-bit input - * IDs to the ACP ID Mapper. Some of the masters have a range of identifier - * values assigned to them and are distinguished by taking a <em>(var)\</em> - * argument. - * @{ - */ - -/*! Bit mask for the relevant 12 bits of an external master ID */ -#define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff - -/*! Master ID for L2M0 */ -#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var))) -/*! Master ID for DMA */ -#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var))) -/*! Master ID for EMAC0 */ -#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var))) -/*! Master ID for EMAC1 */ -#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var))) -/*! Master ID for USB0 */ -#define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803 -/*! Master ID for USB1 */ -#define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806 -/*! Master ID for NAND controller */ -#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var))) -/*! Master ID for Embedded Trace Router (ETR) */ -#define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800 -/*! Master ID for Debug Access Port (DAP) */ -#define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004 -/*! Master ID for SD/MMC controller */ -#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805 -/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */ -#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var))) -/*! @} */ - -/******************************************************************************/ -/*! - * This type defines the enumerations 3-bit output ids to ACP ID mapper. - */ -typedef enum ALT_ACP_ID_OUTPUT_ID_e -{ - ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset. - * After reset, can be either fixed or dynamic, - * programmed by software. - */ - ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */ - ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */ - ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */ - ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */ - ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */ -} ALT_ACP_ID_OUTPUT_ID_t; - -/*! - * This type defines the enumerations used to specify the 1 GiB page view of the - * MPU address space used by an ACP ID mapping configuration. - */ -typedef enum ALT_ACP_ID_MAP_PAGE_e -{ - ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */ - ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */ - ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */ - ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */ -} ALT_ACP_ID_MAP_PAGE_t; - -/******************************************************************************/ -/*! - * Configure a fixed ACP ID mapping for read transactions originating from - * external masters identified by \e input_id. The \e input_id value is - * translated to the specified 3-bit \e output_id required by the ACP slave - * port. - * - * \param input_id - * The 12 bit external master ID originating read transactions - * targeted for ID translation. Valid argument range must be 0 <= - * \e output_id <= 4095. - * - * \param output_id - * The 3-bit output ID value the ACP ID Mapper translates read - * transactions identified by \e input_id to. This is the value - * propogated to the ACP slave port. Valid argument values must be - * 0 <= \e output_id <= 7. - * - * \param page - * The MPU address space page view to use for the ACP window used - * by the ID tranlation mapping. - * - * \param aruser - * The 5-bit AXI ARUSER read user sideband signal value to use for - * masters unable to drive the AXI user sideband signals. Valid - * argument range is 0 <= \e aruser <= 31. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_RESERVED The argument value is reserved or unavailable. - * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or - * more of the \e input_id, and/or \e output_id - * arguments violates its range constraint. - * \retval ALT_E_BAD_ARG The \e page argument is invalid. - */ -ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, - const uint32_t output_id, - const ALT_ACP_ID_MAP_PAGE_t page, - const uint32_t aruser); - -/******************************************************************************/ -/*! - * Configure a fixed ACP ID mapping for write transactions originating from - * external masters identified by \e input_id. The \e input_id value is - * translated to the specified 3-bit \e output_id required by the ACP slave - * port. - * - * \param input_id - * The 12 bit external master ID originating write transactions - * targeted for ID translation. Valid argument range must be 0 <= - * \e output_id <= 4095. - * - * \param output_id - * The 3-bit output ID value the ACP ID Mapper translates write - * transactions identified by \e input_id to. This is the value - * propogated to the ACP slave port. Valid argument values must be - * 0 <= \e output_id <= 7. - * - * \param page - * The MPU address space page view to use for the ACP window used - * by the ID tranlation mapping. - * - * \param awuser - * The 5-bit AXI AWUSER write user sideband signal value to use for - * masters unable to drive the AXI user sideband signals. Valid - * argument range is 0 <= \e awuser <= 31. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_RESERVED The argument value is reserved or unavailable. - * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or - * more of the \e input_id, and/or \e output_id - * arguments violates its range constraint. - * \retval ALT_E_BAD_ARG The \e page argument is invalid. - */ -ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, - const uint32_t output_id, - const ALT_ACP_ID_MAP_PAGE_t page, - const uint32_t awuser); - -/******************************************************************************/ -/*! - * Configure the designated 3-bit output ID as an available identifier resource - * for use by the dynamic ID mapping function of the ACP ID Mapper for read - * transactions. The \e output_id value is available for dynamic assignment to - * external master read transaction IDs that do not have an explicit fixed ID - * mapping. - * - * \param output_id - * The 3-bit output ID value designated as an available ID for use - * by the dynamic mapping function of the ACP ID Mapper. The \e - * ouput_id value is used exclusively for dynamic ID mapping until - * reconfigured as a fixed ID mapping by a call to - * alt_acp_id_map_fixed_read_set(). Valid argument values must be - * 0 <= \e output_id <= 7. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_RESERVED The argument value is reserved or unavailable. - * \retval ALT_E_ARG_RANGE An argument violates a range constraint. - */ -ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id); - -/******************************************************************************/ -/*! - * Configure the designated 3-bit output ID as an available identifier resource - * for use by the dynamic ID mapping function of the ACP ID Mapper for write - * transactions. The \e output_id value is available for dynamic assignment to - * external master write transaction IDs that do not have an explicit fixed ID - * mapping. - * - * \param output_id - * The 3-bit output ID value designated as an available ID for use - * by the dynamic mapping function of the ACP ID Mapper. The \e - * ouput_id value is used exclusively for dynamic ID mapping until - * reconfigured as a fixed ID mapping by a call to - * alt_acp_id_map_fixed_write_set(). Valid argument values must be - * 0 <= \e output_id <= 7. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_RESERVED The argument value is reserved or unavailable. - * \retval ALT_E_ARG_RANGE An argument violates a range constraint. - */ -ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id); - -/******************************************************************************/ -/*! - * Configure the page and user read sideband signal options that are applied to - * all read transactions that have their input IDs dynamically mapped. - * - * \param page - * The MPU address space page view to use for the ACP window used - * by the dynamic ID tranlation mapping. - * - * \param aruser - * The 5-bit AXI ARUSER read user sideband signal value to use for - * masters unable to drive the AXI user sideband signals. Valid - * argument range is 0 <= \e aruser <= 31. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_RESERVED The argument value is reserved or unavailable. - * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or - * more of the \e page and/or \e aruser - * arguments violates its range constraint. - * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master - * identifier. - */ -ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, - const uint32_t aruser); - -/******************************************************************************/ -/*! - * Configure the page and user write sideband signal options that are applied to - * all write transactions that have their input IDs dynamically mapped. - * - * \param page - * The MPU address space page view to use for the ACP window used - * by the dynamic ID tranlation mapping. - * - * \param awuser - * The 5-bit AXI AWUSER write user sideband signal value to use for - * masters unable to drive the AXI user sideband signals. Valid - * argument range is 0 <= \e aruser <= 31. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_RESERVED The argument value is reserved or unavailable. - * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or - * more of the \e page and/or \e awuser - * arguments violates its range constraint. - * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master - * identifier. - */ -ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, - const uint32_t awuser); - -/******************************************************************************/ -/*! - * Return the current read transaction mapping configuration used by the ACP ID - * Mapper for the specified output ID. - * - * If \e output_id is configured as a fixed mapping then \b true is returned in - * the \e fixed output parameter and the translation mapping options configured - * for that \e output_id are returned in the other output parameters. - * - * If \e output_id is configured as a dynamic mapping then \b false is returned - * in the \e fixed output parameter and the translation mapping options - * configured for all dynamically remapped output IDs are returned in the other - * output parameters. - * - * \param output_id - * The output ID to return the mapping configuration for. 0 <= \e - * output_id <= 7. - * - * \param fixed - * [out] Set to \b true if the specified \e output_id is a fixed ID - * mapping configuration. Set to \b false if the mapping - * configuration is dynamic. - * - * \param input_id - * [out] The input ID of the external master that a fixed ID - * mapping is applied to for the \e output_id. If \e fixed is \b - * false then this output parameter is set to 0 and its value - * should be considered as not applicable. - * - * \param page - * [out] The MPU address space page view used by the mapping - * configuration. - * - * \param aruser - * [out] The 5-bit AXI ARUSER read user sideband signal value used - * by the mapping configuration when masters are unable to drive - * the AXI user sideband signals. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_RESERVED The argument value is reserved or unavailable. - * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e - * output_id argument violates its range constraint. - */ -ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, - bool* fixed, - uint32_t* input_id, - ALT_ACP_ID_MAP_PAGE_t* page, - uint32_t* aruser); - -/******************************************************************************/ -/*! - * Return the current write transaction mapping configuration used by the ACP ID - * Mapper for the specified output ID. - * - * If \e output_id is configured as a fixed mapping then \b true is returned in - * the \e fixed output parameter and the translation mapping options configured - * for that \e output_id are returned in the other output parameters. - * - * If \e output_id is configured as a dynamic mapping then \b false is returned - * in the \e fixed output parameter and the translation mapping options - * configured for all dynamically remapped output IDs are returned in the other - * output parameters. - * - * \param output_id - * The output ID to return the mapping configuration for. 0 <= \e - * output_id <= 7. - * - * \param fixed - * [out] Set to \b true if the specified \e output_id is a fixed ID - * mapping configuration. Set to \b false if the mapping - * configuration is dynamic. - * - * \param input_id - * [out] The input ID of the external master that a fixed ID - * mapping is applied to for the \e output_id. If \e fixed is \b - * false then this output parameter is set to 0 and its value - * should be considered as not applicable. - * - * \param page - * [out] The MPU address space page view used by the mapping - * configuration. - * - * \param awuser - * [out] The 5-bit AXI AWUSER write user sideband signal value used - * by the mapping configuration when masters are unable to drive - * the AXI user sideband signals. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_RESERVED The argument value is reserved or unavailable. - * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e - * output_id argument violates its range constraint. - */ -ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, - bool* fixed, - uint32_t* input_id, - ALT_ACP_ID_MAP_PAGE_t* page, - uint32_t* awuser); - -/*! @} */ - -/*! @} */ - -#endif /* __ASSEMBLY__ */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALT_ADDRESS_SPACE_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_cache.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_cache.h deleted file mode 100644 index 8d088ab744..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_cache.h +++ /dev/null @@ -1,964 +0,0 @@ -/****************************************************************************** - * - * Copyright 2013 Altera Corporation. All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - ******************************************************************************/ - -#ifndef __ALT_CACHE_H__ -#define __ALT_CACHE_H__ - -#include "hwlib.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! - * \addtogroup CACHE_MGR Cache Management API - * - * This module defines the cache management API for enabling and disabling L1 - * data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1 - * TLB cache, and L2 cache in the SoC. As well, many it allows users to perform - * cache maintenance operations on these caches. This includes the following - * operations: - * * Invalidate: Marks the cache line as being invalid, freeing up the space - * to cache other data. All APIs which enable caches invalidates the memory - * before being enabling the cache. - * * Clean: If the cache line is dirty, it synchronizes the cache line data - * with the upper level memory system and marks that line as clean. All APIs - * which disable caches cleans the memory before disabling the cache. - * * Purge: A term used in this API as a short form for clean and invalidate. - * This operation cleans and invalidates a cache line in that order, as a - * single command to the cache controller. - * - * The following reference materials were used in the design of this API: - * * ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition - * * Cortex™-A9 Technical Reference Manual - * * Cortex™-A9 MPCore Technical Reference Manual - * * CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference - * Manual - * - * @{ - */ - -/*! - * \addtogroup CACHE_SYS System Level Cache Management API - * - * This API group provides cache maintenance operations which affects multiple - * cache levels. - * - * The enable and disable functions enables and disables all caches in the - * system respectively. For caches shared by the CPU core(s), particularly the - * L2 cache, once that cache is enabled or disabled it will not be invalidated - * or cleaned again respectively. This allows the safe system-wide enable and - * disable to be used in single-core and multi-core scenarios. - * - * For cache maintenance operations, this API implements the procedures - * outlined in the L2C-310 Technical Reference Manual, section 3.3.10, - * subsection "System cache maintenance considerations". This allows for a - * convenient way to invalidate, clean, or clean and invalidate cache data from - * the L1 to L2 to L3 while avoiding any potential race conditions in - * mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is - * set in "non-exclusive" mode. This means a segment of data can reside in both - * the L1 and L2 simultaneously. This is the default mode for caches in the - * system. - * - * The current implementation of the system cache APIs assumes that the MMU is - * configured with a flat memory mapping or that every virtual address matches - * perfectly with the physical address. This restriction may be lifted in a - * future release of the cache API implementation. - * - * @{ - */ - -/*! - * Enables support for a non-flat virtual memory. A flat virtual memory is - * where every virtual address matches exactly to the physical address, making - * the virtual to physical translation trivial. Adding support for non-flat - * adds some overhead for the VA to PA translation and error detection. - * - * To enable non-flat virtual memory support, defined - * ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling - * HWLibs. - */ -#ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY -#define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0) -#endif - -/*! - * This is the system wide cache line size, given in bytes. - */ -#define ALT_CACHE_LINE_SIZE 32 - -/*! - * Enables all caches and features which improve reliability and speed on all - * cache controllers visible to the current CPU core. This includes parity - * error detection. Cache controllers visible to multiple CPU cores, for - * example the L2, will first be checked to be disabled before being enabled. - * All necessary cache maintenance operations will be done automatically. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_system_enable(void); - -/*! - * Disables all cache controllers visible to the current CPU core. Cache - * controllers visible to multiple CPU cores, for example the L2, will first - * be checked to be enabled before being disabled. All necessary cache - * maintenance operations will be done automatically. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_system_disable(void); - -/*! - * Invalidates the specified contents of all cache levels visible to the - * current CPU core for the given memory segment. - * - * The memory segment address and length specified must align to the - * characteristics of the cache line. This means the address and length must be - * multiples of the cache line size. To determine the cache line size, use the - * \b ALT_CACHE_LINE_SIZE macro. - * - * The following pseudocode outlines the operations carried out by this - * function: - * -# L2 invalidate address(es) - * -# L2 cache sync - * -# L1 invalidate address(es) - * -# DSB instruction - * - * The current implementation of the system cache APIs assumes that the MMU is - * configured with a flat memory mapping or that every virtual address matches - * perfectly with the physical address. This restriction may be lifted in a - * future release of the cache API implementation. - * - * \param vaddress - * The virtual address of the memory segment to be invalidated. - * - * \param length - * The length of the memory segment to be invalidated. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The memory segment is invalid. - * \retval ALT_E_TMO The memory operation timed out. - */ -ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length); - -/*! - * Cleans the specified contents of all cache levels visible to the current - * CPU core for the given memory segment. - * - * The memory segment address and length specified must align to the - * characteristics of the cache line. This means the address and length must be - * multiples of the cache line size. To determine the cache line size, use the - * \b ALT_CACHE_LINE_SIZE macro. - * - * The following pseudocode outlines the operations carried out by this - * function: - * -# L1 clean address(es) - * -# DSB instruction - * -# L2 clean address(es) - * -# L2 cache sync - * - * The current implementation of the system cache APIs assumes that the MMU is - * configured with a flat memory mapping or that every virtual address matches - * perfectly with the physical address. This restriction may be lifted in a - * future release of the cache API implementation. - * - * \param vaddress - * The virtual address of the memory segment to be cleaned. - * - * \param length - * The length of the memory segment to be cleaned. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The memory segment is invalid. - * \retval ALT_E_TMO The memory operation timed out. - */ -ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length); - -/*! - * Cleans and invalidates the specified contents of all cache levels visible - * to the current CPU core for the given memory segment. - * - * The memory segment address and length specified must align to the - * characteristics of the cache line. This means the address and length must be - * multiples of the cache line size. To determine the cache line size, use the - * \b ALT_CACHE_LINE_SIZE macro. - * - * The following pseudocode outlines the operations carried out by this - * function: - * -# L1 clean address(es) - * -# DSB instruction - * -# L2 clean and invalidate address(es) - * -# L2 cache sync - * -# L1 invalidate address(es) - * -# DSB instruction - * - * The current implementation of the system cache APIs assumes that the MMU is - * configured with a flat memory mapping or that every virtual address matches - * perfectly with the physical address. This restriction may be lifted in a - * future release of the cache API implementation. - * - * \param vaddress - * The virtual address of the memory segment to be purged. - * - * \param length - * The length of the memory segment to be purged. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The memory segment is invalid. - * \retval ALT_E_TMO The memory operation timed out. - */ -ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length); - -/*! - * @} - */ - -/*! - * \addtogroup CACHE_L1 L1 Cache Management API - * - * This API group provides functions to interact with various components of the - * L1 cache on the SoCFPGA. This includes the following cache components: - * * Instruction Cache - * * Data Cache - * * Parity error detection - * * Dynamic branch prediction - * * Data prefetching - * - * The API within this group only affects the L1 cache on the current CPU. To - * interact the L1 cache on another CPU, the API must be called from that other - * CPU. - * - * With respect to bring-up, the L1 and L2 cache controller setups are fully - * independent. The L2 can be setup at any time, before or after the L1 is setup. - * \internal - * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". - * \endinternal - * - * @{ - */ - -/*! - * Enables all L1 caches and features on the current CPU core. This includes - * the instruction cache, data cache, parity error detection, branch target - * address cache, global history buffer, and data prefetching. All necessary - * maintenance tasks will be taken care of. - * - * This function should not be mixed with other L1 cache related functions - * which enable or disable caches individually. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_enable_all(void); - -/*! - * Disables all L1 caches and features on the current CPU core. This includes - * the instruction cache, data cache, parity error detection, branch target - * address cache, global history buffer, and data prefetching. All necessary - * maintenance tasks will be taken care of. - * - * This function should not be mixed with other L1 cache related functions - * which enable or disable caches individually. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_disable_all(void); - -/*! - * Enables the L1 instruction cache on the current CPU core. If the cache is - * already enabled, nothing is done. Otherwise the instruction cache is first - * invalidated before being enabled. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_instruction_enable(void); - -/*! - * Disables the L1 instruction cache on the current CPU core. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_instruction_disable(void); - -/*! - * Returns \b true when the L1 instruction cache is enabled and \b false when - * it is disabled on the current CPU core. - * - * \retval true The L1 instruction cache is enabled. - * \retval false The L1 instruction cache is disabled. - */ -bool alt_cache_l1_instruction_is_enabled(void); - -/*! - * Invalidates the contents of the L1 instruction cache on the current CPU - * core. - * - * Normally this is done automatically as part of - * alt_cache_l1_instruction_enable(), but in certain circumstances it may be - * necessary to invalidate it manually. An example of this situation is when - * the address space is remapped and the processor executes instructions from - * the new memory area. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void); - -/*! - * Enables the L1 data cache on the current CPU core. - * - * If the cache is already enabled nothing is done. Otherwise the data cache is - * first invalidated before being enabled. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_data_enable(void); - -/*! - * Disables the L1 data cache on the current CPU core. - * - * If the cache is already disabled nothing is done. Otherwise the data cache - * is first cleaned before being disabled. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_data_disable(void); - -/*! - * Returns \b true when the L1 data cache is enabled and \b false when it is - * disabled on the current CPU core. - * - * \retval true The L1 data cache is enabled. - * \retval false The L1 data cache is disabled. - */ -bool alt_cache_l1_data_is_enabled(void); - -/*! - * Invalidates the specified contents of the L1 data cache on the current CPU - * core for the given memory segment. - * - * The memory segment address and length specified must align to the - * characteristics of the cache line. This means the address and length must be - * multiples of the cache line size. To determine the cache line size, use the - * \b ALT_CACHE_LINE_SIZE macro. - * - * \param vaddress - * The virtual address of the memory segment to be invalidated. - * - * \param length - * The length of the memory segment to be invalidated. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The memory segment is invalid. - */ -ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length); - -/*! - * Invalidates the entire contents of the L1 data cache on the current CPU - * core. - * - * Normally this is done automatically as part of alt_cache_l1_data_enable(), - * but in certain circumstances it may be necessary to invalidate it manually. - * An example of this situation is when the address space is remapped and the - * processor accesses memory from the new memory area. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void); - -/*! - * Cleans the specified contents of the L1 data cache on the current CPU core - * for the given memory segment. - * - * The memory segment address and length specified must align to the - * characteristics of the cache line. This means the address and length must be - * multiples of the cache line size. To determine the cache line size, use the - * \b ALT_CACHE_LINE_SIZE macro. - * - * \param vaddress - * The virtual address of the memory segment to be cleaned. - * - * \param length - * The length of the memory segment to be cleaned. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The memory segment is invalid. - */ -ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length); - -/*! - * Cleans the entire L1 data cache for the current CPU core. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_data_clean_all(void); - -/*! - * Cleans and invalidates the specified contents of the L1 data cache on the - * current CPU core for the given memory segment. - * - * The memory segment address and length specified must align to the - * characteristics of the cache line. This means the address and length must be - * multiples of the cache line size. To determine the cache line size, use the - * \b ALT_CACHE_LINE_SIZE macro. - * - * Normally this is done automatically as part of alt_cache_l1_data_disable(), - * but in certain circumstances it may be necessary to purged it manually. - * An example of this situation is when the address space is remapped and the - * processor accesses memory from the new memory area. - * - * \param vaddress - * The virtual address of the memory segment to be purged. - * - * \param length - * The length of the memory segment to be purged. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The memory segment is invalid. - */ -ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length); - -/*! - * Cleans and invalidates the entire L1 data cache for the current CPU core. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_data_purge_all(void); - -/*! - * Enables the parity error detection feature in the L1 caches on the current - * CPU core. - * - * Ideally parity should be enabled before any L1 caches are enabled. If the - * instruction, data, and / or dynamic branch predictor caches are already - * enabled, they will first be cleaned (if needed) and disabled before parity - * is enabled in hardware. Afterwards, the affected caches will be invalidated - * and enabled. - * - * Parity and TLB interaction deserves special attention. The TLB is considered - * to be a L1 cache but is enabled when the MMU, which is grouped in another - * API, is enabled. Due to the system-wide influence of the MMU, it cannot be - * disabled and enabled with impunity as the other L1 caches, which are - * designed to operate as transparently as possible. Thus parity error - * detection must be enabled before the L1 TLB cache, and by extension the MMU, - * is enabled. - * - * For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt - * for the current CPU core must be enabled using the interrupt controller API. - * For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error - * is detected while the other PARITYFAIL interrupts are for parity errors in a - * specific memory. Refer to the interrupt controller API for more details - * about programming the interrupt controller. - * - * In the event of a parity error is detected, the appropriate CPU parity - * interrupt will be raised. CPU parity interrupts are all edge triggered and - * are cleared by acknowledging them in the interrupt controller API. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_parity_enable(void); - -/*! - * Disables parity error detection in the L1 caches. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_parity_disable(void); - -/*! - * Returns \b true when parity error detection is enabled and \b false when it - * is disabled on the current CPU core. - * - * \retval true Parity error detection for L1 caches is - * enabled. - * \retval false Parity error detection for L1 caches is - * disabled. - */ -bool alt_cache_l1_parity_is_enabled(void); - -/*! - * Enables the dynamic branch predictor features on the current CPU core. - * - * This operation enables both the Branch Target Address Cache (BTAC) and - * the Global History Buffer (GHB). Affected caches are automatically - * invalidated before use. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_branch_enable(void); - -/*! - * Disables the dynamic branch predictor features on the current CPU core. - * - * This operation disables both the Branch Target Address Cache (BTAC) and - * the Global History Buffer (GHB). - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_branch_disable(void); - -/*! - * Returns \b true when both the dynamic predictor features are enabled and - * \b false when they are disabled on the current CPU core. - * - * \retval true The L1 branch predictor caches are all enabled. - * \retval false Some or all L1 branch predictor caches are - * disabled. - */ -bool alt_cache_l1_branch_is_enabled(void); - -/*! - * Invalidates the dynamic branch predictor feature caches on the current CPU - * core. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void); - -/*! - * Enables the L1 cache data prefetch feature on the current CPU core. - * - * This allows data to be prefetched into the data cache before it is to be - * used. For example in a loop the current iteration may want to preload the - * data which will be used in the next teration. This is done by using the PLD - * instructions. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void); - -/*! - * Disables the L1 cache data prefetch feature on the current CPU core. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void); - -/*! - * Returns \b true if the L1 cache data prefetch feature is enabled and - * \b false if it is disabled on the current CPU core. - * - * \retval true The L1 data cache prefetch feature is enabled. - * \retval false The L1 data cache prefetch feature is disabled. - */ -bool alt_cache_l1_prefetch_is_enabled(void); - -/*! - * @} - */ - -/*! - * \addtogroup CACHE_L2 L2 Cache Management API - * - * This API group provides functions to interact with various features of the - * L2 cache on the SoCFPGA. This includes the following features: - * * L2 cache - * * Parity error detection - * * Data prefetching - * * Interrupt Management - * - * \internal - * Additional features that may be implemented in the future: - * * Lockdown - * * Event counter - * \endinternal - * - * The API within this group affects the L2 cache which is visible to all CPUs - * on the system. - * - * With respect to bring-up, the L1 and L2 cache controller setups are fully - * independent. The L2 can be setup at any time, before or after the L1 is setup. - * \internal - * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up". - * \endinternal - * - * @{ - */ - -/*! - * Initializes the L2 cache controller. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_cache_l2_init(void); - -/*! - * Uninitializes the L2 cache controller. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_cache_l2_uninit(void); - -/*! - * Enables the L2 cache features for data and instruction prefetching. - * - * Prefetching can be enabled or disabled while the L2 cache is enabled. - * \internal - * Source: Use the Prefetch Control Register. - * \endinternal - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void); - -/*! - * Disables the L2 cache features for data and instruction prefetching. - * - * Prefetching can be enabled or disabled while the L2 cache is enabled. - * \internal - * Source: Use the Prefetch Control Register. - * \endinternal - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void); - -/*! - * Returns \b true if either L2 cache data or instruction prefetch features are - * enabled and \b false if no prefetching features are enabled. - * - * \retval true The L2 data and instruction prefetch features - * are enabled. - * \retval false Some L2 data and instruction prefetch features - * are disabled. - */ -bool alt_cache_l2_prefetch_is_enabled(void); - -/*! - * Enables parity error detection in the L2 cache. - * - * Ideally parity should be enabled before the L2 cache is enabled. If the - * cache is already enabled, it will first be cleaned and disabled before - * parity is enabled in hardware. Afterwards, the cache will be invalidated and - * enabled. - * - * For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or - * ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is - * done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt - * must be enabled using the interrupt controller API. Refer to the interrupt - * controller API for more details about programming the interrupt controller. - * - * In the event of a parity error is detected, the appropriate L2 cache parity - * interrupt will be raised. To clear the parity interrupt(s), the appropriate - * L2 cache parity interrupt must be cleared by calling - * alt_cache_l2_int_status_clear(). - * - * For ECC support, refer to the ECC related API documentation for more - * information. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l2_parity_enable(void); - -/*! - * Disables parity error detection in the L2 cache. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l2_parity_disable(void); - -/*! - * Returns \b true when parity error detection is enabled and \b false when it - * is disabled. - * - * \retval true The L2 cache parity error detection feature is - * enabled. - * \retval false The L2 cache parity error detection feature is - * disabled. - */ -bool alt_cache_l2_parity_is_enabled(void); - -/*! - * Enables the L2 cache. - * - * If the L2 cache is already enabled, nothing is done. Otherwise the entire - * contents of the cache is first invalidated before being enabled. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l2_enable(void); - -/*! - * Disables the L2 cache. - * - * If the L2 cache is already disabled, nothing is done. Otherwise the entire - * contents of the cache is first cleaned before being disabled. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l2_disable(void); - -/*! - * Returns \b true when the L2 cache is enabled and \b false when it is - * disabled. - * - * \retval true The L2 cache is enabled. - * \retval false The L2 cache is disabled. - */ -bool alt_cache_l2_is_enabled(void); - -/*! - * Flushes the L2 cache controller hardware buffers. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_TMO The memory operation timed out. - */ -ALT_STATUS_CODE alt_cache_l2_sync(void); - -/*! - * Invalidates the specified contents of the L2 cache for the given memory - * segment. - * - * The memory segment address and length specified must align to the - * characteristics of the cache line. This means the address and length must be - * multiples of the cache line size. To determine the cache line size, use the - * \b ALT_CACHE_LINE_SIZE macro. - * - * \param paddress - * The physical address of the memory segment to be invalidated. - * - * \param length - * The length of the memory segment to be invalidated. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The memory segment is invalid. - * \retval ALT_E_TMO The memory operation timed out. - */ -ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length); - -/*! - * Invalidates th entire contents of the L2 cache. - * - * Normally this is done automatically as part of alt_cache_l2_enable(), but - * in certain circumstances it may be necessary to invalidate it manually. An - * example of this situation is when the address space is remapped and the - * processor accesses memory from the new memory area. - - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_TMO The memory operation timed out. - */ -ALT_STATUS_CODE alt_cache_l2_invalidate_all(void); - -/*! - * Cleans the specified contents of the L2 cache for the given memory segment. - * - * The memory segment address and length specified must align to the - * characteristics of the cache line. This means the address and length must be - * multiples of the cache line size. To determine the cache line size, use the - * \b ALT_CACHE_LINE_SIZE macro. - * - * \param paddress - * The physical address of the memory segment to be cleaned. - * - * \param length - * The length of the memory segment to be cleaned. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The memory segment is invalid. - * \retval ALT_E_TMO The memory operation timed out. - */ -ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length); - -/*! - * Cleans the entire L2 cache. All L2 cache controller interrupts will be - * temporarily disabled while the clean operation is in progress and restored - * once the it is finished. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_TMO The memory operation timed out. - */ -ALT_STATUS_CODE alt_cache_l2_clean_all(void); - -/*! - * Cleans and invalidates the specified contents of the L2 cache for the - * given memory segment. - * - * The memory segment address and length specified must align to the - * characteristics of the cache line. This means the address and length must be - * multiples of the cache line size. To determine the cache line size, use the - * \b ALT_CACHE_LINE_SIZE macro. - * - * \param paddress - * The physical address of the memory segment to be purged. - * - * \param length - * The length of the memory segment to be purged. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The memory segment is invalid. - */ -ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length); - -/*! - * Cleans and invalidates the entire L2 cache. All L2 cache controller - * interrupts will be temporarily disabled while the clean and invalidate - * operation is in progress and restored once the it is finished. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_TMO The memory operation timed out. - */ -ALT_STATUS_CODE alt_cache_l2_purge_all(void); - -/*! - * This type definition enumerates all the interrupt conditions that can be - * generated by the L2 cache controller as register mask values. - */ -enum ALT_CACHE_L2_INTERRUPT_e -{ - /*! Decode error received on the master ports from L3. */ - ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8, - - /*! Slave error received on the master ports from L3. */ - ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7, - - /*! Error on the L2 data RAM read. */ - ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6, - - /*! Error on the L2 tag RAM read. */ - ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5, - - /*! Error on the L2 data RAM write. */ - ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4, - - /*! Error on the L2 tag RAM write. */ - ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3, - - /*! Parity error on the L2 data RAM read. */ - ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2, - - /*! Parity error on the L2 tag RAM read. */ - ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1, - - /*! Event counter overflow or increment. */ - ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0 -}; -typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t; - -/*! - * Enables the L2 cache controller interrupts for the specified set of - * condition(s). - * - * \param interrupt - * A register mask of the selected L2 cache controller - * interrupting conditions. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt); - -/*! - * Disables the L2 cache controller interrupts for the specified set of - * condition(s). - * - * \param interrupt - * A register mask of the selected L2 cache controller - * interrupting conditions. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt); - -/*! - * Gets the condition(s) causing the L2 cache controller to interrupt as a - * register mask. - * - * \returns A register mask of the currently asserted and enabled - * conditions resulting in an interrupt being generated. - */ -uint32_t alt_cache_l2_int_status_get(void); - -/*! - * Clears the specified conditon(s) causing the L2 cache controller to - * interrupt as a mask. Condition(s) specified which are not causing an - * interrupt or condition(s) specified which are not enabled are ignored. - * - * \param interrupt - * A register mask of the selected L2 cache controller - * interrupting conditions. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt); - -/*! - * @} - */ - -/*! - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_CACHE_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h deleted file mode 100644 index a43608e9f3..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h +++ /dev/null @@ -1,114 +0,0 @@ -/****************************************************************************** - * - * Copyright 2013 Altera Corporation. All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - ******************************************************************************/ - -/*! - * \file - * - * Contains the definition of an opaque data structure that contains raw - * configuration information for a clock group. - */ - -#ifndef __ALT_CLK_GRP_H__ -#define __ALT_CLK_GRP_H__ - -#include "hwlib.h" -#include "socal/alt_clkmgr.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/*! - * This type definition enumerates the clock groups - */ -typedef enum ALT_CLK_GRP_e -{ - ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ - - ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ - - ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ - -} ALT_CLK_GRP_t; - -/*! - * This type definition defines an opaque data structure for holding the - * configuration settings for a complete clock group. - */ -typedef struct ALT_CLK_GROUP_RAW_CFG_s -{ - uint32_t verid; /*!< SoC FPGA version identifier. This field - * encapsulates the silicon identifier and - * version information associated with this - * clock group configuration. It is used to - * assert that this clock group configuration - * is valid for this device. */ - - uint32_t siliid2; /*!< Reserved register - reserved for future - * device IDs or capability flags. */ - - ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */ - - /*! - * This union holds the register values for configuration of the set of - * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator - * identifies the valid clock group union data member. - */ - union ALT_CLK_GROUP_RAW_CFG_u - { - /*! Clock group configuration for Main PLL group. */ - union - { - ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */ - ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */ - } mainpllgrp; - - /*! Clock group configuration for Peripheral PLL group. */ - union - { - ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */ - ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */ - } perpllgrp; - - /*! Clock group configuration for SDRAM PLL group. */ - union - { - ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */ - ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */ - } sdrpllgrp; - - } clkgrp; -} ALT_CLK_GROUP_RAW_CFG_t; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALT_CLK_GRP_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h deleted file mode 100644 index d6d96544f7..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h +++ /dev/null @@ -1,1434 +0,0 @@ -/*! \file - * Contains definitions for the Altera Hardware Libraries Clock Manager - * Application Programming Interface - */ - -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ALT_CLK_MGR_H__ -#define __ALT_CLK_MGR_H__ - -#include "hwlib.h" -#include "alt_clock_group.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/*! \addtogroup CLK_MGR The Clock Manager API - * - * This module defines the Clock Manager API for accessing, configuring, and - * controlling the HPS clock resources. - * - * @{ - */ - -/******************************************************************************/ -/*! - * This type definition is an opaque type definition for clock frequency values - * in Hz. - */ -typedef uint32_t alt_freq_t; - -/******************************************************************************/ -/*! - * This type definition enumerates the names of the clock and PLL resources - * managed by the Clock Manager. - */ -typedef enum ALT_CLK_e -{ - /* Clock Input Pins */ - ALT_CLK_IN_PIN_OSC1, - /*!< \b OSC_CLK_1_HPS - * External oscillator input: - * * Input Pin - * * Clock source to Main PLL - * * Clock source to SDRAM PLL - * and Peripheral PLL if selected via - * register write - * * Clock source for clock in safe mode - */ - - ALT_CLK_IN_PIN_OSC2, - /*!< \b OSC_CLK_2_HPS - * External Oscillator input: - * * Input Pin - * * Optional clock source to SDRAM PLL - * and Peripheral PLL if selected - * * Typically used for Ethernet - * reference clock - */ - - - /* FPGA Clock Sources External to HPS */ - ALT_CLK_F2H_PERIPH_REF, - /*<! Alternate clock source from FPGA - * for HPS Peripheral PLL. */ - - ALT_CLK_F2H_SDRAM_REF, - /*<! Alternate clock source from FPGA - * for HPS SDRAM PLL. */ - - - /* Other Clock Sources External to HPS */ - ALT_CLK_IN_PIN_JTAG, - /*!< \b JTAG_TCK_HPS - * * Input Pin - * * External HPS JTAG clock input. - */ - - ALT_CLK_IN_PIN_ULPI0, - /*!< \b ULPI0_CLK - * ULPI Clock provided by external USB0 - * PHY - * * Input Pin - */ - - ALT_CLK_IN_PIN_ULPI1, - /*!< \b ULPI1_CLK - * ULPI Clock provided by external USB1 - * PHY - * * Input Pin - */ - - ALT_CLK_IN_PIN_EMAC0_RX, - /*!< \b EMAC0:RX_CLK - * Rx Reference Clock for EMAC0 - * * Input Pin - */ - - ALT_CLK_IN_PIN_EMAC1_RX, - /*!< \b EMAC1:RX_CLK - * Rx Reference Clock for EMAC1 - * * Input Pin - */ - - - /* PLLs */ - ALT_CLK_MAIN_PLL, - /*!< \b main_pll_ref_clkin - * Main PLL input reference clock, - * used to designate the Main PLL in - * PLL clock selections. - */ - - ALT_CLK_PERIPHERAL_PLL, - /*!< \b periph_pll_ref_clkin - * Peripheral PLL input reference - * clock, used to designate the - * Peripheral PLL in PLL clock - * selections. - */ - - ALT_CLK_SDRAM_PLL, - /*!< \b sdram_pll_ref_clkin - * SDRAM PLL input reference clock, - * used to designate the SDRAM PLL in - * PLL clock selections. - */ - - /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived - * directly from the osc_clk_1_HPS pin */ - ALT_CLK_OSC1, - /*!< \b osc1_clk - * OSC1 Clock Group - The - * OSC1 clock group contains - * those clocks which are - * derived directly from the - * osc_clk_1_HPS pin. - * * alias for ALT_CLK_IN_PIN_OSC1 - */ - - /* Main Clock Group - The following clocks are derived from the Main PLL. */ - ALT_CLK_MAIN_PLL_C0, - /*!< \b Main PLL C0 Output */ - - ALT_CLK_MAIN_PLL_C1, - /*!< \b Main PLL C1 Output */ - - ALT_CLK_MAIN_PLL_C2, - /*!< \b Main PLL C2 Output */ - - ALT_CLK_MAIN_PLL_C3, - /*!< \b Main PLL C3 Output */ - - ALT_CLK_MAIN_PLL_C4, - /*!< \b Main PLL C4 Output */ - - ALT_CLK_MAIN_PLL_C5, - /*!< \b Main PLL C5 Output */ - - ALT_CLK_MPU, - /*!< \b mpu_clk - * Main PLL C0 Output. Clock for MPU - * subsystem, including CPU0 and CPU1. - * * Alias for \e ALT_CLK_MAIN_PLL_C0 - */ - - ALT_CLK_MPU_L2_RAM, - /*!< \b mpu_l2_ram_clk - * Clock for MPU level 2 (L2) RAM - */ - - ALT_CLK_MPU_PERIPH, - /*!< \b mpu_periph_clk - * Clock for MPU snoop control unit - * (SCU) peripherals, such as the - * general interrupt controller (GIC) - */ - - ALT_CLK_L3_MAIN, - /*!< \b main_clk - * Main PLL C1 Output - * * Alias for \e ALT_CLK_MAIN_PLL_C1 - */ - - ALT_CLK_L3_MP, - /*!< \b l3_mp_clk - * Clock for L3 Master Peripheral Switch - */ - - ALT_CLK_L3_SP, - /*!< \b l3_sp_clk - * Clock for L3 Slave Peripheral Switch - */ - - ALT_CLK_L4_MAIN, - /*!< \b l4_main_clk - * Clock for L4 main bus - * * Clock for DMA - * * Clock for SPI masters - */ - - ALT_CLK_L4_MP, - /*!< \b l4_mp_clk - * Clock for L4 master peripherals (MP) bus - */ - - ALT_CLK_L4_SP, - /*!< \b l4_sp_clk - * Clock for L4 slave peripherals (SP) bus - */ - - ALT_CLK_DBG_BASE, - /*!< \b dbg_base_clk - * Main PLL C2 Output - * * Alias for \e ALT_CLK_MAIN_PLL_C2 - */ - - ALT_CLK_DBG_AT, - /*!< \b dbg_at_clk - * Clock for CoreSight debug Advanced - * Microcontroller Bus Architecture - * (AMBA) Trace Bus (ATB) - */ - - ALT_CLK_DBG_TRACE, - /*!< \b dbg_trace_clk - * Clock for CoreSight debug Trace - * Port Interface Unit (TPIU) - */ - - ALT_CLK_DBG_TIMER, - /*!< \b dbg_timer_clk - * Clock for the trace timestamp - * generator - */ - - ALT_CLK_DBG, - /*!< \b dbg_clk - * Clock for Debug Access Port (DAP) - * and debug Advanced Peripheral Bus - * (APB) - */ - - ALT_CLK_MAIN_QSPI, - /*!< \b main_qspi_clk - * Main PLL C3 Output. Quad SPI flash - * internal logic clock. - * * Alias for \e ALT_CLK_MAIN_PLL_C3 - */ - - ALT_CLK_MAIN_NAND_SDMMC, - /*!< \b main_nand_sdmmc_clk - * Main PLL C4 Output. Input clock to - * flash controller clocks block. - * * Alias for \e ALT_CLK_MAIN_PLL_C4 - */ - - ALT_CLK_CFG, - /*!< \b cfg_clk - * FPGA manager configuration clock. - */ - - ALT_CLK_H2F_USER0, - /*!< \b h2f_user0_clock - * Clock to FPGA fabric - */ - - - /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */ - ALT_CLK_PERIPHERAL_PLL_C0, - /*!< \b Peripheral PLL C0 Output */ - - ALT_CLK_PERIPHERAL_PLL_C1, - /*!< \b Peripheral PLL C1 Output */ - - ALT_CLK_PERIPHERAL_PLL_C2, - /*!< \b Peripheral PLL C2 Output */ - - ALT_CLK_PERIPHERAL_PLL_C3, - /*!< \b Peripheral PLL C3 Output */ - - ALT_CLK_PERIPHERAL_PLL_C4, - /*!< \b Peripheral PLL C4 Output */ - - ALT_CLK_PERIPHERAL_PLL_C5, - /*!< \b Peripheral PLL C5 Output */ - - ALT_CLK_USB_MP, - /*!< \b usb_mp_clk - * Clock for USB - */ - - ALT_CLK_SPI_M, - /*!< \b spi_m_clk - * Clock for L4 SPI master bus - */ - - ALT_CLK_QSPI, - /*!< \b qspi_clk - * Clock for Quad SPI - */ - - ALT_CLK_NAND_X, - /*!< \b nand_x_clk - * NAND flash controller master and - * slave clock - */ - - ALT_CLK_NAND, - /*!< \b nand_clk - * Main clock for NAND flash - * controller - */ - - ALT_CLK_SDMMC, - /*!< \b sdmmc_clk - * Clock for SD/MMC logic input clock - */ - - ALT_CLK_EMAC0, - /*!< \b emac0_clk - * EMAC 0 clock - Peripheral PLL C0 - * Output - * * Alias for \e ALT_CLK_PERIPHERAL_PLL_C0 - */ - - ALT_CLK_EMAC1, - /*!< \b emac1_clk - * EMAC 1 clock - Peripheral PLL C1 - * Output - * * Alias for \e ALT_CLK_PERIPHERAL_PLL_C1 - */ - - ALT_CLK_CAN0, - /*!< \b can0_clk - * Controller area network (CAN) - * controller 0 clock - */ - - ALT_CLK_CAN1, - /*!< \b can1_clk - * Controller area network (CAN) - * controller 1 clock - */ - - ALT_CLK_GPIO_DB, - /*!< \b gpio_db_clk - * Debounce clock for GPIO0, GPIO1, - * and GPIO2 - */ - - ALT_CLK_H2F_USER1, - /*!< \b h2f_user1_clock - * Clock to FPGA fabric - Peripheral - * PLL C5 Output - * * Alias for \e ALT_CLK_PERIPHERAL_PLL_C5 - */ - - - /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */ - ALT_CLK_SDRAM_PLL_C0, - /*!< \b SDRAM PLL C0 Output */ - - ALT_CLK_SDRAM_PLL_C1, - /*!< \b SDRAM PLL C1 Output */ - - ALT_CLK_SDRAM_PLL_C2, - /*!< \b SDRAM PLL C2 Output */ - - ALT_CLK_SDRAM_PLL_C3, - /*!< \b SDRAM PLL C3 Output */ - - ALT_CLK_SDRAM_PLL_C4, - /*!< \b SDRAM PLL C4 Output */ - - ALT_CLK_SDRAM_PLL_C5, - /*!< \b SDRAM PLL C5 Output */ - - ALT_CLK_DDR_DQS, - /*!< \b ddr_dqs_clk - * Clock for MPFE, single-port - * controller, CSR access, and PHY - - * SDRAM PLL C0 Output - * * Alias for \e ALT_CLK_SDRAM_PLL_C0 - */ - - ALT_CLK_DDR_2X_DQS, - /*!< \b ddr_2x_dqs_clk - * Clock for PHY - SDRAM PLL C1 Output - * * Alias for \e ALT_CLK_SDRAM_PLL_C1 - */ - - ALT_CLK_DDR_DQ, - /*!< \b ddr_dq_clk - * Clock for PHY - SDRAM PLL C2 Output - * * Alias for \e ALT_CLK_SDRAM_PLL_C2 - */ - - ALT_CLK_H2F_USER2, - /*!< \b h2f_user2_clock - * Clock to FPGA fabric - SDRAM PLL C5 - * Output - * * Alias for \e ALT_CLK_SDRAM_PLL_C5 - */ - - /* Clock Output Pins */ - ALT_CLK_OUT_PIN_EMAC0_TX, - /*!< \b EMAC0:TX_CLK - * Tx Reference Clock for EMAC0 - * * Output Pin - */ - - ALT_CLK_OUT_PIN_EMAC1_TX, - /*!< \b EMAC1:TX_CLK - * Tx Reference Clock for EMAC1 - * * Output Pin - */ - - ALT_CLK_OUT_PIN_SDMMC, - /*!< \b SDMMC:CLK - * SD/MMC Card Clock - * * Output Pin - */ - - ALT_CLK_OUT_PIN_I2C0_SCL, - /*!< \b I2C0:SCL - * I2C Clock for I2C0 - * * Output Pin - */ - - ALT_CLK_OUT_PIN_I2C1_SCL, - /*!< \b I2C1:SCL - * I2C Clock for I2C1 - * * Output Pin - */ - - ALT_CLK_OUT_PIN_I2C2_SCL, - /*!< \b I2C2:SCL - * I2C Clock for I2C2/2 wire - * * Output Pin - */ - - ALT_CLK_OUT_PIN_I2C3_SCL, - /*!< \b I2C3:SCL - * I2C Clock for I2C1/2 wire - * * Output Pin - */ - - ALT_CLK_OUT_PIN_SPIM0, - /*!< \b SPIM0:CLK - * SPI Clock - * * Output Pin - */ - - ALT_CLK_OUT_PIN_SPIM1, - /*!< \b SPIM1:CLK - * SPI Clock - * * Output Pin - */ - - ALT_CLK_OUT_PIN_QSPI, - /*!< \b QSPI:CLK - * QSPI Flash Clock - * * Output Pin - */ - - ALT_CLK_UNKNOWN -} ALT_CLK_t; - -/******************************************************************************/ -/*! \addtogroup CLK_MGR_STATUS Clock Manager Status - * - * This functional group provides status information on various aspects and - * properties of the Clock Manager state. - * - * @{ - */ -/******************************************************************************/ -/*! - * This type definition defines the lock condition status codes for each of the - * PLLs. If the PLL lock status condition is enabled (See: alt_clk_irq_enable()) - * then it contributes to the overall \b clkmgr_IRQ signal assertion state. - */ -typedef enum ALT_CLK_PLL_LOCK_STATUS_e -{ - ALT_MAIN_PLL_LOCK_ACHV = 0x00000001, /*!< This condition is set if the Main - * PLL has achieved lock at least once - * since this condition was last - * cleared. - */ - ALT_PERIPH_PLL_LOCK_ACHV = 0x00000002, /*!< This condition is set if the Peripheral - * PLL has achieved lock at least once - * since this condition was last - * cleared. - */ - ALT_SDR_PLL_LOCK_ACHV = 0x00000004, /*!< This condition is set if the SDRAM - * PLL has achieved lock at least once - * since this condition was last - * cleared. - */ - ALT_MAIN_PLL_LOCK_LOST = 0x00000008, /*!< This condition is set if the Main - * PLL has lost lock at least once - * since this condition was last - * cleared. - */ - ALT_PERIPH_PLL_LOCK_LOST = 0x00000010, /*!< This condition is set if the Peripheral - * PLL has lost lock at least once - * since this condition was last - * cleared. - */ - ALT_SDR_PLL_LOCK_LOST = 0x00000020 /*!< This condition is set if the SDRAM - * PLL has lost lock at least once - * since this condition was last - * cleared. - */ -} ALT_CLK_PLL_LOCK_STATUS_t; - -/******************************************************************************/ -/*! - * Clear the selected PLL lock status conditions. - * - * This function clears assertions of one or more of the PLL lock status - * conditions. - * - * NOTE: This function is used to clear \b clkmgr_IRQ interrupt signal source - * assertion conditions. - * - * \param lock_stat_mask - * Specifies the PLL lock status conditions to clear. \e lock_stat_mask - * is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t - * values designating the PLL lock conditions to clear. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an - * unknown condition value. - */ -ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask); - -/******************************************************************************/ -/*! - * Returns the PLL lock status condition values. - * - * This function returns the value of the PLL lock status conditions. - * - * \returns The current values of the PLL lock status conditions as defined by - * the \ref ALT_CLK_PLL_LOCK_STATUS_t mask bits. If the corresponding bit is set - * then the condition is asserted. - */ -uint32_t alt_clk_lock_status_get(void); - -/******************************************************************************/ -/*! - * Returns ALT_E_TRUE if the designated PLL is currently locked and ALT_E_FALSE - * otherwise. - * - * \param pll - * The PLL to return the lock status of. - * - * \retval ALT_E_TRUE The specified PLL is currently locked. - * \retval ALT_E_FALSE The specified PLL is currently not locked. - * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock - * value. - * \internal - * NOTE: This function uses the - * * \b hps::clkmgr::inter::mainplllocked - * * \b hps::clkmgr::inter::perplllocked, - * * \b hps::clkmgr::inter::sdrplllocked - * - * bits to determine if the PLL is locked or not. - * \endinternal - */ -ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup CLK_MGR_SAFE_MODE Safe Mode Options - * - * When safe mode is enabled, clocks in the HPS are directly generated from the - * \b osc1_clk clock. Safe mode is enabled by the assertion of a safe mode - * request from the reset manager or by a cold reset. Assertion of the safe mode - * request from the reset manager sets the safe mode bit in the clock manager - * control register. No other control register bits are affected by the safe - * mode request from the reset manager. - * - * While in safe mode, clock manager register settings which control clock - * behavior are not changed. However, the output of the registers which control - * the clock manager state are forced to the safe mode values such that the - * following conditions occur: - * * All PLLs are bypassed to the \b osc1_clk clock, including their counters. - * * Clock dividers select their default reset values. - * * The flash controllers source clock selections are set to the peripheral - * PLL. - * * All clocks are enabled. - * * Safe mode is optionally applied to debug clocks. - * - * A write by software is the only way to clear the safe mode bit. All registers - * and clocks need to be configured correctly and all software-managed clocks - * need to be gated off before clearing safe mode. Software can then gate clocks - * on as required. - * - * On cold reset, all clocks are put in safe mode. - * - * On warm reset, safe mode is optionally and independently applied to debug - * clocks and normal (i.e.non-debug) clocks based on clock manager register - * settings. The default response for warm reset is to put all clocks in safe - * mode. - * - * The APIs in this group provide control of the Clock Manager safe mode warm - * reset response behavior. - * @{ - */ - -/******************************************************************************/ -/*! - * This type definition enumerates the safe mode clock domains under control of - * the Clock Manager. - */ -typedef enum ALT_CLK_SAFE_DOMAIN_e -{ - /*! - * This enumeration literal specifies the normal safe mode domain. The - * normal domain consists of all clocks except debug clocks. - */ - ALT_CLK_DOMAIN_NORMAL, - /*! - * This enumeration literal specifies the debug safe mode domain. The debug - * domain consists of all debug clocks. - */ - ALT_CLK_DOMAIN_DEBUG -} ALT_CLK_SAFE_DOMAIN_t; - -/******************************************************************************/ -/*! - * Clear the safe mode status of the Clock Manager following a reset. - * - * NOTE: Safe mode should only be cleared once clocks have been correctly - * configured. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_clk_safe_mode_clear(void); - -/******************************************************************************/ -/*! - * Return whether the specified safe mode clock domain is in safe mode or not. - * - * \param clk_domain - * The safe mode clock domain to check whether in safe mode or not. - * - * \retval TRUE The safe mode clock domain is in safe mode. - * \retval FALSE The safe mode clock domain is not in safe mode. - */ -bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup CLK_MGR_BYPASS PLL Bypass Control - * - * When a PLL is in bypass, the PLL clock logic is kept in reset. In this - * manner, the PLL clock can be free running while it stabilizes and achieves - * lock. The bypass logic isolates PLL configuration registers from the clock - * while changes are made to the PLL settings. - * - * The bypass controls are used by software to change the source clock input - * reference (for Peripheral and SDRAM PLLs) and is recommended when changing - * settings that may affect the ability of the VCO to maintain lock. When a PLL - * is taken in or out of bypass the PLL output clocks will pause momentarily - * while the clocks are in transition, There will be no glitches or clocks - * shorter than the either the old or the new clock period. - * - * In summary, the PLL bypass controls permit: - * * Each PLL to be individually bypassed. - * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs - * reference clock input source reference clock selection. - * * Isolation of a the PLL VCO frequency registers (multiplier and divider), - phase shift registers (negative phase) , and post scale counters. - * * Glitch free clock transitions. - * @{ - */ -/******************************************************************************/ -/*! - * Disable bypass mode for the specified PLL. This operation takes the PLL out - * of bypass mode. - * - * \param pll - * The PLL to take out of bypass mode. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock - * value. - */ -ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll); - -/******************************************************************************/ -/*! - * Enable bypass mode for the specified PLL. - * - * \param pll - * The PLL to put into bypass mode. - * - * \param use_input_mux - * If TRUE then use the PLLs reference clock input source selection - * to directly drive the bypass clock. If FALSE then use bypass - * clock directly driven by the \b osc1_clk. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL - * clock value. - * \retval ALT_E_INV_OPTION TRUE is an invalid option for - * \e use_input_mux with the \e pll selection. - */ -ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, - bool use_input_mux); - -/******************************************************************************/ -/*! - * Return whether the specified PLL is in bypass or not. - * - * \internal - * This function must also test the \b clkmgr.ctrl.safemode bit in - * addition to the PLLs bypass bit to tell whether the bypass mode is - * effect or not. - * \endinternal - * - * \param pll - * The PLL to check whether in bypass mode or not. - * - * \retval ALT_E_TRUE The PLL is in bypass mode. - * \retval ALT_E_FALSE The PLL is not in bypass mode. - * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock - * value. - */ -ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup CLK_MGR_GATE Clock Gating Control - * - * This functional group provides gating control of selected clock signals. - * - * When a clock is enabled, then its clock signal propogates to its respective - * clocked IP block(s). When a clock is disabled, then its clock signal is - * prevented from propogating to its respective clocked IP block(s). - * - * The following clocks may be gated: - * - * * Main PLL Group - * - l4_main_clk - * - l3_mp_clk - * - l4_mp_clk - * - l4_sp_clk - * - dbg_at_clk - * - dbg_clk - * - dbg_trace_clk - * - dbg_timer_clk - * - cfg_clk - * - s2f_user0_clk - * - * * SDRAM PLL Group - * - ddr_dqs_clk - * - ddr_2x_clk - * - ddr_dq_clk - * - s2f_user2_clk - * - * * Peripheral PLL Group - * - emac0_clk - * - emac1_clk - * - usb_mp_clk - * - spi_m_clk - * - can0_clk - * - can1_clk - * - gpio_db_clk - * - s2f_user1_clk - * - sdmmc_clk - * - nand_clk - * - nand_x_clk - * - qspi_clk - * - * @{ - */ -/******************************************************************************/ -/*! - * Disable the specified clock. Once the clock is disabled, its clock signal does - * not propogate to its clocked elements. - * - * \param clk - * The clock to disable. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock - * value. - */ -ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk); - -/******************************************************************************/ -/*! - * Enable the specified clock. Once the clock is enabled, its clock signal - * propogates to its elements. - * - * \param clk - * The clock to enable. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock - * value. - */ -ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk); - -/******************************************************************************/ -/*! - * Return whether the specified clock is enabled or not. - * - * \param clk - * The clock to check whether enabled or not. - * - * \retval ALT_E_TRUE The clock is enabled. - * \retval ALT_E_FALSE The clock is not enabled. - * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock - * value. - */ -ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup CLK_MGR_CLK_SEL Clock Source Selection - * - * This API group provide access and control to the input reference clock source - * selection for a clock or PLL. - * - * \internal - * These are the clocks that have software configurable input reference clock - * source selection available. Each clock below is listed with its valid - * input reference clock source selections. - * - * + Valid reference clock input selections for \b sdram_pll_ref_clkin - * - osc_clk_1 - * - osc_clk_2 - * - f2h_sdram_ref_clk - * - * + Valid reference clock input selections for \b periph_pll_ref_clkin - * - osc_clk_1 - * - osc_clk_2, - * - f2h_periph_ref_clk - * - * + Valid reference clock input selections for \b l4_mp_clk - * - periph_base_clk - * - main_clk - * - * + Valid reference clock input selections for \b l4_sp_clk - * - periph_base_clk - * - main_clk - * - * + Valid reference clock input selections for \b sdmmc_clk - * - f2h_periph_ref_clk - * - main_nand_sdmmc_clk - * - periph_nand_sdmmc_clk - * - * + Valid reference clock input selections for \b nand_clk - * - f2h_periph_ref_clk - * - main_nand_sdmmc_clk - * - periph_nand_sdmmc_clk - * - * + Valid reference clock input selections for \b qspi_clk - * - f2h_periph_ref_clk - * - main_qspi_clk - * - periph_qspi_clk - * - * \endinternal - * @{ - */ -/******************************************************************************/ -/*! - * Get the input reference clock source selection value for the specified clock - * or PLL. - * - * NOTE: This function returns a clock value even though \e clk may specify a - * clock that does not have a selectable input reference clock source. In - * this case, the clock value returned is the static clock source for the - * specified clock. For example calling alt_clk_source_get() with \e clk - * set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1. - * - * \param clk - * The clock or PLL to retrieve the input reference clock source - * selection value for. - * - * \returns The clock's currently selected input reference clock source. - */ -ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk); - -/******************************************************************************/ -/*! - * Set the specified clock's input reference clock source selection. - * - * \param clk - * The clock or PLL to set the input reference clock source - * selection for. - * - * \param ref_clk - * The input reference clock source selection value. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The \e clk argument designates a clock that - * does not have a selectable input reference - * clock source. - * \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that - * is an invalid reference clock source for the - * specified clock. - */ -ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, - ALT_CLK_t ref_clk); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup CLK_MGR_FREQ Clock Frequency Control - * - * This API group provides access and control of the output frequency of a clock - * or PLL. - * - * @{ - */ - -/******************************************************************************/ -/*! - * Set the external clock frequency value. - * - * The function is used to specify the frequency of the external clock source as - * a measure of Hz. The supplied frequency should be within the Fmin and Fmax - * values allowed for the external clock source. - * - * \param clk - * The external clock source. Valid external clocks are - * * \e ALT_CLK_OSC1 - * * \e ALT_CLK_OSC2 - * * \e ALT_CLK_F2H_PERIPH_REF - * * \e ALT_CLK_F2H_SDRAM_REF - * - * \param freq - * The frequency of the external clock in Hz. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG A bad argument value was passed. Either the \e clk - * argument is bad or not a valid external clock - * source - * \retval ALT_E_ARG_RANGE The frequency value violates the range constraints - * for the specified clock. - - */ -ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk, - alt_freq_t freq); - -/******************************************************************************/ -/*! - * Get the external clock frequency value. - * - * This function returns the frequency of the external clock source as - * a measure of Hz. - * - * \param clk - * The external clock source. Valid external clocks are - * * \e ALT_CLK_OSC1 - * * \e ALT_CLK_OSC2 - * * \e ALT_CLK_F2H_PERIPH_REF - * * \e ALT_CLK_F2H_SDRAM_REF - * - * \retval freq - * The frequency of the external clock in Hz. - * - */ -alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk); - -/******************************************************************************/ -/*! - * This type definition defines a structure to contain the generalized - * configuration settings for a PLL. - */ -typedef struct ALT_CLK_PLL_CFG_s -{ - ALT_CLK_t ref_clk; /*!< PLL Reference Clock Source */ - uint32_t mult; /*!< VCO Frequency Configuration - - * Multiplier (M) value, range 1 to 4096 - */ - uint32_t div; /*!< VCO Frequency Configuration - - * Divider (N) value, range 1 to 64 - */ - uint32_t cntrs[6]; /*!< Post-Scale Counters (C0 - C5) - - * range 1 to 512 - */ - uint32_t pshift[6]; /*!< Phase Shift - 1/8 (45 degrees) of - * negative phase shift per increment, - * range 0 to 4096 - */ -} ALT_CLK_PLL_CFG_t; - -/******************************************************************************/ -/*! - * Get the current PLL configuration. - * - * \param pll - * The PLL to get the configuration from. - * - * \param pll_cfg - * [out] Pointer to an output parameter variable for the returned - * PLL configuration. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, - ALT_CLK_PLL_CFG_t* pll_cfg); - -/******************************************************************************/ -/*! - * Set the PLL configuration using the configuration parameters specified in - * \e pll_cfg. - * - * \param pll - * The PLL to set the configuration for. - * - * \param pll_cfg - * Pointer to a ALT_CLK_PLL_CFG_t structure specifying the desired - * PLL configuration. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, - const ALT_CLK_PLL_CFG_t* pll_cfg); - -/******************************************************************************/ -/*! - * Get the current PLL VCO frequency configuration. - * - * \param pll - * The PLL to get the VCO frequency configuration for. - * - * \param mult - * [out] Pointer to an output variable for the returned - * configured PLL VCO multiplier (M) value. - * - * \param div - * [out] Pointer to an output variable for the returned - * configured PLL VCO divider (N) value. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, - uint32_t* mult, - uint32_t* div); - -/******************************************************************************/ -/*! - * Set the PLL VCO frequency configuration using the supplied multiplier and - * divider arguments. - * - * \param pll - * The PLL to set the VCO frequency configuration for. - * - * \param mult - * The PLL VCO multiplier (M). Expected argument range 1 to 4096. - * - * \param div - * The PLL VCO divider (N). Expected argument range 1 to 64. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll, - uint32_t mult, - uint32_t div); - -/******************************************************************************/ -/*! - * Get the VCO frequency of the specified PLL. - * - * \param pll - * The PLL to retrieve the VCO frequency from. - * - * \param freq - * [out] Pointer to the an output parameter variable to return the - * PLL VCO frequency value. The frequency value is returned as a - * measures of Hz. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG A bad argument value was passed. Either - * the \e pll argument is invalid or a bad - * \e freq pointer value was passed. - */ -ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, - alt_freq_t* freq); - -/******************************************************************************/ -/*! - * Get the PLL frequency guard band value. - * - * \param pll - * The PLL from which to return the current guard band value. - * - * \returns The current guard band range in effect for the PLL. - */ -uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll); - -/******************************************************************************/ -/*! - * Set the PLL frequency guard band value. - * - * Once a PLL has achieved lock, any changes to the PLL VCO frequency that are - * within a specific guard band range (default value 20%) of the reference - * period should not cause the PLL to lose lock. - * - * Programmatic changes to the PLL frequency within this guard band range are - * permitted to be made without the risk of breaking lock during the transition - * to the new frequency. - * - * The clk_mgr_pll_guard_band_set() function changes the guard band from its - * current value to permit a more lenient or stringent policy to be in effect in - * the implementation of the functions configuring PLL VCO frequency. The - * rationale for changing the default guard band value might be to accommodate - * unexpected environmental conditions (noise, temperature, and other - * instability factors) that may affect the PLLs ability to maintain lock during - * a frequency change. - * - * \param pll - * The PLL to set the guard band value for. - * - * \param guard_band - * The guard band value. Value should be 0 <= \e guard_band <= 100. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_ARG_RANGE The guard band value violates its range constraint. - */ -ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll, - uint32_t guard_band); - -/******************************************************************************/ -/*! - * Get the configured divider value for the specified clock. - * - * This function is used to get the configured values of both internal and - * external clock dividers. The internal divider (PLL counters C0-C5) values - * are retrieved by specifying the clock name that is the divider output - * (e.g. ALT_CLK_MPU is used to get the Main PLL C0 counter value). \n - * It returns the actual divider value, not the encoded bitfield stored - * in the register, due to the variety of different encodings. - * - * \param clk - * The clock divider to get the value from. - * - * \param div - * [out] Pointer to an output variable for the returned clock - * divider value. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG An invalid clock argument was specified or a - * clock that does not have a divider. - */ -ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, - uint32_t* div); - -/******************************************************************************/ -/*! - * Set the divider value for the specified clock. - * - * This function is used to set the values of both internal and external clock - * dividers. The internal divider (PLL counters C0-C5) values are set by - * specifying the clock name that is the divider output (e.g. ALT_CLK_MPU is - * used to set the Main PLL C0 counter value). - * - * \param clk - * The clock divider to set the value for. - * - * \param div - * The clock divider value. NOTE: The valid range of clock divider - * values depends on the clock being configured. This is the - * real divisor ratio, not how the divisor is coded into the - * register, and is always one or greater. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG An invalid clock argument was specified or a - * clock that does not have a divider. - * \retval ALT_E_ARG_RANGE The divider value violates the range constraints - * for the clock divider. - */ -ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, - uint32_t div); - -/******************************************************************************/ -/*! - * Get the output frequency of the specified clock. - * - * \param clk - * The clock to retrieve the output frequency from. - * - * \param freq - * [out] Pointer to the an output parameter variable to return the - * clock output frequency value. The frequency value is returned as - * a measures of Hz. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG A bad argument value was passed. Either - * the \e clk argument is invalid or a bad - * \e freq pointer value was passed. - */ -ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, - alt_freq_t* freq); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup CLK_MGR_INT Clock Manager Interrupt Management - * - * The functions in this group provide management of interrupts originating from - * the Clock Manager. - * - * The following interrupt request (IRQ) signals are sourced from the Clock - * Manager: - * - * * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock - * status interrupt is the logical \e OR of six interrupt - * sources defining the loss or achievement of lock status for - * each PLL. The six PLL lock status conditions are: - * - Main PLL Achieved Lock - * - Main PLL Lost Lock - * - Peripheral PLL Achieved Lock - * - Peripheral PLL Lost Lock - * - SDRAM PLL Achieved Lock - * - SDRAM PLL Lost Lock - * - * They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t. - * - * Each PLL lock condition may be individually disabled/enabled - * as a contributor to the determination of the \b clkmgr_IRQ - * assertion status. - * - * The alt_clk_lock_status_clear() function is used to clear - * the PLL lock conditions causing the \b clkmgr_IRQ - * assertion. - * - * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the - * MPU to "wake up" after a transition of the Main PLL into - * or out of bypass mode has been safely achieved. The need - * for the "wake up" notification is because the PLL clocks - * pause for a short number of clock cycles during bypass - * state transition. ARM recommeds that the CPUs are placed - * in standby if the clocks are ever paused. - * - * NOTE: \b mpuwakeup_IRQ appears to be an Altera private interrupt and may not - * be part of the public API although clearly it has important utility in - * implementing safe changes to PLL settings and transitions into and out - * of bypass mode. - * @{ - */ - -/******************************************************************************/ -/*! - * Disable the \b clkmgr_IRQ interrupt signal source lock status condition(s). - * - * This function disables one or more of the lock status conditions as - * contributors to the \b clkmgr_IRQ interrupt signal state. - * - * NOTE: A set bit for a PLL lock status condition in the mask value does not - * have the effect of enabling it as a contributor to the \b clkmgr_IRQ - * interrupt signal state. The function alt_clk_irq_enable is used to enable PLL - * lock status source condition(s). - * - * \param lock_stat_mask - * Specifies the PLL lock status conditions to disable as interrupt - * source contributors. \e lock_stat_mask is a mask of logically - * OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock - * conditions to disable. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an - * unknown condition value. - */ -ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask); - -/******************************************************************************/ -/*! - * Enable the \b clkmgr_IRQ interrupt signal source lock status condition(s). - * - * This function enables one or more of the lock status conditions as - * contributors to the \b clkmgr_IRQ interrupt signal state. - * - * NOTE: A cleared bit for any PLL lock status condition in the mask value does - * not have the effect of disabling it as a contributor to the \b clkmgr_IRQ - * interrupt signal state. The function alt_clk_irq_disable is used to disable - * PLL lock status source condition(s). - * - * \param lock_stat_mask - * Specifies the PLL lock status conditions to enable as interrupt - * source contributors. \e lock_stat_mask is a mask of logically - * OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock - * conditions to enable. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an - * unknown condition value. - */ -ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup CLK_MGR_GROUP_CFG Clock Group Configuration - * - * This API provides the ability to safely set the configuration of a clock - * group with a single function call. - * - * A clock group is defined as set of clocks and signals generated from a common - * PLL VCO. The PLL and its derived clocks are treated as a single clock - * group. The clocks sourced directly or indirectly from the PLL may or may not - * have these features: - * * Clock Gates - * * Clock Dividers - * * Clock Source Selection Options - * - * The use case for application of the Clock Group Configuration functions is the - * ability to safely configure an entire clock group from a known good clock - * group configuration using the run-time function alt_clk_group_cfg_raw_set(). - * - * A known good clock group configuration may be generated by one of the - * following methods: - * - * * As static design information generated by an ACDS clock configuration tool - * and passed to embedded software for dynamic loading. - * - * * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has - * programmatically established a known good clock group configuration using - * the clock manager API configuration functions. - * - * @{ - */ - -/******************************************************************************/ -/*! - * Get the raw configuration state of the designated clock group. - * - * This function is used to capture the configuration state of the specified - * clock group in a private (raw) data structure. The raw data structure may be - * saved and used later to restore the clock group configuration using - * alt_clk_group_cfg_raw_get(). - * - * \param clk_group - * The clock group configuration to capture. - * - * \param clk_group_raw_cfg - * [out] A pointer to a private (raw) data structure to store the - * captured clock group configuration. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, - ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg); - -/******************************************************************************/ -/*! - * Set the clock group configuration. - * - * This function is used to safely set the configuration state of a clock - * group from a raw clock group configuration specification. The raw clock - * group configuration specification may be a configuration previously - * captured with alt_clk_group_cfg_raw_get() or a group clock configuration - * generated by an external utility. - * - * \param clk_group_raw_cfg - * A pointer to the specification to use in the configuration of - * the clock group. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * \retval ALT_E_BAD_VERSION The clock group configuration specification is - * invalid for this device. - */ -ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg); - -ALT_STATUS_CODE alt_clk_clkmgr_init(void); - -/*! @} */ - -/*! @} */ -#ifdef __cplusplus -} - -#endif /* __cplusplus */ -#endif /* __ALT_CLK_MGR_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h deleted file mode 100644 index 6be93fbd32..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma.h +++ /dev/null @@ -1,1007 +0,0 @@ -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ALT_DMA_H__ -#define __ALT_DMA_H__ - -#include "hwlib.h" -#include "alt_dma_common.h" -#include "alt_dma_program.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/*! - * \addtogroup ALT_DMA DMA Controller API - * - * This module defines the API for configuration and use of the general purpose - * DMA controller for the SoC. The DMA controller is an instance of the ARM - * Corelink DMA Controller (DMA-330). - * - * References: - * * ARM DDI 0424C, CoreLink DMA Controller DMA-330 Technical Reference - * Manual. - * * ARM DAI 0239A, Application Note 239 Example Programs for the CoreLink - * DMA Controller DMA-330. - * * Altera, Cyclone V Device Handbook Volume 3: Hard Processor System - * Technical Reference Manual, DMA Controller. - * - * @{ - */ - -/*! - * \addtogroup ALT_DMA_COMPILE DMA API Compile Options - * - * This API provides control over the compile time inclusion of selected - * modules. This can allow for a smaller resulting binary. - * - * @{ - */ - -#ifndef ALT_DMA_PERIPH_PROVISION_16550_SUPPORT -#define ALT_DMA_PERIPH_PROVISION_16550_SUPPORT (1) -#endif - -#ifndef ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT -#define ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT (1) -#endif - -/*! - * @} - */ - -/*! - * \addtogroup ALT_DMA_CSR DMA API for Configuration, Control, and Status - * - * This API provides functions for configuration, control, and status queries - * of the DMA controller. - * - * @{ - */ - -/*! - * This type definition enumerates the operational states that the DMA manager - * may have. - */ -typedef enum ALT_DMA_MANAGER_STATE_e -{ - ALT_DMA_MANAGER_STATE_STOPPED = 0, /*!< Stopped */ - ALT_DMA_MANAGER_STATE_EXECUTING = 1, /*!< Executing */ - ALT_DMA_MANAGER_STATE_CACHE_MISS = 2, /*!< Cache Miss */ - ALT_DMA_MANAGER_STATE_UPDATING_PC = 3, /*!< Updating PC */ - ALT_DMA_MANAGER_STATE_WFE = 4, /*!< Waiting for Event */ - ALT_DMA_MANAGER_STATE_FAULTING = 15 /*!< Faulting */ -} -ALT_DMA_MANAGER_STATE_t; - -/*! - * This type definition enumerates the operational states that a DMA channel - * may have. - */ -typedef enum ALT_DMA_CHANNEL_STATE_e -{ - ALT_DMA_CHANNEL_STATE_STOPPED = 0, /*!< Stopped */ - ALT_DMA_CHANNEL_STATE_EXECUTING = 1, /*!< Executing */ - ALT_DMA_CHANNEL_STATE_CACHE_MISS = 2, /*!< Cache Miss */ - ALT_DMA_CHANNEL_STATE_UPDATING_PC = 3, /*!< Updating PC */ - ALT_DMA_CHANNEL_STATE_WFE = 4, /*!< Waiting for Event */ - ALT_DMA_CHANNEL_STATE_AT_BARRIER = 5, /*!< At Barrier */ - ALT_DMA_CHANNEL_STATE_WFP = 7, /*!< Waiting for Peripheral */ - ALT_DMA_CHANNEL_STATE_KILLING = 8, /*!< Killing */ - ALT_DMA_CHANNEL_STATE_COMPLETING = 9, /*!< Completing */ - ALT_DMA_CHANNEL_STATE_FAULTING_COMPLETING = 14, /*!< Faulting Completing */ - ALT_DMA_CHANNEL_STATE_FAULTING = 15 /*!< Faulting */ -} -ALT_DMA_CHANNEL_STATE_t; - -/*! - * This type definition enumerates the possible fault status that the DMA - * manager can have as a register mask. - */ -typedef enum ALT_DMA_MANAGER_FAULT_e -{ - /*! - * The DMA manager abort occured because of an instruction issued through - * the debug interface. - */ - ALT_DMA_MANAGER_FAULT_DBG_INSTR = (int32_t)(1UL << 30), - - /*! - * The DMA manager instruction fetch AXI bus response was not OKAY. - */ - ALT_DMA_MANAGER_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16), - - /*! - * The DMA manager attempted to execute DMAWFE or DMASEV with - * inappropriate security permissions. - */ - ALT_DMA_MANAGER_FAULT_MGR_EVNT_ERR = (int32_t)(1UL << 5), - - /*! - * The DMA manager attempted to execute DMAGO with inappropriate security - * permissions. - */ - ALT_DMA_MANAGER_FAULT_DMAGO_ERR = (int32_t)(1UL << 4), - - /*! - * The DMA manager attempted to execute an instruction operand that was - * not valid for the DMA configuration. - */ - ALT_DMA_MANAGER_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1), - - /*! - * The DMA manager attempted to execute an undefined instruction. - */ - ALT_DMA_MANAGER_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0) -} -ALT_DMA_MANAGER_FAULT_t; - -/*! - * This type definition enumerates the possible fault status that a channel - * may have as a register mask. - */ -typedef enum ALT_DMA_CHANNEL_FAULT_e -{ - /*! - * The DMA channel has locked up due to resource starvation. - */ - ALT_DMA_CHANNEL_FAULT_LOCKUP_ERR = (int32_t)(1UL << 31), - - /*! - * The DMA channel abort occured because of an instruction issued through - * the debug interface. - */ - ALT_DMA_CHANNEL_FAULT_DBG_INSTR = (int32_t)(1UL << 30), - - /*! - * The DMA channel data read AXI bus reponse was not OKAY. - */ - ALT_DMA_CHANNEL_FAULT_DATA_READ_ERR = (int32_t)(1UL << 18), - - /*! - * The DMA channel data write AXI bus response was not OKAY. - */ - ALT_DMA_CHANNEL_FAULT_DATA_WRITE_ERR = (int32_t)(1UL << 17), - - /*! - * The DMA channel instruction fetch AXI bus response was not OKAY. - */ - ALT_DMA_CHANNEL_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16), - - /*! - * The DMA channel MFIFO did not have the data for the DMAST instruction. - */ - ALT_DMA_CHANNEL_FAULT_ST_DATA_UNAVAILABLE = (int32_t)(1UL << 13), - - /*! - * The DMA channel MFIFO is too small to hold the DMALD instruction data, - * or too small to servic the DMAST instruction request. - */ - ALT_DMA_CHANNEL_FAULT_MFIFO_ERR = (int32_t)(1UL << 12), - - /*! - * The DMA channel in non-secure state attempted to perform a secure read - * or write. - */ - ALT_DMA_CHANNEL_FAULT_CH_RDWR_ERR = (int32_t)(1UL << 7), - - /*! - * The DMA channel in non-secure state attempted to execute the DMAWFP, - * DMALDP, DMASTP, or DMAFLUSHP instruction involving a secure peripheral. - */ - ALT_DMA_CHANNEL_FAULT_CH_PERIPH_ERR = (int32_t)(1UL << 6), - - /*! - * The DMA channel in non-secure state attempted to execute the DMAWFE or - * DMASEV instruction for a secure event or secure interrupt (if - * applicable). - */ - ALT_DMA_CHANNEL_FAULT_CH_EVNT_ERR = (int32_t)(1UL << 5), - - /*! - * The DMA channel attempted to execute an instruction operand that was - * not valid for the DMA configuration. - */ - ALT_DMA_CHANNEL_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1), - - /*! - * The DMA channel attempted to execute an undefined instruction. - */ - ALT_DMA_CHANNEL_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0) -} -ALT_DMA_CHANNEL_FAULT_t; - -/*! - * This type definition enumerates the possible DMA event-interrupt behavior - * option selections when a DMASEV instruction is executed. - */ -typedef enum ALT_DMA_EVENT_SELECT_e -{ - /*! - * If the DMA controller executes DMASEV for the event-interrupt resource - * then the DMA sends the event to all of the channel threads. - */ - ALT_DMA_EVENT_SELECT_SEND_EVT, - - /*! - * If the DMA controller executes DMASEV for the event-interrupt resource - * then the DMA sets the \b irq[N] HIGH. - */ - ALT_DMA_EVENT_SELECT_SIG_IRQ -} -ALT_DMA_EVENT_SELECT_t; - -/*! - * This type enumerates the DMA peripheral interface MUX selection options - * available. - */ -typedef enum ALT_DMA_PERIPH_MUX_e -{ - /*! - * Accept the reset default MUX selection - */ - ALT_DMA_PERIPH_MUX_DEFAULT = 0, - - /*! - * Select FPGA as the peripheral interface - */ - ALT_DMA_PERIPH_MUX_FPGA = 1, - - /*! - * Select CAN as the peripheral interface - */ - ALT_DMA_PERIPH_MUX_CAN = 2 -} -ALT_DMA_PERIPH_MUX_t; - -/*! - * This type defines the structure used to specify the configuration of the - * security states and peripheral interface MUX selections for the DMA - * controller. - */ -typedef struct ALT_DMA_CFG_s -{ - /*! - * DMA Manager security state configuration. - */ - ALT_DMA_SECURITY_t manager_sec; - - /*! - * DMA interrupt output security state configurations. Security state - * configurations are 0-based index-aligned with the enumeration values - * ALT_DMA_EVENT_0 through ALT_DMA_EVENT_7 of the ALT_DMA_EVENT_t type. - */ - ALT_DMA_SECURITY_t irq_sec[8]; - - /*! - * Peripheral request interface security state configurations. Security - * state configurations are 0-based index-aligned with the enumeration - * values of the ALT_DMA_PERIPH_t type. - */ - ALT_DMA_SECURITY_t periph_sec[32]; - - /*! - * DMA Peripheral Register Interface MUX Selections. MUX selections are - * 0-based index-aligned with the enumeration values - * ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 through - * ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 of the ALT_DMA_PERIPH_t type. - */ - ALT_DMA_PERIPH_MUX_t periph_mux[4]; -} -ALT_DMA_CFG_t; - -/*! - * Initialize the DMA controller. - * - * Initializes the DMA controller by setting the necessary control values to - * establish the security state and MUXed peripheral request interface selection - * configurations before taking the DMA controller out of reset. - * - * After the DMA is initialized, the following conditions hold true: - * * All DMA channel threads are in the Stopped state. - * * All DMA channel threads are available for allocation. - * * DMA Manager thread is waiting for an instruction from either APB - * interface. - * * The security state configurations of the DMA Manager, interrupt outputs, - * and peripheral request interfaces are established and immutable until the - * DMA is reset. - * * The MUXed peripheral request interface selection configurations are - * established and immutable until the DMA is reset. - * - * \param dma_cfg - * A pointer to a ALT_DMA_CFG_t structure containing the desired - * DMA controller security state and peripheral request interface - * MUX selections. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg); - -/*! - * Uninitializes the DMA controller. - * - * Uninitializes the DMA controller by killing any running channel threads and - * putting the DMA controller into reset. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_dma_uninit(void); - -/*! - * Allocate a DMA channel resource for use. - * - * \param channel - * A DMA controller channel. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel); - -/*! - * Allocate a free DMA channel resource for use if there are any. - * - * \param allocated - * [out] A pointer to an output parameter that will contain the - * channel allocated. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. An unallocated channel - * may not be available at the time of the API - * call. - */ -ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated); - -/*! - * Free a DMA channel resource for reuse. - * - * \param channel - * The DMA controller channel resource to free. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. The channel may not be in - * the STOPPED state. - */ -ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel); - -/*! - * Start execution of a DMA microcode program on the specified DMA channel - * thread resource. - * - * \param channel - * The DMA channel thread used to execute the microcode program. - * - * \param pgm - * The DMA microcode program. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel, - ALT_DMA_PROGRAM_t * pgm); - -/*! - * Kill (abort) execution of any microcode program executing on the specified - * DMA channel thread resource. - * - * Terminates the channel thread of execution by issuing a DMAKILL instruction - * using the DMA APB slave interface. - * - * \param channel - * The DMA channel thread to abort any executing microcode program - * on. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_TMO Timeout waiting for the channel to change into - * KILLING or STOPPED state. - */ -ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel); - -/*! - * Returns the current register value for the given DMA channel. - * - * \param channel - * The DMA channel thread to abort any executing microcode program - * on. - * - * \param reg - * Register to get the value for. - * - * \param val - * [out] The current value of the requested register. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The specified channel or register is invalid. - */ -ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel, - ALT_DMA_PROGRAM_REG_t reg, uint32_t * val); - -/*! - * Signals the occurrence of an event or interrupt, using the specified event - * number. - * - * Causes the CPU to issue a DMASEV instruction using the DMA APB slave - * interface. - * - * The Interrupt Enable Register (INTEN) register is used to control if each - * event-interrupt resource is either an event or an interrupt. The INTEN - * register sets the event-interrupt resource to function as an: - * * Event - The DMAC generates an event for the specified event-interrupt - * resource. When the DMAC executes a DMAWFE instruction for the - * same event-interrupt resource then it clears the event. - * * Interrupt - The DMAC sets the \b IRQ[N] signal high, where - * \e evt_num is the number of the specified event - * resource. The interrupt must be cleared after being handled. - * - * When the configured to generate an event, this function may be used to - * restart one or more waiting DMA channels (i.e. having executed a DMAWFE - * instruction). - * - * See the following sections from the \e ARM DDI 0424C, CoreLink DMA Controller - * DMA-330 Technical Reference Manual for implementation details and use cases: - * * 2.5.1, Issuing Instructions to the DMAC using a Slave Interface - * * 2.7, Using Events and Interrupts - * - * \param evt_num - * A DMA event-interrupt resource. Allowable event values may be - * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 but ALT_DMA_EVENT_ABORT is - * not. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given event number is invalid. - */ -ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num); - -/*! - * Returns the current operational state of the DMA manager thread. - * - * \param state - * [out] Pointer to an output parameter to contain the DMA - * channel thread state. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state); - -/*! - * Returns the current operational state of the specified DMA channel thread. - * - * \param channel - * The DMA channel thread to return the operational state of. - * - * \param state - * [out] Pointer to an output parameter to contain the DMA - * channel thread state. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given channel identifier is invalid. - */ -ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel, - ALT_DMA_CHANNEL_STATE_t * state); - -/*! - * Return the current fault status of the DMA manager thread. - * - * \param fault - * [out] Pointer to an output parameter to contain the DMA - * manager fault status. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault); - -/*! - * Return the current fault status of the specified DMA channel thread. - * - * \param channel - * The DMA channel thread to return the fault status of. - * - * \param fault - * [out] Pointer to an output parameter to contain the DMA - * channel fault status. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given channel identifier is invalid. - */ -ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel, - ALT_DMA_CHANNEL_FAULT_t * fault); - -/*! - * Select whether the DMA controller sends the specific event to all channel - * threads or signals an interrupt using the corressponding \b irq when a DMASEV - * instruction is executed for the specified event-interrupt resource number. - * - * \param evt_num - * The event-interrupt resource number. Valid values are - * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. - * - * \param opt - * The desired behavior selection for \e evt_num when a DMASEV is - * executed. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given selection identifier is invalid. - */ -ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num, - ALT_DMA_EVENT_SELECT_t opt); - -/*! - * Returns the status of the specified event-interrupt resource. - * - * Returns ALT_E_TRUE if event is active or \b irq[N] is HIGH and returns - * ALT_E_FALSE if event is inactive or \b irq[N] is LOW. - * - * \param evt_num - * The event-interrupt resource number. Valid values are - * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. - * - * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH. - * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given event identifier is invalid. - */ -ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num); - -/*! - * Returns the status of the specified interrupt resource. - * - * Returns ALT_E_TRUE if interrupt is active and therfore \b irq[N] is HIGH and - * returns ALT_E_FALSE if interrupt is inactive and therfore \b irq[N] is LOW. - * - * \param irq_num - * The interrupt resource number. Valid values are - * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. - * - * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH. - * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given event identifier is invalid. - */ -ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num); - -/*! - * Clear the active (HIGH) status of the specified interrupt resource. - * - * If the specified interrupt is HIGH, then sets \b irq[N] to LOW if the - * event-interrupt resource is configured (see: alt_dma_event_int_enable()) - * to signal an interrupt. Otherwise, the status of \b irq[N] does not change. - * - * \param irq_num - * The interrupt resource number. Valid values are - * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given event identifier is invalid. - */ -ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num); - -/*! - * @} - */ - -/*! - * \addtogroup ALT_DMA_STD_OPS DMA API for Standard Operations - * - * The functions in this group provide common DMA operations for common bulk - * data transfers between: - * * Memory to Memory - * * Zero to Memory - * * Memory to Peripheral - * * Peripheral to Memory - * - * All DMA operations are asynchronous. The following are the ways to receive - * notification of a DMA transfer complete operation: - * * Use alt_dma_channel_state_get() and poll for the - * ALT_DMA_CHANNEL_STATE_STOPPED status. - * * In conjunction with the interrupt API, use DMA events to signal an - * interrupt. The event first must be configured to signal an interrupt - * using alt_dma_event_int_select(). Configure the DMA program to send an - * event. - * * Construct a custom program which waits for a particular event number by - * assemblying a DMAWFE using alt_dma_program_DMAWFE(). Then run the custom - * program on a different channel. The custom program will wait until the - * DMA program sends the event. Configure the DMA program to send an event. - * - * Cache related maintenance on the source and/or destinatino buffer are not - * handled the DMA API and are the responsibility of the programmer. This is - * because the DMA API does not have visibility into the current configuration - * of the MMU or know about any special considerations regarding the source - * and/or destination memory. The following are some example scenarios and - * cache maintenance related precautions that may need to be taken: - * * alt_dma_memory_to_memory(): Source buffer should be cleaned or purged, - * destination buffer should be invalidated. - * * alt_dma_zero_to_memory(): Destination buffer should be invalidated. - * * alt_dma_memory_to_register(): Source buffer should be cleaned or purged. - * * alt_dma_register_to_memory(): Destination buffer should be invalidated. - * * alt_dma_memory_to_periph(): Source buffer should be cleaned or purged. - * * alt_dma_periph_to_memory(): Destination buffer should be invalidated. - * - * @{ - */ - -/*! - * Uses the DMA engine to asynchronously copy the specified memory from the - * given source address to the given destination address. - * - * Overlapping memory regions are not supported. - * - * \param channel - * The DMA channel thread to use for the transfer. - * - * \param program - * An allocated DMA program buffer to use for the life of the - * transfer. - * - * \param dest - * The destination memory address to copy to. - * - * \param src - * The source memory address to copy from. - * - * \param size - * The size of the transfer in bytes. - * - * \param send_evt - * If set to true, the DMA engine will be instructed to send an - * event upon completion or fault. - * - * \param evt - * If send_evt is true, the event specified will be sent. - * Otherwise the parameter is ignored. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given channel or event identifier (if - * used) is invalid, or the memory regions - * specified are overlapping. - */ -ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel, - ALT_DMA_PROGRAM_t * program, - void * dest, - const void * src, - size_t size, - bool send_evt, - ALT_DMA_EVENT_t evt); - -/*! - * Uses the DMA engine to asynchronously zero out the specified memory buffer. - * - * \param channel - * The DMA channel thread to use for the transfer. - * - * \param program - * An allocated DMA program buffer to use for the life of the - * transfer. - * - * \param buf - * The buffer memory address to zero out. - * - * \param size - * The size of the buffer in bytes. - * - * \param send_evt - * If set to true, the DMA engine will be instructed to send an - * event upon completion or fault. - * - * \param evt - * If send_evt is true, the event specified will be sent. - * Otherwise the parameter is ignored. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given channel or event identifier (if - * used) is invalid. - */ -ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel, - ALT_DMA_PROGRAM_t * program, - void * buf, - size_t size, - bool send_evt, - ALT_DMA_EVENT_t evt); - -/*! - * Uses the DMA engine to asynchronously transfer the contents of a memory - * buffer to a keyhole register. - * - * \param channel - * The DMA channel thread to use for the transfer. - * - * \param program - * An allocated DMA program buffer to use for the life of the - * transfer. - * - * \param dst_reg - * The address of the register to write buffer to. - * - * \param src_buf - * The address of the memory buffer for the data. - * - * \param count - * The number of transfers to make. - * - * \param register_width_bits - * The width of the register to transfer to in bits. Valid values - * are 8, 16, 32, and 64. - * - * \param send_evt - * If set to true, the DMA engine will be instructed to send an - * event upon completion or fault. - * - * \param evt - * If send_evt is true, the event specified will be sent. - * Otherwise the parameter is ignored. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given channel, event identifier (if used), - * or register width are invalid, or if the - * destination register or source buffer is - * unaligned to the register width. - */ -ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel, - ALT_DMA_PROGRAM_t * program, - void * dst_reg, - const void * src_buf, - size_t count, - uint32_t register_width_bits, - bool send_evt, - ALT_DMA_EVENT_t evt); - -/*! - * Uses the DMA engine to asynchronously transfer the contents of a keyhole - * register to a memory buffer. - * - * \param channel - * The DMA channel thread to use for the transfer. - * - * \param program - * An allocated DMA program buffer to use for the life of the - * transfer. - * - * \param dst_buf - * The address of the memory buffer to copy to. - * - * \param src_reg - * The address of the keyhole register to read from. - * - * \param count - * The number of transfers to make. - * - * \param register_width_bits - * The width of the register to transfer to in bits. Valid values - * are 8, 16, 32, and 64. - * - * \param send_evt - * If set to true, the DMA engine will be instructed to send an - * event upon completion or fault. - * - * \param evt - * If send_evt is true, the event specified will be sent. - * Otherwise the parameter is ignored. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given channel, event identifier (if used), - * or register width are invalid, or if the - * destination buffer or source register is - * unaligned to the register width. - */ -ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel, - ALT_DMA_PROGRAM_t * program, - void * dst_buf, - const void * src_reg, - size_t count, - uint32_t register_width_bits, - bool send_evt, - ALT_DMA_EVENT_t evt); - -/*! - * Uses the DMA engine to asynchronously copy memory from the given source - * address to the specified peripheral. Because different peripheral has - * different characteristics, individual peripherals need to be explicitly - * supported. - * - * The following lists the peripheral IDs supported by this API: - * * ALT_DMA_PERIPH_QSPI_FLASH_TX - * * ALT_DMA_PERIPH_UART0_TX - * * ALT_DMA_PERIPH_UART1_TX - * - * \param channel - * The DMA channel thread to use for the transfer. - * - * \param program - * An allocated DMA program buffer to use for the life of the - * transfer. - * - * \param dest - * The destination peripheral to copy memory to. - * - * \param src - * The source memory address to copy from. - * - * \param size - * The size of the transfer in bytes. - * - * \param periph_info - * A pointer to a peripheral specific data structure. The - * following list shows what data structure should be used for - * peripherals: - * * ALT_DMA_PERIPH_QSPI_FLASH_TX: This parameter is ignored. - * * ALT_DMA_PERIPH_UART0_TX: Use a pointer to the - * ALT_16550_HANDLE_t used to interact with that UART. - * * ALT_DMA_PERIPH_UART1_TX: Use a pointer to the - * ALT_16550_HANDLE_t used to interact with that UART. - * - * \param send_evt - * If set to true, the DMA engine will be instructed to send an - * event upon completion or fault. - * - * \param evt - * If send_evt is true, the event specified will be sent. - * Otherwise the parameter is ignored. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given channel, peripheral, or event - * identifier (if used) is invalid. - * - * \internal - * Priority peripheral IDs to be supported: - * * ALT_DMA_PERIPH_FPGA_0 - * * ALT_DMA_PERIPH_FPGA_1 - * * ALT_DMA_PERIPH_FPGA_2 - * * ALT_DMA_PERIPH_FPGA_3 - * * ALT_DMA_PERIPH_FPGA_4 - * * ALT_DMA_PERIPH_FPGA_5 - * * ALT_DMA_PERIPH_FPGA_6 - * * ALT_DMA_PERIPH_FPGA_7 - * * ALT_DMA_PERIPH_I2C0_TX - * * ALT_DMA_PERIPH_I2C1_TX - * * ALT_DMA_PERIPH_I2C2_TX - * * ALT_DMA_PERIPH_I2C3_TX - * * ALT_DMA_PERIPH_SPI0_MASTER_TX - * * ALT_DMA_PERIPH_SPI0_SLAVE_TX - * * ALT_DMA_PERIPH_SPI1_MASTER_TX - * * ALT_DMA_PERIPH_SPI1_SLAVE_TX - * \endinternal - */ -ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel, - ALT_DMA_PROGRAM_t * program, - ALT_DMA_PERIPH_t dest, - const void * src, - size_t size, - void * periph_info, - bool send_evt, - ALT_DMA_EVENT_t evt); - -/*! - * Uses the DMA engine to copy memory from the specified peripheral to the - * given destination address. Because different peripheral has different - * characteristics, individual peripherals need to be explicitly supported. - * - * The following lists the peripheral IDs supported by this API: - * * ALT_DMA_PERIPH_QSPI_FLASH_RX - * * ALT_DMA_PERIPH_UART0_RX - * * ALT_DMA_PERIPH_UART1_RX - * - * \param channel - * The DMA channel thread to use for the transfer. - * - * \param program - * An allocated DMA program buffer to use for the life of the - * transfer. - * - * \param dest - * The destination memory address to copy to. - * - * \param src - * The source peripheral to copy memory from. - * - * \param size - * The size of the transfer in bytes. - * - * \param periph_info - * A pointer to a peripheral specific data structure. The - * following list shows what data structure should be used for - * peripherals: - * * ALT_DMA_PERIPH_QSPI_FLASH_RX: This parameter is ignored. - * * ALT_DMA_PERIPH_UART0_RX: Use a pointer to the - * ALT_16550_HANDLE_t used to interact with that UART. - * * ALT_DMA_PERIPH_UART1_RX: Use a pointer to the - * ALT_16550_HANDLE_t used to interact with that UART. - * - * \param send_evt - * If set to true, the DMA engine will be instructed to send an - * event upon completion or fault. - * - * \param evt - * If send_evt is true, the event specified will be sent. - * Otherwise the parameter is ignored. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG The given channel, peripheral, or event - * identifier (if used) is invalid. -* - * \internal - * Priority peripheral IDs to be supported: - * * ALT_DMA_PERIPH_FPGA_0 - * * ALT_DMA_PERIPH_FPGA_1 - * * ALT_DMA_PERIPH_FPGA_2 - * * ALT_DMA_PERIPH_FPGA_3 - * * ALT_DMA_PERIPH_FPGA_4 - * * ALT_DMA_PERIPH_FPGA_5 - * * ALT_DMA_PERIPH_FPGA_6 - * * ALT_DMA_PERIPH_FPGA_7 - * * ALT_DMA_PERIPH_I2C0_RX - * * ALT_DMA_PERIPH_I2C1_RX - * * ALT_DMA_PERIPH_I2C2_RX - * * ALT_DMA_PERIPH_I2C3_RX - * * ALT_DMA_PERIPH_SPI0_MASTER_RX - * * ALT_DMA_PERIPH_SPI0_SLAVE_RX - * * ALT_DMA_PERIPH_SPI1_MASTER_RX - * * ALT_DMA_PERIPH_SPI1_SLAVE_RX - * \endinternal - */ -ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel, - ALT_DMA_PROGRAM_t * program, - void * dest, - ALT_DMA_PERIPH_t src, - size_t size, - void * periph_info, - bool send_evt, - ALT_DMA_EVENT_t evt); - -/*! - * @} - */ - -/*! - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_DMA_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h deleted file mode 100644 index e82bc1ae4d..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h +++ /dev/null @@ -1,162 +0,0 @@ -/****************************************************************************** - * - * Copyright 2013 Altera Corporation. All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - ******************************************************************************/ - -#ifndef __ALT_DMA_COMMON_H__ -#define __ALT_DMA_COMMON_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/*! - * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions - * - * This module contains the common definitions for the DMA controller related - * APIs. - * - * @{ - */ - -/*! - * This type definition enumerates the DMA controller channel threads. - */ -typedef enum ALT_DMA_CHANNEL_e -{ - ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */ - ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */ - ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */ - ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */ - ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */ - ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */ - ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */ - ALT_DMA_CHANNEL_7 = 7 /*!< DMA Channel Thread 7 */ -} -ALT_DMA_CHANNEL_t; - -/*! - * This type definition enumerates the SoC system peripherals implementing the - * required request interface that enables direct DMA transfers to/from the - * device. - * - * FPGA soft IP interface to the DMA are required to comply with the Synopsys - * protocol. - * - * Request interface numbers 4 through 7 are multiplexed between the CAN - * controllers and soft logic implemented in the FPGA fabric. The selection - * between the CAN controller and FPGA interfaces is determined at DMA - * initialization. - */ -typedef enum ALT_DMA_PERIPH_e -{ - ALT_DMA_PERIPH_FPGA_0 = 0, /*!< FPGA soft IP interface 0 */ - ALT_DMA_PERIPH_FPGA_1 = 1, /*!< FPGA soft IP interface 1 */ - ALT_DMA_PERIPH_FPGA_2 = 2, /*!< FPGA soft IP interface 2 */ - ALT_DMA_PERIPH_FPGA_3 = 3, /*!< FPGA soft IP interface 3 */ - - ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4, /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */ - ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5, /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */ - ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6, /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */ - ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7, /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */ - - ALT_DMA_PERIPH_FPGA_4 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ - ALT_DMA_PERIPH_FPGA_5 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ - ALT_DMA_PERIPH_FPGA_6 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ - ALT_DMA_PERIPH_FPGA_7 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ - - ALT_DMA_PERIPH_CAN0_IF1 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ - ALT_DMA_PERIPH_CAN0_IF2 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ - ALT_DMA_PERIPH_CAN1_IF1 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ - ALT_DMA_PERIPH_CAN1_IF2 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ - - ALT_DMA_PERIPH_I2C0_TX = 8, /*!< I<sup>2</sup>C 0 TX */ - ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I<sup>2</sup>C 0 RX */ - ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I<sup>2</sup>C 1 TX */ - ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I<sup>2</sup>C 1 RX */ - ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I<sup>2</sup>C 2 TX */ - ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I<sup>2</sup>C 2 RX */ - ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I<sup>2</sup>C 3 TX */ - ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I<sup>2</sup>C 3 RX */ - ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */ - ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */ - ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */ - ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */ - ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */ - ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */ - ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */ - ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */ - ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */ - ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */ - ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */ - ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */ - ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */ - ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */ - ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */ - ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */ -} -ALT_DMA_PERIPH_t; - -/*! - * This type enumerates the DMA security state options available. - */ -typedef enum ALT_DMA_SECURITY_e -{ - ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */ - ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */ - ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */ -} -ALT_DMA_SECURITY_t; - -/*! - * This type definition enumerates the DMA event-interrupt resources. - */ -typedef enum ALT_DMA_EVENT_e -{ - ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */ - ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */ - ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */ - ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */ - ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */ - ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */ - ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */ - ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */ - ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */ -} -ALT_DMA_EVENT_t; - -/*! - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_DMA_COMMON_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h deleted file mode 100644 index 5fa876f237..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_program.h +++ /dev/null @@ -1,951 +0,0 @@ -/****************************************************************************** - * - * Copyright 2013 Altera Corporation. All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - ******************************************************************************/ - -#ifndef __ALT_DMA_PROGRAM_H__ -#define __ALT_DMA_PROGRAM_H__ - -#include "hwlib.h" -#include "alt_dma_common.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/*! - * \addtogroup ALT_DMA_PRG DMA Controller Programming API - * - * This API provides functions for dynamically defining and assembling microcode - * programs for execution on the DMA controller. - * - * The microcode program assembly API provides users with the ability to develop - * highly optimized and tailored algorithms for data transfer between SoC FPGA - * IP blocks and/or system memory. - * - * The same microcode program assembly facilities are also used to implement the - * functions found in the HWLIB Common DMA Operations functional API. - * - * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA - * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated - * from used specified system memory. Once a microcode program has been - * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA - * channel thread. The microcode program may be rerun on any DMA channel thread - * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t - * containing the program is maintained. - * - * @{ - */ - -/*! - * This preprocessor declares the DMA channel thread microcode instruction - * cache line width in bytes. It is recommended that the program buffers be - * sized to a multiple of the cache line size. This will allow for the most - * efficient microcode speed and space utilization. - */ -#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32) - -/*! - * This preprocessor declares the DMA channel thread microcode instruction - * cache line count. Thus the total size of the cache is the cache line size - * multipled by the cache line count. Programs larger than the cache size risk - * having a cache miss while executing. - */ -#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16) - -/*! - * This preprocessor definition determines the size of the program buffer - * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate - * size for most DMA microcode programs. If calls within this API are - * reporting out of memory response codes, consider increasing the provisioned - * program buffersize. - * - * To specify another DMA microcode program buffer size, redefine the macro - * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in - * your Makefile. It is recommended that the size be a multiple of the - * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for - * more information. The largest supported buffer size is 65536 bytes. - */ -#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE -#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT) -#endif - -/*! - * This type defines the structure used to assemble and contain a microcode - * program which can be executed by the DMA controller. The internal members - * are undocumented and should not be altered outside of this API. - */ -typedef struct ALT_DMA_PROGRAM_s -{ - uint32_t flag; - - uint16_t buffer_start; - uint16_t code_size; - - uint16_t loop0; - uint16_t loop1; - - uint16_t sar; - uint16_t dar; - - /* - * Add a little extra space so that regardless of where this structure - * sits in memory, a suitable start address can be aligned to the cache - * line stride while providing the requested buffer space. - */ - uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE + - ALT_DMA_PROGRAM_CACHE_LINE_SIZE]; -} -ALT_DMA_PROGRAM_t; - -/*! - * This type definition enumerates the DMA controller register names for use in - * microcode program definition. - */ -typedef enum ALT_DMA_PROGRAM_REG_e -{ - /*! Source Address Register */ - ALT_DMA_PROGRAM_REG_SAR = 0x0, - - /*! Destination Address Register */ - ALT_DMA_PROGRAM_REG_DAR = 0x2, - - /*! Channel Control Register */ - ALT_DMA_PROGRAM_REG_CCR = 0x1 -} -ALT_DMA_PROGRAM_REG_t; - -/*! - * This type definition enumerates the instruction modifier options available - * for use with selected DMA microcode instructions. - * - * The enumerations values are context dependent upon the instruction being - * modified. - * - * For the <b>DMALD[S|B]</b>, <b>DMALDP\<S|B></b>, <b>DMAST[S|B]</b>, and - * <b>DMASTP\<S|B></b> microcode instructions, the enumeration - * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the <b>S</b> option modifier - * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the <b>B</b> - * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies - * that no modifier is present for instructions where use of <b>[S|B]</b> is - * optional. - * - * For the <b>DMAWFP</b> microcode instruction, the enumerations - * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or - * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding - * options <b>\<single|burst|periph></b>. - */ -typedef enum ALT_DMA_PROGRAM_INST_MOD_e -{ - /*! - * This DMA instruction modifier specifies that no special modifier is - * added to the instruction. - */ - ALT_DMA_PROGRAM_INST_MOD_NONE, - - /*! - * Depending on the DMA microcode instruction modified, this modifier - * specifies <b>S</b> case for a <b>[S|B]</b> or a <b>\<single></b> for a - * <b>\<single|burst|periph></b>. - */ - ALT_DMA_PROGRAM_INST_MOD_SINGLE, - - /*! - * Depending on the DMA microcode instruction modified, this modifier - * specifies <b>B</b> case for a <b>[S|B]</b> or a <b>\<burst></b> for a - * <b>\<single|burst|periph></b>. - */ - ALT_DMA_PROGRAM_INST_MOD_BURST, - - /*! - * This DMA instruction modifier specifies a <b>\<periph></b> for a - * <b>\<single|burst|periph></b>. - */ - ALT_DMA_PROGRAM_INST_MOD_PERIPH -} -ALT_DMA_PROGRAM_INST_MOD_t; - -/*! - * This function initializes a system memory buffer for use as a DMA microcode - * program buffer. This should be the first API call made on the program - * buffer type. - * - * \param pgm - * A pointer to a DMA program buffer structure. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm); - -/*! - * This function verifies that the DMA microcode program buffer is no longer - * in use and performs any needed uninitialization steps. - * - * \param pgm - * A pointer to a DMA program buffer structure. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm); - -/*! - * This function clears the existing DMA microcode program in the given - * program buffer. - * - * \param pgm - * A pointer to a DMA program buffer structure. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR Details about error status code. - */ -ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm); - -/*! - * This function validate that the given DMA microcode program buffer contains - * a well formed program. If caches are enabled, the program buffer contents - * will be cleaned to RAM. - * - * \param pgm - * A pointer to a DMA program buffer structure. - * - * \retval ALT_E_SUCCESS The given program is well formed. - * \retval ALT_E_ERROR The given program is not well formed. - * \retval ALT_E_TMO The cache operation timed out. - */ -ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm); - -/*! - * This function reports the number bytes incremented for the register - * specified. The purpose is to determine the progress of an ongoing DMA - * transfer. - * - * It is implemented by calculating the difference of the programmed SAR or DAR - * with the current channel SAR or DAR register value. - * - * \param pgm - * A pointer to a DMA program buffer structure. - * - * \param channel - * The channel that the program is running on. - * - * \param reg - * Register to change the value for. Valid for only - * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. - * - * \param current - * The current snapshot value of the register read from the DMA - * channel. - * - * \param progress - * [out] A pointer to a memory location that will be used to store - * the number of bytes transfered. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR Details about error status code. - * \retval ALT_E_BAD_ARG The specified channel is invalid, the specified - * register is invalid, or the DMAMOV for the - * specified register has not yet been assembled - * in the current program buffer. - */ -ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_REG_t reg, - uint32_t current, uint32_t * progress); - -/*! - * This function updates a pre-existing DMAMOV value affecting the SAR or DAR - * registers. This allows for pre-assembled programs that can be used on - * different source and destination addresses. - * - * \param pgm - * A pointer to a DMA program buffer structure. - * - * \param reg - * Register to change the value for. Valid for only - * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. - * - * \param val - * The value to update to. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR Details about error status code. - * \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV - * for the specified register has not yet been - * assembled in the current program buffer. - */ -ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_REG_t reg, uint32_t val); - -/*! - */ - -/*! - * Assembles a DMAADDH (Add Halfword) instruction into the microcode program - * buffer. This instruction uses 3 bytes of buffer space. - * - * \param pgm - * The DMA program buffer to contain the assembled instruction. - * - * \param addr_reg - * The channel address register (ALT_DMA_PROGRAM_REG_DAR or - * ALT_DMA_PROGRAM_REG_SAR) to add the value to. - * - * \param val - * The 16-bit unsigned value to add to the channel address - * register. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid channel register specified. - */ -// Assembler Syntax: DMAADDH <address_register>, <16-bit immediate> -ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); - -/*! - * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode - * program buffer. This instruction uses 3 bytes of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param addr_reg - * The channel address register (ALT_DMA_PROGRAM_REG_DAR or - * ALT_DMA_PROGRAM_REG_SAR) to add the value to. - * - * \param val - * The 16-bit unsigned value to add to the channel address - * register. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid channel register specified. - */ -// Assembler Syntax: DMAADNH <address_register>, <16-bit immediate> -ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); - -/*! - * Assembles a DMAEND (End) instruction into the microcode program buffer. - * This instruction uses 1 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - */ -// Assembler Syntax: DMAEND -ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm); - -/*! - * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode - * program buffer. This instruction uses 2 bytes of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param periph - * The peripheral to flush. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid peripheral specified. - */ -// Assembler Syntax: DMAFLUSHP <peripheral> -ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PERIPH_t periph); - -/*! - * Assembles a DMAGO (Go) instruction into the microcode program buffer. This - * instruction uses 6 bytes of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param channel - * The stopped channel to act upon. - * - * \param val - * The value to write to the channel program counter register. - * - * \param sec - * The security state for the operation. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid channel or security specified. - */ -// Assembler Syntax: DMAGO <channel_number>, <32-bit_immediate> [, ns] -ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_CHANNEL_t channel, uint32_t val, - ALT_DMA_SECURITY_t sec); - -/*! - * Assembles a DMAKILL (Kill) instruction into the microcode program buffer. - * This instruction uses 1 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - */ -// Assembler Syntax: DMAKILL -ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm); - -/*! - * Assembles a DMALD (Load) instruction into the microcode program buffer. - * This instruction uses 1 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param mod - * The program instruction modifier for the type of transfer. - * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and - * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. - */ -// Assembler Syntax: DMALD[S|B] -ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_INST_MOD_t mod); - -/*! - * Assembles a DMALDP (Load and notify Peripheral) instruction into the - * microcode program buffer. This instruction uses 2 bytes of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param mod - * The program instruction modifier for the type of transfer. - * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and - * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. - * - * \param periph - * The peripheral to notify. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral - * specified. - */ -// Assembler Syntax: DMALDP<S|B> <peripheral> -ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); - -/*! - * Assembles a DMALP (Loop) instruction into the microcode program buffer. - * This instruction uses 2 bytes of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param iterations - * The number of iterations to run for. Valid values are 1 - 256. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid iterations specified. - * \retval ALT_E_BAD_OPERATION All loop registers are in use. - */ -// Assembler Syntax: DMALP [<LC0>|<LC1>] <loop_iterations> -ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, - uint32_t iterations); - -/*! - * Assembles a DMALPEND (Loop End) instruction into the microcode program - * buffer. This instruction uses 2 bytes of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param mod - * The program instruction modifier for the loop terminator. Only - * ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE - * and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. - * \retval ALT_E_ARG_RANGE Loop size is too large to be supported. - * \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to - * the program buffer before adding this - * DMALPEND instruction. - */ -// Assembler Syntax: DMALPEND[S|B] -ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_INST_MOD_t mod); - -/*! - * Assembles a DMALPFE (Loop Forever) instruction into the microcode program - * buffer. No instruction is added to the buffer but a previous DMALPEND to - * create an infinite loop. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - */ -// Assembler Syntax: DMALPFE -ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm); - -/*! - * Assembles a DMAMOV (Move) instruction into the microcode program buffer. - * This instruction uses 6 bytes of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param chan_reg - * The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR, - * ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy - * the value to. - * - * \param val - * The value to write to the specified register. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid channel register specified. - */ -// Assembler Syntax: DMAMOV <destination_register>, <32-bit_immediate> -ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val); - -/*! - * Assembles a DMANOP (No Operation) instruction into the microcode program - * buffer. This instruction uses 1 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - */ -// Assembler Syntax: DMANOP -ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm); - -/*! - * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode - * program buffer. This instruction uses 1 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - */ -// Assembler Syntax: DMARMB -ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm); - -/*! - * Assembles a DMASEV (Send Event) instruction into the microcode program - * buffer. This instruction uses 2 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param evt - * The event to send. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid event specified. - */ -// Assembler Syntax: DMASEV <event_num> -ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_EVENT_t evt); - -/*! - * Assembles a DMAST (Store) instruction into the microcode program buffer. - * This instruction uses 1 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param mod - * The program instruction modifier for the type of transfer. - * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and - * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - */ -// Assembler Syntax: DMAST[S|B] -ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_INST_MOD_t mod); - -/*! - * Assembles a DMASTP (Store and notify Peripheral) instruction into the - * microcode program buffer. This instruction uses 2 bytes of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param mod - * The program instruction modifier for the type of transfer. - * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and - * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. - * - * \param periph - * The peripheral to notify. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral - * specified. - */ -// Assembler Syntax: DMASTP<S|B> <peripheral> -ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); - -/*! - * Assembles a DMASTZ (Store Zero) instruction into the microcode program - * buffer. This instruction uses 1 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - */ -// Assembler Syntax: DMASTZ -ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm); - -/*! - * Assembles a DMAWFE (Wait For Event) instruction into the microcode program - * buffer. This instruction uses 2 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param evt - * The event to wait for. - * - * \param invalid - * If invalid is set to true, the instruction will be configured - * to invalidate the instruction cache for the current DMA - * thread. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid event specified. - */ -// Assembler Syntax: DMAWFE <event_num>[, invalid] -ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_EVENT_t evt, bool invalid); - -/*! - * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode - * program buffer. This instruction uses 2 bytes of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \param periph - * The peripheral to wait on. - * - * \param mod - * The program instruction modifier for the type of transfer. - * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE, - * ALT_DMA_PROGRAM_INST_MOD_BURST, or - * ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - * \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier - * specified. - */ -// Assembler Syntax: DMAWFP <peripheral>, <single|burst|periph> -ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, - ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod); - -/*! - * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode - * program buffer. This instruction uses 1 byte of buffer space. - * - * \param pgm - * The DMA programm buffer to contain the assembled instruction. - * - * \retval ALT_E_SUCCESS Successful instruction assembly status. - * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. - */ -// Assembler Syntax: DMAWMB -ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm); - -/*! - * \addtogroup DMA_CCR Support for DMAMOV CCR - * - * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the - * dynamic microcode programming of the assembler directive: -\verbatim - -DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA<I|F>] - [SP<imm3>] [SC<imm4>] - [DB<1-16>] [DS<8|16|32|64|128>] [DA<I|F>] - [DP<imm3>] [DC<imm4>] - [ES<8|16|32|64|128>] - -\endverbatim -* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()). -* -* For example the assembler directive: -\verbatim -DMAMOV CCR SB1 SS32 DB1 DS32 -\endverbatim -* would be dynamically programmed with the following API call: -\verbatim -alt_dma_program_DMAMOV( pgm, - ALT_DMA_PROGRAM_REG_CCR, - ( ALT_DMA_CCR_OPT_SB1 - | ALT_DMA_CCR_OPT_SS32 - | ALT_DMA_CCR_OPT_SA_DEFAULT - | ALT_DMA_CCR_OPT_SP_DEFAULT - | ALT_DMA_CCR_OPT_SC_DEFAULT - | ALT_DMA_CCR_OPT_DB1 - | ALT_DMA_CCR_OPT_DS32 - | ALT_DMA_CCR_OPT_DA_DEFAULT - | ALT_DMA_CCR_OPT_DP_DEFAULT - | ALT_DMA_CCR_OPT_DC_DEFAULT - | ALT_DMA_CCR_OPT_ES8 - ) - ); -\endverbatim -* -* Each CCR option category should be specified regardless of whether it -* specifies a custom value or the normal default value (i.e. an -* ALT_DMA_CCR_OPT_*_DEFAULT. -* -* @{ -*/ - -/* - * Source Address {Fixed,Incrementing} - */ -/*! Source Address Fixed address burst. */ -#define ALT_DMA_CCR_OPT_SAF (0 << 0) -/*! Source Address Incrementing address burst. */ -#define ALT_DMA_CCR_OPT_SAI (1 << 0) -/*! Source Address Default value. */ -#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI - -/* - * Source burst Size (in bits) - */ -/*! Source burst Size of 8 bits. */ -#define ALT_DMA_CCR_OPT_SS8 (0 << 1) -/*! Source burst Size of 16 bits. */ -#define ALT_DMA_CCR_OPT_SS16 (1 << 1) -/*! Source burst Size of 32 bits. */ -#define ALT_DMA_CCR_OPT_SS32 (2 << 1) -/*! Source burst Size of 64 bits. */ -#define ALT_DMA_CCR_OPT_SS64 (3 << 1) -/*! Source burst Size of 128 bits. */ -#define ALT_DMA_CCR_OPT_SS128 (4 << 1) -/*! Source burst Size default bits. */ -#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8 - -/* - * Source burst Length (in transfer(s)) - */ -/*! Source Burst length of 1 transfer. */ -#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4) -/*! Source Burst length of 2 transfers. */ -#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4) -/*! Source Burst length of 3 transfers. */ -#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4) -/*! Source Burst length of 4 transfers. */ -#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4) -/*! Source Burst length of 5 transfers. */ -#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4) -/*! Source Burst length of 6 transfers. */ -#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4) -/*! Source Burst length of 7 transfers. */ -#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4) -/*! Source Burst length of 8 transfers. */ -#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4) -/*! Source Burst length of 9 transfers. */ -#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4) -/*! Source Burst length of 10 transfers. */ -#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4) -/*! Source Burst length of 11 transfers. */ -#define ALT_DMA_CCR_OPT_SB11 (0xa << 4) -/*! Source Burst length of 12 transfers. */ -#define ALT_DMA_CCR_OPT_SB12 (0xb << 4) -/*! Source Burst length of 13 transfers. */ -#define ALT_DMA_CCR_OPT_SB13 (0xc << 4) -/*! Source Burst length of 14 transfers. */ -#define ALT_DMA_CCR_OPT_SB14 (0xd << 4) -/*! Source Burst length of 15 transfers. */ -#define ALT_DMA_CCR_OPT_SB15 (0xe << 4) -/*! Source Burst length of 16 transfers. */ -#define ALT_DMA_CCR_OPT_SB16 (0xf << 4) -/*! Source Burst length default transfers. */ -#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1 - -/* - * Source Protection - */ -/*! Source Protection bits for AXI bus ARPROT[2:0]. */ -#define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8) -/*! Source Protection bits default value. */ -#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0) - -/* - * Source cache - */ -/*! Source Cache bits for AXI bus ARCACHE[2:0]. */ -#define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11) -/*! Source Cache bits default value. */ -#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0) - -/* - * Destination Address {Fixed,Incrementing} - */ -/*! Destination Address Fixed address burst. */ -#define ALT_DMA_CCR_OPT_DAF (0 << 14) -/*! Destination Address Incrementing address burst. */ -#define ALT_DMA_CCR_OPT_DAI (1 << 14) -/*! Destination Address Default value. */ -#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI - -/* - * Destination burst Size (in bits) - */ -/*! Destination burst Size of 8 bits. */ -#define ALT_DMA_CCR_OPT_DS8 (0 << 15) -/*! Destination burst Size of 16 bits. */ -#define ALT_DMA_CCR_OPT_DS16 (1 << 15) -/*! Destination burst Size of 32 bits. */ -#define ALT_DMA_CCR_OPT_DS32 (2 << 15) -/*! Destination burst Size of 64 bits. */ -#define ALT_DMA_CCR_OPT_DS64 (3 << 15) -/*! Destination burst Size of 128 bits. */ -#define ALT_DMA_CCR_OPT_DS128 (4 << 15) -/*! Destination burst Size default bits. */ -#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8 - -/* - * Destination Burst length (in transfer(s)) - */ -/*! Destination Burst length of 1 transfer. */ -#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18) -/*! Destination Burst length of 2 transfers. */ -#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18) -/*! Destination Burst length of 3 transfers. */ -#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18) -/*! Destination Burst length of 4 transfers. */ -#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18) -/*! Destination Burst length of 5 transfers. */ -#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18) -/*! Destination Burst length of 6 transfers. */ -#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18) -/*! Destination Burst length of 7 transfers. */ -#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18) -/*! Destination Burst length of 8 transfers. */ -#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18) -/*! Destination Burst length of 9 transfers. */ -#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18) -/*! Destination Burst length of 10 transfers. */ -#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18) -/*! Destination Burst length of 11 transfers. */ -#define ALT_DMA_CCR_OPT_DB11 (0xa << 18) -/*! Destination Burst length of 12 transfers. */ -#define ALT_DMA_CCR_OPT_DB12 (0xb << 18) -/*! Destination Burst length of 13 transfers. */ -#define ALT_DMA_CCR_OPT_DB13 (0xc << 18) -/*! Destination Burst length of 14 transfers. */ -#define ALT_DMA_CCR_OPT_DB14 (0xd << 18) -/*! Destination Burst length of 15 transfers. */ -#define ALT_DMA_CCR_OPT_DB15 (0xe << 18) -/*! Destination Burst length of 16 transfers. */ -#define ALT_DMA_CCR_OPT_DB16 (0xf << 18) -/*! Destination Burst length default transfers. */ -#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1 - -/* - * Destination Protection - */ -/*! Destination Protection bits for AXI bus AWPROT[2:0]. */ -#define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22) -/*! Destination Protection bits default value. */ -#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0) - -/* - * Destination Cache - */ -/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */ -#define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25) -/*! Destination Cache bits default value. */ -#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0) - -/* - * Endian Swap size (in bits) - */ -/*! Endian Swap: No swap, 8-bit data. */ -#define ALT_DMA_CCR_OPT_ES8 (0 << 28) -/*! Endian Swap: Swap bytes within 16-bit data. */ -#define ALT_DMA_CCR_OPT_ES16 (1 << 28) -/*! Endian Swap: Swap bytes within 32-bit data. */ -#define ALT_DMA_CCR_OPT_ES32 (2 << 28) -/*! Endian Swap: Swap bytes within 64-bit data. */ -#define ALT_DMA_CCR_OPT_ES64 (3 << 28) -/*! Endian Swap: Swap bytes within 128-bit data. */ -#define ALT_DMA_CCR_OPT_ES128 (4 << 28) -/*! Endian Swap: Default byte swap. */ -#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8 - -/*! Default CCR register options for a DMAMOV CCR assembler directive. */ -#define ALT_DMA_CCR_OPT_DEFAULT \ - (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \ - ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \ - ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \ - ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \ - ALT_DMA_CCR_OPT_ES8) - -/*! - * @} - */ - -/*! - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_DMA_PROGRAM_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h deleted file mode 100644 index 0a7abaef8e..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h +++ /dev/null @@ -1,1254 +0,0 @@ -/*! \file - * Altera - GPIO Module - */ - -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ALT_GPIO_H__ -#define __ALT_GPIO_H__ - -#include <stdint.h> -#include "hwlib.h" - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define ALT_GPIO_BITMASK 0x1FFFFFFF - -/* If the GPIO special test mode flag was not defined in the makefile, */ - /* set the ALT_GPIO_DATAREAD_TEST_MODE flag to false to specify that */ - /* the production code version of alt_gpio_port_data_read() is included. */ - /* If the flag is defined as true in the makefile, then the test version */ - /* located in the test code file is substituted instead of the version */ - /* in this file. */ -#ifndef ALT_GPIO_DATAREAD_TEST_MODE -#define ALT_GPIO_DATAREAD_TEST_MODE false -#endif - -/******************************************************************************/ -/*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API - * - * This module defines the General Purpose Input/Output Manager API for - * accessing, configuring, and controlling the General Purpose Input/Output - * Manager resources. These include both the general-purpose GPIO signals and - * the input-only GPI signals that are shared with the DDR interface.\n \n - * The GPIO API presents two views or perspectives of the GPIO signals. The first - * is to view the GPIO signals in a traditional way, as separate GPIO ports - * each comprised of a number of GPIO bits. The second perspective is of a - * unified flat view that presents the GPIO and GPI signals as a set of indexed - * bits, a view that allows the programmer to mostly ignore the port and pin - * hardware configuration and read/write/configure the GPIO and GPI signals - * independently of the underlying hardware implementation. - * - * @{ - */ - -/******************************************************************************/ -/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions - * - * This functional group contains functions to control, configure and manage - * the general-purpose IO signals as individual signals or as groups of signals. - * This group of functions can operate on multiple bits within the same GPIO - * port and accepts a bit mask to specify which bits an operation will operate on. - * Other bits within the same GPIO port are not changed. - * - * This example shows how multiple drivers or applications can use this feature - * to easily prevent conflict while accessing the same GPIO port: - * \verbatim - #define DRIVER_0_GPIO_MSK 0x0010FF03; - #define DRIVER_1_GPIO_MSK 0x002000F8; - #define DRIVER_2_GPIO_MSK 0x03C00004; - #define DRIVER_3_GPIO_MSK 0x000F0000; - - alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_0_GPIO_MSK, init_val0); - alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, init_val1); - alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_2_GPIO_MSK, init_val2); - alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_3_GPIO_MSK, init_val3); - alt_gpio_port_int_type_set(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, config_val1); - \endverbatim - * - * @{ - */ -/******************************************************************************/ -/*! - * This type definition enumerates the data direction (input or output) of - * the GPIO signals. - */ - -typedef enum ALT_GPIO_PIN_DIR_e -{ - /*! # */ - ALT_GPIO_PIN_INPUT, - /*! # */ - ALT_GPIO_PIN_OUTPUT -} ALT_GPIO_PIN_DIR_t; - -/******************************************************************************/ -/*! - * This type definition enumerates the type of interrupt source - * (level-triggered or edge-triggered) of the GPIO signals. - */ - -typedef enum ALT_GPIO_PIN_TYPE_e -{ - /*! # */ - ALT_GPIO_PIN_LEVEL_TRIG_INT, - /*! # */ - ALT_GPIO_PIN_EDGE_TRIG_INT -} ALT_GPIO_PIN_TYPE_t; - -/******************************************************************************/ -/*! - * This type definition enumerates the polarity of the interrupt sources - * (falling-edge or rising-edge for edge-triggered interrupts, active-low or - * active-high for level-triggered interrupts) of the GPIO signals. - */ - -typedef enum ALT_GPIO_PIN_POL_e -{ - /*! Indicates active-low for level-triggered interrupts and - * falling-edge for edge-triggered interrupts */ - ALT_GPIO_PIN_ACTIVE_LOW, - - /*! Indicates active-high for level-triggered interrupts and - * rising-edge for edge-triggered interrupt */ - ALT_GPIO_PIN_ACTIVE_HIGH -} ALT_GPIO_PIN_POL_t; - -/******************************************************************************/ -/*! - * This type definition enumerates whether or not the debounce metastability - * flip-flops are inserted or not. These are used to debounce signals presented - * to the GPIO inputs. A signal must be steady for two periods of the - * gpio_db_clk clock before it is considered valid. The frequency of the - * gpio_db_clk clock may be set using the Clock Manager API. - */ - -typedef enum ALT_GPIO_PIN_DEBOUNCE_e -{ - /*! # */ - ALT_GPIO_PIN_NODEBOUNCE, - /*! # */ - ALT_GPIO_PIN_DEBOUNCE -} ALT_GPIO_PIN_DEBOUNCE_t; - -/******************************************************************************/ -/*! - * This type definition enumerates whether or not level-sensitive interrupts - * are synchronized to the internal pclk_intr clock. It has no effect for GPIO - * signals that are selected as outputs, or if the interrupt is not enabled, - * or if the interrupt is set to be edge-triggered. This is a port-wide option. - */ - -typedef enum ALT_GPIO_PIN_SYNC_e -{ - /*! # */ - ALT_GPIO_PIN_NOSYNC, - /*! # */ - ALT_GPIO_PIN_SYNC -} ALT_GPIO_PIN_SYNC_t; - -/******************************************************************************/ -/*! - * This type definition enumerates the possible data states of the GPIO bits. - */ - -typedef enum ALT_GPIO_PIN_DATA_e -{ - /*! # */ - ALT_GPIO_PIN_DATAZERO, - /*! # */ - ALT_GPIO_PIN_DATAONE -} ALT_GPIO_PIN_DATA_t; - - -/******************************************************************************/ -/*! - * This type definition enumerates the GPIO ports that the GPIO manager - * handles. - */ - -typedef enum ALT_GPIO_PORT_e -{ - /*! - * \b Port \b A - 29-bit GPIO port A. - */ - ALT_GPIO_PORTA, - - /*! - * \b Port \b B - 29-bit GPIO port B. - */ - ALT_GPIO_PORTB, - - /*! - * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals, - * 14 bits are used for GPI-only signals that are shared - * with the DDR interface, 2 bits are not used. Some signals - * may not be connected on some versions. See the relevant - * pin mux data. - */ - ALT_GPIO_PORTC, - - /*! - * \b Unknown \b Port - Used to indicate an error. - */ - ALT_GPIO_PORT_UNKNOWN -} ALT_GPIO_PORT_t; - - -/******************************************************************************/ -/*! - * This type definition enumerates the individual bits within the GPIO ports - * used by the GPIO manager. The bit-ordering must match the hardware - * bit-ordering. Since the ordering and packing of bitfields is not - * standardized in C/C++, the following are defined as masks. \n - * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits - * had previously been set to outputs), the user could use the syntax: \par - * \b alt_gpio_port_data_write(\b ALT_GPIO_PORTB, \b ALT_GPIO_BIT3 \b | \b - * ALT_GPIO_BIT4); - */ - -typedef enum ALT_GPIO_PORTBIT_e -{ - /*! # */ - ALT_GPIO_BIT0 = ALT_TWO_TO_POW0, - /*! # */ - ALT_GPIO_BIT1 = ALT_TWO_TO_POW1, - /*! # */ - ALT_GPIO_BIT2 = ALT_TWO_TO_POW2, - /*! # */ - ALT_GPIO_BIT3 = ALT_TWO_TO_POW3, - /*! # */ - ALT_GPIO_BIT4 = ALT_TWO_TO_POW4, - /*! # */ - ALT_GPIO_BIT5 = ALT_TWO_TO_POW5, - /*! # */ - ALT_GPIO_BIT6 = ALT_TWO_TO_POW6, - /*! # */ - ALT_GPIO_BIT7 = ALT_TWO_TO_POW7, - /*! # */ - ALT_GPIO_BIT8 = ALT_TWO_TO_POW8, - /*! # */ - ALT_GPIO_BIT9 = ALT_TWO_TO_POW9, - /*! # */ - ALT_GPIO_BIT10 = ALT_TWO_TO_POW10, - /*! # */ - ALT_GPIO_BIT11 = ALT_TWO_TO_POW11, - /*! # */ - ALT_GPIO_BIT12 = ALT_TWO_TO_POW12, - /*! # */ - ALT_GPIO_BIT13 = ALT_TWO_TO_POW13, - /*! # */ - ALT_GPIO_BIT14 = ALT_TWO_TO_POW14, - /*! # */ - ALT_GPIO_BIT15 = ALT_TWO_TO_POW15, - /*! # */ - ALT_GPIO_BIT16 = ALT_TWO_TO_POW16, - /*! # */ - ALT_GPIO_BIT17 = ALT_TWO_TO_POW17, - /*! # */ - ALT_GPIO_BIT18 = ALT_TWO_TO_POW18, - /*! # */ - ALT_GPIO_BIT19 = ALT_TWO_TO_POW19, - /*! # */ - ALT_GPIO_BIT20 = ALT_TWO_TO_POW20, - /*! # */ - ALT_GPIO_BIT21 = ALT_TWO_TO_POW21, - /*! # */ - ALT_GPIO_BIT22 = ALT_TWO_TO_POW22, - /*! # */ - ALT_GPIO_BIT23 = ALT_TWO_TO_POW23, - /*! # */ - ALT_GPIO_BIT24 = ALT_TWO_TO_POW24, - /*! # */ - ALT_GPIO_BIT25 = ALT_TWO_TO_POW25, - /*! # */ - ALT_GPIO_BIT26 = ALT_TWO_TO_POW26, - /*! # */ - ALT_GPIO_BIT27 = ALT_TWO_TO_POW27, - /*! # */ - ALT_GPIO_BIT28 = ALT_TWO_TO_POW28, - ALT_GPIO_BIT29 = ALT_TWO_TO_POW29, /* Not currently used */ - ALT_GPIO_BIT30 = ALT_TWO_TO_POW30, /* Not currently used */ - ALT_GPIO_BIT31 = (int32_t) (1UL<<31), /* Not currently used */ - - ALT_GPIO_BITNUM_MAX = (28), - ALT_GPIO_BIT_MAX = (1 << ALT_GPIO_BITNUM_MAX), - ALT_END_OF_GPIO_PORT_SIGNALS = (32) -} ALT_GPIO_PORTBIT_t; - - - -/******************************************************************************/ -/*! - * Initialize the GPIO modules before use - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_gpio_init(void); - -/******************************************************************************/ -/*! - * Uninitialize the GPIO modules & return to reset state - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_gpio_uninit(void); - -/******************************************************************************/ -/*! - * Sets the specified GPIO data bits to use the data direction(s) - * specified. - * - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (where mask bits equal one) to apply this - * operation to. Other bits (where mask bits equal zero) are - * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to - * configure all data direction bits of the port. - * \param config - * The data-directions of the bits to be set in this operation. - * Individual bits are: \n \b 0 - Use as an input (default). \n - * \b 1 - Use as an output. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Bad input argument. - */ -ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask, uint32_t config); - -/******************************************************************************/ -/*! - * Returns the data direction configuration of selected bits of the - * specified GPIO module. - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (where mask bits equal one) to read and - * return. Other bits (where mask bits equal zero) are returned - * as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to - * return all data direction bits of the port. - * - * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is - * configured as an input. - * \n \b 1 - The signal is configured as an output. - * - */ -uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask); - -/******************************************************************************/ -/*! - * Sets the GPIO data outputs of the specified GPIO module to a logic one or - * zero. Outputs are only set if the data direction for those bits is also - * set to configure them as outputs. - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (mask bits equal one) to apply this - * operation to. Other bits (mask bits equal zero) are - * not changed. - * \param val - * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs - * are used. Setting the three MSBs causes an error. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Bad input argument. - */ -ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask, uint32_t val); - -/******************************************************************************/ -/*! - * Returns the value of the data inputs of the specified GPIO module. This is - * the current logic value of the pin, whether set to be an input or an output. - * \n If a given signal is set to be an output, this input value can be read to - * determine if the pin is grounded, pulled high, or is floating. - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify - * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of - * the port. - * - * \retval uint32_t The current value of the GPIO module input signals. - */ -uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask); - - -/*! @} */ -/******************************************************************************/ -/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions - * - * This functional group contains functions to control and manage the - * interrupts of the General-Purpose IO modules. - * - * @{ - */ -/******************************************************************************/ -/*! - * Sets edge-triggered or level-triggered interrupt configuration for the - * specified signals of the specified GPIO module. - * - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (where mask bits equal one) to apply this - * operation to. Other bits (where mask bits equal zero) are - * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to - * configure all interrupt type bits of the port. - * \param config - * The interrupt configuration to write. Individual bits - * are: \n \b 0 - Set the - * interrupt for this bit to be level-sensitive (default). \n \b - * 1 - Set the interrupt for this bit to be edge-sensitive. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input data. - */ -ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask, uint32_t config); - -/******************************************************************************/ -/*! - * Returns the interrupt configuration (edge-triggered or level-triggered) for - * the specified bits of the specified GPIO module. - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify - * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration - * bits of the port. - * \retval uint32_t - * The current interrupt source configuration. Individual bits - * are: \n \b 0 - The interrupt for this bit is set to be - * level-sensitive. \n \b 1 - - * The interrupt for this bit is set to be edge-sensitive. - * - */ -uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask); - -/******************************************************************************/ -/*! - * Sets the interrupt polarity of the signals of the specified GPIO register - * (when used as inputs) to active-high or active-low (for level-sensitive - * interrupts) or to rising-edge or falling-edge (for edge-sensitive interrupts). - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (where mask bits equal one) to apply this - * operation to. Other bits (where mask bits equal zero) are - * not changed. - * \param config - * The interrupt polarity configuration to set. Individual bits - * are: \n \b 0 - Set the interrupt polarity for this bit to - * active-low or falling-edge mode (default). \n \b 1 - Set the - * interrupt polarity for this bit to active-high or rising-edge mode. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input data. - */ -ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask, uint32_t config); - -/******************************************************************************/ -/*! - * Returns the active-high or active-low polarity configuration for the - * possible interrupt sources of the specified GPIO module. - * - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify - * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the - * configuration bits of the port. - * - * \retval uint32_t - * The current polarity configuration. Individual bits are: \n - * \b 0 = The interrupt polarity for this bit is set to - * active-low or falling-edge mode. \n \b 1 = The interrupt - * polarity for this bit is set to active-high or rising-edge mode. - * - */ -uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask); - - -/*! @} */ -/******************************************************************************/ -/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions - * - * @{ - */ -/******************************************************************************/ -/*! - * Sets the debounce configuration for input signals of the specified GPIO - * module. If debounce is selected, metastability flip-flops are inserted to - * debounce signals presented to the GPIO inputs. A signal must be steady for - * two periods of the gpio_db_clk clock before it is considered valid. The - * frequency of the gpio_db_clk clock may be set using the Clock Manager API. - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (where mask bits equal one) to apply this - * operation to. Other bits (where mask bits equal zero) are - * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to - * configure the debounce setting for all bits of the port. - * \param config - * The debounce configuration to set. Individual bits are: \n - * \b 0 - Debounce is not selected for this signal (default). \n - * \b 1 - Debounce is selected for this signal. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input data. - */ -ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask, uint32_t config); - -/******************************************************************************/ -/*! - * Returns the debounce configuration for the input signals of the specified - * GPIO register. If debounce is selected, metastability flip-flops are - * inserted to debounce signals presented to the GPIO inputs. - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits (where mask bits equal one) to return. Other - * bits (where mask bits equal zero) are returned as zero. Specify - * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce - * configuration bits of the port. - * - * \retval uint32_t - * The current debounce configuration.Individual bits are: \n - * \b 0 - Debounce is not selected for this signal. \n \b 1 - - * Debounce is selected for this signal. - * - */ -uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask); - -/******************************************************************************/ -/*! - * Sets the synchronization configuration for the signals of the specified - * GPIO register. This allows for synchronizing level-sensitive interrupts to - * an internal clock signal. This is a port-wide option that controls all - * level-sensitive interrupt signals of that GPIO port. - * - * \param gpio_pid - * The GPIO port identifier. - * \param config - * \n \b Any \b non-zero \b value - Synchronize to internal clock signal. - * \n \b Zero - Do not synchronize to internal clock signal. - * - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input data. - */ -ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, - uint32_t config); - -/******************************************************************************/ -/*! - * - * Returns the synchronization configuration for the signals of the - * specified GPIO register. This allows for synchronizing level-sensitive - * interrupts to the internal clock signal. This is a port-wide option that - * controls all level-sensitive interrupt signals of that GPIO port. - * - * \param gpio_pid - * The GPIO port identifier. - - - * \retval ALT_E_TRUE Synchronization to clock is enabled for - * level-sensitive interrupts. - * \retval ALT_E_FALSE Synchronization to clock is disabled for - * level-sensitive interrupts. - * \retval ALT_E_BAD_ARG Invalid input argument. - */ -ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid); - -/******************************************************************************/ -/*! - * Configures a group of GPIO signals with identical setup parameters. Allows - * for configuring all parameters of a given port at one time. - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * The group of bits to apply this operation to. Other bits (mask - * set to zero) are not changed. - * \param dir - * Data direction. - * \param type - * Edge-triggered or level-triggered interrupts. - * \param pol - * Active-high or active-low polarity. - * \param debounc - * Debounce signals or not. - * \param data - * Set the data output to this value. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input argument. - - */ -ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, - ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc, - uint32_t data); - -/*! @} */ -/******************************************************************************/ -/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions - * - * @{ - */ -/******************************************************************************/ -/*! - * Enables the specified GPIO data input interrupts. - * - * - * \param gpio_pid - * The GPIO port identifier. - * \param config - * Individual bit interrupt enables \n - * \b 0 - Interrupt disabled. \n - * \b 1 - Interrupt enabled. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Bad input argument. - */ -ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config); - -/******************************************************************************/ -/*! - * Disables the specified GPIO data module interrupt. - * - * - * \param gpio_pid - * The GPIO port identifier. - * \param config - * Individual bit interrupt enables \n - * \b 0 - Interrupt disabled. \n - * \b 1 - Interrupt enabled. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Bad input argument. - */ -ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config); - -/******************************************************************************/ -/*! - * Returns the current state of the specified GPIO port interrupts enables. - * - * \param gpio_pid - * The GPIO port identifier. - * - * \retval uint32_t - * The interrupt enable configuration that was read. Individual bits - * are: \n \b 0 = The interrupt for this bit is not enabled. \n \b - * 1 = The interrupt for this bit is enabled. - */ -uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid); - - -/******************************************************************************/ -/*! - * Masks or unmasks selected interrupt source bits of the data register of - * the specified GPIO module. Uses a second bit mask to determine which - * signals may be changed by this call. - * - * - * \param gpio_pid - * The GPIO port identifier. - * \param mask - * Which bits to change among the port \n \b 0 = - * Do not change this bit. \n \b 1 = Allow this bit to change. - * \param val - * The interrupt mask to write. Individual bits are: \n \b 0 = - * Do not mask the interrupt for this bit (default). \n \b 1 = - * Mask the interrupt for this bit. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input data. - */ -ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid, - uint32_t mask, uint32_t val); - -/******************************************************************************/ -/*! - * Returns the interrupt mask of the specified GPIO module. - * - * - * \param gpio_pid - * The GPIO port identifier. - * - * \retval uint32_t - * The interrupt mask that was read. Individual bits are: \n - * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The - * interrupt for this bit is masked. - * - */ -uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid); - -/******************************************************************************/ -/*! - * Returns the interrupt pending status of all signals of the specified GPIO - * register. - * - * - * \param gpio_pid - * The GPIO port identifier. - - * \retval uint32_t - * The current interrupt pending status. Individual bits are: \n - * \b 0 - The interrupt for this bit is not pending. \n \b 1 - - * The interrupt for this bit is pending. - * - */ -uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid); - -/******************************************************************************/ -/*! - * Clear the interrupt pending status of selected signals of the - * specified GPIO register. - * - * - * \param gpio_pid - * The GPIO port identifier. - * \param clrmask - * The interrupt bits to clear. Individual bits are: \n \b 0 - - * The interrupt for this bit will not be changed. \n \b 1 - - * The interrupt for this bit will be cleared. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input data. - */ -ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid, - uint32_t clrmask); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index - * - * This functional group presents a perspective of the General-Purpose IO - * signals as individual GPIO and GPI bits spread across a number of signals - * across several GPIO ports. This allows the programmer the freedom to generally - * ignore the underlying port and signal structure of the GPIO hardware if - * desired. - * - * @{ - */ -/******************************************************************************/ -/*! - * This type definition enumerates the individual bits as one flat array spread - * across the multiple GPIO ports handled by the GPIO manager. The bit-ordering - * must match the hardware bit-ordering. - * - */ -typedef enum ALT_GPIO_1BIT_e -{ - /*! # */ - ALT_GPIO_1BIT_0, - /*! # */ - ALT_GPIO_1BIT_1, - /*! # */ - ALT_GPIO_1BIT_2, - /*! # */ - ALT_GPIO_1BIT_3, - /*! # */ - ALT_GPIO_1BIT_4, - /*! # */ - ALT_GPIO_1BIT_5, - /*! # */ - ALT_GPIO_1BIT_6, - /*! # */ - ALT_GPIO_1BIT_7, - /*! # */ - ALT_GPIO_1BIT_8, - /*! # */ - ALT_GPIO_1BIT_9, - /*! # */ - ALT_GPIO_1BIT_10, - /*! # */ - ALT_GPIO_1BIT_11, - /*! # */ - ALT_GPIO_1BIT_12, - /*! # */ - ALT_GPIO_1BIT_13, - /*! # */ - ALT_GPIO_1BIT_14, - /*! # */ - ALT_GPIO_1BIT_15, - /*! # */ - ALT_GPIO_1BIT_16, - /*! # */ - ALT_GPIO_1BIT_17, - /*! # */ - ALT_GPIO_1BIT_18, - /*! # */ - ALT_GPIO_1BIT_19, - /*! # */ - ALT_GPIO_1BIT_20, - /*! # */ - ALT_GPIO_1BIT_21, - /*! # */ - ALT_GPIO_1BIT_22, - /*! # */ - ALT_GPIO_1BIT_23, - /*! # */ - ALT_GPIO_1BIT_24, - /*! # */ - ALT_GPIO_1BIT_25, - /*! # */ - ALT_GPIO_1BIT_26, - /*! # */ - ALT_GPIO_1BIT_27, - /*! # */ - ALT_GPIO_1BIT_28, - /*! # */ - ALT_GPIO_1BIT_29, - /*! # */ - ALT_GPIO_1BIT_30, - /*! # */ - ALT_GPIO_1BIT_31, - /*! # */ - ALT_GPIO_1BIT_32, - /*! # */ - ALT_GPIO_1BIT_33, - /*! # */ - ALT_GPIO_1BIT_34, - /*! # */ - ALT_GPIO_1BIT_35, - /*! # */ - ALT_GPIO_1BIT_36, - /*! # */ - ALT_GPIO_1BIT_37, - /*! # */ - ALT_GPIO_1BIT_38, - /*! # */ - ALT_GPIO_1BIT_39, - /*! # */ - ALT_GPIO_1BIT_40, - /*! # */ - ALT_GPIO_1BIT_41, - /*! # */ - ALT_GPIO_1BIT_42, - /*! # */ - ALT_GPIO_1BIT_43, - /*! # */ - ALT_GPIO_1BIT_44, - /*! # */ - ALT_GPIO_1BIT_45, - /*! # */ - ALT_GPIO_1BIT_46, - /*! # */ - ALT_GPIO_1BIT_47, - /*! # */ - ALT_GPIO_1BIT_48, - /*! # */ - ALT_GPIO_1BIT_49, - /*! # */ - ALT_GPIO_1BIT_50, - /*! # */ - ALT_GPIO_1BIT_51, - /*! # */ - ALT_GPIO_1BIT_52, - /*! # */ - ALT_GPIO_1BIT_53, - /*! # */ - ALT_GPIO_1BIT_54, - /*! # */ - ALT_GPIO_1BIT_55, - /*! # */ - ALT_GPIO_1BIT_56, - /*! # */ - ALT_GPIO_1BIT_57, - /*! # */ - ALT_GPIO_1BIT_58, - /*! # */ - ALT_GPIO_1BIT_59, - /*! # */ - ALT_GPIO_1BIT_60, - /*! # */ - ALT_GPIO_1BIT_61, - /*! # */ - ALT_GPIO_1BIT_62, - /*! # */ - ALT_GPIO_1BIT_63, - /*! # */ - ALT_GPIO_1BIT_64, - /*! # */ - ALT_GPIO_1BIT_65, - /*! # */ - ALT_GPIO_1BIT_66, - /*! # */ - ALT_GPIO_1BIT_67, /* Not bonded out on some versions */ - /*! # */ - ALT_GPIO_1BIT_68, /* Not bonded out on some versions */ - /*! # */ - ALT_GPIO_1BIT_69, /* Not bonded out on some versions */ - - /*! The last of the input/output bits */ - ALT_GPIO_1BIT_70, /* Not bonded out on some versions */ - - - /*! This and the following signals are not present on all SoCs. \n - * If present, the selection between their use as 14 General-purpose inputs or - * use as 14 DDR interface signals is made in the IOCSR (IO Configuration Shift - * Register) and software to make this selection is in the IO Manager API. If - * they are present, they are restricted to using the same power supply voltage - * as the SDRAM module.*/ - ALT_HLGPI_0, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_1, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_2, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_3, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_4, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_5, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_6, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_7, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_8, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_9, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_10, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_11, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_12, /* Not bonded out on some versions */ - /*! # */ - ALT_HLGPI_13, /* Not bonded out on some versions */ - - ALT_HLGPI_14, /* Not bonded out */ - - ALT_HLGPI_15, /* Not bonded out */ - - ALT_GPIO_INVALID, - ALT_END_OF_GPIO_SIGNALS = -1, - ALT_LAST_VALID_GPIO_BIT = ALT_HLGPI_15 -} ALT_GPIO_1BIT_t; - - -/******************************************************************************/ -/*! - * This configuration record definition is used for configuring bits and - * groups of bits of the GPIO interface. - */ -typedef struct ALT_GPIO_CONFIG_RECORD_s -{ - /*! - * The index number of the signal to configure. */ - ALT_GPIO_1BIT_t signal_number; - /*! - * The data direction of the signal. */ - ALT_GPIO_PIN_DIR_t direction; - /*! - * Edge-triggered or level triggered interrupts. */ - ALT_GPIO_PIN_TYPE_t type; - /*! - * Active-high or active-low trigger for the interrupt. */ - ALT_GPIO_PIN_POL_t polarity; - /*! - * Enable or disable GPIO debounce capability. */ - ALT_GPIO_PIN_DEBOUNCE_t debounce; - /*! - * If the signal is an output, the data value to be output. */ - ALT_GPIO_PIN_DATA_t data; -} ALT_GPIO_CONFIG_RECORD_t; - -/******************************************************************************/ -/*! - * This pin record type definition is comprised of the signal index and - * associated input or output data. - */ -typedef struct ALT_GPIO_PIN_RECORD_s -{ - /*! - * The index number of the signal. */ - ALT_GPIO_1BIT_t signal_number; - /*! - * Data - zero or one. */ - ALT_GPIO_PIN_DATA_t val; -} ALT_GPIO_PIN_RECORD_t; - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index - * - * @{ - */ -/******************************************************************************/ -/*! - * Configures all parameters for one bit (signal) of the GPIO ports. - * - * \param signal_num - * The GPIO port signal index. - * \param dir - * The data direction for this signal. - * \param type - * Edge-triggered or Level-triggered interrupt for this signal. - * \param pol - * Active-high or active-low interrupt polarity for this signal. - * \param debounce - * Enable the debounce flip-flops for this signal or not. - * \param data - * If the GPIO signal is set to be an output, set it to - * this value - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input argument. - */ -ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num, - ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type, - ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce, - ALT_GPIO_PIN_DATA_t data); - -/******************************************************************************/ -/*! - * Returns the configuration parameters of a given GPIO bit. - * - * \param signal_num - * The GPIO port signal index. - * \param config - * Pointer to a single GPIO_CONFIG_RECORD_s configuration record. - * The fields of this configuration record are filled in - * by the function. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input argument. - - */ -ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num, - ALT_GPIO_CONFIG_RECORD_t *config); - -/******************************************************************************/ -/*! - * Configures a list of GPIO bits. The GPIO bits do not have to be - * configured the same, as was the case for the mask version of this function, - * alt_gpio_port_config(). Each bit may be configured differently and bits may - * be listed in any order. - * - * \param config_array - * Pointer to an array of GPIO_CONFIG_RECORD_s configuration - * records. These definitions contain all the parameters - * needed to set up the listed pins. All or - * any subset of the GPIO signals can be configured. Signals do - * not have to be listed in numerical order or be unique. If a - * signal number is listed multiple times, the last configuration - * listed is used. \n Configuration terminates either when \b len - * signals have been configured or if the next signal number index - * in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1). - * - * \param len - * Length of array to configure. - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input argument. - - */ -ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, - uint32_t len); - -/******************************************************************************/ -/*! - * Returns a list of the pin signal indices and the associated configuration - * settings (data direction, interrupt type, polarity, and debounce) of that - * list of signals. - * - * \param config_array - * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration - * records. Only the signal indices in the first field of each - * configuration record need be filled in. This function will - * fill in all the other fields of the configuration record, - * returning all configuration parameters in the array. - * Signals do not have to be listed in numerical order or be - * unique. If a signal number is listed multiple times, the - * configuration record will contain multiple entries for - * that signal. \n Configuration reading terminates either when - * \b len signal configurations have been read or if the next - * signal number index in the array is equal to - * \b ALT_END_OF_GPIO_SIGNALS (-1). - * \param len - * Length of configuration array to read and return. - * - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input argument. - - */ -ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array, - uint32_t len); - -/******************************************************************************/ -/*! - * Returns a list of the pin signal indices and the associated configuration - * settings (data direction, interrupt type, polarity, and debounce) of that - * list of signals. The difference between this version and - * alt_gpio_group_config_get() is this version follows a separate list of - * signal indices instead of having the signal list provided in the first - * field of the configuration records in the array. - * - * \param pinid_array - * Pointer to a list of signal index numbers. These indices - * are copied to the first field of each configuration record - * in the returned array. - * \param config_array - * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration - * records. This function will fill in the fields of the - * configuration record, returning all configuration parameters - * in the array. Signals do not have to be listed in numerical - * order or be unique. If a signal number is listed multiple - * times, the configuration record array will contain multiple - * identical entries for that signal. \n Configuration reading - * terminates either when \b len signal configurations have been - * read or if the next signal number index in the array is equal - * to \b ALT_END_OF_GPIO_SIGNALS (-1). - * \param len - * Length of configuration array to read. - * - * - * \retval ALT_E_SUCCESS The operation was successful. - * \retval ALT_E_ERROR The operation failed. - * \retval ALT_E_BAD_ARG Invalid input argument. - * - */ -ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array, - ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len); - - -/*! @} */ -/******************************************************************************/ -/*! \addtogroup ALT_GPIO_UTILITY General-Purpose IO Utility Functions - * - * These are useful utility functions for the general-purpose input & output - * module. - * - * @{ */ -/******************************************************************************/ -/*! - * Returns the ID code of the specified GPIO module. - * - * \param gpio_pid - * The GPIO port identifier. - * - * - * \retval uint32_t The component code of the module, GPIO_MODULE_IDCODE. - */ -uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid); - -/******************************************************************************/ -/*! - * Returns the version code of the specified GPIO module. - * - * \param gpio_pid - * The GPIO port identifier. - * - * - * \retval uint32_t The encoded revision number of the module. - */ -uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid); - - -/******************************************************************************/ -/*! - * Extracts the GPIO port ID from the supplied GPIO Signal Index Number. - */ -ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num); - - -/******************************************************************************/ -/*! - * Extracts the GPIO signal (pin) offset from the supplied GPIO Signal Index - * Number. - * */ -ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num); - -/******************************************************************************/ -/*! - * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and - * signal mask. If passed a bitmask composed of more than one signal, the - * signal number of the lowest bit in the bitmask presented is returned. - * - */ -ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid, - uint32_t bitmask); - - -/*! @} */ -/*! @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALT_GPIO_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h deleted file mode 100644 index 7596d50d66..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h +++ /dev/null @@ -1,56 +0,0 @@ -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ALT_HWLIBS_VER_H__ - -/*********************************************************************** - * - * Set of macros to provide version information - * - ***********************************************************************/ - -/* This is the major revision of the Altera ACDS Release */ -#define ALTERA_ACDS_MAJOR_REV 13 - -/* This is the minor revision of the Altera ACDS Release */ -#define ALTERA_ACDS_MINOR_REV 1 - -/* This is an internal HwLibs revision/feature control code. */ -/* End-users should NOT depend upon the value of this field */ -#define ALTERA_HWLIBS_REV 0 - -/* This is a text string containing the current release and service pack IDs */ -#define ALTERA_ACDS_REV_STR "13.1" - -/* This is a text string containing the current SoC EDS ID */ -#define ALTERA_SOCEDS_REV_STR "Altera SoC Embedded Design Suite v13.1" - - -#endif /* __ALT_HWLIBS_VER_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_i2c.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_i2c.h deleted file mode 100644 index 7af55cf4ac..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_i2c.h +++ /dev/null @@ -1,2024 +0,0 @@ -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -/*! \file - * Altera - I2C Controller API - */ - -#ifndef __ALT_I2C_H__ -#define __ALT_I2C_H__ - -#include "hwlib.h" -#include "alt_clock_manager.h" -#include "socal/alt_i2c.h" -#include "socal/alt_rstmgr.h" -#include "socal/hps.h" -#include "socal/socal.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/******************************************************************************/ -/*! \addtogroup ALT_I2C I2C Controller API - * - * This module defines an API for configuring and managing the HPS I2C controllers. - * - * The I2C controller provides support for a communication link between integrated - * circuits on a board. It is a simple two-wire bus which consists of a serial - * data line (SDA) and a serial clock (SCL) for use in applications such as - * temperature sensors and voltage level translators to EEPROMs, A/D and D/A - * converters, CODECs, and many types of microprocessors. - * - * The Hard Processor System (HPS) provides four I2C controllers to enable system - * software to communicate serially with I2C buses. Each I2C controller can - * operate in master or slave mode, and support standard mode of up to 100 - * kilobits per second (Kbps) or fast mode of up to 400 Kbps. These I2C - * controllers are instances of the Synopsys DesignWare APB I2C (DW_apb_i2c) - * controller. - * - * NOTE: Each I2C controller must be programmed to operate in either master or - * slave mode only. Operating as a master and slave simultaneously is not - * supported. - * - * Features of the I2C Controller: - * * Support both 100 KBps and 400 KBps modes - * * One of the following I2C operations: master or slave - * * Support both 7-bit and 10-bit addressing modes - * * Mixed read and write combined-format transactions - * * Bulk transmit mode - * * DMA handshaking interface - * - * For a complete details on the configuration and operation of I2C controller, - * consult the following references: - * * <em>Cyclone V Device Handbook Volume 3: Hard Processor System Technical - * Reference Manual, Chapter 20. I2C Controller (cv_54020-1.2)</em> - * * <em>Synopsys DesignWare DW_apb_i2c Databook DW_apb_i2c, Version 1.15a</em> - * * <em>The I2C-Bus Specification Version 2.1</em> - * - * @{ - */ - -/******************************************************************************/ -/*! - * This type definition enumerates the operational state of I2C by - * transfer operation. - */ -typedef enum ALT_I2C_TRANSFER_TYPE_e -{ - ALT_I2C_TRANSFER_NONE = 0, /*!< No transfer operation */ - ALT_I2C_TRANSFER_START = 1, /*!< Start detect */ - ALT_I2C_TRANSFER_COMPLETE = 2, /*!< All operations done */ - ALT_I2C_TRANSFER_READ = 3, /*!< Read operation is active */ - ALT_I2C_TRANSFER_WRITE = 4, /*!< Write operation is active */ -} -ALT_I2C_TRANSFER_TYPE_t; - - -/* - * A pointer or handle to the I2C controller device instance. The ALT_I2C_DEV_t is - * initialized by a call to alt_i2c_init() and subsequently used by the other I2C - * controller API functions as a reference to a specific device. - * - * \internal - * ALT_I2C_DEV_t may be a struct or reference to an opaque data - * structure. Whatever "internal" type is suited to the needs of the - * implementation. - * \endinternal - */ -typedef struct ALT_I2C_DEV_s -{ - void * location; /*!< HPS address of I2C instance. */ - alt_freq_t clock_freq; /*!< Input clock frequency. */ - uint32_t last_target; /*!< Last issued target address. */ -} -ALT_I2C_DEV_t; - -/*! - * This type enumerates the HPS I2C controller instances. - */ -typedef enum ALT_I2C_CTLR_e -{ - ALT_I2C_I2C0 = (int)ALT_I2C0_OFST, /*!< I2C0 instance. */ - ALT_I2C_I2C1 = (int)ALT_I2C1_OFST, /*!< I2C1 instance. */ - ALT_I2C_I2C2 = (int)ALT_I2C2_OFST, /*!< I2C2 instance. */ - ALT_I2C_I2C3 = (int)ALT_I2C3_OFST, /*!< I2C3 instance. */ -} ALT_I2C_CTLR_t; - -/*! - * This type enumerates the modes that the I2C controller may operate in. - * - * NOTE: Each I2C controller must be programmed to operate in either master or - * slave mode only. Operating as a master and slave simultaneously is not - * supported. - */ -typedef enum ALT_I2C_MODE_e -{ - ALT_I2C_MODE_SLAVE = ALT_I2C_CON_MST_MOD_E_DIS, /*!< Slave Mode */ - ALT_I2C_MODE_MASTER = ALT_I2C_CON_MST_MOD_E_EN /*!< Master Mode */ -} ALT_I2C_MODE_t; - -/*! - * This type enumerates the I2C controller operational speed modes. - * - * The I2C controller can operate in standard mode (with data rates 0 to 100 Kbps) - * or fast mode (with data rates less than or equal to 400 Kbps). Additionally, - * fast mode devices are downward compatible. For instance, fast mode devices can - * communicate with standard mode devices in 0 to 100 Kbps I2C bus - * system. However, standard mode devices are not upward compatible and should not - * be incorporated in a fast-mode I2C bus system as they cannot follow the higher - * transfer rate and therefore unpredictable states would occur. - * - * This setting is relevant only if one is operating the I2C in master mode. - */ -typedef enum ALT_I2C_SPEED_e -{ - ALT_I2C_SPEED_STANDARD = ALT_I2C_CON_SPEED_E_STANDARD, - /*!< Standard mode (0 to 100 Kbps) */ - ALT_I2C_SPEED_FAST = ALT_I2C_CON_SPEED_E_FAST - /*!< Fast mode (<= 400 Kbps) */ -} ALT_I2C_SPEED_t; - -/*! - * This type enumerates the two addressing modes formats supported by the I2C - * controller. - * - * The I2C controller does not support mixed address format - that is, a 7-bit - * address transaction followed by a 10-bit address transaction or vice versa - - * combined format transactions. - */ -typedef enum ALT_I2C_ADDR_MODE_e -{ - ALT_I2C_ADDR_MODE_7_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START7, - /*!< 7-Bit Address Format */ - ALT_I2C_ADDR_MODE_10_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 - /*!< 10-Bit Address Format */ -} ALT_I2C_ADDR_MODE_t; - -/*! - * This type enumerates interrupt status conditions for the I2C controller. - */ -typedef enum ALT_I2C_STATUS_e -{ - ALT_I2C_STATUS_RX_UNDER = 1UL << 0, - /*!< Set if the processor attempts to read the - * receive buffer when it is empty. If the I2C - * controller is disabled, this status keeps - * maintains its state until the master or slave - * state machines go into idle, then this - * interrupt is cleared. - */ - ALT_I2C_STATUS_RX_OVER = 1UL << 1, - /*!< Set if the receive buffer is completely - * filled to capacity and an additional byte is - * received from an external I2C device. The I2C - * controller acknowledges this, but any data - * bytes received after the FIFO is full are - * discarded. If the I2C controller is disabled, - * this status maintains its statue until the - * master or slave state machines go into idle, - * then this interrupt is cleared. - */ - ALT_I2C_STATUS_RX_FULL = 1UL << 2, - /*!< Set when the receive buffer reaches or goes - * above the RX_TL threshold. It is - * automatically cleared by hardware when buffer - * level goes below the threshold. If the I2C - * controller is disabled, the RX FIFO is - * flushed and held in reset; therefore the RX - * FIFO is not full. So this bit is cleared once - * the I2C controller is disabled, regardless of - * the activity that continues. - */ - ALT_I2C_STATUS_TX_OVER = 1UL << 3, - /*!< Set during transmit if the transmit buffer is - * filled to capacity and the processor attempts - * to issue another I2C command. When the I2C - * controller is disabled, this bit maintains - * its state until the master or slave state - * machines go into idle, then this interrupt is - * cleared. - */ - ALT_I2C_STATUS_TX_EMPTY = 1UL << 4, - /*!< This bit is set to 1 when the transmit buffer - * is at or below the configured threshold - * value. It is automatically cleared by - * hardware when the buffer level goes above the - * threshold. When the I2C controller is - * disabled, the TX FIFO is flushed and held in - * reset. The TX FIFO appears as if it has no - * data in it, so this bit is set to 1, provided - * there is activity in the master or slave - * state machines. When there is no longer - * activity, then this bit is set to 0. - * - */ - ALT_I2C_STATUS_RD_REQ = 1UL << 5, - /*!< This bit is set to 1 when I2C is acting as a - * slave and another I2C master is attempting to - * read data from the I2C. The I2C holds the bus - * in a wait state until this interrupt is - * serviced, which means that the slave has been - * addressed by a remote master that is asking - * for data to be transferred. The processor - * must respond to this interrupt and then write - * the requested data. This bit is set to 0 just - * after the processor by calling - * alt_i2c_int_clear() with - * ALT_I2C_STATUS_RD_REQ in the mask.. - */ - ALT_I2C_STATUS_TX_ABORT = 1UL << 6, - /*!< This bit indicates if I2C, as an I2C - * transmitter, is unable to complete the - * intended actions on the contents of the - * transmit FIFO. This situation can occur both - * as an I2C master or an I2C slave, and is - * referred to as a 'transmit abort'. When this - * bit is set to 1, the IC_TX_ABRT_SOURCE - * register indicates the reason why the - * transmit abort takes places. - * - * NOTE: The I2C flushes/resets/empties the TX - * FIFO whenever this bit is set. The TX FIFO - * remains in this flushed state until the - * register alt_i2c_int_clear() with - * ALT_I2C_STATUS_TX_ABORT in the mask is - * called. Once this happens, the TX FIFO is - * then ready to accept more data bytes from the - * APB interface. - */ - ALT_I2C_STATUS_RX_DONE = 1UL << 7, - /*!< When the I2C is acting as a - * slave-transmitter, this bit is set to 1 if - * the master does not acknowledge a transmitted - * byte. This occurs on the last byte of the - * transmission, indicating that the - * transmission is done. - */ - ALT_I2C_STATUS_ACTIVITY = 1UL << 8, - /*!< This bit captures I2C activity and stays set - * until it is cleared. There are four ways to - * clear it: - * * Disabling the I2C controller - * * Calling alt_i2c_int_clear() with - * ALT_I2C_STATUS_ACTIVITY in the mask. - * * Calling alt_i2c_int_clear() with - * ALT_I2C_STATUS_ALL in the mask. - * * System reset - * - * Once this bit is set, it stays set unless one - * of the four methods is used to clear it. Even - * if the I2C module is idle, this bit remains - * set until cleared, indicating that there was - * activity on the bus. - */ - ALT_I2C_STATUS_STOP_DET = 1UL << 9, - /*!< Indicates whether a STOP condition has - * occurred on the I2C interface regardless of - * whether I2C is operating in slave or master - * mode. - */ - ALT_I2C_STATUS_START_DET = 1UL << 10, - /*!< Indicates whether a START or RESTART - * condition has occurred on the I2C interface - * regardless of whether I2C is operating in - * slave or master mode. - */ - ALT_I2C_STATUS_INT_CALL = 1UL << 11, - /*!< Set only when a General Call address is - * received and it is acknowledged. It stays set - * until it is cleared either by disabling I2C - * or when alt_i2c_int_clear() with - * ALT_I2C_STATUS_CALL in the mask is - * called. I2C stores the received data in the - * Rx buffer. - */ - ALT_I2C_STATUS_INT_ALL = 0xFFF, - /*!< All Combined and Individual Interrupts. This - * enumeration value can be used to clear, - * disable, and enable the combined interrupt - * and all individual interrupt status - * conditions. As a side effect, when passed to - * alt_i2c_int_clear(), clears the source causes - * (\ref ALT_I2C_TX_ABORT_CAUSE_t) of the - * ALT_I2C_STATUS_TX_ABORT condition. - */ -} ALT_I2C_STATUS_t; - -/*! - * This type enumerates the source causes of a ALT_I2C_STATUS_TX_ABORT condition. - * - * The active ALT_I2C_TX_ABORT_CAUSE_t source conditions are cleared when - * alt_i2c_int_clear() with is called ALT_I2C_STATUS_TX_ABORT in the mask or - * alt_i2c_int_clear() is called with ALT_I2C_STATUS_ALL in the mask. - * - * \internal - * Discuss special handling of abrt_sbyte_norstrt TX_ABRT source required in ???() function. - * \endinternal - */ -typedef enum ALT_I2C_TX_ABORT_CAUSE_e -{ - ALT_I2C_TX_ABORT_CAUSE_7B_ADDR_NOACK = 1UL << 0, - /*!< Master Abort 7 Bit Address - If set (1), - * Master is in 7-bit addressing mode and the - * address sent was not acknowledged by any - * slave. - * - * Role of I2C: Master-Transmitter or - * Master-Receiver - */ - ALT_I2C_TX_ABORT_CAUSE_10ADDR1_NOACK = 1UL << 1, - /*!< Master Abort 10 Bit Address Byte 1 - If set - * (1), Master is in 10-bit address mode and the - * first 10-bit address byte was not - * acknowledged by any slave. - * - * Role of I2C: Master-Transmitter or - * Master-Receiver - */ - ALT_I2C_TX_ABORT_CAUSE_10ADDR2_NOACK = 1UL << 2, - /*!< Master Abort 10 Bit Address Byte 2 - If set - * (1), Master is in 10-bit address mode and the - * second address byte of the 10-bit address was - * not acknowledged by any slave - * - * Role of I2C: Master-Transmitter or - * Master-Receiver - */ - ALT_I2C_TX_ABORT_CAUSE_TXDATA_NOACK = 1UL << 3, - /*!< Master Abort TX NOACK Bit - If set (1), - * Master has received an acknowledgement for - * the address, but when it sent data byte(s) - * following the address, it did not receive an - * acknowledge from the remote slave(s). This is - * a master-mode only bit. - * - * Role of I2C: Master-Transmitter. - */ - ALT_I2C_TX_ABORT_CAUSE_GCALL_NOACK = 1UL << 4, - /*!< Master Abort GC Noack Bit - If set (1), I2C - * controller in master mode sent a General Call - * and no slave on the bus acknowledged the - * General Call. - * - * Role of I2C: Master-Transmitter. - */ - ALT_I2C_TX_ABORT_CAUSE_GCALL_RD = 1UL << 5, - /*!< Master Abort GC Read Bit - If set (1), I2C - * controller in master mode sent a General Call - * but the user programmed the byte following - * the General Call to be a read from the bus - * (IC_DATA_CMD[9] is set to 1). - * - * Role of I2C: Master-Transmitter. - */ - ALT_I2C_TX_ABORT_CAUSE_HS_ACKDET = 1UL << 6, - /*!< Master HS MC Ack - If set (1), Master is in - * High Speed mode and the High Speed Master - * code was acknowledged (wrong behavior). - * - * Role of I2C: Master. - */ - ALT_I2C_TX_ABORT_CAUSE_SBYTE_ACKDET = 1UL << 7, - /*!< Master Abort START Byte - If set (1), Master - * has sent a START Byte and the START Byte was - * acknowledged (wrong behavior). - * - * Role of I2C: Master. - */ - ALT_I2C_TX_ABORT_CAUSE_HS_NORSTRT = 1UL << 8, - /*!< Master HS Restart Disabled - If set (1), the - * restart is disabled (IC_RESTART_EN bit - * (IC_CON[5]) = 0) and the user is trying to - * use the master to transfer data in High Speed - * mode. - * - * Role of I2C: Master-Transmitter or - * Master-Receiver - */ - ALT_I2C_TX_ABORT_CAUSE_SBYTE_NORSTRT = 1UL << 9, - /*!< Master Abort START No Restart - To clear, the - * source of the ABRT_SBYTE_NORSTRT must be - * fixed first; restart must be enabled - * (IC_CON[5]=1), the SPECIAL bit must be - * cleared (IC_TAR[11]), or the GC_OR_START bit - * must be cleared (IC_TAR[10]). Once the source - * of the ABRT_SBYTE_NORSTRT is fixed, then this - * bit can be cleared in the same manner as - * other bits in this register. If the source of - * the ABRT_SBYTE_NORSTRT is not fixed before - * attempting to clear this bit, bit 9 clears - * for one cycle and then gets re-asserted. - * - * If set (1), the restart is disabled - * (IC_RESTART_EN bit (IC_CON[5]) = 0) and the - * user is trying to send a START Byte. - * - * Role of I2C: Master. - */ - ALT_I2C_TX_ABORT_CAUSE_10B_RD_NORSTRT = 1UL << 10, - /*!< Master Abort 10 Bit No Restart - If set (1), - * the restart is disabled (IC_RESTART_EN bit - * (IC_CON[5]) = 0) and the master sends a read - * command in 10-bit addressing mode. - * - * Role of I2C: Master Receiver. - */ - ALT_I2C_TX_ABORT_CAUSE_MST_DIS = 1UL << 11, - /*!< Master Operation with Master Disabled - If set - * (1), user tries to initiate a Master - * operation with the Master mode disabled. - * - * Role of I2C: Master or Slave-Receiver. - */ - ALT_I2C_TX_ABORT_CAUSE_ARB_LOST = 1UL << 12, - /*!< Master Abort Arbitration Lost - If set (1), - * master has lost arbitration, or if - * IC_TX_ABRT_SOURCE[14] is also set, then the - * slave transmitter has lost arbitration. Note: - * I2C can be both master and slave at the same - * time. - * - * Role of I2C: Master or Slave-Transmitter. - */ - ALT_I2C_TX_ABORT_CAUSE_SLVFLUSH_TXFIFO = 1UL << 13, - /*!< Slave Abort Flush TXFIFO - If set (1), Slave - * has received a read command and some data - * exists in the TX FIFO so the slave issues a - * TX_ABRT interrupt to flush old data in TX - * FIFO. - * - * Role of I2C: Slave-Transmitter. - */ - ALT_I2C_TX_ABORT_CAUSE_SLV_ARBLOST = 1UL << 14, - /*!< Slave Abort Arbitration Lost - If set (1), - * Slave lost the bus while transmitting data to - * a remote master. IC_TX_ABRT_SOURCE[12] is set - * at the same time. - * - * Note: Even though the slave never owns the - * bus, something could go wrong on the - * bus. This is a fail safe check. For instance, - * during a data transmission at the low-to-high - * transition of SCL, if what is on the data bus - * is not what is supposed to be transmitted, - * then DW_apb_i2c no longer own the bus. - * - * Role of I2C: Slave-Transmitter. - */ - ALT_I2C_TX_ABORT_CAUSE_SLVRD_INTX = 1UL << 15 - /*!< Slave Abort Read TX - If set (1), - * when the processor side responds to a - * slave mode request for data to be transmitted - * to a remote master and user writes a 1 in CMD - * (bit 8) of IC_DATA_CMD register. - * - * Role of I2C: Slave-Transmitter. - */ -} ALT_I2C_TX_ABORT_CAUSE_t; - -/*! - * This type defines a structure for configuration of the SCL high and low counts - * to ensure proper I/O timing with the device interface. - * - * The SCL count values are only relevant if the I2C controller is enabled to as - * an I2C master. The SCL count values are ignored when the I2C controller is - * enabled as an I2C slave. - * - * See: Clock Frequency Configuration section of <em>Chapter 20. I2C - * Controller</em> in the <em>Cyclone V Device Handbook Volume 3: Hard - * Processor System Technical Reference Manual</em> for a complete discussion - * of calculation of the proper SCL clock high and low times. - */ -typedef struct ALT_I2C_MASTER_CONFIG_s -{ - ALT_I2C_ADDR_MODE_t addr_mode; - /*!< The address mode (7 or 10 bit) when - * acting as a master. - */ - bool restart_enable; - /*!< This setting determines whether RESTART - * conditions may be sent when acting as a - * master. When the \e restart_enable is - * false, the I2C controller master is - * incapable of performing the following - * functions: - * * Sending a START BYTE - * * Performing any high-speed mode - * operation - * * Performing direction changes in - * combined format mode - * * Performing a read operation with a - * 10-bit address - */ - ALT_I2C_SPEED_t speed_mode; - /*!< The speed mode of the I2C operation. - */ - uint16_t ss_scl_hcnt; - /*!< The SCL clock high-period count for - * standard speed. - */ - uint16_t ss_scl_lcnt; - /*!< The SCL clock low-period count for - * standard speed. - */ - uint16_t fs_scl_hcnt; - /*!< The SCL clock high-period count for fast - * speed. - */ - uint16_t fs_scl_lcnt; - /*!< The SCL clock low-period count for fast - * speed. - */ - uint8_t fs_spklen; - /*!< The duration, measured in ic_clk cycles, - * of the longest spike that is filtered out - * by the spike suppression logic when the - * component is operating in SS or FS modes. - */ -} ALT_I2C_MASTER_CONFIG_t; - -/*! - * This type defines a structure for configuration of the I2C controller when it - * is operating in slave mode. - */ -typedef struct ALT_I2C_SLAVE_CONFIG_s -{ - ALT_I2C_ADDR_MODE_t addr_mode; /*!< The address mode (7 or 10 bit) when - * acting as a slave. - */ - uint32_t addr; /*!< The slave address to which the I2C - * controller responds when acting as a - * slave. - */ - bool nack_enable; /*!< Enable generation of a NACK. when the - * I2C controller is a - * slave-receiver. If \b true, it can - * only generate a NACK after a data - * byte is received; hence, the data - * transfer is aborted and the data - * received is not pushed onto the - * receive buffer. When \b false, it - * generates NACK/ACK, depending on - * normal criteria. - * * \b true = generate NACK after data - * byte received - * * \b false = generate NACK/ACK normally - */ -} ALT_I2C_SLAVE_CONFIG_t; - -/*! - * Initialize the specified I2C controller instance for use and return a device - * handle referencing it. - * - * \param i2c - * The HPS I2C controller instance to initialize. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * Initialization process: - * * Initialize internal driver state - * * Check clock setup (ALT_CLK_L4_SP) - * * Take I2C instance out of reset (System Manager) - * * Disable and clear all interrupts and status conditions - * * Setup and initialize any expected initial I2C controller state - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, ALT_I2C_DEV_t *i2c_dev); - -/*! - * Reset the specified I2C controller instance for use. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * Reset process: - * * Disable controller - * * Initialize internal driver state - * * Check clock setup (ALT_CLK_L4_SP) - * * Take I2C instance out of reset (System Manager) - * * Disable and clear all interrupts and status conditions - * * Setup and initialize any expected initial I2C controller state - * * Enable controller - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev); - -/*! - * Uninitialize the I2C controller referenced by the \e i2c_dev handle. - * - * This function attempts to gracefully shutdown the I2C controller by waiting for - * any inpcomplete transactions to finish and then putting the I2C controller into - * reset. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Disables the I2C controller. - * - * When the I2C controller is disabled, the following occurs: - * * The TX FIFO and RX FIFO get flushed. - * * The I2C interrupt status conditions remain active until the I2C controller - * goes into IDLE state. - * - * If the controller is transmitting, it stops as well as deletes the contents of - * the transmit buffer after the current transfer is complete. If the module is - * receiving, the controller stops the current transfer at the end of the current - * byte and does not acknowledge the transfer. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_ENABLE.ENABLE = 0 - * Follow the procedure in section 3.8.3 Disabling DW_apb_i2c of the DW Databook. - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Enables the I2C controller. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_ENABLE.ENABLE = 1 - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Returns ALT_E_TRUE if the I2C controller is enabled. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_ENABLE.ENABLE == 1 - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Gets the current configuration of the I2C controller when operating in master - * mode. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param cfg - * [out] Pointer to a ALT_I2C_MASTER_CONFIG_t structure for holding - * the returned I2C master mode configuration parameters. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev, - ALT_I2C_MASTER_CONFIG_t* cfg); - -/*! - * Sets the configuration of the I2C controller with operational parameters for - * operating in master mode. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param cfg - * Pointer to a ALT_I2C_MASTER_CONFIG_t structure holding the desired - * I2C master mode operational parameters. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev, - const ALT_I2C_MASTER_CONFIG_t* cfg); - -/*! - * This is a utility function that returns the speed based on parameters of the - * I2C master configuration. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param cfg - * A pointer to the master confugurations. - * - * \param speed_in_hz - * [out] Speed (Hz) of the I2C bus currently configured at. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev, - const ALT_I2C_MASTER_CONFIG_t* cfg, - uint32_t * speed_in_hz); - -/*! - * This is a utility function that computes parameters for the I2C master - * configuration that best matches the speed requested. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param cfg - * A pointer to the master confugurations. - * - * \param speed_in_hz - * Speed (Hz) of the I2C bus to configure. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev, - ALT_I2C_MASTER_CONFIG_t * cfg, - uint32_t speed_in_hz); - -/*! - * Definition included for backwards compatibility. - */ -#define alt_i2c_cfg_to_speed(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_get((i2c_dev), (cfg), (speed_in_hz)) - -/*! - * Definition included for backwards compatibility. - */ -#define alt_i2c_speed_to_cfg(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_set((i2c_dev), (cfg), (speed_in_hz)) - -/*! - * Gets the current configuration of the I2C controller when operating in slave - * mode. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param cfg - * [out] Pointer to a ALT_I2C_SLAVE_CONFIG_t structure for holding - * the returned I2C slave mode configuration parameters. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev, - ALT_I2C_SLAVE_CONFIG_t* cfg); - -/*! - * Sets the configuration of the I2C controller with operational parameters for - * operating in slave mode. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param cfg - * Pointer to a ALT_I2C_SLAVE_CONFIG_t structure holding the desired - * I2C slave mode operational parameters. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev, - const ALT_I2C_SLAVE_CONFIG_t* cfg); - -/*! \addtogroup ALT_I2C_SDA_HOLD SDA Hold Time Configuration - * - * The I2C protocol specification requires 300ns of hold time on the SDA signal in - * standard and fast speed modes. Board delays on the SCL and SDA signals can mean - * that the hold-time requirement is met at the I2C master, but not at the I2C - * slave (or vice-versa). Because each system may encounter differing board signal - * delays, the I2C controller provides the capability to adjust of the SDA - * hold-time. - * - * The functions in this section provide software configuration of SDA hold time - * for the I2C controller. - * - * @{ - */ - -/*! - * Gets the currently configured value for the SDA hold time in I2C controller - * clock (\ref ALT_CLK_L4_SP) clock ticks. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param hold_time - * [out] The configured SDA hold time in \ref ALT_CLK_L4_SP clock - * ticks. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev, - uint16_t *hold_time); - -/*! - * Sets the configured value for the SDA hold time in terms of I2C controller - * clock (\ref ALT_CLK_L4_SP) clock ticks. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param hold_time - * The SDA hold time in \ref ALT_CLK_L4_SP clock ticks. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_SDA_HOLD is 16 bits wide. hold_time must be in range 0..65535. - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev, - const uint16_t hold_time); - -/*! @} */ - -/*! - * Gets the current operational mode of the I2C controller. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param mode - * [out] The current operational mode enabled for the I2C - * controller. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev, - ALT_I2C_MODE_t* mode); - -/*! - * Sets the operational mode of the I2C controller. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param mode - * The operational mode to enable for the I2C controller. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev, - const ALT_I2C_MODE_t mode); - -/*! - * Returns ALT_E_TRUE if the I2C controller is busy. The I2C controller is busy if - * either the Slave Finite State Machine (FSM) is not in the IDLE state or the - * Master Finite State Machine (FSM) is not in the IDLE state. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_STATUS.ACTIVITY == 1 - * NOTE: IC_STATUS[0] that is, the ACTIVITY bit is the OR of SLV_ACTIVITY and - * MST_ACTIVITY bits. - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev); - -/*! - * This function reads a single data byte from the receive FIFO. - * - * This function is used to perform low level access to the data bytes - * received by the I2C controller and buffered in the receive FIFO. It - * may be used by master-receivers or slave receivers. - * - * This function does not check for valid data in the receive FIFO - * beforehand and may cause an underflow if improperly used. It is - * meant to be called from a context where preconditions have been - * previously asserted such as in the implementation of the - * alt_i2c_slave_receive() or alt_i2c_master_receive() function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param val - * [out] The single data byte read from the receive FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *val); - -/*! - * This function writes a single data byte to the transmit FIFO. - * - * This function is used to perform low level writes of data to the - * transmit FIFO for transmission by the I2C controller. It may be - * used by slave receivers. - * - * This function does not check whether the transmit FIFO is full or - * not beforehand and may cause an overflow if improperly used. It is - * meant to be called from a context where preconditions have been - * previously asserted such as in the implementation of the - * alt_i2c_slave_transmit() function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param val - * The data byte to write to the transmission FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t val); - -/*! - * This function acts in the role of a slave-receiver by receiving a single data - * byte from the I2C bus in response to a write command from the master. - * - * This API is suitable for being called during an interrupt context. It is the - * programmer's responsibility to ensure that there is data in the RX FIFO to - * accomodate the request made. - * - * The I2C controller must be in slave mode before calling this function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param data - * [out] A pointer to a buffer to contain the received data byte. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t *i2c_dev, - uint8_t *data); - -/*! - * This function acts in the role of a slave-transmitter by transmitting a single - * data byte to the I2C bus in response to a read request from the master. - * - * This API is suitable for being called during an interrupt context. It is the - * programmer's responsibility to ensure that there is enough space in the TX - * FIFO to accomodate the request made. - * - * The I2C controller must be in slave mode before calling this function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param data - * The data byte to transmit. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev, - const uint8_t data); - -/*! - * This function acts in the role of a slave-transmitter by transmitting data in - * bulk to the I2C bus in response to a series of read requests from a master. - * - * In the standard I2C protocol, all transactions are single byte transactions and - * the slave responds to a remote master read request by writing one byte into the - * slave's TX FIFO. When a slave (slave-transmitter) is issued with a read request - * from the remote master (master-receiver), at a minimum there should be at least - * one entry placed into the slave-transmitter's TX FIFO. The I2C controller is - * capable of handling more data in the TX FIFO so that subsequent read requests - * can receive that data without raising an interrupt or software having to poll - * to request more data. This eliminates overhead latencies from being incurred by - * servicing the interrupt or polling for data requests each time had there been a - * restriction of having only one entry placed in the TX FIFO. - * - * If the remote master acknowledges the data sent by the slave-transmitter and - * there is no data in the slave's TX FIFO, the I2C controller raises the read - * request interrupt and waits for data to be written into the TX FIFO before it - * can be sent to the remote master. - * - * If the programmer knows in advance that the master is requesting a packet of \e - * n bytes, then when another master request for data is received, the TX FIFO - * could be written with \e n number bytes and the master receives it as a - * continuous stream of data. For example, the slave continues to send data to the - * master as long as the master is acknowledging the data sent and there is data - * available in the TX FIFO. There is no need to hold the SCL line low or to issue - * READ request again. - * - * If the remote master is to receive \e n bytes from the slave but the programmer - * wrote a number of bytes larger than \e n to the TX FIFO, then when the slave - * finishes sending the requested \e n bytes, it clears the TX FIFO and ignores - * any excess bytes. - * - * This API is suitable for being called during an interrupt context. It is the - * programmer's responsibility to ensure that there is enough space in the TX - * FIFO to accomodate the request made. - * - * The I2C controller must be in slave mode before calling this function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param data - * A pointer to the data buffer to transmit. - * - * \param size - * The size of the data buffer in bytes to place in the TX FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * See: Section <em>Slave-Transfer Operation for Bulk Transfers</em> of the DW - * Databook for details of implementation and error conditions that may occur. - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev, - const void * data, - const size_t size); - -/*! - * This function returns the current target address. - * - * The I2C controller must be in master mode before calling this function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param target_addr - * [out] The 7 or 10 bit slave target address. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code. - */ -ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr); - -/*! - * This function updates the target slave address for any upcoming I2C bus IO. - * - * This API is not suitlabe for being called in an interrupt context as it - * will wait for the TX FIFO to flush before applying the changes. If the TX - * FIFO is known to be empty and the controller idle, then it can be safely - * called. - * - * The I2C controller must be in master mode before calling this function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param target_addr - * The 7 or 10 bit slave target address. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code. - */ -ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr); - -/*! - * This function acts in the role of a master-transmitter by issuing a write - * command and transmitting data to the I2C bus. - * - * This API is not suitable for being called in an interrupt context as it may - * wait for certain controller states before completing. - * - * The I2C controller must be in master mode before calling this function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param data - * A pointer to a data buffer to transmit - * - * \param size - * The size of the data buffer in bytes to place in the TX FIFO. - * - * \param issue_restart - * This parameter controls whether a RESTART is issued before the - * byte is sent or received. If: - * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued before the data is sent/received - * (according to the value of CMD), regardless of whether or not - * the transfer direction is changing from the previous command; if - * \e restart_enabled is \b false, a STOP followed by a START is - * issued instead. - * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued only if the transfer direction - * is changing from the previous command; if \e restart_enabled is - * \b false, a STOP followed by a START is issued instead. - * - * \param issue_stop - * This parameter controls whether a STOP is issued after the byte is - * sent or received. If: - * * \b true - STOP is issued after this byte, regardless of whether or - * not the Tx FIFO is empty. If the Tx FIFO is not empty, the - * master immediately tries to start a new transfer by issuing a - * START and arbitrating for the bus. - * * \b false - STOP is not issued after this byte, regardless of - * whether or not the Tx FIFO is empty. If the Tx FIFO is not - * empty, the master continues the current transfer by - * sending/receiving data bytes according to the value of the CMD - * bit. If the Tx FIFO is empty, the master holds the SCL line low - * and stalls the bus until a new command is available in the Tx - * FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev, - const void * data, - const size_t size, - const bool issue_restart, - const bool issue_stop); - -/*! - * This function acts in the role of a master-receiver by receiving one or more - * data bytes transmitted from a slave in response to read requests issued from - * this master. - * - * This function causes the master to issue the required number of read requests - * to the slave and read the received data bytes from the Rx FIFO. - * - * The \e issue_restart and \e issue_stop parameters apply to the final read - * request transaction in the \e num_data_entries sequence required to fulfill the - * aggregate receive request. - * - * This API is not suitable for being called in an interrupt context as it may - * wait for certain controller states before completing. - * - * The I2C controller must be in master mode before calling this function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param data - * [out] The data buffer to receive the requested \e size bytes. - * - * \param size - * The size of the data buffer to read from the RX FIFO. - * - * \param issue_restart - * This parameter controls whether a RESTART is issued before the - * byte is sent or received. If: - * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued before the data is sent/received - * (according to the value of CMD), regardless of whether or not - * the transfer direction is changing from the previous command; if - * \e restart_enabled is \b false, a STOP followed by a START is - * issued instead. - * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued only if the transfer direction - * is changing from the previous command; if \e restart_enabled is - * \b false, a STOP followed by a START is issued instead. - * - * \param issue_stop - * This parameter controls whether a STOP is issued after the byte is - * sent or received. If: - * * \b true - STOP is issued after this byte, regardless of whether or - * not the Tx FIFO is empty. If the Tx FIFO is not empty, the - * master immediately tries to start a new transfer by issuing a - * START and arbitrating for the bus. - * * \b false - STOP is not issued after this byte, regardless of - * whether or not the Tx FIFO is empty. If the Tx FIFO is not - * empty, the master continues the current transfer by - * sending/receiving data bytes according to the value of the CMD - * bit. If the Tx FIFO is empty, the master holds the SCL line low - * and stalls the bus until a new command is available in the Tx - * FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev, - void * data, - const size_t size, - const bool issue_restart, - const bool issue_stop); - -/*! - * This function causes the I2C controller master to issue a READ request on the - * bus. This function is typically used during master-receiver transfers. - * - * The I2C controller must be in master mode before calling this function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param issue_restart - * This parameter controls whether a RESTART is issued before the - * byte is sent or received. If: - * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued before the data is sent/received - * (according to the value of CMD), regardless of whether or not - * the transfer direction is changing from the previous command; if - * \e restart_enabled is \b false, a STOP followed by a START is - * issued instead. - * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued only if the transfer direction - * is changing from the previous command; if \e restart_enabled is - * \b false, a STOP followed by a START is issued instead. - * - * \param issue_stop - * This parameter controls whether a STOP is issued after the byte is - * sent or received. If: - * * \b true - STOP is issued after this byte, regardless of whether or - * not the Tx FIFO is empty. If the Tx FIFO is not empty, the - * master immediately tries to start a new transfer by issuing a - * START and arbitrating for the bus. - * * \b false - STOP is not issued after this byte, regardless of - * whether or not the Tx FIFO is empty. If the Tx FIFO is not - * empty, the master continues the current transfer by - * sending/receiving data bytes according to the value of the CMD - * bit. If the Tx FIFO is empty, the master holds the SCL line low - * and stalls the bus until a new command is available in the Tx - * FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * Write IC_DATA_CMD.CMD = 1 (read request). IC_DATA_CMD.DAT is - * written with "don't care" values as these bits are ignored by the - * I2C controller . - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev, - const bool issue_restart, - const bool issue_stop); - -/*! - * This function causes the I2C controller master to issue a send byte on the - * bus. This function is typically used during master-transmitter/slave-transmitter - * transfers. - * - * The I2C controller must be in master mode before calling this function. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param value - * The data item to be transmitted. - * - * \param issue_restart - * This parameter controls whether a RESTART is issued before the - * byte is sent or received. If: - * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued before the data is sent/received - * (according to the value of CMD), regardless of whether or not - * the transfer direction is changing from the previous command; if - * \e restart_enabled is \b false, a STOP followed by a START is - * issued instead. - * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued only if the transfer direction - * is changing from the previous command; if \e restart_enabled is - * \b false, a STOP followed by a START is issued instead. - * - * \param issue_stop - * This parameter controls whether a STOP is issued after the byte is - * sent or received. If: - * * \b true - STOP is issued after this byte, regardless of whether or - * not the Tx FIFO is empty. If the Tx FIFO is not empty, the - * master immediately tries to start a new transfer by issuing a - * START and arbitrating for the bus. - * * \b false - STOP is not issued after this byte, regardless of - * whether or not the Tx FIFO is empty. If the Tx FIFO is not - * empty, the master continues the current transfer by - * sending/receiving data bytes according to the value of the CMD - * bit. If the Tx FIFO is empty, the master holds the SCL line low - * and stalls the bus until a new command is available in the Tx - * FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * Write IC_DATA_CMD.CMD = 0 (write request). - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev, - const uint8_t value, - const bool issue_restart, - const bool issue_stop); - -/******************************************************************************/ -/*! \addtogroup ALT_I2C_GEN_CALL General Call - * - * The functions in this group support General Call addresses. - * - * The general call address is for addressing every device connected to the I2C - * bus at the same time. However, if a device does not need any of the data - * supplied within the general call structure, it can ignore this address by not - * issuing an acknowledgment. If a device does require data from a general call - * address, it acknowledges this address and behaves as a slave-receiver. The - * master does not actually know how many devices acknowledged if one or more - * devices respond. The second and following bytes are acknowledged by every - * slave-receiver capable of handling this data. A slave who cannot process one of - * these bytes must ignore it by not-acknowledging. If one or more slaves - * acknowledge, the not-acknowledge will not be seen by the master. - * - * The functions in this group do not provide any general call functional command - * interpretation or implementation (e.g. software reset). - * - * @{ - */ - -/*! - * This function acts in the role of a master-transmitter by issuing a general - * call command to all devices connected to the I2C bus. - * - * The \e issue_restart and \e issue_stop parameters apply to the final write - * transaction in the \e num_data_entries byte transmission sequence. - * - * The I2C controller must be in master mode before calling this function. - * - * The target slave address will be modified by this function. Call - * alt_i2c_master_target_set() to reset the slave target address for - * subsequent IO. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param data - * An array of data byte(s) to transmit. - * - * \param num_data_entries - * The number of entries (bytes) in \e data to place in the TX FIFO. - * - * \param issue_restart - * This parameter controls whether a RESTART is issued before the - * byte is sent or received. If: - * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued before the data is sent/received - * (according to the value of CMD), regardless of whether or not - * the transfer direction is changing from the previous command; if - * \e restart_enabled is \b false, a STOP followed by a START is - * issued instead. - * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t - * is \b true, a RESTART is issued only if the transfer direction - * is changing from the previous command; if \e restart_enabled is - * \b false, a STOP followed by a START is issued instead. - * - * \param issue_stop - * This parameter controls whether a STOP is issued after the byte is - * sent or received. If: - * * \b true - STOP is issued after this byte, regardless of whether or - * not the Tx FIFO is empty. If the Tx FIFO is not empty, the - * master immediately tries to start a new transfer by issuing a - * START and arbitrating for the bus. - * * \b false - STOP is not issued after this byte, regardless of - * whether or not the Tx FIFO is empty. If the Tx FIFO is not - * empty, the master continues the current transfer by - * sending/receiving data bytes according to the value of the CMD - * bit. If the Tx FIFO is empty, the master holds the SCL line low - * and stalls the bus until a new command is available in the Tx - * FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev, - const void * data, - const size_t size, - const bool issue_restart, - const bool issue_stop); - -/*! - * Disables the I2C controller from responding to a General Call address. The - * controller will respond with a NACK and no General Call status conditions or - * interrupts are generated. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 0 - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Enables the I2C controller to respond with an ACK when it receives a General - * Call address. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 1 - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call - * addresses. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_ACK_GENERAL_CALL.ACK_GEN_CALL == 1 - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup ALT_I2C_INT Interrupt and Status Conditions - * - * The functions in this group provide management for the I2C controller status - * conditions and interrupts. - * - * Each I2C controller has a single combined interrupt output (\b - * ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ). The following events can generate an - * interrupt: - * * General Call Address Received - * * Start or Restart Condition Occurred - * * Stop Condition Occurred - * * I2C Controller Activity - * * Receive Done - * * Transmit Abort - * * Read Request - * * Transmit Buffer Empty - * * Transmit Overflow - * * Receive Buffer Full - * * Receive Overflow - * * Receive Underflow - * - * These interrupt status conditions may be monitored either by polling their - * status or by configuring interrupt handlers using the HWLIB Interrupt - * Controller API. - * - * Functions to get the current status, enable or disable (i.e. mass or unmask), - * and clear interrupt status conditions for the I2C controller are defined in - * this section. - * - * @{ - */ - -/*! - * Returns the current I2C controller interrupt status conditions. - * - * This function returns the current value of the I2C controller interrupt status - * register value which reflects the current I2C controller status conditions that - * are not disabled (i.e. masked). - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param status - * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t - * interrupt and status conditions. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_INTR_STAT - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev, - uint32_t *status); - -/*! - * Returns the I2C controller raw interrupt status conditions irrespective of - * the interrupt status condition enablement state. - * - * This function returns the current value of the I2C controller raw interrupt - * status register value which reflects the current I2C controller status - * conditions regardless of whether they are disabled (i.e. masked) or not. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param status - * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t - * interrupt and status conditions. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_INTR_STAT - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev, - uint32_t *status); - -/*! - * Clears the specified I2C controller interrupt status conditions identified - * in the mask. - * - * This function clears one or more of the status conditions as contributors to - * the \b ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param mask - * Specifies the QSPI interrupt status conditions to clear. \e mask - * is a mask of logically OR'ed \ref ALT_I2C_STATUS_t values that - * designate the status conditions to clear. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); - -/*! - * Disable the specified I2C controller interrupt status conditions identified in - * the mask. - * - * This function disables one or more of the status conditions as contributors to - * the \b ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state. - * - * NOTE: A cleared bit for any status condition in the mask value does not have - * the effect of enabling it as a contributor to the \b - * ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state. The function - * alt_i2c_int_enable() is used to enable status source conditions. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param mask - * Specifies the status conditions to disable as interrupt source - * contributors. \e mask is a mask of logically OR'ed \ref - * ALT_I2C_STATUS_t values that designate the status conditions to - * disable. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); - -/*! - * Enable the specified I2C controller interrupt status conditions identified in - * the mask. - * - * This function enables one or more of the status conditions as contributors to - * the \b ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state. - * - * NOTE: A cleared bit for any status condition in the mask value does not have - * the effect of disabling it as a contributor to the \b - * ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state. The function - * alt_i2c_int_disable() is used to disable status source conditions. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param mask - * Specifies the status conditions to enable as interrupt source - * contributors. \e mask is a mask of logically OR'ed \ref - * ALT_I2C_STATUS_t values that designate the status conditions to - * enable. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask); - -/*! - * Gets the cause of I2C transmission abort. A I2C transmission abort indicates - * that the I2C transmitter is unable to complete the intended actions on the - * contents of the transmit FIFO. This situation can occur both as an I2C master - * or an I2C slave, and is referred to as a "transmit abort". - * - * The returned value of this function is the value of the IC_TX_ABRT_SOURCE - * register which indicates the cause why the transmit abort occurred. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param cause - * [out] A pointer to a bit mask of the \ref ALT_I2C_TX_ABORT_CAUSE_t - * causes of the transmission abort. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_TX_ABRT_SOURCE - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev, - ALT_I2C_TX_ABORT_CAUSE_t *cause); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup ALT_I2C_RX_FIFO RX FIFO Management - * - * The receive FIFO has a configurable threshold value that controls the level of - * entries (or above) that sets the RX_FULL status condition and triggers an - * interrupt. The valid range is 0 - (ALT_I2C_RX_FIFO_NUM_ENTRIES-1), with the - * additional restriction that I2C controller does not allow this value to be set - * to a value larger than the depth of the buffer. If an attempt is made to do - * that, the actual value set will be the maximum depth of the buffer. A value of - * 0 sets the threshold for 1 entry, and a value of (ALT_I2C_RX_FIFO_NUM_ENTRIES-1) - * sets the threshold for ALT_I2C_RX_FIFO_NUM_ENTRIES entries. - * - * @{ - */ - -/*! - * The number of entries (depth) of the I2C controller receive FIFO. - */ -#define ALT_I2C_RX_FIFO_NUM_ENTRIES 64 - -/*! - * Returns ALT_E_TRUE when the receive FIFO is empty. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_STATUS.RFNE == 0 - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Returns ALT_E_TRUE when the receive FIFO is completely full. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_STATUS.RFF == 1 - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Returns the number of valid entries in the receive FIFO. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param num_entries - * [out] The number of entries in the receive FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_RXFLR.RXFLR - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, - uint32_t *num_entries); - -/*! - * Gets the current receive FIFO threshold level value. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param threshold - * [out] The current threshold value. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_RX_TL.RX_TL - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, - uint8_t *threshold); - -/*! - * Sets the current receive FIFO threshold level value. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param threshold - * The threshold value. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_RX_TL.RX_TL = threshold - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, - const uint8_t threshold); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup ALT_I2C_TX_FIFO TX FIFO Management - * - * The transmit FIFO has a configurable threshold value that controls the level of - * entries (or below) that sets the TX_EMPTY status condition and triggers an - * interrupt. The valid range is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES-1), with the - * additional restriction that I2C controller does not allow this value to be set - * to a value larger than the depth of the buffer. If an attempt is made to do - * that, the actual value set will be the maximum depth of the buffer. A value of - * 0 sets the threshold for 0 entries, and a value of (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) - * sets the threshold for (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) entries. - * - * @{ - */ - -/*! - * The number of entries (depth) of the I2C controller transmit FIFO. - */ -#define ALT_I2C_TX_FIFO_NUM_ENTRIES 64 - -/*! - * Returns ALT_E_TRUE when the transmit FIFO is empty. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_STATUS.TFE == 1 - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Returns ALT_E_TRUE when the transmit FIFO is completely full. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_STATUS.TFNF == 0 - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev); - -/*! - * Returns the number of valid entries in the transmit FIFO. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param num_entries - * [out] The number of entries in the transmit FIFO. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_TXFLR.TXFLR - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev, - uint32_t *num_entries); - -/*! - * Gets the current transmit FIFO threshold level value. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param threshold - * [out] The current threshold value. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_TX_TL.TX_TL - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev, - uint8_t *threshold); - -/*! - * Sets the current transmit FIFO threshold level value. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param threshold - * The threshold value. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - * - * \internal - * IC_TX_TL.TX_TL = threshold - * \endinternal - */ -ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev, - const uint8_t threshold); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup ALT_I2C_DMA DMA Interface - * - * The DMA interface has a configurable threshold value that controls the - * level of entries that triggers the burst handshaking request used for DMA - * integration. - * - * For the TX threshold, if the number of entries in the TX FIFO is at or - * below the set threshold, a DMA handshaking request will be made. The valid - * range for the TX threshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). - * - * For the RX threshold, if the number of entries in the RX FIFO is above the - * set threshold, a DMA handshaking request will be made. The valid range for - * the RX treshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1). - * - * Having a higher threshold can improve the AXI bus utilization at the - * expense of the likelyhoold of overflow / underflow conditions. - * @{ - */ - -/*! - * Gets the current RX DMA threshold level value. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param threshold - * [out] The threshold value. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); - -/*! - * Sets the current RX DMA threshold level value. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param threshold - * The threshold value. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); - -/*! - * Gets the current TX DMA threshold level value. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param threshold - * [out] The threshold value. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold); - -/*! - * Sets the current TX DMA threshold level value. - * - * \param i2c_dev - * A pointer to the I2C controller device block instance. - * - * \param threshold - * The threshold value. - * - * \retval ALT_E_SUCCESS Successful status. - * \retval ALT_E_ERROR Details about error status code - */ -ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold); - -/*! @} */ - -/*! @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALT_I2C_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h deleted file mode 100644 index 004fd3188c..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h +++ /dev/null @@ -1,533 +0,0 @@ -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ALT_INT_COMMON_H__ -#define __ALT_INT_COMMON_H__ - -#include "hwlib.h" -#include <stdbool.h> -#include <stddef.h> - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! - * \addtogroup INT_COMMON Interrupt Controller Common Definitions - * - * This module contains the definitions common to the Interrupt Controller - * Low-Level API and Interrupt Controller Manager Interface. - * - * @{ - */ - -/*! - * This type definition enumerates all the interrupt identification types. - */ -typedef enum ALT_INT_INTERRUPT_e -{ - ALT_INT_INTERRUPT_SGI0 = 0, /*!< # */ - ALT_INT_INTERRUPT_SGI1 = 1, /*!< # */ - ALT_INT_INTERRUPT_SGI2 = 2, /*!< # */ - ALT_INT_INTERRUPT_SGI3 = 3, /*!< # */ - ALT_INT_INTERRUPT_SGI4 = 4, /*!< # */ - ALT_INT_INTERRUPT_SGI5 = 5, /*!< # */ - ALT_INT_INTERRUPT_SGI6 = 6, /*!< # */ - ALT_INT_INTERRUPT_SGI7 = 7, /*!< # */ - ALT_INT_INTERRUPT_SGI8 = 8, /*!< # */ - ALT_INT_INTERRUPT_SGI9 = 9, /*!< # */ - ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */ - ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */ - ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */ - ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */ - ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */ - ALT_INT_INTERRUPT_SGI15 = 15, - /*!< - * Software Generated Interrupts (SGI), 0 - 15. - * * All interrupts in this group are software triggered. - */ - - ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL = 27, /*!< # */ - ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE = 29, /*!< # */ - ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */ - /*!< - * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU - * private timer, and watchdog timer. - * * All interrupts in this group are edge triggered. - */ - - ALT_INT_INTERRUPT_CPU0_PARITYFAIL = 32, /*!< # */ - ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC = 33, /*!< # */ - ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB = 34, /*!< # */ - ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG = 35, /*!< # */ - ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA = 36, /*!< # */ - ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB = 37, /*!< # */ - ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */ - ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG = 39, /*!< # */ - ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA = 40, /*!< # */ - ALT_INT_INTERRUPT_CPU0_DEFLAGS0 = 41, /*!< # */ - ALT_INT_INTERRUPT_CPU0_DEFLAGS1 = 42, /*!< # */ - ALT_INT_INTERRUPT_CPU0_DEFLAGS2 = 43, /*!< # */ - ALT_INT_INTERRUPT_CPU0_DEFLAGS3 = 44, /*!< # */ - ALT_INT_INTERRUPT_CPU0_DEFLAGS4 = 45, /*!< # */ - ALT_INT_INTERRUPT_CPU0_DEFLAGS5 = 46, /*!< # */ - ALT_INT_INTERRUPT_CPU0_DEFLAGS6 = 47, - /*!< - * Interrupts sourced from CPU0. - * - * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the - * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts - * for CPU0. - * - * * PARITYFAIL interrupts in this group are edge triggered. - * * DEFFLAGS interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_CPU1_PARITYFAIL = 48, /*!< # */ - ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC = 49, /*!< # */ - ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB = 50, /*!< # */ - ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG = 51, /*!< # */ - ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA = 52, /*!< # */ - ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB = 53, /*!< # */ - ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */ - ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG = 55, /*!< # */ - ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA = 56, /*!< # */ - ALT_INT_INTERRUPT_CPU1_DEFLAGS0 = 57, /*!< # */ - ALT_INT_INTERRUPT_CPU1_DEFLAGS1 = 58, /*!< # */ - ALT_INT_INTERRUPT_CPU1_DEFLAGS2 = 59, /*!< # */ - ALT_INT_INTERRUPT_CPU1_DEFLAGS3 = 60, /*!< # */ - ALT_INT_INTERRUPT_CPU1_DEFLAGS4 = 61, /*!< # */ - ALT_INT_INTERRUPT_CPU1_DEFLAGS5 = 62, /*!< # */ - ALT_INT_INTERRUPT_CPU1_DEFLAGS6 = 63, - /*!< - * Interrupts sourced from CPU1. - * - * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the - * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts - * for CPU1. - * - * * PARITYFAIL interrupts in this group are edge triggered. - * * DEFFLAGS interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_SCU_PARITYFAIL0 = 64, /*!< # */ - ALT_INT_INTERRUPT_SCU_PARITYFAIL1 = 65, /*!< # */ - ALT_INT_INTERRUPT_SCU_EV_ABORT = 66, - /*!< - * Interrupts sourced from the Snoop Control Unit (SCU). - * * All interrupts in this group are edge triggered. - */ - - ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ = 67, /*!< # */ - ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ = 68, /*!< # */ - ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */ - ALT_INT_INTERRUPT_L2_COMBINED_IRQ = 70, - /*!< - * Interrupts sourced from the L2 Cache Controller. - * - * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache - * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR, - * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts. - * Consult the L2C documentation for information on these interrupts. - * - * * ECC interrupts in this group are edge triggered. - * * Other interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ = 71, - /*!< - * Interrupts sourced from the SDRAM Controller. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_F2S_FPGA_IRQ0 = 72, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ1 = 73, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ2 = 74, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ3 = 75, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ4 = 76, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ5 = 77, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ6 = 78, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ7 = 79, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ8 = 80, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ9 = 81, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 = 82, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 = 83, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 = 84, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 = 85, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 = 86, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 = 87, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 = 88, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 = 89, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 = 90, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 = 91, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 = 92, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 = 93, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 = 94, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 = 95, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 = 96, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 = 97, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 = 98, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 = 99, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */ - ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135, - /*!< - * Interrupt request from the FPGA logic, 0 - 63. - * * Trigger type depends on the implementation in the FPGA. - */ - - ALT_INT_INTERRUPT_DMA_IRQ0 = 136, /*!< # */ - ALT_INT_INTERRUPT_DMA_IRQ1 = 137, /*!< # */ - ALT_INT_INTERRUPT_DMA_IRQ2 = 138, /*!< # */ - ALT_INT_INTERRUPT_DMA_IRQ3 = 139, /*!< # */ - ALT_INT_INTERRUPT_DMA_IRQ4 = 140, /*!< # */ - ALT_INT_INTERRUPT_DMA_IRQ5 = 141, /*!< # */ - ALT_INT_INTERRUPT_DMA_IRQ6 = 142, /*!< # */ - ALT_INT_INTERRUPT_DMA_IRQ7 = 143, /*!< # */ - ALT_INT_INTERRUPT_DMA_IRQ_ABORT = 144, /*!< # */ - ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ = 145, /*!< # */ - ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146, - /*!< - * Interrupts sourced from the DMA Controller. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_EMAC0_IRQ = 147, /*!< # */ - ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ = 148, /*!< # */ - ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */ - ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ = 150, /*!< # */ - ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151, - /*!< - * Interrupts sourced from the Ethernet MAC 0 (EMAC0). - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_EMAC1_IRQ = 152, /*!< # */ - ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ = 153, /*!< # */ - ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */ - ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ = 155, /*!< # */ - ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156, - /*!< - * Interrupts sourced from the Ethernet MAC 1 (EMAC1). - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_USB0_IRQ = 157, /*!< # */ - ALT_INT_INTERRUPT_USB0_ECC_CORRECTED = 158, /*!< # */ - ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159, - /*!< - * Interrupts sourced from the USB OTG 0. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_USB1_IRQ = 160, /*!< # */ - ALT_INT_INTERRUPT_USB1_ECC_CORRECTED = 161, /*!< # */ - ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162, - /*!< - * Interrupts sourced from the USB OTG 1. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_CAN0_STS_IRQ = 163, /*!< # */ - ALT_INT_INTERRUPT_CAN0_MO_IRQ = 164, /*!< # */ - ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ = 165, /*!< # */ - ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166, - /*!< - * Interrupts sourced from the CAN Controller 0. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_CAN1_STS_IRQ = 167, /*!< # */ - ALT_INT_INTERRUPT_CAN1_MO_IRQ = 168, /*!< # */ - ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ = 169, /*!< # */ - ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170, - /*!< - * Interrupts sourced from the CAN Controller 1. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_SDMMC_IRQ = 171, /*!< # */ - ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED = 172, /*!< # */ - ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */ - ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED = 174, /*!< # */ - ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175, - /*!< - * Interrupts sourced from the SDMMC Controller. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_NAND_IRQ = 176, /*!< # */ - ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ = 177, /*!< # */ - ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */ - ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ = 179, /*!< # */ - ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */ - ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ = 181, /*!< # */ - ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182, - /*!< - * Interrupts sourced from the NAND Controller. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_QSPI_IRQ = 183, /*!< # */ - ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ = 184, /*!< # */ - ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185, - /*!< - * Interrupts sourced from the QSPI Controller. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */ - ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */ - ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */ - ALT_INT_INTERRUPT_SPI3_IRQ = 189, - /*!< - * Interrupts sourced from the SPI Controllers 0 - 3. - * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1. - * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */ - ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */ - ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */ - ALT_INT_INTERRUPT_I2C3_IRQ = 193, - /*!< - * Interrupts sourced from the I2C Controllers 0 - 3. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_UART0 = 194, /*!< # */ - ALT_INT_INTERRUPT_UART1 = 195, - /*!< - * Interrupts sourced from the UARTs 0 - 1. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */ - ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */ - ALT_INT_INTERRUPT_GPIO2 = 198, - /*!< - * Interrupts sourced from the GPIO 0 - 2. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */ - ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */ - ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */ - ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202, - /*!< - * Interrupts sourced from the Timer controllers. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */ - ALT_INT_INTERRUPT_WDOG1_IRQ = 204, - /*!< - * Interrupts sourced from the Watchdog Timers 0 - 1. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_CLKMGR_IRQ = 205, - /*!< - * Interrupts sourced from the Clock Manager. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206, - /*!< - * Interrupts sourced from the Clock Manager MPU Wakeup. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207, - /*!< - * Interrupts sourced from the FPGA Manager. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */ - ALT_INT_INTERRUPT_NCTIIRQ1 = 209, - /*!< - * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI. - * * All interrupts in this group are level triggered. - */ - - ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ = 210, /*!< # */ - ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211 - /*!< - * Interrupts sourced from the On-chip RAM. - * * All interrupts in this group are level triggered. - */ - -} ALT_INT_INTERRUPT_t; - -/*! - * This is the CPU target type. It is used to specify a set of CPUs on the - * system. If only bit 0 is set then it specifies a set of CPUs containing - * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit - * up to the number of CPUs on the system. - */ -typedef uint32_t alt_int_cpu_target_t; - -/*! - * This type definition enumerates all the interrupt trigger types. - */ -typedef enum ALT_INT_TRIGGER_e -{ - /*! - * Edge triggered interrupt. This applies to Private Peripheral Interrupts - * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs - * 16 - 1019. - */ - ALT_INT_TRIGGER_EDGE, - - /*! - * Level triggered interrupt. This applies to Private Peripheral - * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with - * interrupt IDs 16 - 1019. - */ - ALT_INT_TRIGGER_LEVEL, - - /*! - * Software triggered interrupt. This applies to Software Generated - * Interrupts (SGI) only, with interrupt IDs 0 - 15. - */ - ALT_INT_TRIGGER_SOFTWARE, - - /*! - * All triggering types except for those in the Shared Peripheral Interrupts - * (SPI) F2S FPGA family interrupts can be determined by the system - * automatically. In all functions which ask for the triggering type, the - * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger - * type for all non F2S interrupt types. - */ - ALT_INT_TRIGGER_AUTODETECT, - - /*! - * The interrupt triggering information is not applicable. This is possibly - * due to querying an invalid interrupt identifier. - */ - ALT_INT_TRIGGER_NA -} -ALT_INT_TRIGGER_t; - -/*! - * This type definition enumerates all the target list filter options. This is - * used by the trigger Software Generated Interrupt (SGI) feature to issue a - * SGI to the specified processor(s) in the system. Depending on the target - * list filter and the target list, interrupts can be routed to any - * combinations of CPUs. - */ -typedef enum ALT_INT_SGI_TARGET_e -{ - /*! - * This filter list uses the target list parameter to specify which CPUs - * to send the interrupt to. If target list is 0, no interrupts are sent. - */ - ALT_INT_SGI_TARGET_LIST, - - /*! - * This filter list sends the interrupt all CPUs except the current CPU. - * The target list parameter is ignored. - */ - ALT_INT_SGI_TARGET_ALL_EXCL_SENDER, - - /*! - * This filter list sends the interrupt to the current CPU only. The - * target list parameter is ignored. - */ - ALT_INT_SGI_TARGET_SENDER_ONLY -} -ALT_INT_SGI_TARGET_t; - -/*! - * Extracts the CPUID field from the ICCIAR register. - */ -#define ALT_INT_ICCIAR_CPUID_GET(icciar) ((icciar >> 10) & 0x7) - -/*! - * Extracts the ACKINTID field from the ICCIAR register. - */ -#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF) - -/*! - * The callback to use when an interrupt needs to be serviced. - * - * \param icciar The Interrupt Controller CPU Interrupt - * Acknowledgement Register value (ICCIAR) value - * corresponding to the current interrupt. - * - * \param context The user provided context. - */ -typedef void (*alt_int_callback_t)(uint32_t icciar, void * context); - -/*! - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_INT_COMMON_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h deleted file mode 100644 index 2ead15df86..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_mpu_registers.h +++ /dev/null @@ -1,156 +0,0 @@ - -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ALT_MPUSCU_H__ -#define __ALT_MPUSCU_H__ - - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - - -/************************************************************************************************************/ -/* alt_mpuscu.h */ -/* */ -/* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */ -/* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */ -/* */ -/************************************************************************************************************/ - -#ifndef ALT_HPS_ADDR -#define ALT_HPS_ADDR 0x00 -#endif - - -/* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */ -/* and is the address of the base of the Snoop Control Unit (SCU) */ -#define GLOBALTMR_BASE (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET) -#define CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET) -#define CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET) -#define CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET) -#define CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET) - - - /* offsets */ - /* Global Timer offsets */ -#define GLOBALTMR_MODULE_BASE_OFFSET 0x00000200 -#define GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000 -#define GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004 -#define GLOBALTMR_CTRL_REG_OFFSET 0x00000008 -#define GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C -#define GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010 -#define GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014 -#define GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018 - -/* Global Timer bitmasks */ -#define GLOBALTMR_ENABLE_BIT 0x00000001 -#define GLOBALTMR_COMP_ENABLE_BIT 0x00000002 -#define GLOBALTMR_INT_ENABLE_BIT 0x00000004 -#define GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008 -#define GLOBALTMR_PS_MASK 0x0000FF00 -#define GLOBALTMR_PS_SHIFT 8 -#define GLOBALTMR_INT_STATUS_BIT 0x00000001 - -/* Global timer constants */ -#define GLOBALTMR_MAX 0xFFFFFFFF -#define GLOBALTMR_PS_MAX 0x000000FF - - -/* Private timer offsets */ -#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600 -#define CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000 -#define CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004 -#define CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008 -#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C - -/* Private timer bitmasks */ -#define CPU_PRIV_TMR_ENABLE 0x00000001 -#define CPU_PRIV_TMR_AUTO_RELOAD 0x00000002 -#define CPU_PRIV_TMR_INT_EN 0x00000004 -#define CPU_PRIV_TMR_PS_MASK 0x0000FF00 -#define CPU_PRIV_TMR_PS_SHIFT 8 -#define CPU_PRIV_TMR_INT_STATUS 0x00000001 - -/* Private timer constants */ -#define CPU_PRIV_TMR_MAX 0xFFFFFFFF -#define CPU_PRIV_TMR_PS_MAX 0x000000FF - - - - /* Watchdog timer offsets */ -#define WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620 -#define WDOG_LOAD_REG_OFFSET 0x00000000 -#define WDOG_CNTR_REG_OFFSET 0x00000004 -#define WDOG_CTRL_REG_OFFSET 0x00000008 -#define WDOG_INTSTAT_REG_OFFSET 0x0000000C -#define WDOG_RSTSTAT_REG_OFFSET 0x00000010 -#define WDOG_DISABLE_REG_OFFSET 0x00000014 - - /* Watchdog timer bitmasks : */ - /* Control Register bitmasks */ -#define WDOG_TMR_ENABLE 0x00000001 -#define WDOG_AUTO_RELOAD 0x00000002 -#define WDOG_INT_EN 0x00000004 -#define WDOG_WDT_MODE 0x00000008 -#define WDOG_PS_MASK 0x0000FF00 -#define WDOG_PS_SHIFT 8 - /* Interrupt Status Register bitmasks */ -#define WDOG_INT_STAT_BIT 0x00000001 - /* Reset Status Register bitmasks */ -#define WDOG_RST_STAT_BIT 0x00000001 - - /* Watchdog timer constants */ -#define WDOG_TMR_MAX UINT32_MAX -#define WDOG_PS_MAX UINT8_MAX -#define WDOG_DISABLE_VAL0 0x12345678 -#define WDOG_DISABLE_VAL1 0x87654321 - - - - /* Interrupt Manager offsets */ -/* <Add definitions here> */ -#define INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100 -#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000 -#define INT_DIST_TYPE_REG 0x00000004 - - -/* Upper bound of the MPUSCU address space */ -#define MPUSCU_MAX 0x00001FFF - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_MPUSCU_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h deleted file mode 100644 index 21fd3a957d..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h +++ /dev/null @@ -1,167 +0,0 @@ -/****************************************************************************** - * - * Copyright 2013 Altera Corporation. All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - ******************************************************************************/ - -/*! \file - * Altera - QSPI Flash Controller Module - */ - -#ifndef __ALT_QSPI_PRIVATE_H__ -#define __ALT_QSPI_PRIVATE_H__ - -#include "socal/socal.h" - -// -// This section provisions support for various flash devices. -// - -#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1 - -///// - -#define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00 -#define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B -#define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000 -#define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B -#define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000 -#define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB -#define ALT_QSPI_BANK_ADDR_MSK 0xFF000000 -#define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB - -#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT -#define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000 -#define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB -#endif - -///// - -// Default delay timing (in ns) for N25Q. -// These values are from the N25Q handbook. The timing correctness is difficult -// to test because the test setup does not feature mutliple chips. -#define ALT_QSPI_TSHSL_NS_DEF (50) -#define ALT_QSPI_TSD2D_NS_DEF (0) -#define ALT_QSPI_TCHSH_NS_DEF (4) -#define ALT_QSPI_TSLCH_NS_DEF (4) - -/* -// Default delay timing (in ns) -#define ALT_QSPI_TSHSL_NS_DEF (200) -#define ALT_QSPI_TSD2D_NS_DEF (255) -#define ALT_QSPI_TCHSH_NS_DEF (20) -#define ALT_QSPI_TSLCH_NS_DEF (20) -*/ - -// Flash commands -#define ALT_QSPI_STIG_OPCODE_READ (0x03) -#define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13) -#define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B) -#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B) -#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B) -#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB) -#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB) -#define ALT_QSPI_STIG_OPCODE_PP (0x02) -#define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2) -#define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32) -#define ALT_QSPI_STIG_OPCODE_RDID (0x9F) -#define ALT_QSPI_STIG_OPCODE_WREN (0x06) -#define ALT_QSPI_STIG_OPCODE_WRDIS (0x04) -#define ALT_QSPI_STIG_OPCODE_RDSR (0x05) -#define ALT_QSPI_STIG_OPCODE_WRSR (0x01) -#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20) -#define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8) -#define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7) -#define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4) -#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60) -#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8) -#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5) -#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05) -#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01) -#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7) -#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9) - -// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts. -#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT -#define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66) -#define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99) -#define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70) -#define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50) -#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A) -#endif - -// Spansion commands -// #define OPCODE_ECRM (0xFF) // Exit continuous read mode - -#define QSPI_READ_CLK_MHZ (50) -#define QSPI_FASTREAD_CLK_MHZ (100) - -// Manufacturer ID -#define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20) -#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron -#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF) -#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion -#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2) -#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F) - -#define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff) -#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff) - -#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1) -#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1) -#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1) -#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1) -#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1) -#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1) -#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1) - -#define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1) - -///// - -#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff) - -ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size); - -ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout); -ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy, - uint32_t num_bytes, uint32_t * output, - uint32_t timeout); -ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy, - uint32_t num_bytes, const uint32_t * input, - uint32_t timeout); -ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy, - uint32_t address, - uint32_t timeout); - -ALT_STATUS_CODE alt_qspi_device_wren(void); -ALT_STATUS_CODE alt_qspi_device_wrdis(void); -ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid); -ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param); -ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank); - -#endif // __ALT_PRIVATE_QSPI_H__ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h deleted file mode 100644 index d719e3f05e..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h +++ /dev/null @@ -1,291 +0,0 @@ -/*! \file - * Altera - SoC Reset Manager - */ - -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ALT_RESET_MGR_H__ -#define __ALT_RESET_MGR_H__ - -#include "hwlib.h" -#include <stdbool.h> - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/*! \addtogroup RST_MGR The Reset Manager - * - * The Reset Manager API defines functions for accessing, configuring, and - * controlling the HPS reset behavior. - * @{ - */ - -/******************************************************************************/ -/*! \addtogroup RST_MGR_STATUS Reset Status - * - * This functional group provides information on various aspects of SoC reset - * status and timeout events. - * - * @{ - */ - -/******************************************************************************/ -/*! - * This type definition enumerates the set of reset causes and timeout events as - * register mask values. - */ -typedef enum ALT_RESET_EVENT_e -{ - /*! Power-On Voltage Detector Cold Reset */ - ALT_RESET_EVENT_PORVOLTRST = 0x00000001, - - /*! nPOR Pin Cold Reset */ - ALT_RESET_EVENT_NPORPINRST = 0x00000002, - - /*! FPGA Core Cold Reset */ - ALT_RESET_EVENT_FPGACOLDRST = 0x00000004, - - /*! CONFIG_IO Cold Reset */ - ALT_RESET_EVENT_CONFIGIOCOLDRST = 0x00000008, - - /*! Software Cold Reset */ - ALT_RESET_EVENT_SWCOLDRST = 0x00000010, - - /*! nRST Pin Warm Reset */ - ALT_RESET_EVENT_NRSTPINRST = 0x00000100, - - /*! FPGA Core Warm Reset */ - ALT_RESET_EVENT_FPGAWARMRST = 0x00000200, - - /*! Software Warm Reset */ - ALT_RESET_EVENT_SWWARMRST = 0x00000400, - - /*! MPU Watchdog 0 Warm Reset */ - ALT_RESET_EVENT_MPUWD0RST = 0x00001000, - - /*! MPU Watchdog 1 Warm Reset */ - ALT_RESET_EVENT_MPUWD1RST = 0x00002000, - - /*! L4 Watchdog 0 Warm Reset */ - ALT_RESET_EVENT_L4WD0RST = 0x00004000, - - /*! L4 Watchdog 1 Warm Reset */ - ALT_RESET_EVENT_L4WD1RST = 0x00008000, - - /*! FPGA Core Debug Reset */ - ALT_RESET_EVENT_FPGADBGRST = 0x00040000, - - /*! DAP Debug Reset */ - ALT_RESET_EVENT_CDBGREQRST = 0x00080000, - - /*! SDRAM Self-Refresh Timeout */ - ALT_RESET_EVENT_SDRSELFREFTIMEOUT = 0x01000000, - - /*! FPGA manager handshake Timeout */ - ALT_RESET_EVENT_FPGAMGRHSTIMEOUT = 0x02000000, - - /*! SCAN manager handshake Timeout */ - ALT_RESET_EVENT_SCANHSTIMEOUT = 0x04000000, - - /*! FPGA handshake Timeout */ - ALT_RESET_EVENT_FPGAHSTIMEOUT = 0x08000000, - - /*! ETR Stall Timeout */ - ALT_RESET_EVENT_ETRSTALLTIMEOUT = 0x10000000 -} ALT_RESET_EVENT_t; - -/******************************************************************************/ -/*! - * Gets the reset and timeout events that caused the last reset. - * - * The ALT_RESET_EVENT_t enumeration values should be used to selectively - * examine the returned reset cause(s). - * - * \returns A mask of the reset and/or timeout events that caused the last - * reset. - */ -uint32_t alt_reset_event_get(void); - -/******************************************************************************/ -/*! - * Clears the reset and timeout events that caused the last reset. - * - * \param event_mask - * A mask of the selected reset and timeout events to clear in the - * Reset Manager \e stat register. The mask selection can be formed - * using the ALT_RESET_EVENT_t enumeration values. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask); - -/*! @} */ - -/******************************************************************************/ -/*! \addtogroup RST_MGR_CTRL Reset Control - * - * This functional group provides global and selective reset control for the SoC - * and its constituent modules. - * - * @{ - */ - -/******************************************************************************/ -/*! - * Initiate a cold reset of the SoC. - * - * If this function is successful, then it should never return. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_reset_cold_reset(void); - -/******************************************************************************/ -/*! - * Initiate a warm reset of the SoC. - * - * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced - * reset handshake with certain modules can optionally be requested in an - * attempt to ensure an orderly reset transition. - * - * \param warm_reset_delay - * Specifies the number of cycles after the Reset Manager releases - * the Clock Manager reset before releasing any other hardware - * controlled resets. Value must be greater than 16 and less than - * 256. - * - * \param nRST_pin_clk_assertion - * Specifies that number of clock cycles (osc1_clk?) to externally - * assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <= - * (2**20 - 1). A value of 0 prevents any assertion of nRST. - * - * \param sdram_refresh - * Controls whether the contents of SDRAM survive a hardware - * sequenced warm reset. The reset manager requests the SDRAM - * controller to put SDRAM devices into self-refresh mode before - * asserting warm reset signals. An argument value of \b true - * enables the option, \b false disables the option. - * - * \param fpga_mgr_handshake - * Controls whether a handshake between the reset manager and FPGA - * manager occurs before a warm reset. The handshake is used to - * warn the FPGA manager that a warm reset is imminent so it can - * prepare for it by driving its output clock to a quiescent state - * to avoid glitches. An argument value of \b true enables the - * option, \b false disables the option. - * - * \param scan_mgr_handshake - * Controls whether a handshake between the reset manager and scan - * manager occurs before a warm reset. The handshake is used to - * warn the scan manager that a warm reset is imminent so it can - * prepare for it by driving its output clock to a quiescent state - * to avoid glitches. An argument value of \b true enables the - * option, \b false disables the option. - * - * \param fpga_handshake - * Controls whether a handshake between the reset manager and the - * FPGA occurs before a warm reset. The handshake is used to warn - * the FPGA that a warm reset is imminent so that the FPGA prepare - * for the reset event in soft IP. An argument value of \b true - * enables the option, \b false disables the option. - * - * \param etr_stall - * Controls whether the ETR is requested to idle its AXI master - * interface (i.e. finish outstanding transactions and not initiate - * any more) to the L3 Interconnect before a warm reset. An - * argument value of \b true enables the option, \b false disables - * the option. - * - * \retval ALT_E_SUCCESS The operation was succesful. - * \retval ALT_E_ERROR The operation failed. - */ -ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay, - uint32_t nRST_pin_clk_assertion, - bool sdram_refresh, - bool fpga_mgr_handshake, - bool scan_mgr_handshake, - bool fpga_handshake, - bool etr_stall); - -#if 0 -/*! \addtogroup RST_MGR_MPU - * - * This functional group provides reset control for the Cortex-A9 MPU module. - * - * @{ - */ - -/*! @} */ - -/*! \addtogroup RST_MGR_PERIPH - * - * This functional group provides inidividual reset control for the HPS - * peripheral modules. - * - * @{ - */ - -/*! @} */ - -/*! \addtogroup RST_MGR_BRG - * - * This functional group provides inidividual reset control for the bridge - * interfaces between the HPS and FPGA. - * - * @{ - */ - -/*! @} */ - -/*! \addtogroup RST_MGR_MISC - * - * This functional group provides inidividual reset control for miscellaneous - * HPS modules. - * - * @{ - */ - -/*! @} */ - -#endif - -/*! @} */ - -/*! @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALT_RESET_MGR_H__ */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h deleted file mode 100644 index aba7e877c4..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h +++ /dev/null @@ -1,189 +0,0 @@ -/****************************************************************************** -* -* Copyright 2013 Altera Corporation. All Rights Reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -* OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HWLIB_H__ -#define __HWLIB_H__ - -#ifdef __cplusplus -#include <cstddef> -#include <cstdbool> -#include <cstdint> -#else /* __cplusplus */ -#include <stddef.h> -#include <stdbool.h> -#include <stdint.h> -#endif /* __cplusplus */ - -#include "alt_hwlibs_ver.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/*! - * The type definition for status codes returned by the HWLIB. - */ -typedef int32_t ALT_STATUS_CODE; - -/*! Definitions of status codes returned by the HWLIB. */ - -/*! The operation was successful. */ -#define ALT_E_SUCCESS 0 - -/*! The operation failed. */ -#define ALT_E_ERROR (-1) -/*! FPGA configuration error detected.*/ -#define ALT_E_FPGA_CFG (-2) -/*! FPGA CRC error detected. */ -#define ALT_E_FPGA_CRC (-3) -/*! An error occurred on the FPGA configuration bitstream input source. */ -#define ALT_E_FPGA_CFG_STM (-4) -/*! The FPGA is powered off. */ -#define ALT_E_FPGA_PWR_OFF (-5) -/*! The SoC does not currently control the FPGA. */ -#define ALT_E_FPGA_NO_SOC_CTRL (-6) -/*! The FPGA is not in USER mode. */ -#define ALT_E_FPGA_NOT_USER_MODE (-7) -/*! An argument violates a range constraint. */ -#define ALT_E_ARG_RANGE (-8) -/*! A bad argument value was passed. */ -#define ALT_E_BAD_ARG (-9) -/*! The operation is invalid or illegal. */ -#define ALT_E_BAD_OPERATION (-10) -/*! An invalid option was selected. */ -#define ALT_E_INV_OPTION (-11) -/*! An operation or response timeout period expired. */ -#define ALT_E_TMO (-12) -/*! The argument value is reserved or unavailable. */ -#define ALT_E_RESERVED (-13) -/*! A clock is not enabled or violates an operational constraint. */ -#define ALT_E_BAD_CLK (-14) -/*! The version ID is invalid. */ -#define ALT_E_BAD_VERSION (-15) -/*! The buffer does not contain enough free space for the operation. */ -#define ALT_E_BUF_OVF (-20) - -/*! - * Indicates a FALSE condition. - */ -#define ALT_E_FALSE (0) -/*! - * Indicates a TRUE condition. - */ -#define ALT_E_TRUE (1) - -/* Note, additional positive status codes may be defined to return - * a TRUE condition with additional information */ - - -/* Some other useful definitions */ - -/*! - * Specifies the current major and minor revision of the HWLibs. The - * MS four decimal digits specify the Altera ACDS release number, the - * LS two decimal digits specify minor revisions of the HWLibs, if any. - * - * A typical use is: - * \code - * #if ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0) - * \endcode - * for a dependency on the major or minor ACDS revision - * or - * \code - * #if ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12) - * \endcode - * for a dependency on the hwlibs revision - * - */ -#define ALT_HWLIBS_VERSION(a,b,c) (((a)*10000)+((b)*100)+(c)) - -#define ALTERA_HWLIBS_VERSION_CODE ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \ - ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV) - -/*! - * Allow some parts of the documentation to be hidden by setting to zero - */ -#define ALTERA_INTERNAL_ONLY_DOCS 1 - - -/*! - * Provide base address of MPU address space - */ - -#ifndef ALT_HPS_ADDR -#define ALT_HPS_ADDR 0 -#endif - -/*! - * These constants are sometimes useful: - */ -#define ALT_MILLISECS_IN_A_SEC 1000 -#define ALT_MICROSECS_IN_A_SEC 1000000 -#define ALT_NANOSECS_IN_A_SEC 1000000000 - -#define ALT_TWO_TO_POW0 (1) -#define ALT_TWO_TO_POW1 (1<<1) -#define ALT_TWO_TO_POW2 (1<<2) -#define ALT_TWO_TO_POW3 (1<<3) -#define ALT_TWO_TO_POW4 (1<<4) -#define ALT_TWO_TO_POW5 (1<<5) -#define ALT_TWO_TO_POW6 (1<<6) -#define ALT_TWO_TO_POW7 (1<<7) -#define ALT_TWO_TO_POW8 (1<<8) -#define ALT_TWO_TO_POW9 (1<<9) -#define ALT_TWO_TO_POW10 (1<<10) -#define ALT_TWO_TO_POW11 (1<<11) -#define ALT_TWO_TO_POW12 (1<<12) -#define ALT_TWO_TO_POW13 (1<<13) -#define ALT_TWO_TO_POW14 (1<<14) -#define ALT_TWO_TO_POW15 (1<<15) -#define ALT_TWO_TO_POW16 (1<<16) -#define ALT_TWO_TO_POW17 (1<<17) -#define ALT_TWO_TO_POW18 (1<<18) -#define ALT_TWO_TO_POW19 (1<<19) -#define ALT_TWO_TO_POW20 (1<<20) -#define ALT_TWO_TO_POW21 (1<<21) -#define ALT_TWO_TO_POW22 (1<<22) -#define ALT_TWO_TO_POW23 (1<<23) -#define ALT_TWO_TO_POW24 (1<<24) -#define ALT_TWO_TO_POW25 (1<<25) -#define ALT_TWO_TO_POW26 (1<<26) -#define ALT_TWO_TO_POW27 (1<<27) -#define ALT_TWO_TO_POW28 (1<<28) -#define ALT_TWO_TO_POW29 (1<<29) -#define ALT_TWO_TO_POW30 (1<<30) -#define ALT_TWO_TO_POW31 (1<<31) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __HWLIB_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h deleted file mode 100644 index 3a6bf0fffa..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_acpidmap.h +++ /dev/null @@ -1,3569 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_ACPIDMAP */ - -#ifndef __ALTERA_ALT_ACPIDMAP_H__ -#define __ALTERA_ALT_ACPIDMAP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : ACP ID Mapper Registers - ALT_ACPIDMAP - * ACP ID Mapper Registers - * - * Registers in the ACP ID Mapper module - * - */ -/* - * Register : Read AXI Master Mapping Register for Fixed Virtual ID 2 - vid2rd - * - * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x1 | ARUSER value to SCU for ID=2 - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x4 | Remap Master ID = DAP ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x1 | Force Mapping for ID=2 - * - */ -/* - * Field : ARUSER value to SCU for ID=2 - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ -#define ALT_ACPIDMAP_VID2RD_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */ -#define ALT_ACPIDMAP_VID2RD_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID2RD_USER register field. */ -#define ALT_ACPIDMAP_VID2RD_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID2RD_USER register field value. */ -#define ALT_ACPIDMAP_VID2RD_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID2RD_USER register field value. */ -#define ALT_ACPIDMAP_VID2RD_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID2RD_USER register field. */ -#define ALT_ACPIDMAP_VID2RD_USER_RESET 0x1 -/* Extracts the ALT_ACPIDMAP_VID2RD_USER field value from a register. */ -#define ALT_ACPIDMAP_VID2RD_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID2RD_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2RD_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID2RD_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID2RD_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID2RD_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID2RD_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID2RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID2RD_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID2RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID2RD_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID2RD_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID2RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID2RD_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2RD_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID = DAP ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ -#define ALT_ACPIDMAP_VID2RD_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */ -#define ALT_ACPIDMAP_VID2RD_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID2RD_MID register field. */ -#define ALT_ACPIDMAP_VID2RD_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID2RD_MID register field value. */ -#define ALT_ACPIDMAP_VID2RD_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID2RD_MID register field value. */ -#define ALT_ACPIDMAP_VID2RD_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID2RD_MID register field. */ -#define ALT_ACPIDMAP_VID2RD_MID_RESET 0x4 -/* Extracts the ALT_ACPIDMAP_VID2RD_MID field value from a register. */ -#define ALT_ACPIDMAP_VID2RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID2RD_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2RD_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping for ID=2 - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID2RD_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID2RD_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID2RD_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID2RD_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID2RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID2RD_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID2RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID2RD_FORCE_RESET 0x1 -/* Extracts the ALT_ACPIDMAP_VID2RD_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID2RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID2RD_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2RD_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID2RD. - */ -struct ALT_ACPIDMAP_VID2RD_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* ARUSER value to SCU for ID=2 */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* ARADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID = DAP ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping for ID=2 */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID2RD. */ -typedef volatile struct ALT_ACPIDMAP_VID2RD_s ALT_ACPIDMAP_VID2RD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID2RD register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID2RD_OFST 0x0 - -/* - * Register : Write AXI Master Mapping Register for Fixed Virtual ID 2 - vid2wr - * - * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x1 | AWUSER value to SCU for ID=2 - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x4 | Remap Master ID = DAP ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x1 | Force Mapping for ID=2 - * - */ -/* - * Field : AWUSER value to SCU for ID=2 - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ -#define ALT_ACPIDMAP_VID2WR_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */ -#define ALT_ACPIDMAP_VID2WR_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID2WR_USER register field. */ -#define ALT_ACPIDMAP_VID2WR_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID2WR_USER register field value. */ -#define ALT_ACPIDMAP_VID2WR_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID2WR_USER register field value. */ -#define ALT_ACPIDMAP_VID2WR_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID2WR_USER register field. */ -#define ALT_ACPIDMAP_VID2WR_USER_RESET 0x1 -/* Extracts the ALT_ACPIDMAP_VID2WR_USER field value from a register. */ -#define ALT_ACPIDMAP_VID2WR_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID2WR_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2WR_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID2WR_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID2WR_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID2WR_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID2WR_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID2WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID2WR_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID2WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID2WR_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID2WR_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID2WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID2WR_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2WR_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID = DAP ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ -#define ALT_ACPIDMAP_VID2WR_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */ -#define ALT_ACPIDMAP_VID2WR_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID2WR_MID register field. */ -#define ALT_ACPIDMAP_VID2WR_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID2WR_MID register field value. */ -#define ALT_ACPIDMAP_VID2WR_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID2WR_MID register field value. */ -#define ALT_ACPIDMAP_VID2WR_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID2WR_MID register field. */ -#define ALT_ACPIDMAP_VID2WR_MID_RESET 0x4 -/* Extracts the ALT_ACPIDMAP_VID2WR_MID field value from a register. */ -#define ALT_ACPIDMAP_VID2WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID2WR_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2WR_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping for ID=2 - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID2WR_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID2WR_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID2WR_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID2WR_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID2WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID2WR_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID2WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID2WR_FORCE_RESET 0x1 -/* Extracts the ALT_ACPIDMAP_VID2WR_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID2WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID2WR_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2WR_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID2WR. - */ -struct ALT_ACPIDMAP_VID2WR_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* AWUSER value to SCU for ID=2 */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* AWADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID = DAP ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping for ID=2 */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID2WR. */ -typedef volatile struct ALT_ACPIDMAP_VID2WR_s ALT_ACPIDMAP_VID2WR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID2WR register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID2WR_OFST 0x4 - -/* - * Register : Read AXI Master Mapping Register for Fixed Virtual ID 3 - vid3rd - * - * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | ARUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x0 | Remap Master ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x0 | Force Mapping - * - */ -/* - * Field : ARUSER value to SCU - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ -#define ALT_ACPIDMAP_VID3RD_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */ -#define ALT_ACPIDMAP_VID3RD_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID3RD_USER register field. */ -#define ALT_ACPIDMAP_VID3RD_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID3RD_USER register field value. */ -#define ALT_ACPIDMAP_VID3RD_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID3RD_USER register field value. */ -#define ALT_ACPIDMAP_VID3RD_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID3RD_USER register field. */ -#define ALT_ACPIDMAP_VID3RD_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3RD_USER field value from a register. */ -#define ALT_ACPIDMAP_VID3RD_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID3RD_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3RD_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID3RD_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID3RD_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID3RD_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID3RD_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID3RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID3RD_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID3RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID3RD_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3RD_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID3RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID3RD_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3RD_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ -#define ALT_ACPIDMAP_VID3RD_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */ -#define ALT_ACPIDMAP_VID3RD_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID3RD_MID register field. */ -#define ALT_ACPIDMAP_VID3RD_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID3RD_MID register field value. */ -#define ALT_ACPIDMAP_VID3RD_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID3RD_MID register field value. */ -#define ALT_ACPIDMAP_VID3RD_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID3RD_MID register field. */ -#define ALT_ACPIDMAP_VID3RD_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3RD_MID field value from a register. */ -#define ALT_ACPIDMAP_VID3RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID3RD_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3RD_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID3RD_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID3RD_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID3RD_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID3RD_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID3RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID3RD_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID3RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID3RD_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3RD_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID3RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID3RD_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3RD_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID3RD. - */ -struct ALT_ACPIDMAP_VID3RD_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* ARUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* ARADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID3RD. */ -typedef volatile struct ALT_ACPIDMAP_VID3RD_s ALT_ACPIDMAP_VID3RD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID3RD register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID3RD_OFST 0x8 - -/* - * Register : Write AXI Master Mapping Register for Fixed Virtual ID 3 - vid3wr - * - * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | AWUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x0 | Remap Master ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x0 | Force Mapping - * - */ -/* - * Field : AWUSER value to SCU - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ -#define ALT_ACPIDMAP_VID3WR_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_USER register field. */ -#define ALT_ACPIDMAP_VID3WR_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID3WR_USER register field. */ -#define ALT_ACPIDMAP_VID3WR_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID3WR_USER register field value. */ -#define ALT_ACPIDMAP_VID3WR_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID3WR_USER register field value. */ -#define ALT_ACPIDMAP_VID3WR_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID3WR_USER register field. */ -#define ALT_ACPIDMAP_VID3WR_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3WR_USER field value from a register. */ -#define ALT_ACPIDMAP_VID3WR_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID3WR_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3WR_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID3WR_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID3WR_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID3WR_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID3WR_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID3WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID3WR_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID3WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID3WR_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3WR_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID3WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID3WR_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3WR_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ -#define ALT_ACPIDMAP_VID3WR_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_MID register field. */ -#define ALT_ACPIDMAP_VID3WR_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID3WR_MID register field. */ -#define ALT_ACPIDMAP_VID3WR_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID3WR_MID register field value. */ -#define ALT_ACPIDMAP_VID3WR_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID3WR_MID register field value. */ -#define ALT_ACPIDMAP_VID3WR_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID3WR_MID register field. */ -#define ALT_ACPIDMAP_VID3WR_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3WR_MID field value from a register. */ -#define ALT_ACPIDMAP_VID3WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID3WR_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3WR_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID3WR_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID3WR_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID3WR_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID3WR_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID3WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID3WR_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID3WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID3WR_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3WR_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID3WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID3WR_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3WR_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID3WR. - */ -struct ALT_ACPIDMAP_VID3WR_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* AWUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* AWADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID3WR. */ -typedef volatile struct ALT_ACPIDMAP_VID3WR_s ALT_ACPIDMAP_VID3WR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID3WR register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID3WR_OFST 0xc - -/* - * Register : Read AXI Master Mapping Register for Fixed Virtual ID 4 - vid4rd - * - * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | ARUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x0 | Remap Master ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x0 | Force Mapping - * - */ -/* - * Field : ARUSER value to SCU - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ -#define ALT_ACPIDMAP_VID4RD_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_USER register field. */ -#define ALT_ACPIDMAP_VID4RD_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID4RD_USER register field. */ -#define ALT_ACPIDMAP_VID4RD_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID4RD_USER register field value. */ -#define ALT_ACPIDMAP_VID4RD_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID4RD_USER register field value. */ -#define ALT_ACPIDMAP_VID4RD_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID4RD_USER register field. */ -#define ALT_ACPIDMAP_VID4RD_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4RD_USER field value from a register. */ -#define ALT_ACPIDMAP_VID4RD_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID4RD_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4RD_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID4RD_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID4RD_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID4RD_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID4RD_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID4RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID4RD_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID4RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID4RD_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4RD_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID4RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID4RD_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4RD_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ -#define ALT_ACPIDMAP_VID4RD_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_MID register field. */ -#define ALT_ACPIDMAP_VID4RD_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID4RD_MID register field. */ -#define ALT_ACPIDMAP_VID4RD_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID4RD_MID register field value. */ -#define ALT_ACPIDMAP_VID4RD_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID4RD_MID register field value. */ -#define ALT_ACPIDMAP_VID4RD_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID4RD_MID register field. */ -#define ALT_ACPIDMAP_VID4RD_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4RD_MID field value from a register. */ -#define ALT_ACPIDMAP_VID4RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID4RD_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4RD_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID4RD_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID4RD_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID4RD_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID4RD_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID4RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID4RD_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID4RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID4RD_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4RD_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID4RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID4RD_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4RD_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID4RD. - */ -struct ALT_ACPIDMAP_VID4RD_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* ARUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* ARADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID4RD. */ -typedef volatile struct ALT_ACPIDMAP_VID4RD_s ALT_ACPIDMAP_VID4RD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID4RD register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID4RD_OFST 0x10 - -/* - * Register : Write AXI Master Mapping Register for Fixed Virtual ID 4 - vid4wr - * - * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | AWUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x0 | Remap Master ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x0 | Force Mapping - * - */ -/* - * Field : AWUSER value to SCU - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ -#define ALT_ACPIDMAP_VID4WR_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_USER register field. */ -#define ALT_ACPIDMAP_VID4WR_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID4WR_USER register field. */ -#define ALT_ACPIDMAP_VID4WR_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID4WR_USER register field value. */ -#define ALT_ACPIDMAP_VID4WR_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID4WR_USER register field value. */ -#define ALT_ACPIDMAP_VID4WR_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID4WR_USER register field. */ -#define ALT_ACPIDMAP_VID4WR_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4WR_USER field value from a register. */ -#define ALT_ACPIDMAP_VID4WR_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID4WR_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4WR_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID4WR_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID4WR_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID4WR_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID4WR_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID4WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID4WR_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID4WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID4WR_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4WR_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID4WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID4WR_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4WR_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ -#define ALT_ACPIDMAP_VID4WR_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_MID register field. */ -#define ALT_ACPIDMAP_VID4WR_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID4WR_MID register field. */ -#define ALT_ACPIDMAP_VID4WR_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID4WR_MID register field value. */ -#define ALT_ACPIDMAP_VID4WR_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID4WR_MID register field value. */ -#define ALT_ACPIDMAP_VID4WR_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID4WR_MID register field. */ -#define ALT_ACPIDMAP_VID4WR_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4WR_MID field value from a register. */ -#define ALT_ACPIDMAP_VID4WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID4WR_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4WR_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID4WR_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID4WR_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID4WR_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID4WR_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID4WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID4WR_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID4WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID4WR_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4WR_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID4WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID4WR_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4WR_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID4WR. - */ -struct ALT_ACPIDMAP_VID4WR_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* AWUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* AWADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID4WR. */ -typedef volatile struct ALT_ACPIDMAP_VID4WR_s ALT_ACPIDMAP_VID4WR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID4WR register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID4WR_OFST 0x14 - -/* - * Register : Read AXI Master Mapping Register for Fixed Virtual ID 5 - vid5rd - * - * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | ARUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x0 | Remap Master ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x0 | Force Mapping - * - */ -/* - * Field : ARUSER value to SCU - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ -#define ALT_ACPIDMAP_VID5RD_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_USER register field. */ -#define ALT_ACPIDMAP_VID5RD_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID5RD_USER register field. */ -#define ALT_ACPIDMAP_VID5RD_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID5RD_USER register field value. */ -#define ALT_ACPIDMAP_VID5RD_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID5RD_USER register field value. */ -#define ALT_ACPIDMAP_VID5RD_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID5RD_USER register field. */ -#define ALT_ACPIDMAP_VID5RD_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5RD_USER field value from a register. */ -#define ALT_ACPIDMAP_VID5RD_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID5RD_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5RD_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID5RD_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID5RD_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID5RD_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID5RD_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID5RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID5RD_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID5RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID5RD_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5RD_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID5RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID5RD_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5RD_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ -#define ALT_ACPIDMAP_VID5RD_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_MID register field. */ -#define ALT_ACPIDMAP_VID5RD_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID5RD_MID register field. */ -#define ALT_ACPIDMAP_VID5RD_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID5RD_MID register field value. */ -#define ALT_ACPIDMAP_VID5RD_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID5RD_MID register field value. */ -#define ALT_ACPIDMAP_VID5RD_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID5RD_MID register field. */ -#define ALT_ACPIDMAP_VID5RD_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5RD_MID field value from a register. */ -#define ALT_ACPIDMAP_VID5RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID5RD_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5RD_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID5RD_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID5RD_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID5RD_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID5RD_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID5RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID5RD_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID5RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID5RD_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5RD_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID5RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID5RD_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5RD_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID5RD. - */ -struct ALT_ACPIDMAP_VID5RD_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* ARUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* ARADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID5RD. */ -typedef volatile struct ALT_ACPIDMAP_VID5RD_s ALT_ACPIDMAP_VID5RD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID5RD register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID5RD_OFST 0x18 - -/* - * Register : Write AXI Master Mapping Register for Fixed Virtual ID 5 - vid5wr - * - * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | AWUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x0 | Remap Master ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x0 | Force Mapping - * - */ -/* - * Field : AWUSER value to SCU - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ -#define ALT_ACPIDMAP_VID5WR_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_USER register field. */ -#define ALT_ACPIDMAP_VID5WR_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID5WR_USER register field. */ -#define ALT_ACPIDMAP_VID5WR_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID5WR_USER register field value. */ -#define ALT_ACPIDMAP_VID5WR_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID5WR_USER register field value. */ -#define ALT_ACPIDMAP_VID5WR_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID5WR_USER register field. */ -#define ALT_ACPIDMAP_VID5WR_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5WR_USER field value from a register. */ -#define ALT_ACPIDMAP_VID5WR_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID5WR_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5WR_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID5WR_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID5WR_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID5WR_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID5WR_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID5WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID5WR_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID5WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID5WR_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5WR_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID5WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID5WR_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5WR_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ -#define ALT_ACPIDMAP_VID5WR_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_MID register field. */ -#define ALT_ACPIDMAP_VID5WR_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID5WR_MID register field. */ -#define ALT_ACPIDMAP_VID5WR_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID5WR_MID register field value. */ -#define ALT_ACPIDMAP_VID5WR_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID5WR_MID register field value. */ -#define ALT_ACPIDMAP_VID5WR_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID5WR_MID register field. */ -#define ALT_ACPIDMAP_VID5WR_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5WR_MID field value from a register. */ -#define ALT_ACPIDMAP_VID5WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID5WR_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5WR_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID5WR_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID5WR_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID5WR_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID5WR_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID5WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID5WR_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID5WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID5WR_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5WR_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID5WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID5WR_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5WR_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID5WR. - */ -struct ALT_ACPIDMAP_VID5WR_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* AWUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* AWADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID5WR. */ -typedef volatile struct ALT_ACPIDMAP_VID5WR_s ALT_ACPIDMAP_VID5WR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID5WR register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID5WR_OFST 0x1c - -/* - * Register : Read AXI Master Mapping Register for Fixed Virtual ID 6 - vid6rd - * - * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | ARUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x0 | Remap Master ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x0 | Force Mapping - * - */ -/* - * Field : ARUSER value to SCU - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ -#define ALT_ACPIDMAP_VID6RD_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_USER register field. */ -#define ALT_ACPIDMAP_VID6RD_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID6RD_USER register field. */ -#define ALT_ACPIDMAP_VID6RD_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID6RD_USER register field value. */ -#define ALT_ACPIDMAP_VID6RD_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID6RD_USER register field value. */ -#define ALT_ACPIDMAP_VID6RD_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID6RD_USER register field. */ -#define ALT_ACPIDMAP_VID6RD_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6RD_USER field value from a register. */ -#define ALT_ACPIDMAP_VID6RD_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID6RD_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6RD_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID6RD_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID6RD_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID6RD_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID6RD_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID6RD_PAGE register field value. */ -#define ALT_ACPIDMAP_VID6RD_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID6RD_PAGE register field. */ -#define ALT_ACPIDMAP_VID6RD_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6RD_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID6RD_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID6RD_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6RD_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ -#define ALT_ACPIDMAP_VID6RD_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_MID register field. */ -#define ALT_ACPIDMAP_VID6RD_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID6RD_MID register field. */ -#define ALT_ACPIDMAP_VID6RD_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID6RD_MID register field value. */ -#define ALT_ACPIDMAP_VID6RD_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID6RD_MID register field value. */ -#define ALT_ACPIDMAP_VID6RD_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID6RD_MID register field. */ -#define ALT_ACPIDMAP_VID6RD_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6RD_MID field value from a register. */ -#define ALT_ACPIDMAP_VID6RD_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID6RD_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6RD_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID6RD_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID6RD_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID6RD_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID6RD_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID6RD_FORCE register field value. */ -#define ALT_ACPIDMAP_VID6RD_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID6RD_FORCE register field. */ -#define ALT_ACPIDMAP_VID6RD_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6RD_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID6RD_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID6RD_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6RD_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID6RD. - */ -struct ALT_ACPIDMAP_VID6RD_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* ARUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* ARADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID6RD. */ -typedef volatile struct ALT_ACPIDMAP_VID6RD_s ALT_ACPIDMAP_VID6RD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID6RD register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID6RD_OFST 0x20 - -/* - * Register : Write AXI Master Mapping Register for Fixed Virtual ID 6 - vid6wr - * - * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID - * signals mapping values for particular transaction with 12-bit ID which locks the - * fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | AWUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | RW | 0x0 | Remap Master ID - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | RW | 0x0 | Force Mapping - * - */ -/* - * Field : AWUSER value to SCU - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ -#define ALT_ACPIDMAP_VID6WR_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_USER register field. */ -#define ALT_ACPIDMAP_VID6WR_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID6WR_USER register field. */ -#define ALT_ACPIDMAP_VID6WR_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID6WR_USER register field value. */ -#define ALT_ACPIDMAP_VID6WR_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID6WR_USER register field value. */ -#define ALT_ACPIDMAP_VID6WR_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID6WR_USER register field. */ -#define ALT_ACPIDMAP_VID6WR_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6WR_USER field value from a register. */ -#define ALT_ACPIDMAP_VID6WR_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID6WR_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6WR_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID6WR_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID6WR_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID6WR_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID6WR_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID6WR_PAGE register field value. */ -#define ALT_ACPIDMAP_VID6WR_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID6WR_PAGE register field. */ -#define ALT_ACPIDMAP_VID6WR_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6WR_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID6WR_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID6WR_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6WR_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ -#define ALT_ACPIDMAP_VID6WR_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_MID register field. */ -#define ALT_ACPIDMAP_VID6WR_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID6WR_MID register field. */ -#define ALT_ACPIDMAP_VID6WR_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID6WR_MID register field value. */ -#define ALT_ACPIDMAP_VID6WR_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID6WR_MID register field value. */ -#define ALT_ACPIDMAP_VID6WR_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID6WR_MID register field. */ -#define ALT_ACPIDMAP_VID6WR_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6WR_MID field value from a register. */ -#define ALT_ACPIDMAP_VID6WR_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID6WR_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6WR_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID6WR_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID6WR_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID6WR_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID6WR_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID6WR_FORCE register field value. */ -#define ALT_ACPIDMAP_VID6WR_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID6WR_FORCE register field. */ -#define ALT_ACPIDMAP_VID6WR_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6WR_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID6WR_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID6WR_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6WR_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID6WR. - */ -struct ALT_ACPIDMAP_VID6WR_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* AWUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* AWADDR 1GB Page Decoder */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t mid : 12; /* Remap Master ID */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t force : 1; /* Force Mapping */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID6WR. */ -typedef volatile struct ALT_ACPIDMAP_VID6WR_s ALT_ACPIDMAP_VID6WR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID6WR register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID6WR_OFST 0x24 - -/* - * Register : Read AXI Master Mapping Register for Dynamic Virtual ID Remap - dynrd - * - * The Read AXI Master Mapping Register contains the USER, and ADDR page signals - * mapping values for transaction that dynamically remapped to one of the available - * 3-bit virtual IDs. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | ARUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder - * [31:14] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : ARUSER value to SCU - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ -#define ALT_ACPIDMAP_DYNRD_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_USER register field. */ -#define ALT_ACPIDMAP_DYNRD_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_DYNRD_USER register field. */ -#define ALT_ACPIDMAP_DYNRD_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_DYNRD_USER register field value. */ -#define ALT_ACPIDMAP_DYNRD_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_DYNRD_USER register field value. */ -#define ALT_ACPIDMAP_DYNRD_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_DYNRD_USER register field. */ -#define ALT_ACPIDMAP_DYNRD_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_DYNRD_USER field value from a register. */ -#define ALT_ACPIDMAP_DYNRD_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_DYNRD_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_DYNRD_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ -#define ALT_ACPIDMAP_DYNRD_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ -#define ALT_ACPIDMAP_DYNRD_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ -#define ALT_ACPIDMAP_DYNRD_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ -#define ALT_ACPIDMAP_DYNRD_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_DYNRD_PAGE register field value. */ -#define ALT_ACPIDMAP_DYNRD_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_DYNRD_PAGE register field. */ -#define ALT_ACPIDMAP_DYNRD_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_DYNRD_PAGE field value from a register. */ -#define ALT_ACPIDMAP_DYNRD_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_DYNRD_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_DYNRD_PAGE_SET(value) (((value) << 12) & 0x00003000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_DYNRD. - */ -struct ALT_ACPIDMAP_DYNRD_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* ARUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* ARADDR 1GB Page Decoder */ - uint32_t : 18; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_DYNRD. */ -typedef volatile struct ALT_ACPIDMAP_DYNRD_s ALT_ACPIDMAP_DYNRD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_DYNRD register from the beginning of the component. */ -#define ALT_ACPIDMAP_DYNRD_OFST 0x28 - -/* - * Register : Write AXI Master Mapping Register for Dynamic Virtual ID Remap - dynwr - * - * The Write AXI Master Mapping Register contains the USER, and ADDR page signals - * mapping values for transaction that dynamically remapped to one of the available - * 3-bit virtual IDs. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | RW | 0x0 | AWUSER value to SCU - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder - * [31:14] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : AWUSER value to SCU - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ -#define ALT_ACPIDMAP_DYNWR_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_USER register field. */ -#define ALT_ACPIDMAP_DYNWR_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_DYNWR_USER register field. */ -#define ALT_ACPIDMAP_DYNWR_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_DYNWR_USER register field value. */ -#define ALT_ACPIDMAP_DYNWR_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_DYNWR_USER register field value. */ -#define ALT_ACPIDMAP_DYNWR_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_DYNWR_USER register field. */ -#define ALT_ACPIDMAP_DYNWR_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_DYNWR_USER field value from a register. */ -#define ALT_ACPIDMAP_DYNWR_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_DYNWR_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_DYNWR_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ -#define ALT_ACPIDMAP_DYNWR_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ -#define ALT_ACPIDMAP_DYNWR_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ -#define ALT_ACPIDMAP_DYNWR_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ -#define ALT_ACPIDMAP_DYNWR_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_DYNWR_PAGE register field value. */ -#define ALT_ACPIDMAP_DYNWR_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_DYNWR_PAGE register field. */ -#define ALT_ACPIDMAP_DYNWR_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_DYNWR_PAGE field value from a register. */ -#define ALT_ACPIDMAP_DYNWR_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_DYNWR_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_DYNWR_PAGE_SET(value) (((value) << 12) & 0x00003000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_DYNWR. - */ -struct ALT_ACPIDMAP_DYNWR_s -{ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t user : 5; /* AWUSER value to SCU */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t page : 2; /* AWADDR 1GB Page Decoder */ - uint32_t : 18; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_DYNWR. */ -typedef volatile struct ALT_ACPIDMAP_DYNWR_s ALT_ACPIDMAP_DYNWR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_DYNWR register from the beginning of the component. */ -#define ALT_ACPIDMAP_DYNWR_OFST 0x2c - -/* - * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2rd_s - * - * The Read AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:-------------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | 0x1 | ARUSER value to SCU for ID=2 (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | 0x1 | Force Mapping for ID=2 (Status) - * - */ -/* - * Field : ARUSER value to SCU for ID=2 (Status) - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID2RD_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID2RD_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID2RD_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID2RD_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID2RD_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID2RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID2RD_S_USER_RESET 0x1 -/* Extracts the ALT_ACPIDMAP_VID2RD_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID2RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID2RD_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder (Status) - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID2RD_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID2RD_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID2RD_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID2RD_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID2RD_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID2RD_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID2RD_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID2RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID2RD_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID = DAP ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID2RD_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID2RD_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID2RD_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID2RD_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID2RD_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID2RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID2RD_S_MID_RESET 0x4 -/* Extracts the ALT_ACPIDMAP_VID2RD_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID2RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID2RD_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping for ID=2 (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID2RD_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID2RD_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID2RD_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID2RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID2RD_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID2RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID2RD_S_FORCE_RESET 0x1 -/* Extracts the ALT_ACPIDMAP_VID2RD_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID2RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID2RD_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID2RD_S. - */ -struct ALT_ACPIDMAP_VID2RD_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* ARUSER value to SCU for ID=2 (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID2RD_S. */ -typedef volatile struct ALT_ACPIDMAP_VID2RD_S_s ALT_ACPIDMAP_VID2RD_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID2RD_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID2RD_S_OFST 0x30 - -/* - * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 2 - vid2wr_s - * - * The Write AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:-------------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | 0x1 | AWUSER value to SCU for ID=2 (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | 0x4 | Remap Master ID = DAP ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | 0x1 | Force Mapping for ID=2 (Status) - * - */ -/* - * Field : AWUSER value to SCU for ID=2 (Status) - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID2WR_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID2WR_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID2WR_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID2WR_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID2WR_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID2WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID2WR_S_USER_RESET 0x1 -/* Extracts the ALT_ACPIDMAP_VID2WR_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID2WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID2WR_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder (Status) - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID2WR_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID2WR_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID2WR_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID2WR_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID2WR_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID2WR_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID2WR_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID2WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID2WR_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID = DAP ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID2WR_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID2WR_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID2WR_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID2WR_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID2WR_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID2WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID2WR_S_MID_RESET 0x4 -/* Extracts the ALT_ACPIDMAP_VID2WR_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID2WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID2WR_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping for ID=2 (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID2WR_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID2WR_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID2WR_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID2WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID2WR_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID2WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID2WR_S_FORCE_RESET 0x1 -/* Extracts the ALT_ACPIDMAP_VID2WR_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID2WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID2WR_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID2WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID2WR_S. - */ -struct ALT_ACPIDMAP_VID2WR_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* AWUSER value to SCU for ID=2 (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID = DAP ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping for ID=2 (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID2WR_S. */ -typedef volatile struct ALT_ACPIDMAP_VID2WR_S_s ALT_ACPIDMAP_VID2WR_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID2WR_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID2WR_S_OFST 0x34 - -/* - * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3rd_s - * - * The Read AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | ARUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | Unknown | Remap Master ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | Unknown | Force Mapping (Status) - * - */ -/* - * Field : ARUSER value to SCU (Status) - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID3RD_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID3RD_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID3RD_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID3RD_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID3RD_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID3RD_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID3RD_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3RD_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID3RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID3RD_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder (Status) - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID3RD_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID3RD_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID3RD_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID3RD_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID3RD_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID3RD_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3RD_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID3RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID3RD_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID3RD_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID3RD_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID3RD_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID3RD_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID3RD_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID3RD_S_MID register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID3RD_S_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3RD_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID3RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID3RD_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID3RD_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID3RD_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID3RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID3RD_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID3RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID3RD_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID3RD_S_FORCE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID3RD_S_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3RD_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID3RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID3RD_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID3RD_S. - */ -struct ALT_ACPIDMAP_VID3RD_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* ARUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID3RD_S. */ -typedef volatile struct ALT_ACPIDMAP_VID3RD_S_s ALT_ACPIDMAP_VID3RD_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID3RD_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID3RD_S_OFST 0x38 - -/* - * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 3 - vid3wr_s - * - * The Write AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | AWUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | Unknown | Remap Master ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | Unknown | Force Mapping (Status) - * - */ -/* - * Field : AWUSER value to SCU (Status) - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID3WR_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID3WR_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID3WR_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID3WR_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID3WR_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID3WR_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID3WR_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3WR_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID3WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID3WR_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder (Status) - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID3WR_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID3WR_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID3WR_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID3WR_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID3WR_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID3WR_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3WR_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID3WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID3WR_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID3WR_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID3WR_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID3WR_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID3WR_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID3WR_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID3WR_S_MID register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID3WR_S_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3WR_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID3WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID3WR_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID3WR_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID3WR_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID3WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID3WR_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID3WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID3WR_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID3WR_S_FORCE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID3WR_S_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID3WR_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID3WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID3WR_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID3WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID3WR_S. - */ -struct ALT_ACPIDMAP_VID3WR_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* AWUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID3WR_S. */ -typedef volatile struct ALT_ACPIDMAP_VID3WR_S_s ALT_ACPIDMAP_VID3WR_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID3WR_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID3WR_S_OFST 0x3c - -/* - * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4rd_s - * - * The Read AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | ARUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | Unknown | Remap Master ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | Unknown | Force Mapping (Status) - * - */ -/* - * Field : ARUSER value to SCU (Status) - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID4RD_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID4RD_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID4RD_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID4RD_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID4RD_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID4RD_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID4RD_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4RD_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID4RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID4RD_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder (Status) - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID4RD_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID4RD_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID4RD_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID4RD_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID4RD_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID4RD_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4RD_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID4RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID4RD_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID4RD_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID4RD_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID4RD_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID4RD_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID4RD_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID4RD_S_MID register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID4RD_S_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4RD_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID4RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID4RD_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID4RD_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID4RD_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID4RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID4RD_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID4RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID4RD_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID4RD_S_FORCE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID4RD_S_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4RD_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID4RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID4RD_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID4RD_S. - */ -struct ALT_ACPIDMAP_VID4RD_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* ARUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID4RD_S. */ -typedef volatile struct ALT_ACPIDMAP_VID4RD_S_s ALT_ACPIDMAP_VID4RD_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID4RD_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID4RD_S_OFST 0x40 - -/* - * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 4 - vid4wr_s - * - * The Write AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | AWUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | Unknown | Remap Master ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | Unknown | Force Mapping (Status) - * - */ -/* - * Field : AWUSER value to SCU (Status) - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID4WR_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID4WR_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID4WR_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID4WR_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID4WR_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID4WR_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID4WR_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4WR_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID4WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID4WR_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder (Status) - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID4WR_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID4WR_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID4WR_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID4WR_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID4WR_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID4WR_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4WR_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID4WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID4WR_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID4WR_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID4WR_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID4WR_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID4WR_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID4WR_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID4WR_S_MID register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID4WR_S_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4WR_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID4WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID4WR_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID4WR_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID4WR_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID4WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID4WR_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID4WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID4WR_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID4WR_S_FORCE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID4WR_S_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID4WR_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID4WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID4WR_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID4WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID4WR_S. - */ -struct ALT_ACPIDMAP_VID4WR_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* AWUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID4WR_S. */ -typedef volatile struct ALT_ACPIDMAP_VID4WR_S_s ALT_ACPIDMAP_VID4WR_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID4WR_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID4WR_S_OFST 0x44 - -/* - * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5rd_s - * - * The Read AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | ARUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | Unknown | Remap Master ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | Unknown | Force Mapping (Status) - * - */ -/* - * Field : ARUSER value to SCU (Status) - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID5RD_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID5RD_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID5RD_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID5RD_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID5RD_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID5RD_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID5RD_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5RD_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID5RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID5RD_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder (Status) - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID5RD_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID5RD_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID5RD_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID5RD_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID5RD_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID5RD_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5RD_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID5RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID5RD_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID5RD_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID5RD_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID5RD_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID5RD_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID5RD_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID5RD_S_MID register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID5RD_S_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5RD_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID5RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID5RD_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID5RD_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID5RD_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID5RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID5RD_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID5RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID5RD_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID5RD_S_FORCE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID5RD_S_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5RD_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID5RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID5RD_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID5RD_S. - */ -struct ALT_ACPIDMAP_VID5RD_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* ARUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID5RD_S. */ -typedef volatile struct ALT_ACPIDMAP_VID5RD_S_s ALT_ACPIDMAP_VID5RD_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID5RD_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID5RD_S_OFST 0x48 - -/* - * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 5 - vid5wr_s - * - * The Write AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | AWUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | Unknown | Remap Master ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | Unknown | Force Mapping (Status) - * - */ -/* - * Field : AWUSER value to SCU (Status) - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID5WR_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID5WR_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID5WR_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID5WR_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID5WR_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID5WR_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID5WR_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5WR_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID5WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID5WR_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder (Status) - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID5WR_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID5WR_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID5WR_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID5WR_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID5WR_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID5WR_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5WR_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID5WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID5WR_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID5WR_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID5WR_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID5WR_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID5WR_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID5WR_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID5WR_S_MID register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID5WR_S_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5WR_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID5WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID5WR_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID5WR_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID5WR_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID5WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID5WR_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID5WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID5WR_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID5WR_S_FORCE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID5WR_S_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID5WR_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID5WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID5WR_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID5WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID5WR_S. - */ -struct ALT_ACPIDMAP_VID5WR_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* AWUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID5WR_S. */ -typedef volatile struct ALT_ACPIDMAP_VID5WR_S_s ALT_ACPIDMAP_VID5WR_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID5WR_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID5WR_S_OFST 0x4c - -/* - * Register : Read AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6rd_s - * - * The Read AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | ARUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | Unknown | Remap Master ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | Unknown | Force Mapping (Status) - * - */ -/* - * Field : ARUSER value to SCU (Status) - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID6RD_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID6RD_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_USER register field. */ -#define ALT_ACPIDMAP_VID6RD_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID6RD_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_USER register field value. */ -#define ALT_ACPIDMAP_VID6RD_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID6RD_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID6RD_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6RD_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID6RD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID6RD_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6RD_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder (Status) - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID6RD_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID6RD_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID6RD_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID6RD_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID6RD_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID6RD_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6RD_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID6RD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID6RD_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6RD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID6RD_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID6RD_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_MID register field. */ -#define ALT_ACPIDMAP_VID6RD_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID6RD_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_MID register field value. */ -#define ALT_ACPIDMAP_VID6RD_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID6RD_S_MID register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID6RD_S_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6RD_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID6RD_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID6RD_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6RD_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID6RD_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID6RD_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID6RD_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID6RD_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID6RD_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID6RD_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID6RD_S_FORCE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID6RD_S_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6RD_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID6RD_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID6RD_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6RD_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID6RD_S. - */ -struct ALT_ACPIDMAP_VID6RD_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* ARUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID6RD_S. */ -typedef volatile struct ALT_ACPIDMAP_VID6RD_S_s ALT_ACPIDMAP_VID6RD_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID6RD_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID6RD_S_OFST 0x50 - -/* - * Register : Write AXI Master Mapping Status Register for Fixed Virtual ID 6 - vid6wr_s - * - * The Write AXI Master Mapping Status Register contains the configured USER, ADDR - * page, and ID signals mapping values for particular transaction with 12-bit ID - * which locks the fixed 3-bit virtual ID. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | AWUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [27:16] | R | Unknown | Remap Master ID (Status) - * [30:28] | ??? | 0x0 | *UNDEFINED* - * [31] | R | Unknown | Force Mapping (Status) - * - */ -/* - * Field : AWUSER value to SCU (Status) - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID6WR_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID6WR_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_USER register field. */ -#define ALT_ACPIDMAP_VID6WR_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID6WR_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_USER register field value. */ -#define ALT_ACPIDMAP_VID6WR_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_VID6WR_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID6WR_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6WR_S_USER field value from a register. */ -#define ALT_ACPIDMAP_VID6WR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_VID6WR_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6WR_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder (Status) - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID6WR_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID6WR_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_PAGE register field. */ -#define ALT_ACPIDMAP_VID6WR_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_VID6WR_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_VID6WR_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID6WR_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6WR_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_VID6WR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_VID6WR_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6WR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Remap Master ID (Status) - mid - * - * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit - * ID to use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID6WR_S_MID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID6WR_S_MID_MSB 27 -/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_MID register field. */ -#define ALT_ACPIDMAP_VID6WR_S_MID_WIDTH 12 -/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID6WR_S_MID_SET_MSK 0x0fff0000 -/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_MID register field value. */ -#define ALT_ACPIDMAP_VID6WR_S_MID_CLR_MSK 0xf000ffff -/* The reset value of the ALT_ACPIDMAP_VID6WR_S_MID register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID6WR_S_MID_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6WR_S_MID field value from a register. */ -#define ALT_ACPIDMAP_VID6WR_S_MID_GET(value) (((value) & 0x0fff0000) >> 16) -/* Produces a ALT_ACPIDMAP_VID6WR_S_MID register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6WR_S_MID_SET(value) (((value) << 16) & 0x0fff0000) - -/* - * Field : Force Mapping (Status) - force - * - * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set - * to 0 to allow the 3-bit ID N to be dynamically allocated. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID6WR_S_FORCE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID6WR_S_FORCE_MSB 31 -/* The width in bits of the ALT_ACPIDMAP_VID6WR_S_FORCE register field. */ -#define ALT_ACPIDMAP_VID6WR_S_FORCE_WIDTH 1 -/* The mask used to set the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_ACPIDMAP_VID6WR_S_FORCE register field value. */ -#define ALT_ACPIDMAP_VID6WR_S_FORCE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_ACPIDMAP_VID6WR_S_FORCE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_VID6WR_S_FORCE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_VID6WR_S_FORCE field value from a register. */ -#define ALT_ACPIDMAP_VID6WR_S_FORCE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_ACPIDMAP_VID6WR_S_FORCE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_VID6WR_S_FORCE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_VID6WR_S. - */ -struct ALT_ACPIDMAP_VID6WR_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* AWUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t mid : 12; /* Remap Master ID (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t force : 1; /* Force Mapping (Status) */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_VID6WR_S. */ -typedef volatile struct ALT_ACPIDMAP_VID6WR_S_s ALT_ACPIDMAP_VID6WR_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_VID6WR_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_VID6WR_S_OFST 0x54 - -/* - * Register : Read AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynrd_s - * - * The Read AXI Master Mapping Status Register contains the configured USER, and - * ADDR page signals mapping values for transaction that dynamically remapped to - * one of the available 3-bit virtual IDs. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | ARUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | ARADDR 1GB Page Decoder (Status) - * [31:14] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : ARUSER value to SCU (Status) - user - * - * This value is propagated to SCU as ARUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ -#define ALT_ACPIDMAP_DYNRD_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ -#define ALT_ACPIDMAP_DYNRD_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_USER register field. */ -#define ALT_ACPIDMAP_DYNRD_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ -#define ALT_ACPIDMAP_DYNRD_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_USER register field value. */ -#define ALT_ACPIDMAP_DYNRD_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_DYNRD_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_DYNRD_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_DYNRD_S_USER field value from a register. */ -#define ALT_ACPIDMAP_DYNRD_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_DYNRD_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_DYNRD_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : ARADDR 1GB Page Decoder (Status) - page - * - * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ -#define ALT_ACPIDMAP_DYNRD_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ -#define ALT_ACPIDMAP_DYNRD_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_DYNRD_S_PAGE register field. */ -#define ALT_ACPIDMAP_DYNRD_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_DYNRD_S_PAGE register field value. */ -#define ALT_ACPIDMAP_DYNRD_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_DYNRD_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_DYNRD_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_DYNRD_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_DYNRD_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_DYNRD_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_DYNRD_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_DYNRD_S. - */ -struct ALT_ACPIDMAP_DYNRD_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* ARUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* ARADDR 1GB Page Decoder (Status) */ - uint32_t : 18; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_DYNRD_S. */ -typedef volatile struct ALT_ACPIDMAP_DYNRD_S_s ALT_ACPIDMAP_DYNRD_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_DYNRD_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_DYNRD_S_OFST 0x58 - -/* - * Register : Write AXI Master Mapping Status Register for Dynamic Virtual ID Remap - dynwr_s - * - * The Write AXI Master Mapping Status Register contains the configured USER, and - * ADDR page signals mapping values for transaction that dynamically remapped to - * one of the available 3-bit virtual IDs. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------- - * [3:0] | ??? | 0x0 | *UNDEFINED* - * [8:4] | R | Unknown | AWUSER value to SCU (Status) - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [13:12] | R | Unknown | AWADDR 1GB Page Decoder (Status) - * [31:14] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : AWUSER value to SCU (Status) - user - * - * This value is propagated to SCU as AWUSERS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ -#define ALT_ACPIDMAP_DYNWR_S_USER_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ -#define ALT_ACPIDMAP_DYNWR_S_USER_MSB 8 -/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_USER register field. */ -#define ALT_ACPIDMAP_DYNWR_S_USER_WIDTH 5 -/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ -#define ALT_ACPIDMAP_DYNWR_S_USER_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_USER register field value. */ -#define ALT_ACPIDMAP_DYNWR_S_USER_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_ACPIDMAP_DYNWR_S_USER register field is UNKNOWN. */ -#define ALT_ACPIDMAP_DYNWR_S_USER_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_DYNWR_S_USER field value from a register. */ -#define ALT_ACPIDMAP_DYNWR_S_USER_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_ACPIDMAP_DYNWR_S_USER register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_DYNWR_S_USER_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : AWADDR 1GB Page Decoder (Status) - page - * - * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ -#define ALT_ACPIDMAP_DYNWR_S_PAGE_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ -#define ALT_ACPIDMAP_DYNWR_S_PAGE_MSB 13 -/* The width in bits of the ALT_ACPIDMAP_DYNWR_S_PAGE register field. */ -#define ALT_ACPIDMAP_DYNWR_S_PAGE_WIDTH 2 -/* The mask used to set the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET_MSK 0x00003000 -/* The mask used to clear the ALT_ACPIDMAP_DYNWR_S_PAGE register field value. */ -#define ALT_ACPIDMAP_DYNWR_S_PAGE_CLR_MSK 0xffffcfff -/* The reset value of the ALT_ACPIDMAP_DYNWR_S_PAGE register field is UNKNOWN. */ -#define ALT_ACPIDMAP_DYNWR_S_PAGE_RESET 0x0 -/* Extracts the ALT_ACPIDMAP_DYNWR_S_PAGE field value from a register. */ -#define ALT_ACPIDMAP_DYNWR_S_PAGE_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_ACPIDMAP_DYNWR_S_PAGE register field value suitable for setting the register. */ -#define ALT_ACPIDMAP_DYNWR_S_PAGE_SET(value) (((value) << 12) & 0x00003000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_ACPIDMAP_DYNWR_S. - */ -struct ALT_ACPIDMAP_DYNWR_S_s -{ - uint32_t : 4; /* *UNDEFINED* */ - const uint32_t user : 5; /* AWUSER value to SCU (Status) */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t page : 2; /* AWADDR 1GB Page Decoder (Status) */ - uint32_t : 18; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_ACPIDMAP_DYNWR_S. */ -typedef volatile struct ALT_ACPIDMAP_DYNWR_S_s ALT_ACPIDMAP_DYNWR_S_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_ACPIDMAP_DYNWR_S register from the beginning of the component. */ -#define ALT_ACPIDMAP_DYNWR_S_OFST 0x5c - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_ACPIDMAP. - */ -struct ALT_ACPIDMAP_s -{ - volatile ALT_ACPIDMAP_VID2RD_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ - volatile ALT_ACPIDMAP_VID2WR_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ - volatile ALT_ACPIDMAP_VID3RD_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ - volatile ALT_ACPIDMAP_VID3WR_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ - volatile ALT_ACPIDMAP_VID4RD_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ - volatile ALT_ACPIDMAP_VID4WR_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ - volatile ALT_ACPIDMAP_VID5RD_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ - volatile ALT_ACPIDMAP_VID5WR_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ - volatile ALT_ACPIDMAP_VID6RD_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ - volatile ALT_ACPIDMAP_VID6WR_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ - volatile ALT_ACPIDMAP_DYNRD_t dynrd; /* ALT_ACPIDMAP_DYNRD */ - volatile ALT_ACPIDMAP_DYNWR_t dynwr; /* ALT_ACPIDMAP_DYNWR */ - volatile ALT_ACPIDMAP_VID2RD_S_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ - volatile ALT_ACPIDMAP_VID2WR_S_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ - volatile ALT_ACPIDMAP_VID3RD_S_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ - volatile ALT_ACPIDMAP_VID3WR_S_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ - volatile ALT_ACPIDMAP_VID4RD_S_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ - volatile ALT_ACPIDMAP_VID4WR_S_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ - volatile ALT_ACPIDMAP_VID5RD_S_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ - volatile ALT_ACPIDMAP_VID5WR_S_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ - volatile ALT_ACPIDMAP_VID6RD_S_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ - volatile ALT_ACPIDMAP_VID6WR_S_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ - volatile ALT_ACPIDMAP_DYNRD_S_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ - volatile ALT_ACPIDMAP_DYNWR_S_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ - volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_ACPIDMAP. */ -typedef volatile struct ALT_ACPIDMAP_s ALT_ACPIDMAP_t; -/* The struct declaration for the raw register contents of register group ALT_ACPIDMAP. */ -struct ALT_ACPIDMAP_raw_s -{ - volatile uint32_t vid2rd; /* ALT_ACPIDMAP_VID2RD */ - volatile uint32_t vid2wr; /* ALT_ACPIDMAP_VID2WR */ - volatile uint32_t vid3rd; /* ALT_ACPIDMAP_VID3RD */ - volatile uint32_t vid3wr; /* ALT_ACPIDMAP_VID3WR */ - volatile uint32_t vid4rd; /* ALT_ACPIDMAP_VID4RD */ - volatile uint32_t vid4wr; /* ALT_ACPIDMAP_VID4WR */ - volatile uint32_t vid5rd; /* ALT_ACPIDMAP_VID5RD */ - volatile uint32_t vid5wr; /* ALT_ACPIDMAP_VID5WR */ - volatile uint32_t vid6rd; /* ALT_ACPIDMAP_VID6RD */ - volatile uint32_t vid6wr; /* ALT_ACPIDMAP_VID6WR */ - volatile uint32_t dynrd; /* ALT_ACPIDMAP_DYNRD */ - volatile uint32_t dynwr; /* ALT_ACPIDMAP_DYNWR */ - volatile uint32_t vid2rd_s; /* ALT_ACPIDMAP_VID2RD_S */ - volatile uint32_t vid2wr_s; /* ALT_ACPIDMAP_VID2WR_S */ - volatile uint32_t vid3rd_s; /* ALT_ACPIDMAP_VID3RD_S */ - volatile uint32_t vid3wr_s; /* ALT_ACPIDMAP_VID3WR_S */ - volatile uint32_t vid4rd_s; /* ALT_ACPIDMAP_VID4RD_S */ - volatile uint32_t vid4wr_s; /* ALT_ACPIDMAP_VID4WR_S */ - volatile uint32_t vid5rd_s; /* ALT_ACPIDMAP_VID5RD_S */ - volatile uint32_t vid5wr_s; /* ALT_ACPIDMAP_VID5WR_S */ - volatile uint32_t vid6rd_s; /* ALT_ACPIDMAP_VID6RD_S */ - volatile uint32_t vid6wr_s; /* ALT_ACPIDMAP_VID6WR_S */ - volatile uint32_t dynrd_s; /* ALT_ACPIDMAP_DYNRD_S */ - volatile uint32_t dynwr_s; /* ALT_ACPIDMAP_DYNWR_S */ - volatile uint32_t _pad_0x60_0x1000[1000]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_ACPIDMAP. */ -typedef volatile struct ALT_ACPIDMAP_raw_s ALT_ACPIDMAP_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_ACPIDMAP_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_clkmgr.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_clkmgr.h deleted file mode 100644 index 1875a84f10..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_clkmgr.h +++ /dev/null @@ -1,6464 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_CLKMGR */ - -#ifndef __ALTERA_ALT_CLKMGR_H__ -#define __ALTERA_ALT_CLKMGR_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : Clock Manager Module - ALT_CLKMGR - * Clock Manager Module - * - * Registers in the Clock Manager module - * - */ -/* - * Register : Control Register - ctrl - * - * Contains fields that control the entire Clock Manager. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [0] | RW | 0x1 | Safe Mode - * [1] | ??? | 0x0 | *UNDEFINED* - * [2] | RW | 0x1 | Enable SafeMode on Warm Reset - * [31:3] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Safe Mode - safemode - * - * When set the Clock Manager is in Safe Mode. - * - * In Safe Mode Clock Manager register settings defining clock behavior are ignored - * and clocks are set to a Safe Mode state.In Safe Mode all clocks with the - * optional exception of debug clocks, are directly generated from the EOSC1 clock - * input, all PLLs are bypassed, all programmable dividers are set to 1 and all - * clocks are enabled. - * - * This bit should only be cleared when clocks have been correctly configured - * - * This field is set on a cold reset and optionally on a warm reset and may not be - * set by SW. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */ -#define ALT_CLKMGR_CTL_SAFEMOD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field. */ -#define ALT_CLKMGR_CTL_SAFEMOD_MSB 0 -/* The width in bits of the ALT_CLKMGR_CTL_SAFEMOD register field. */ -#define ALT_CLKMGR_CTL_SAFEMOD_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_CTL_SAFEMOD register field value. */ -#define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_CTL_SAFEMOD register field value. */ -#define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_CTL_SAFEMOD register field. */ -#define ALT_CLKMGR_CTL_SAFEMOD_RESET 0x1 -/* Extracts the ALT_CLKMGR_CTL_SAFEMOD field value from a register. */ -#define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_CTL_SAFEMOD register field value suitable for setting the register. */ -#define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Enable SafeMode on Warm Reset - ensfmdwr - * - * When set the Clock Manager will respond to a Safe Mode request from the Reset - * Manager on a warm reset by setting the Safe Mode bit. When clear the clock - * manager will not set the the Safe Mode bit on a warm reset This bit is cleared - * on a cold reset. Warm reset has no affect on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ -#define ALT_CLKMGR_CTL_ENSFMDWR_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ -#define ALT_CLKMGR_CTL_ENSFMDWR_MSB 2 -/* The width in bits of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ -#define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_CTL_ENSFMDWR register field value. */ -#define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_CTL_ENSFMDWR register field value. */ -#define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_CTL_ENSFMDWR register field. */ -#define ALT_CLKMGR_CTL_ENSFMDWR_RESET 0x1 -/* Extracts the ALT_CLKMGR_CTL_ENSFMDWR field value from a register. */ -#define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_CTL_ENSFMDWR register field value suitable for setting the register. */ -#define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_CTL. - */ -struct ALT_CLKMGR_CTL_s -{ - uint32_t safemode : 1; /* Safe Mode */ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t ensfmdwr : 1; /* Enable SafeMode on Warm Reset */ - uint32_t : 29; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_CTL. */ -typedef volatile struct ALT_CLKMGR_CTL_s ALT_CLKMGR_CTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_CTL register from the beginning of the component. */ -#define ALT_CLKMGR_CTL_OFST 0x0 - -/* - * Register : PLL Bypass Register - bypass - * - * Contains fields that control bypassing each PLL. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [0] | RW | 0x1 | Main PLL Bypass - * [1] | RW | 0x1 | SDRAM PLL Bypass - * [2] | RW | 0x0 | SDRAM PLL Bypass Source - * [3] | RW | 0x1 | Peripheral PLL Bypass - * [4] | RW | 0x0 | Peripheral PLL Bypass Source - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Main PLL Bypass - mainpll - * - * When set, causes the Main PLL VCO and counters to be bypassed so that all clocks - * generated by the Main PLL are directly driven from the Main PLL input clock. The - * bypass source for Main PLL is the external eosc1_clk. - * - * The reset value for this bit is applied on a cold reset. Warm reset has no - * affect on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ -#define ALT_CLKMGR_BYPASS_MAINPLL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ -#define ALT_CLKMGR_BYPASS_MAINPLL_MSB 0 -/* The width in bits of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ -#define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_BYPASS_MAINPLL register field value. */ -#define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_BYPASS_MAINPLL register field value. */ -#define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_BYPASS_MAINPLL register field. */ -#define ALT_CLKMGR_BYPASS_MAINPLL_RESET 0x1 -/* Extracts the ALT_CLKMGR_BYPASS_MAINPLL field value from a register. */ -#define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_BYPASS_MAINPLL register field value suitable for setting the register. */ -#define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : SDRAM PLL Bypass - sdrpll - * - * When set, causes the SDRAM PLL VCO and counters to be bypassed so that all - * clocks generated by the SDRAM PLL are directly driven from either eosc1_clk or - * the SDRAM PLL input clock. - * - * The bypass clock source for SDRAM PLL is determined by the SDRAM PLL Bypass - * Source Register bit. - * - * The reset value for this bit is applied on a cold reset. Warm reset has no - * affect on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ -#define ALT_CLKMGR_BYPASS_SDRPLL_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ -#define ALT_CLKMGR_BYPASS_SDRPLL_MSB 1 -/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ -#define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLL register field value. */ -#define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLL register field value. */ -#define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLL register field. */ -#define ALT_CLKMGR_BYPASS_SDRPLL_RESET 0x1 -/* Extracts the ALT_CLKMGR_BYPASS_SDRPLL field value from a register. */ -#define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_BYPASS_SDRPLL register field value suitable for setting the register. */ -#define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : SDRAM PLL Bypass Source - sdrpllsrc - * - * This bit defines the bypass source forSDRAM PLL. - * - * When changing fields that affect VCO lock the PLL must be bypassed and this bit - * must be set to OSC1_CLK. - * - * The reset value for this bit is applied on a cold reset. Warm reset has no - * affect on this bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------------|:------|:--------------------- - * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1 - * ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC - * - * Select EOSC1 - */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_BYPASS_SDRPLLSRC - * - * Select PLL Input Mux - */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB 2 -/* The width in bits of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_BYPASS_SDRPLLSRC register field value. */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_BYPASS_SDRPLLSRC register field. */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET 0x0 -/* Extracts the ALT_CLKMGR_BYPASS_SDRPLLSRC field value from a register. */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_BYPASS_SDRPLLSRC register field value suitable for setting the register. */ -#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Peripheral PLL Bypass - perpll - * - * When set, causes the Peripheral PLL VCO and counters to be bypassed so that all - * clocks generated by the Peripheral PLL are directly driven from either eosc1_clk - * or the Peripheral PLL input clock. - * - * The bypass clock source for Peripheral PLL is determined by the Peripheral PLL - * Bypass Source Register bit. - * - * The reset value for this bit is applied on a cold reset. Warm reset has no - * affect on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */ -#define ALT_CLKMGR_BYPASS_PERPLL_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLL register field. */ -#define ALT_CLKMGR_BYPASS_PERPLL_MSB 3 -/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLL register field. */ -#define ALT_CLKMGR_BYPASS_PERPLL_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLL register field value. */ -#define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK 0x00000008 -/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLL register field value. */ -#define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_CLKMGR_BYPASS_PERPLL register field. */ -#define ALT_CLKMGR_BYPASS_PERPLL_RESET 0x1 -/* Extracts the ALT_CLKMGR_BYPASS_PERPLL field value from a register. */ -#define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_CLKMGR_BYPASS_PERPLL register field value suitable for setting the register. */ -#define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Peripheral PLL Bypass Source - perpllsrc - * - * This bit defines the bypass source forPeripheral PLL. - * - * When changing fields that affect VCO lock the PLL must be bypassed and this bit - * must be set to OSC1_CLK. - * - * The reset value for this bit is applied on a cold reset. Warm reset has no - * affect on this bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------------|:------|:--------------------- - * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 | 0x0 | Select EOSC1 - * ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX | 0x1 | Select PLL Input Mux - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC - * - * Select EOSC1 - */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_BYPASS_PERPLLSRC - * - * Select PLL Input Mux - */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB 4 -/* The width in bits of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK 0x00000010 -/* The mask used to clear the ALT_CLKMGR_BYPASS_PERPLLSRC register field value. */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK 0xffffffef -/* The reset value of the ALT_CLKMGR_BYPASS_PERPLLSRC register field. */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET 0x0 -/* Extracts the ALT_CLKMGR_BYPASS_PERPLLSRC field value from a register. */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_CLKMGR_BYPASS_PERPLLSRC register field value suitable for setting the register. */ -#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_BYPASS. - */ -struct ALT_CLKMGR_BYPASS_s -{ - uint32_t mainpll : 1; /* Main PLL Bypass */ - uint32_t sdrpll : 1; /* SDRAM PLL Bypass */ - uint32_t sdrpllsrc : 1; /* SDRAM PLL Bypass Source */ - uint32_t perpll : 1; /* Peripheral PLL Bypass */ - uint32_t perpllsrc : 1; /* Peripheral PLL Bypass Source */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_BYPASS. */ -typedef volatile struct ALT_CLKMGR_BYPASS_s ALT_CLKMGR_BYPASS_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_BYPASS register from the beginning of the component. */ -#define ALT_CLKMGR_BYPASS_OFST 0x4 - -/* - * Register : Interrupt Status Register - inter - * - * Contains fields that indicate the PLL lock status. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:----------------------------------- - * [0] | RW | 0x0 | Main PLL Achieved Lock - * [1] | RW | 0x0 | Peripheral PLL Achieved Lock - * [2] | RW | 0x0 | SDRAM PLL Achieved Lock - * [3] | RW | 0x0 | Main PLL Lost Lock - * [4] | RW | 0x0 | Peripheral PLL Lost Lock - * [5] | RW | 0x0 | SDRAM PLL Lost Lock - * [6] | R | Unknown | Main PLL Current Lock Status - * [7] | R | Unknown | Peripheral PLL Current Lock Status - * [8] | R | Unknown | SDRAM PLL Current Lock Status - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Main PLL Achieved Lock - mainpllachieved - * - * If 1, the Main PLL has achieved lock at least once since this bit was cleared. - * If 0, the Main PLL has not achieved lock since this bit was cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB 0 -/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_INTER_MAINPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTER_MAINPLLACHIEVED field value from a register. */ -#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_INTER_MAINPLLACHIEVED register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Peripheral PLL Achieved Lock - perpllachieved - * - * If 1, the Peripheral PLL has achieved lock at least once since this bit was - * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was - * cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB 1 -/* The width in bits of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_INTER_PERPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTER_PERPLLACHIEVED field value from a register. */ -#define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_INTER_PERPLLACHIEVED register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : SDRAM PLL Achieved Lock - sdrpllachieved - * - * If 1, the SDRAM PLL has achieved lock at least once since this bit was cleared. - * If 0, the SDRAM PLL has not achieved lock since this bit was cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB 2 -/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_INTER_SDRPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTER_SDRPLLACHIEVED field value from a register. */ -#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_INTER_SDRPLLACHIEVED register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Main PLL Lost Lock - mainplllost - * - * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0, - * the Main PLL has not lost lock since this bit was cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ -#define ALT_CLKMGR_INTER_MAINPLLLOST_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ -#define ALT_CLKMGR_INTER_MAINPLLLOST_MSB 3 -/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ -#define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */ -#define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK 0x00000008 -/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOST register field value. */ -#define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOST register field. */ -#define ALT_CLKMGR_INTER_MAINPLLLOST_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOST field value from a register. */ -#define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_CLKMGR_INTER_MAINPLLLOST register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Peripheral PLL Lost Lock - perplllost - * - * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared. - * If 0, the Peripheral PLL has not lost lock since this bit was cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ -#define ALT_CLKMGR_INTER_PERPLLLOST_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ -#define ALT_CLKMGR_INTER_PERPLLLOST_MSB 4 -/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ -#define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOST register field value. */ -#define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK 0x00000010 -/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOST register field value. */ -#define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK 0xffffffef -/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOST register field. */ -#define ALT_CLKMGR_INTER_PERPLLLOST_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTER_PERPLLLOST field value from a register. */ -#define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_CLKMGR_INTER_PERPLLLOST register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : SDRAM PLL Lost Lock - sdrplllost - * - * If 1, the SDRAM PLL has lost lock at least once since this bit was cleared. If - * 0, the SDRAM PLL has not lost lock since this bit was cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ -#define ALT_CLKMGR_INTER_SDRPLLLOST_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ -#define ALT_CLKMGR_INTER_SDRPLLLOST_MSB 5 -/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ -#define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */ -#define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK 0x00000020 -/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOST register field value. */ -#define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK 0xffffffdf -/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOST register field. */ -#define ALT_CLKMGR_INTER_SDRPLLLOST_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOST field value from a register. */ -#define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_CLKMGR_INTER_SDRPLLLOST register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Main PLL Current Lock Status - mainplllocked - * - * If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not - * locked. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ -#define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ -#define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB 6 -/* The width in bits of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field. */ -#define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */ -#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK 0x00000040 -/* The mask used to clear the ALT_CLKMGR_INTER_MAINPLLLOCKED register field value. */ -#define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK 0xffffffbf -/* The reset value of the ALT_CLKMGR_INTER_MAINPLLLOCKED register field is UNKNOWN. */ -#define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTER_MAINPLLLOCKED field value from a register. */ -#define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_CLKMGR_INTER_MAINPLLLOCKED register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Peripheral PLL Current Lock Status - perplllocked - * - * If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is - * currently not locked. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ -#define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ -#define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB 7 -/* The width in bits of the ALT_CLKMGR_INTER_PERPLLLOCKED register field. */ -#define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */ -#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK 0x00000080 -/* The mask used to clear the ALT_CLKMGR_INTER_PERPLLLOCKED register field value. */ -#define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK 0xffffff7f -/* The reset value of the ALT_CLKMGR_INTER_PERPLLLOCKED register field is UNKNOWN. */ -#define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTER_PERPLLLOCKED field value from a register. */ -#define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_CLKMGR_INTER_PERPLLLOCKED register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : SDRAM PLL Current Lock Status - sdrplllocked - * - * If 1, the SDRAM PLL is currently locked. If 0, the SDRAM PLL is currently not - * locked. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ -#define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ -#define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB 8 -/* The width in bits of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field. */ -#define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */ -#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK 0x00000100 -/* The mask used to clear the ALT_CLKMGR_INTER_SDRPLLLOCKED register field value. */ -#define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK 0xfffffeff -/* The reset value of the ALT_CLKMGR_INTER_SDRPLLLOCKED register field is UNKNOWN. */ -#define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTER_SDRPLLLOCKED field value from a register. */ -#define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_CLKMGR_INTER_SDRPLLLOCKED register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_INTER. - */ -struct ALT_CLKMGR_INTER_s -{ - uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock */ - uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock */ - uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock */ - uint32_t mainplllost : 1; /* Main PLL Lost Lock */ - uint32_t perplllost : 1; /* Peripheral PLL Lost Lock */ - uint32_t sdrplllost : 1; /* SDRAM PLL Lost Lock */ - const uint32_t mainplllocked : 1; /* Main PLL Current Lock Status */ - const uint32_t perplllocked : 1; /* Peripheral PLL Current Lock Status */ - const uint32_t sdrplllocked : 1; /* SDRAM PLL Current Lock Status */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_INTER. */ -typedef volatile struct ALT_CLKMGR_INTER_s ALT_CLKMGR_INTER_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_INTER register from the beginning of the component. */ -#define ALT_CLKMGR_INTER_OFST 0x8 - -/* - * Register : Interrupt Enable Register - intren - * - * Contain fields that enable the interrupt. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------------- - * [0] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable - * [1] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable - * [2] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable - * [3] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable - * [4] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable - * [5] | RW | 0x0 | SDRAM PLL Achieved Lock Interrupt Enable - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved - * - * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager - * interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into - * the Clock Manager interrupt output. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0 -/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTREN_MAINPLLACHIEVED field value from a register. */ -#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_INTREN_MAINPLLACHIEVED register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved - * - * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock - * Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is - * not ORed into the Clock Manager interrupt output. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1 -/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_INTREN_PERPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTREN_PERPLLACHIEVED field value from a register. */ -#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_INTREN_PERPLLACHIEVED register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrpllachieved - * - * When set to 1, the SDRAM PLL achieved lock bit is ORed into the Clock Manager - * interrupt output. When set to 0 the SDRAM PLL achieved lock bit is not ORed - * into the Clock Manager interrupt output. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB 2 -/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value. */ -#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field. */ -#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTREN_SDRPLLACHIEVED field value from a register. */ -#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_INTREN_SDRPLLACHIEVED register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost - * - * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager - * interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the - * Clock Manager interrupt output. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB 3 -/* The width in bits of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */ -#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000008 -/* The mask used to clear the ALT_CLKMGR_INTREN_MAINPLLLOST register field value. */ -#define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_CLKMGR_INTREN_MAINPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTREN_MAINPLLLOST field value from a register. */ -#define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_CLKMGR_INTREN_MAINPLLLOST register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost - * - * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager - * interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed - * into the Clock Manager interrupt output. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_PERPLLLOST_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_PERPLLLOST_MSB 4 -/* The width in bits of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */ -#define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000010 -/* The mask used to clear the ALT_CLKMGR_INTREN_PERPLLLOST register field value. */ -#define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xffffffef -/* The reset value of the ALT_CLKMGR_INTREN_PERPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_PERPLLLOST_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTREN_PERPLLLOST field value from a register. */ -#define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_CLKMGR_INTREN_PERPLLLOST register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : SDRAM PLL Achieved Lock Interrupt Enable - sdrplllost - * - * When set to 1, the SDRAM PLL lost lock bit is ORed into the Clock Manager - * interrupt output. When set to 0 the SDRAM PLL lost lock bit is not ORed into - * the Clock Manager interrupt output. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB 5 -/* The width in bits of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */ -#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK 0x00000020 -/* The mask used to clear the ALT_CLKMGR_INTREN_SDRPLLLOST register field value. */ -#define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK 0xffffffdf -/* The reset value of the ALT_CLKMGR_INTREN_SDRPLLLOST register field. */ -#define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET 0x0 -/* Extracts the ALT_CLKMGR_INTREN_SDRPLLLOST field value from a register. */ -#define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_CLKMGR_INTREN_SDRPLLLOST register field value suitable for setting the register. */ -#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_INTREN. - */ -struct ALT_CLKMGR_INTREN_s -{ - uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock Interrupt Enable */ - uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */ - uint32_t sdrpllachieved : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */ - uint32_t mainplllost : 1; /* Main PLL Achieved Lock Interrupt Enable */ - uint32_t perplllost : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */ - uint32_t sdrplllost : 1; /* SDRAM PLL Achieved Lock Interrupt Enable */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_INTREN. */ -typedef volatile struct ALT_CLKMGR_INTREN_s ALT_CLKMGR_INTREN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_INTREN register from the beginning of the component. */ -#define ALT_CLKMGR_INTREN_OFST 0xc - -/* - * Register : Debug clock Control Register - dbctrl - * - * Contains fields that control the debug clocks. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [0] | RW | 0x1 | Debug Clocks Stay on EOSC1_CLK - * [1] | RW | 0x1 | Debug Clocks Enable Safe Mode - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Debug Clocks Stay on EOSC1_CLK - stayosc1 - * - * When this bit is set the debug root clock (Main PLL C2 output) will always be - * bypassed to the EOSC1_clk independent of any other clock manager settings. - * When clear the debug source will be a function of register settings in the clock - * manager. Clocks affected by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk, - * and dbg_timer_clk. - * - * The reset value for this bit is applied on a cold reset. Warm reset has no - * affect on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ -#define ALT_CLKMGR_DBCTL_STAYOSC1_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ -#define ALT_CLKMGR_DBCTL_STAYOSC1_MSB 0 -/* The width in bits of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ -#define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */ -#define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_DBCTL_STAYOSC1 register field value. */ -#define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_DBCTL_STAYOSC1 register field. */ -#define ALT_CLKMGR_DBCTL_STAYOSC1_RESET 0x1 -/* Extracts the ALT_CLKMGR_DBCTL_STAYOSC1 field value from a register. */ -#define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_DBCTL_STAYOSC1 register field value suitable for setting the register. */ -#define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Debug Clocks Enable Safe Mode - ensfmdwr - * - * When this bit is set the debug clocks will be affected by the assertion of Safe - * Mode on a warm reset if Stay OSC1 is not set. - * - * When this bit is clear the debug clocks will not be affected by the assertion of - * Safe Mode on a warm reset. - * - * If Debug Clocks are in Safe Mode they are taken out of Safe Mode when the Safe - * Mode bit is cleared independent of this bit.The reset value of this bit is - * applied on a cold reset; warm reset has no affect on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ -#define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ -#define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB 1 -/* The width in bits of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ -#define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */ -#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_DBCTL_ENSFMDWR register field value. */ -#define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_DBCTL_ENSFMDWR register field. */ -#define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET 0x1 -/* Extracts the ALT_CLKMGR_DBCTL_ENSFMDWR field value from a register. */ -#define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_DBCTL_ENSFMDWR register field value suitable for setting the register. */ -#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_DBCTL. - */ -struct ALT_CLKMGR_DBCTL_s -{ - uint32_t stayosc1 : 1; /* Debug Clocks Stay on EOSC1_CLK */ - uint32_t ensfmdwr : 1; /* Debug Clocks Enable Safe Mode */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_DBCTL. */ -typedef volatile struct ALT_CLKMGR_DBCTL_s ALT_CLKMGR_DBCTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_DBCTL register from the beginning of the component. */ -#define ALT_CLKMGR_DBCTL_OFST 0x10 - -/* - * Register : Status Register - stat - * - * Provides status of Hardware Managed Clock transition State Machine. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------- - * [0] | R | 0x0 | HW Managed Clocks BUSY - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : HW Managed Clocks BUSY - busy - * - * This read only bit indicates that the Hardware Managed clock's state machine is - * active. If the state machine is active, then the clocks are in transition. - * Software should poll this bit after changing the source of internal clocks when - * writing to the BYPASS, CTRL or DBCTRL registers. Immediately following writes - * to any of these registers, SW should wait until this bit is IDLE before - * proceeding with any other register writes in the Clock Manager. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:--------------------- - * ALT_CLKMGR_STAT_BUSY_E_IDLE | 0x0 | Clocks stable - * ALT_CLKMGR_STAT_BUSY_E_BUSY | 0x1 | Clocks in transition - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_STAT_BUSY - * - * Clocks stable - */ -#define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_STAT_BUSY - * - * Clocks in transition - */ -#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BUSY register field. */ -#define ALT_CLKMGR_STAT_BUSY_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BUSY register field. */ -#define ALT_CLKMGR_STAT_BUSY_MSB 0 -/* The width in bits of the ALT_CLKMGR_STAT_BUSY register field. */ -#define ALT_CLKMGR_STAT_BUSY_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_STAT_BUSY register field value. */ -#define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_STAT_BUSY register field value. */ -#define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_STAT_BUSY register field. */ -#define ALT_CLKMGR_STAT_BUSY_RESET 0x0 -/* Extracts the ALT_CLKMGR_STAT_BUSY field value from a register. */ -#define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_STAT_BUSY register field value suitable for setting the register. */ -#define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_STAT. - */ -struct ALT_CLKMGR_STAT_s -{ - const uint32_t busy : 1; /* HW Managed Clocks BUSY */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_STAT. */ -typedef volatile struct ALT_CLKMGR_STAT_s ALT_CLKMGR_STAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_STAT register from the beginning of the component. */ -#define ALT_CLKMGR_STAT_OFST 0x14 - -/* - * Register Group : Main PLL Group - ALT_CLKMGR_MAINPLL - * Main PLL Group - * - * Contains registers with settings for the Main PLL. - * - */ -/* - * Register : Main PLL VCO Control Register - vco - * - * Contains settings that control the Main PLL VCO. The VCO output frequency is the - * input frequency multiplied by the numerator (M+1) and divided by the denominator - * (N+1). The VCO input clock source is always eosc1_clk. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------------------- - * [0] | RW | 0x1 | BG PWRDN - * [1] | RW | 0x0 | Enable - * [2] | RW | 0x1 | Power down - * [15:3] | RW | 0x1 | Numerator (M) - * [21:16] | RW | 0x1 | Denominator (N) - * [23:22] | ??? | 0x0 | *UNDEFINED* - * [24] | RW | 0x0 | All Output Counter Reset - * [30:25] | RW | 0x0 | Output Counter Reset - * [31] | RW | 0x1 | External Regulator Input Select - * - */ -/* - * Field : BG PWRDN - bgpwrdn - * - * If '1', powers down bandgap. If '0', bandgap is not power down. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB 0 -/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_VCO_BGPWRDN field value from a register. */ -#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_VCO_BGPWRDN register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Enable - en - * - * If '1', VCO is enabled. If '0', VCO is in reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_EN_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_EN_MSB 1 -/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_EN register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_EN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_EN_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_VCO_EN field value from a register. */ -#define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_MAINPLL_VCO_EN register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Power down - pwrdn - * - * If '1', power down analog circuitry. If '0', analog circuitry not powered down. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB 2 -/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_VCO_PWRDN field value from a register. */ -#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_MAINPLL_VCO_PWRDN register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Numerator (M) - numer - * - * Numerator in VCO output frequency equation. For incremental frequency change, if - * the new value lead to less than 20% of the frequency change, this value can be - * changed without resetting the PLL. The Numerator and Denominator can not be - * changed at the same time for incremental frequency changed. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB 15 -/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH 13 -/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK 0x0000fff8 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_NUMER register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK 0xffff0007 -/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_VCO_NUMER field value from a register. */ -#define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) -/* Produces a ALT_CLKMGR_MAINPLL_VCO_NUMER register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) - -/* - * Field : Denominator (N) - denom - * - * Denominator in VCO output frequency equation. For incremental frequency change, - * if the new value lead to less than 20% of the frequency change, this value can - * be changed without resetting the PLL. The Numerator and Denominator can not be - * changed at the same time for incremental frequency changed. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB 21 -/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH 6 -/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK 0x003f0000 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_DENOM register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK 0xffc0ffff -/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_VCO_DENOM field value from a register. */ -#define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) -/* Produces a ALT_CLKMGR_MAINPLL_VCO_DENOM register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) - -/* - * Field : All Output Counter Reset - outresetall - * - * Before releasing Bypass, All Output Counter Reset must be set and cleared by - * software for correct clock operation. - * - * If '1', Reset phase multiplexer and all output counter state. So that after the - * assertion all the clocks output are start from rising edge align. - * - * If '0', phase multiplexer and output counter state not reset and no change to - * the phase of the clock outputs. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB 24 -/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff -/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL field value from a register. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) -/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) - -/* - * Field : Output Counter Reset - outreset - * - * Resets the individual PLL output counter. - * - * For software to change the PLL output counter without producing glitches on the - * respective clock, SW must set the VCO register respective Output Counter Reset - * bit. Software then polls the respective Output Counter Reset Acknowledge bit in - * the Output Counter Reset Ack Status Register. Software then writes the - * appropriate counter register, and then clears the respective VCO register Output - * Counter Reset bit. - * - * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. - * - * If set to '1', reset output divider, no clock output from counter. - * - * If set to '0', counter is not reset. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB 25 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB 30 -/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH 6 -/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK 0x7e000000 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK 0x81ffffff -/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_VCO_OUTRST field value from a register. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) -/* Produces a ALT_CLKMGR_MAINPLL_VCO_OUTRST register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) - -/* - * Field : External Regulator Input Select - regextsel - * - * If set to '1', the external regulator is selected for the PLL. - * - * If set to '0', the internal regulator is slected. - * - * It is strongly recommended to select the external regulator while the PLL is not - * enabled (in reset), and then disable the external regulater once the PLL - * becomes enabled. Software should simulateously update the 'Enable' bit and the - * 'External Regulator Input Select' in the same write access to the VCO register. - * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be - * set, and vice versa. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB 31 -/* The width in bits of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value. */ -#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff -/* The reset value of the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL field value from a register. */ -#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_VCO. - */ -struct ALT_CLKMGR_MAINPLL_VCO_s -{ - uint32_t bgpwrdn : 1; /* BG PWRDN */ - uint32_t en : 1; /* Enable */ - uint32_t pwrdn : 1; /* Power down */ - uint32_t numer : 13; /* Numerator (M) */ - uint32_t denom : 6; /* Denominator (N) */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t outresetall : 1; /* All Output Counter Reset */ - uint32_t outreset : 6; /* Output Counter Reset */ - uint32_t regextsel : 1; /* External Regulator Input Select */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_VCO_s ALT_CLKMGR_MAINPLL_VCO_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_VCO register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_VCO_OFST 0x0 - -/* - * Register : Main PLL VCO Advanced Control Register - misc - * - * Contains VCO control signals and other PLL control signals need to be - * controllable through register. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------ - * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled - * [12:1] | RW | 0x1 | Loop Bandwidth Adjust - * [13] | RW | 0x0 | Fast Locking Enable - * [14] | RW | 0x1 | Saturation Enable - * [31:15] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Loop Bandwidth Adjust Enabled - bwadjen - * - * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth - * Adjust field. - * - * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 - * value of the VCO Control Register. The M divided by 2 is the upper 12 bits - * (12:1) of the M field in the VCO register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB 0 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJEN field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJEN register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Loop Bandwidth Adjust - bwadj - * - * Provides Loop Bandwidth Adjust value. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB 12 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH 12 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK 0x00001ffe -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK 0xffffe001 -/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_BWADJ register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_MISC_BWADJ field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) -/* Produces a ALT_CLKMGR_MAINPLL_MISC_BWADJ register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) - -/* - * Field : Fast Locking Enable - fasten - * - * Enables fast locking circuit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB 13 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */ -#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK 0x00002000 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value. */ -#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK 0xffffdfff -/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_FASTEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_MISC_FASTEN field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_CLKMGR_MAINPLL_MISC_FASTEN register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : Saturation Enable - saten - * - * Enables saturation behavior. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB 14 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */ -#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK 0x00004000 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MISC_SATEN register field value. */ -#define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK 0xffffbfff -/* The reset value of the ALT_CLKMGR_MAINPLL_MISC_SATEN register field. */ -#define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_MISC_SATEN field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_CLKMGR_MAINPLL_MISC_SATEN register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_MISC. - */ -struct ALT_CLKMGR_MAINPLL_MISC_s -{ - uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ - uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ - uint32_t fasten : 1; /* Fast Locking Enable */ - uint32_t saten : 1; /* Saturation Enable */ - uint32_t : 17; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MISC. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_MISC_s ALT_CLKMGR_MAINPLL_MISC_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_MISC register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_MISC_OFST 0x4 - -/* - * Register : Main PLL C0 Control Register for Clock mpu_clk - mpuclk - * - * Contains settings that control clock mpu_clk generated from the C0 output of the - * Main PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x0 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO/2 frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_CNT field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. - */ -struct ALT_CLKMGR_MAINPLL_MPUCLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_MPUCLK_s ALT_CLKMGR_MAINPLL_MPUCLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_MPUCLK register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x8 - -/* - * Register : Main PLL C1 Control Register for Clock main_clk - mainclk - * - * Contains settings that control clock main_clk generated from the C1 output of - * the Main PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x0 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO/4 frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_MAINCLK_CNT field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_MAINCLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. - */ -struct ALT_CLKMGR_MAINPLL_MAINCLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINCLK. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_MAINCLK_s ALT_CLKMGR_MAINPLL_MAINCLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINCLK register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_OFST 0xc - -/* - * Register : Main PLL C2 Control Register for Clock dbg_base_clk - dbgatclk - * - * Contains settings that control clock dbg_base_clk generated from the C2 output - * of the Main PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x0 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO/4 frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_DBGATCLK_CNT field value from a register. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_DBGATCLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. - */ -struct ALT_CLKMGR_MAINPLL_DBGATCLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGATCLK. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_DBGATCLK_s ALT_CLKMGR_MAINPLL_DBGATCLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGATCLK register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST 0x10 - -/* - * Register : Main PLL C3 Control Register for Clock main_qspi_clk - mainqspiclk - * - * Contains settings that control clock main_qspi_clk generated from the C3 output - * of the Main PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x3 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET 0x3 -/* Extracts the ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. - */ -struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINQSPICLK. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s ALT_CLKMGR_MAINPLL_MAINQSPICLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST 0x14 - -/* - * Register : Main PLL C4 Control Register for Clock main_nand_sdmmc_clk - mainnandsdmmcclk - * - * Contains settings that control clock main_nand_sdmmc_clk generated from the C4 - * output of the Main PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x3 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET 0x3 -/* Extracts the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. - */ -struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST 0x18 - -/* - * Register : Main PLL C5 Control Register for Clock cfg_s2f_user0_clk - cfgs2fuser0clk - * - * Contains settings that control clock cfg_s2f_user0_clk generated from the C5 - * output of the Main PLL. - * - * Qsys and user documenation refer to cfg_s2f_user0_clk as cfg_h2f_user0_clk. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0xf | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET 0xf -/* Extracts the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT field value from a register. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. - */ -struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST 0x1c - -/* - * Register : Enable Register - en - * - * Contains fields that control clock enables for clocks derived from the Main PLL. - * - * 1: The clock is enabled. - * - * 0: The clock is disabled. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:--------------------- - * [0] | RW | 0x1 | l4_main_clk Enable - * [1] | RW | 0x1 | l3_mp_clk Enable - * [2] | RW | 0x1 | l4_mp_clk Enable - * [3] | RW | 0x1 | l4_sp_clk Enable - * [4] | RW | 0x1 | dbg_at_clk Enable - * [5] | RW | 0x1 | dbg_clk Enable - * [6] | RW | 0x1 | dbg_trace_clk Enable - * [7] | RW | 0x1 | dbg_timer_clk Enable - * [8] | RW | 0x1 | cfg_clk Enable - * [9] | RW | 0x1 | s2f_user0_clk Enable - * [31:10] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : l4_main_clk Enable - l4mainclk - * - * Enables clock l4_main_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : l3_mp_clk Enable - l3mpclk - * - * Enables clock l3_mp_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_L3MPCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : l4_mp_clk Enable - l4mpclk - * - * Enables clock l4_mp_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : l4_sp_clk Enable - l4spclk - * - * Enables clock l4_sp_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : dbg_at_clk Enable - dbgatclk - * - * Enables clock dbg_at_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGATCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : dbg_clk Enable - dbgclk - * - * Enables clock dbg_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : dbg_trace_clk Enable - dbgtraceclk - * - * Enables clock dbg_trace_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : dbg_timer_clk Enable - dbgtimerclk - * - * Enables clock dbg_timer_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : cfg_clk Enable - cfgclk - * - * Enables clock cfg_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_CFGCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : s2f_user0_clk Enable - s2fuser0clk - * - * Enables clock s2f_user0_clk output. - * - * Qsys and user documenation refer to s2f_user0_clk as h2f_user0_clk. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9 -/* The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value. */ -#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff -/* The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field. */ -#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_EN. - */ -struct ALT_CLKMGR_MAINPLL_EN_s -{ - uint32_t l4mainclk : 1; /* l4_main_clk Enable */ - uint32_t l3mpclk : 1; /* l3_mp_clk Enable */ - uint32_t l4mpclk : 1; /* l4_mp_clk Enable */ - uint32_t l4spclk : 1; /* l4_sp_clk Enable */ - uint32_t dbgatclk : 1; /* dbg_at_clk Enable */ - uint32_t dbgclk : 1; /* dbg_clk Enable */ - uint32_t dbgtraceclk : 1; /* dbg_trace_clk Enable */ - uint32_t dbgtimerclk : 1; /* dbg_timer_clk Enable */ - uint32_t cfgclk : 1; /* cfg_clk Enable */ - uint32_t s2fuser0clk : 1; /* s2f_user0_clk Enable */ - uint32_t : 22; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_EN. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_EN_OFST 0x20 - -/* - * Register : Main Divide Register - maindiv - * - * Contains fields that control clock dividers for main clocks derived from the - * Main PLL - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------- - * [1:0] | RW | 0x0 | L3 MP Clock Divider - * [3:2] | RW | 0x0 | L3 SP Clock Divider - * [6:4] | RW | 0x0 | L4 MP Clock Divider - * [9:7] | RW | 0x0 | L4 SP Clock Divider - * [31:10] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : L3 MP Clock Divider - l3mpclk - * - * The l3_mp_clk is divided down from the l3_main_clk by the value specified in - * this field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------ - * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 | 0x0 | Divide by 1 - * ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 | 0x1 | Divide by 2 - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK - * - * Divide by 1 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK - * - * Divide by 2 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc -/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : L3 SP Clock Divider - l3spclk - * - * The l3_sp_clk is divided down from the l3_mp_clk by the value specified in this - * field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------ - * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 | 0x0 | Divide by 1 - * ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 | 0x1 | Divide by 2 - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK - * - * Divide by 1 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK - * - * Divide by 2 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3 -/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2) -/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c) - -/* - * Field : L4 MP Clock Divider - l4mpclk - * - * The l4_mp_clk is divided down from the periph_base_clk by the value specified in - * this field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------- - * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 | 0x0 | Divide By 1 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 | 0x1 | Divide By 2 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 | 0x2 | Divide By 4 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 | 0x3 | Divide By 8 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 | 0x4 | Divide By 16 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 | 0x5 | Reserved - * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 | 0x6 | Reserved - * ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 | 0x7 | Reserved - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK - * - * Divide By 1 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK - * - * Divide By 2 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK - * - * Divide By 4 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK - * - * Divide By 8 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK - * - * Divide By 16 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK - * - * Reserved - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK - * - * Reserved - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK - * - * Reserved - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f -/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4) -/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070) - -/* - * Field : L4 SP Clock Divider - l4spclk - * - * The l4_sp_clk is divided down from the periph_base_clk by the value specified in - * this field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------- - * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 | 0x0 | Divide By 1 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 | 0x1 | Divide By 2 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 | 0x2 | Divide By 4 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 | 0x3 | Divide By 8 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 | 0x4 | Divide By 16 - * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 | 0x5 | Reserved - * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 | 0x6 | Reserved - * ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 | 0x7 | Reserved - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK - * - * Divide By 1 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK - * - * Divide By 2 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK - * - * Divide By 4 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK - * - * Divide By 8 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK - * - * Divide By 16 - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK - * - * Reserved - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK - * - * Reserved - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK - * - * Reserved - */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9 -/* The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3 -/* The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f -/* The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7) -/* Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. - */ -struct ALT_CLKMGR_MAINPLL_MAINDIV_s -{ - uint32_t l3mpclk : 2; /* L3 MP Clock Divider */ - uint32_t l3spclk : 2; /* L3 SP Clock Divider */ - uint32_t l4mpclk : 3; /* L4 MP Clock Divider */ - uint32_t l4spclk : 3; /* L4 SP Clock Divider */ - uint32_t : 22; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINDIV. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_MAINDIV_s ALT_CLKMGR_MAINPLL_MAINDIV_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_MAINDIV register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24 - -/* - * Register : Debug Divide Register - dbgdiv - * - * Contains fields that control clock dividers for debug clocks derived from the - * Main PLL - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------- - * [1:0] | RW | 0x0 | Debug AT Clock Divider - * [3:2] | RW | 0x1 | Debug Clock Divider - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Debug AT Clock Divider - dbgatclk - * - * The dbg_at_clk is divided down from the C2 output of the Main PLL by the value - * specified in this field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------ - * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 | 0x0 | Divide by 1 - * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 | 0x1 | Divide by 2 - * ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 | 0x2 | Divide by 4 - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK - * - * Divide by 1 - */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK - * - * Divide by 2 - */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK - * - * Divide by 4 - */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1 -/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2 -/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc -/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : Debug Clock Divider - dbgclk - * - * The dbg_clk is divided down from the dbg_at_clk by the value specified in this - * field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:------------ - * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 | 0x1 | Divide by 2 - * ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 | 0x2 | Divide by 4 - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK - * - * Divide by 2 - */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK - * - * Divide by 4 - */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3 -/* The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2 -/* The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c -/* The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3 -/* The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2) -/* Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. - */ -struct ALT_CLKMGR_MAINPLL_DBGDIV_s -{ - uint32_t dbgatclk : 2; /* Debug AT Clock Divider */ - uint32_t dbgclk : 2; /* Debug Clock Divider */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGDIV. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_DBGDIV_s ALT_CLKMGR_MAINPLL_DBGDIV_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_DBGDIV register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28 - -/* - * Register : Debug Trace Divide Register - tracediv - * - * Contains a field that controls the clock divider for the debug trace clock - * derived from the Main PLL - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------- - * [2:0] | RW | 0x0 | Debug Trace Clock Divider - * [31:3] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Debug Trace Clock Divider - traceclk - * - * The dbg_trace_clk is divided down from the C2 output of the Main PLL by the - * value specified in this field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------------|:------|:------------- - * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 | 0x0 | Divide By 1 - * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 | 0x1 | Divide By 2 - * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 | 0x2 | Divide By 4 - * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 | 0x3 | Divide By 8 - * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 | 0x4 | Divide By 16 - * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 | 0x5 | Reserved - * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 | 0x6 | Reserved - * ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 | 0x7 | Reserved - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK - * - * Divide By 1 - */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK - * - * Divide By 2 - */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK - * - * Divide By 4 - */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK - * - * Divide By 8 - */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK - * - * Divide By 16 - */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK - * - * Reserved - */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK - * - * Reserved - */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK - * - * Reserved - */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB 2 -/* The width in bits of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH 3 -/* The mask used to set the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK 0x00000007 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK 0xfffffff8 -/* The reset value of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. - */ -struct ALT_CLKMGR_MAINPLL_TRACEDIV_s -{ - uint32_t traceclk : 3; /* Debug Trace Clock Divider */ - uint32_t : 29; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_TRACEDIV_s ALT_CLKMGR_MAINPLL_TRACEDIV_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_TRACEDIV register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST 0x2c - -/* - * Register : L4 MP SP APB Clock Source - l4src - * - * Contains fields that select the clock source for L4 MP and SP APB interconnect - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------- - * [0] | RW | 0x0 | l4_mp_clk Source - * [1] | RW | 0x0 | l4_sp_clk Source - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : l4_mp_clk Source - l4mp - * - * Selects the source for l4_mp_clk - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:---------------- - * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL | 0x0 | main_clk - * ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL | 0x1 | periph_base_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP - * - * main_clk - */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP - * - * periph_base_clk - */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB 0 -/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4MP field value from a register. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : l4_sp_clk Source - l4sp - * - * Selects the source for l4_sp_clk - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:---------------- - * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL | 0x0 | main_clk - * ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL | 0x1 | periph_base_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP - * - * main_clk - */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP - * - * periph_base_clk - */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB 1 -/* The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4SP field value from a register. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_L4SRC. - */ -struct ALT_CLKMGR_MAINPLL_L4SRC_s -{ - uint32_t l4mp : 1; /* l4_mp_clk Source */ - uint32_t l4sp : 1; /* l4_sp_clk Source */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_L4SRC. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_L4SRC_s ALT_CLKMGR_MAINPLL_L4SRC_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_L4SRC register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_OFST 0x30 - -/* - * Register : Main PLL Output Counter Reset Ack Status Register - stat - * - * Contains Output Clock Counter Reset acknowledge status. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [5:0] | R | 0x0 | Output Counter Reset Acknowledge - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Output Counter Reset Acknowledge - outresetack - * - * These read only bits per PLL output indicate that the PLL has received the - * Output Reset Counter request and has gracefully stopped the respective PLL - * output clock. - * - * For software to change the PLL output counter without producing glitches on the - * respective clock, SW must set the VCO register respective Output Counter Reset - * bit. Software then polls the respective Output Counter Reset Acknowledge bit in - * the Output Counter Reset Ack Status Register. Software then writes the - * appropriate counter register, and then clears the respective VCO register Output - * Counter Reset bit. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------------------------------- - * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle - * ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK - * - * Idle - */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK - * - * Output Counter Acknowledge received. - */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB 5 -/* The width in bits of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH 6 -/* The mask used to set the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f -/* The mask used to clear the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value. */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 -/* The reset value of the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET 0x0 -/* Extracts the ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK field value from a register. */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) -/* Produces a ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ -#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_MAINPLL_STAT. - */ -struct ALT_CLKMGR_MAINPLL_STAT_s -{ - const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_MAINPLL_STAT. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_STAT_s ALT_CLKMGR_MAINPLL_STAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_MAINPLL_STAT register from the beginning of the component. */ -#define ALT_CLKMGR_MAINPLL_STAT_OFST 0x34 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_CLKMGR_MAINPLL. - */ -struct ALT_CLKMGR_MAINPLL_s -{ - volatile ALT_CLKMGR_MAINPLL_VCO_t vco; /* ALT_CLKMGR_MAINPLL_VCO */ - volatile ALT_CLKMGR_MAINPLL_MISC_t misc; /* ALT_CLKMGR_MAINPLL_MISC */ - volatile ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */ - volatile ALT_CLKMGR_MAINPLL_MAINCLK_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */ - volatile ALT_CLKMGR_MAINPLL_DBGATCLK_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */ - volatile ALT_CLKMGR_MAINPLL_MAINQSPICLK_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */ - volatile ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */ - volatile ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */ - volatile ALT_CLKMGR_MAINPLL_EN_t en; /* ALT_CLKMGR_MAINPLL_EN */ - volatile ALT_CLKMGR_MAINPLL_MAINDIV_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */ - volatile ALT_CLKMGR_MAINPLL_DBGDIV_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */ - volatile ALT_CLKMGR_MAINPLL_TRACEDIV_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */ - volatile ALT_CLKMGR_MAINPLL_L4SRC_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */ - volatile ALT_CLKMGR_MAINPLL_STAT_t stat; /* ALT_CLKMGR_MAINPLL_STAT */ - volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_CLKMGR_MAINPLL. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_s ALT_CLKMGR_MAINPLL_t; -/* The struct declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */ -struct ALT_CLKMGR_MAINPLL_raw_s -{ - volatile uint32_t vco; /* ALT_CLKMGR_MAINPLL_VCO */ - volatile uint32_t misc; /* ALT_CLKMGR_MAINPLL_MISC */ - volatile uint32_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */ - volatile uint32_t mainclk; /* ALT_CLKMGR_MAINPLL_MAINCLK */ - volatile uint32_t dbgatclk; /* ALT_CLKMGR_MAINPLL_DBGATCLK */ - volatile uint32_t mainqspiclk; /* ALT_CLKMGR_MAINPLL_MAINQSPICLK */ - volatile uint32_t mainnandsdmmcclk; /* ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK */ - volatile uint32_t cfgs2fuser0clk; /* ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK */ - volatile uint32_t en; /* ALT_CLKMGR_MAINPLL_EN */ - volatile uint32_t maindiv; /* ALT_CLKMGR_MAINPLL_MAINDIV */ - volatile uint32_t dbgdiv; /* ALT_CLKMGR_MAINPLL_DBGDIV */ - volatile uint32_t tracediv; /* ALT_CLKMGR_MAINPLL_TRACEDIV */ - volatile uint32_t l4src; /* ALT_CLKMGR_MAINPLL_L4SRC */ - volatile uint32_t stat; /* ALT_CLKMGR_MAINPLL_STAT */ - volatile uint32_t _pad_0x38_0x40[2]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */ -typedef volatile struct ALT_CLKMGR_MAINPLL_raw_s ALT_CLKMGR_MAINPLL_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Peripheral PLL Group - ALT_CLKMGR_PERPLL - * Peripheral PLL Group - * - * Contains registers with settings for the Peripheral PLL. - * - */ -/* - * Register : Peripheral PLL VCO Control Register - vco - * - * Contains settings that control the Peripheral PLL VCO. The VCO output frequency - * is the input frequency multiplied by the numerator (M+1) and divided by the - * denominator (N+1). - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------------------- - * [0] | RW | 0x1 | BG PWRDN - * [1] | RW | 0x0 | Enable - * [2] | RW | 0x1 | Power down - * [15:3] | RW | 0x1 | Numerator (M) - * [21:16] | RW | 0x1 | Denominator (N) - * [23:22] | RW | 0x0 | Clock Source - * [24] | RW | 0x0 | All Output Counter Reset - * [30:25] | RW | 0x0 | Output Counter Reset - * [31] | RW | 0x1 | External Regulator Input Select - * - */ -/* - * Field : BG PWRDN - bgpwrdn - * - * If '1', powers down bandgap. If '0', bandgap is not power down. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB 0 -/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_VCO_BGPWRDN field value from a register. */ -#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_VCO_BGPWRDN register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Enable - en - * - * If '1', VCO is enabled. If '0', VCO is in reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_EN_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_EN_MSB 1 -/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_EN register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_EN register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_PERPLL_VCO_EN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_EN_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_VCO_EN field value from a register. */ -#define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_PERPLL_VCO_EN register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Power down - pwrdn - * - * If '1', power down analog circuitry. If '0', analog circuitry not powered down. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB 2 -/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PWRDN register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_VCO_PWRDN field value from a register. */ -#define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_PERPLL_VCO_PWRDN register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Numerator (M) - numer - * - * Numerator in VCO output frequency equation. For incremental frequency change, if - * the new value lead to less than 20% of the frequency change, this value can be - * changed without resetting the PLL. The Numerator and Denominator can not be - * changed at the same time for incremental frequency changed. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB 15 -/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH 13 -/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK 0x0000fff8 -/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_NUMER register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK 0xffff0007 -/* The reset value of the ALT_CLKMGR_PERPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_VCO_NUMER field value from a register. */ -#define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) -/* Produces a ALT_CLKMGR_PERPLL_VCO_NUMER register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) - -/* - * Field : Denominator (N) - denom - * - * Denominator in VCO output frequency equation. For incremental frequency change, - * if the new value lead to less than 20% of the frequency change, this value can - * be changed without resetting the PLL. The Numerator and Denominator can not be - * changed at the same time for incremental frequency changed. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB 21 -/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH 6 -/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK 0x003f0000 -/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_DENOM register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK 0xffc0ffff -/* The reset value of the ALT_CLKMGR_PERPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_VCO_DENOM field value from a register. */ -#define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) -/* Produces a ALT_CLKMGR_PERPLL_VCO_DENOM register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) - -/* - * Field : Clock Source - psrc - * - * Controls the VCO input clock source. - * - * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------------- - * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 | 0x0 | eosc1_clk - * ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 | 0x1 | eosc2_clk - * ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF | 0x2 | f2s_periph_ref_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC - * - * eosc1_clk - */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC - * - * eosc2_clk - */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO_PSRC - * - * f2s_periph_ref_clk - */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB 22 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB 23 -/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH 2 -/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK 0x00c00000 -/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_PSRC register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK 0xff3fffff -/* The reset value of the ALT_CLKMGR_PERPLL_VCO_PSRC register field. */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_VCO_PSRC field value from a register. */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22) -/* Produces a ALT_CLKMGR_PERPLL_VCO_PSRC register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000) - -/* - * Field : All Output Counter Reset - outresetall - * - * Before releasing Bypass, All Output Counter Reset must be set and cleared by - * software for correct clock operation. - * - * If '1', Reset phase multiplexer and all output counter state. So that after the - * assertion all the clocks output are start from rising edge align. - * - * If '0', phase multiplexer and output counter state not reset and no change to - * the phase of the clock outputs. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB 24 -/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 -/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff -/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRSTALL field value from a register. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) -/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) - -/* - * Field : Output Counter Reset - outreset - * - * Resets the individual PLL output counter. - * - * For software to change the PLL output counter without producing glitches on the - * respective clock, SW must set the VCO register respective Output Counter Reset - * bit. Software then polls the respective Output Counter Reset Acknowledge bit in - * the Output Counter Reset Ack Status Register. Software then writes the - * appropriate counter register, and then clears the respective VCO register Output - * Counter Reset bit. - * - * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. - * - * If set to '1', reset output divider, no clock output from counter. - * - * If set to '0', counter is not reset. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB 25 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB 30 -/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH 6 -/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK 0x7e000000 -/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_OUTRST register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK 0x81ffffff -/* The reset value of the ALT_CLKMGR_PERPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_VCO_OUTRST field value from a register. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) -/* Produces a ALT_CLKMGR_PERPLL_VCO_OUTRST register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) - -/* - * Field : External Regulator Input Select - regextsel - * - * If set to '1', the external regulator is selected for the PLL. - * - * If set to '0', the internal regulator is slected. - * - * It is strongly recommended to select the external regulator while the PLL is not - * enabled (in reset), and then disable the external regulater once the PLL - * becomes enabled. Software should simulateously update the 'Enable' bit and the - * 'External Regulator Input Select' in the same write access to the VCO register. - * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be - * set, and vice versa. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB 31 -/* The width in bits of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 -/* The mask used to clear the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value. */ -#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff -/* The reset value of the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_VCO_REGEXTSEL field value from a register. */ -#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_CLKMGR_PERPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_VCO. - */ -struct ALT_CLKMGR_PERPLL_VCO_s -{ - uint32_t bgpwrdn : 1; /* BG PWRDN */ - uint32_t en : 1; /* Enable */ - uint32_t pwrdn : 1; /* Power down */ - uint32_t numer : 13; /* Numerator (M) */ - uint32_t denom : 6; /* Denominator (N) */ - uint32_t psrc : 2; /* Clock Source */ - uint32_t outresetall : 1; /* All Output Counter Reset */ - uint32_t outreset : 6; /* Output Counter Reset */ - uint32_t regextsel : 1; /* External Regulator Input Select */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_VCO. */ -typedef volatile struct ALT_CLKMGR_PERPLL_VCO_s ALT_CLKMGR_PERPLL_VCO_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_VCO register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_VCO_OFST 0x0 - -/* - * Register : Peripheral PLL VCO Advanced Control Register - misc - * - * Contains VCO control signals and other PLL control signals need to be - * controllable through register. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------ - * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled - * [12:1] | RW | 0x1 | Loop Bandwidth Adjust - * [13] | RW | 0x0 | Fast Locking Enable - * [14] | RW | 0x1 | Saturation Enable - * [31:15] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Loop Bandwidth Adjust Enabled - bwadjen - * - * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth - * Adjust field. - * - * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 - * value of the VCO Control Register. The M divided by 2 is the upper 12 bits - * (12:1) of the M field in the VCO register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB 0 -/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJEN field value from a register. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJEN register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Loop Bandwidth Adjust - bwadj - * - * Provides Loop Bandwidth Adjust value. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB 12 -/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH 12 -/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK 0x00001ffe -/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_BWADJ register field value. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK 0xffffe001 -/* The reset value of the ALT_CLKMGR_PERPLL_MISC_BWADJ register field. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_MISC_BWADJ field value from a register. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) -/* Produces a ALT_CLKMGR_PERPLL_MISC_BWADJ register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) - -/* - * Field : Fast Locking Enable - fasten - * - * Enables fast locking circuit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB 13 -/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */ -#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK 0x00002000 -/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_FASTEN register field value. */ -#define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK 0xffffdfff -/* The reset value of the ALT_CLKMGR_PERPLL_MISC_FASTEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_MISC_FASTEN field value from a register. */ -#define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_CLKMGR_PERPLL_MISC_FASTEN register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : Saturation Enable - saten - * - * Enables saturation behavior. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB 14 -/* The width in bits of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */ -#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK 0x00004000 -/* The mask used to clear the ALT_CLKMGR_PERPLL_MISC_SATEN register field value. */ -#define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK 0xffffbfff -/* The reset value of the ALT_CLKMGR_PERPLL_MISC_SATEN register field. */ -#define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_MISC_SATEN field value from a register. */ -#define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_CLKMGR_PERPLL_MISC_SATEN register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_MISC. - */ -struct ALT_CLKMGR_PERPLL_MISC_s -{ - uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ - uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ - uint32_t fasten : 1; /* Fast Locking Enable */ - uint32_t saten : 1; /* Saturation Enable */ - uint32_t : 17; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_MISC. */ -typedef volatile struct ALT_CLKMGR_PERPLL_MISC_s ALT_CLKMGR_PERPLL_MISC_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_MISC register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_MISC_OFST 0x4 - -/* - * Register : Peripheral PLL C0 Control Register for Clock emac0_clk - emac0clk - * - * Contains settings that control clock emac0_clk generated from the C0 output of - * the Peripheral PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT field value from a register. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. - */ -struct ALT_CLKMGR_PERPLL_EMAC0CLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK. */ -typedef volatile struct ALT_CLKMGR_PERPLL_EMAC0CLK_s ALT_CLKMGR_PERPLL_EMAC0CLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC0CLK register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST 0x8 - -/* - * Register : Peripheral PLL C1 Control Register for Clock emac1_clk - emac1clk - * - * Contains settings that control clock emac1_clk generated from the C1 output of - * the Peripheral PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EMAC1CLK_CNT field value from a register. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_EMAC1CLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. - */ -struct ALT_CLKMGR_PERPLL_EMAC1CLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC1CLK. */ -typedef volatile struct ALT_CLKMGR_PERPLL_EMAC1CLK_s ALT_CLKMGR_PERPLL_EMAC1CLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_EMAC1CLK register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST 0xc - -/* - * Register : Peripheral PLL C2 Control Register for Clock periph_qspi_clk - perqspiclk - * - * Contains settings that control clock periph_qspi_clk generated from the C2 - * output of the Peripheral PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_PERQSPICLK_CNT field value from a register. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_PERQSPICLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. - */ -struct ALT_CLKMGR_PERPLL_PERQSPICLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERQSPICLK. */ -typedef volatile struct ALT_CLKMGR_PERPLL_PERQSPICLK_s ALT_CLKMGR_PERPLL_PERQSPICLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_PERQSPICLK register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST 0x10 - -/* - * Register : Peripheral PLL C3 Control Register for Clock periph_nand_sdmmc_clk - pernandsdmmcclk - * - * Contains settings that control clock periph_nand_sdmmc_clk generated from the C3 - * output of the Peripheral PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT field value from a register. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. - */ -struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK. */ -typedef volatile struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST 0x14 - -/* - * Register : Peripheral PLL C4 Control Register for Clock periph_base_clk - perbaseclk - * - * Contains settings that control clock periph_base_clk generated from the C4 - * output of the Peripheral PLL. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_PERBASECLK_CNT field value from a register. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_PERBASECLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. - */ -struct ALT_CLKMGR_PERPLL_PERBASECLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_PERBASECLK. */ -typedef volatile struct ALT_CLKMGR_PERPLL_PERBASECLK_s ALT_CLKMGR_PERPLL_PERBASECLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_PERBASECLK register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_OFST 0x18 - -/* - * Register : Peripheral PLL C5 Control Register for Clock s2f_user1_clk - s2fuser1clk - * - * Contains settings that control clock s2f_user1_clk generated from the C5 output - * of the Peripheral PLL. - * - * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT field value from a register. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. - */ -struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_S2FUSER1CLK. */ -typedef volatile struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s ALT_CLKMGR_PERPLL_S2FUSER1CLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST 0x1c - -/* - * Register : Enable Register - en - * - * Contains fields that control clock enables for clocks derived from the - * Peripheral PLL - * - * 1: The clock is enabled. - * - * 0: The clock is disabled. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:--------------------- - * [0] | RW | 0x1 | emac0_clk Enable - * [1] | RW | 0x1 | emac1_clk Enable - * [2] | RW | 0x1 | usb_mp_clk Enable - * [3] | RW | 0x1 | spi_m_clk Enable - * [4] | RW | 0x1 | can0_clk Enable - * [5] | RW | 0x1 | can1_clk Enable - * [6] | RW | 0x1 | gpio_clk Enable - * [7] | RW | 0x1 | s2f_user1_clk Enable - * [8] | RW | 0x1 | sdmmc_clk Enable - * [9] | RW | 0x1 | nand_x_clk Enable - * [10] | RW | 0x1 | nand_clk Enable - * [11] | RW | 0x1 | qspi_clk Enable - * [31:12] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_clk Enable - emac0clk - * - * Enables clock emac0_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0CLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : emac1_clk Enable - emac1clk - * - * Enables clock emac1_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1CLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : usb_mp_clk Enable - usbclk - * - * Enables clock usb_mp_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_USBCLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_PERPLL_EN_USBCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : spi_m_clk Enable - spimclk - * - * Enables clock spi_m_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : can0_clk Enable - can0clk - * - * Enables clock can0_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef -/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN0CLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : can1_clk Enable - can1clk - * - * Enables clock can1_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf -/* The reset value of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_CAN1CLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : gpio_clk Enable - gpioclk - * - * Enables clock gpio_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf -/* The reset value of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_GPIOCLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : s2f_user1_clk Enable - s2fuser1clk - * - * Enables clock s2f_user1_clk output. - * - * Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f -/* The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : sdmmc_clk Enable - sdmmcclk - * - * Enables clock sdmmc_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff -/* The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : nand_x_clk Enable - nandxclk - * - * Enables clock nand_x_clk output - * - * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and - * the nand_x_clk Enable should always be asserted before the nand_clk Enable is - * asserted. A brief delay is also required between switching the enables (8 * - * nand_clk period). - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff -/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDXCLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : nand_clk Enable - nandclk - * - * Enables clock nand_clk output - * - * nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and - * the nand_x_clk Enable should always be asserted before the nand_clk Enable is - * asserted. A brief delay is also required between switching the enables (8 * - * nand_clk period). - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff -/* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_CLKMGR_PERPLL_EN_NANDCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : qspi_clk Enable - qspiclk - * - * Enables clock qspi_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11 -/* The width in bits of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800 -/* The mask used to clear the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value. */ -#define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field. */ -#define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_EN_QSPICLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_CLKMGR_PERPLL_EN_QSPICLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_EN. - */ -struct ALT_CLKMGR_PERPLL_EN_s -{ - uint32_t emac0clk : 1; /* emac0_clk Enable */ - uint32_t emac1clk : 1; /* emac1_clk Enable */ - uint32_t usbclk : 1; /* usb_mp_clk Enable */ - uint32_t spimclk : 1; /* spi_m_clk Enable */ - uint32_t can0clk : 1; /* can0_clk Enable */ - uint32_t can1clk : 1; /* can1_clk Enable */ - uint32_t gpioclk : 1; /* gpio_clk Enable */ - uint32_t s2fuser1clk : 1; /* s2f_user1_clk Enable */ - uint32_t sdmmcclk : 1; /* sdmmc_clk Enable */ - uint32_t nandxclk : 1; /* nand_x_clk Enable */ - uint32_t nandclk : 1; /* nand_clk Enable */ - uint32_t qspiclk : 1; /* qspi_clk Enable */ - uint32_t : 20; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_EN. */ -typedef volatile struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_EN_OFST 0x20 - -/* - * Register : Divide Register - div - * - * Contains fields that control clock dividers for clocks derived from the - * Peripheral PLL - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------- - * [2:0] | RW | 0x0 | USB Clock Divider - * [5:3] | RW | 0x0 | SPI Master Clock Divider - * [8:6] | RW | 0x0 | CAN0 Clock Divider - * [11:9] | RW | 0x0 | CAN1 Clock Divider - * [31:12] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : USB Clock Divider - usbclk - * - * The usb_mp_clk is divided down from the periph_base_clk by the value specified - * in this field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------|:------|:------------- - * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 | 0x0 | Divide By 1 - * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 | 0x1 | Divide By 2 - * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 | 0x2 | Divide By 4 - * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 | 0x3 | Divide By 8 - * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 | 0x4 | Divide By 16 - * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 | 0x5 | Reserved - * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 | 0x6 | Reserved - * ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 | 0x7 | Reserved - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK - * - * Divide By 1 - */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK - * - * Divide By 2 - */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK - * - * Divide By 4 - */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK - * - * Divide By 8 - */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK - * - * Divide By 16 - */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2 -/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3 -/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007 -/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value. */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8 -/* The reset value of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_DIV_USBCLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_DIV_USBCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007) - -/* - * Field : SPI Master Clock Divider - spimclk - * - * The spi_m_clk is divided down from the periph_base_clk by the value specified in - * this field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:------------- - * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 | 0x0 | Divide By 1 - * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 | 0x1 | Divide By 2 - * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 | 0x2 | Divide By 4 - * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 | 0x3 | Divide By 8 - * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 | 0x4 | Divide By 16 - * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 | 0x5 | Reserved - * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 | 0x6 | Reserved - * ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 | 0x7 | Reserved - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK - * - * Divide By 1 - */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK - * - * Divide By 2 - */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK - * - * Divide By 4 - */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK - * - * Divide By 8 - */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK - * - * Divide By 16 - */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5 -/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3 -/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038 -/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value. */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7 -/* The reset value of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_DIV_SPIMCLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3) -/* Produces a ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038) - -/* - * Field : CAN0 Clock Divider - can0clk - * - * The can0_clk is divided down from the periph_base_clk by the value specified in - * this field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:------------- - * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 | 0x0 | Divide By 1 - * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 | 0x1 | Divide By 2 - * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 | 0x2 | Divide By 4 - * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 | 0x3 | Divide By 8 - * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 | 0x4 | Divide By 16 - * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 | 0x5 | Reserved - * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 | 0x6 | Reserved - * ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 | 0x7 | Reserved - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK - * - * Divide By 1 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK - * - * Divide By 2 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK - * - * Divide By 4 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK - * - * Divide By 8 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK - * - * Divide By 16 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8 -/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3 -/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0 -/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f -/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN0CLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6) -/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0) - -/* - * Field : CAN1 Clock Divider - can1clk - * - * The can1_clk is divided down from the periph_base_clk by the value specified in - * this field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:------------- - * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 | 0x0 | Divide By 1 - * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 | 0x1 | Divide By 2 - * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 | 0x2 | Divide By 4 - * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 | 0x3 | Divide By 8 - * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 | 0x4 | Divide By 16 - * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 | 0x5 | Reserved - * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 | 0x6 | Reserved - * ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 | 0x7 | Reserved - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK - * - * Divide By 1 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK - * - * Divide By 2 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK - * - * Divide By 4 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK - * - * Divide By 8 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK - * - * Divide By 16 - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK - * - * Reserved - */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11 -/* The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3 -/* The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00 -/* The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff -/* The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_DIV_CAN1CLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9) -/* Produces a ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_DIV. - */ -struct ALT_CLKMGR_PERPLL_DIV_s -{ - uint32_t usbclk : 3; /* USB Clock Divider */ - uint32_t spimclk : 3; /* SPI Master Clock Divider */ - uint32_t can0clk : 3; /* CAN0 Clock Divider */ - uint32_t can1clk : 3; /* CAN1 Clock Divider */ - uint32_t : 20; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_DIV. */ -typedef volatile struct ALT_CLKMGR_PERPLL_DIV_s ALT_CLKMGR_PERPLL_DIV_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_DIV register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_DIV_OFST 0x24 - -/* - * Register : GPIO Divide Register - gpiodiv - * - * Contains a field that controls the clock divider for the GPIO De-bounce clock. - * - * Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------------- - * [23:0] | RW | 0x1 | GPIO De-bounce Clock Divider - * [31:24] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO De-bounce Clock Divider - gpiodbclk - * - * The gpio_db_clk is divided down from the periph_base_clk by the value plus one - * specified in this field. The value 0 (divide by 1) is illegal. A value of 1 - * indicates divide by 2, 2 divide by 3, etc. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 23 -/* The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 24 -/* The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x00ffffff -/* The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xff000000 -/* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV. - */ -struct ALT_CLKMGR_PERPLL_GPIODIV_s -{ - uint32_t gpiodbclk : 24; /* GPIO De-bounce Clock Divider */ - uint32_t : 8; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV. */ -typedef volatile struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x28 - -/* - * Register : Flash Clock Source Register - src - * - * Contains fields that select the source clocks for the flash controllers. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------- - * [1:0] | RW | 0x1 | SDMMC Clock Source - * [3:2] | RW | 0x1 | NAND Clock Source - * [5:4] | RW | 0x1 | QSPI Clock Source - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : SDMMC Clock Source - sdmmc - * - * Selects the source clock for the SDMMC. - * - * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------|:------|:---------------------- - * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk - * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk - * ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC - * - * f2s_periph_ref_clk - */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC - * - * main_nand_sdmmc_clk - */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC - * - * periph_nand_sdmmc_clk - */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB 1 -/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH 2 -/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK 0x00000003 -/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value. */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK 0xfffffffc -/* The reset value of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field. */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_SRC_SDMMC field value from a register. */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_SRC_SDMMC register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : NAND Clock Source - nand - * - * Selects the source clock for the NAND. - * - * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------------|:------|:---------------------- - * ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk - * ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK | 0x1 | main_nand_sdmmc_clk - * ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK | 0x2 | periph_nand_sdmmc_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND - * - * f2s_periph_ref_clk - */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND - * - * main_nand_sdmmc_clk - */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND - * - * periph_nand_sdmmc_clk - */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_MSB 3 -/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH 2 -/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK 0x0000000c -/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_NAND register field value. */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK 0xfffffff3 -/* The reset value of the ALT_CLKMGR_PERPLL_SRC_NAND register field. */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_SRC_NAND field value from a register. */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2) -/* Produces a ALT_CLKMGR_PERPLL_SRC_NAND register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c) - -/* - * Field : QSPI Clock Source - qspi - * - * Selects the source clock for the QSPI. - * - * Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------------|:------|:------------------- - * ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK | 0x0 | f2s_periph_ref_clk - * ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK | 0x1 | main_qspi_clk - * ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK | 0x2 | periph_qspi_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI - * - * f2s_periph_ref_clk - */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI - * - * main_qspi_clk - */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI - * - * periph_qspi_clk - */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB 5 -/* The width in bits of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH 2 -/* The mask used to set the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK 0x00000030 -/* The mask used to clear the ALT_CLKMGR_PERPLL_SRC_QSPI register field value. */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK 0xffffffcf -/* The reset value of the ALT_CLKMGR_PERPLL_SRC_QSPI register field. */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET 0x1 -/* Extracts the ALT_CLKMGR_PERPLL_SRC_QSPI field value from a register. */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4) -/* Produces a ALT_CLKMGR_PERPLL_SRC_QSPI register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_SRC. - */ -struct ALT_CLKMGR_PERPLL_SRC_s -{ - uint32_t sdmmc : 2; /* SDMMC Clock Source */ - uint32_t nand : 2; /* NAND Clock Source */ - uint32_t qspi : 2; /* QSPI Clock Source */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_SRC. */ -typedef volatile struct ALT_CLKMGR_PERPLL_SRC_s ALT_CLKMGR_PERPLL_SRC_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_SRC register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_SRC_OFST 0x2c - -/* - * Register : Peripheral PLL Output Counter Reset Ack Status Register - stat - * - * Contains Output Clock Counter Reset acknowledge status. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [5:0] | R | 0x0 | Output Counter Reset Acknowledge - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Output Counter Reset Acknowledge - outresetack - * - * These read only bits per PLL output indicate that the PLL has received the - * Output Reset Counter request and has gracefully stopped the respective PLL - * output clock. - * - * For software to change the PLL output counter without producing glitches on the - * respective clock, SW must set the VCO register respective Output Counter Reset - * bit. Software then polls the respective Output Counter Reset Acknowledge bit in - * the Output Counter Reset Ack Status Register. Software then writes the - * appropriate counter register, and then clears the respective VCO register Output - * Counter Reset bit. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:------------------------------------- - * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle - * ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK - * - * Idle - */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_PERPLL_STAT_OUTRSTACK - * - * Output Counter Acknowledge received. - */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB 5 -/* The width in bits of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH 6 -/* The mask used to set the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f -/* The mask used to clear the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value. */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 -/* The reset value of the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET 0x0 -/* Extracts the ALT_CLKMGR_PERPLL_STAT_OUTRSTACK field value from a register. */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) -/* Produces a ALT_CLKMGR_PERPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ -#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_PERPLL_STAT. - */ -struct ALT_CLKMGR_PERPLL_STAT_s -{ - const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_PERPLL_STAT. */ -typedef volatile struct ALT_CLKMGR_PERPLL_STAT_s ALT_CLKMGR_PERPLL_STAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_PERPLL_STAT register from the beginning of the component. */ -#define ALT_CLKMGR_PERPLL_STAT_OFST 0x30 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_CLKMGR_PERPLL. - */ -struct ALT_CLKMGR_PERPLL_s -{ - volatile ALT_CLKMGR_PERPLL_VCO_t vco; /* ALT_CLKMGR_PERPLL_VCO */ - volatile ALT_CLKMGR_PERPLL_MISC_t misc; /* ALT_CLKMGR_PERPLL_MISC */ - volatile ALT_CLKMGR_PERPLL_EMAC0CLK_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */ - volatile ALT_CLKMGR_PERPLL_EMAC1CLK_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */ - volatile ALT_CLKMGR_PERPLL_PERQSPICLK_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */ - volatile ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */ - volatile ALT_CLKMGR_PERPLL_PERBASECLK_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */ - volatile ALT_CLKMGR_PERPLL_S2FUSER1CLK_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */ - volatile ALT_CLKMGR_PERPLL_EN_t en; /* ALT_CLKMGR_PERPLL_EN */ - volatile ALT_CLKMGR_PERPLL_DIV_t div; /* ALT_CLKMGR_PERPLL_DIV */ - volatile ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */ - volatile ALT_CLKMGR_PERPLL_SRC_t src; /* ALT_CLKMGR_PERPLL_SRC */ - volatile ALT_CLKMGR_PERPLL_STAT_t stat; /* ALT_CLKMGR_PERPLL_STAT */ - volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_CLKMGR_PERPLL. */ -typedef volatile struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t; -/* The struct declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */ -struct ALT_CLKMGR_PERPLL_raw_s -{ - volatile uint32_t vco; /* ALT_CLKMGR_PERPLL_VCO */ - volatile uint32_t misc; /* ALT_CLKMGR_PERPLL_MISC */ - volatile uint32_t emac0clk; /* ALT_CLKMGR_PERPLL_EMAC0CLK */ - volatile uint32_t emac1clk; /* ALT_CLKMGR_PERPLL_EMAC1CLK */ - volatile uint32_t perqspiclk; /* ALT_CLKMGR_PERPLL_PERQSPICLK */ - volatile uint32_t pernandsdmmcclk; /* ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK */ - volatile uint32_t perbaseclk; /* ALT_CLKMGR_PERPLL_PERBASECLK */ - volatile uint32_t s2fuser1clk; /* ALT_CLKMGR_PERPLL_S2FUSER1CLK */ - volatile uint32_t en; /* ALT_CLKMGR_PERPLL_EN */ - volatile uint32_t div; /* ALT_CLKMGR_PERPLL_DIV */ - volatile uint32_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */ - volatile uint32_t src; /* ALT_CLKMGR_PERPLL_SRC */ - volatile uint32_t stat; /* ALT_CLKMGR_PERPLL_STAT */ - volatile uint32_t _pad_0x34_0x40[3]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */ -typedef volatile struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : SDRAM PLL Group - ALT_CLKMGR_SDRPLL - * SDRAM PLL Group - * - * Contains registers with settings for the SDRAM PLL. - * - */ -/* - * Register : SDRAM PLL VCO Control Register - vco - * - * Contains settings that control the SDRAM PLL VCO. The VCO output frequency is - * the input frequency multiplied by the numerator (M+1) and divided by the - * denominator (N+1). - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------------------- - * [0] | RW | 0x1 | BG PWRDN - * [1] | RW | 0x0 | Enable - * [2] | RW | 0x1 | Power down - * [15:3] | RW | 0x1 | Numerator (M) - * [21:16] | RW | 0x1 | Denominator (N) - * [23:22] | RW | 0x0 | Clock Source - * [24] | RW | 0x0 | SDRAM All Output Counter Reset - * [30:25] | RW | 0x0 | Output Counter Reset - * [31] | RW | 0x1 | External Regulator Input Select - * - */ -/* - * Field : BG PWRDN - bgpwrdn - * - * If '1', powers down bandgap. If '0', bandgap is not power down. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0 -/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN field value from a register. */ -#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Enable - en - * - * If '1', VCO is enabled. If '0', VCO is in reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1 -/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_EN register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_EN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_VCO_EN field value from a register. */ -#define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_SDRPLL_VCO_EN register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Power down - pwrdn - * - * If '1', power down analog circuitry. If '0', analog circuitry not powered down. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2 -/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_VCO_PWRDN field value from a register. */ -#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Numerator (M) - numer - * - * Numerator in VCO output frequency equation. For incremental frequency change, if - * the new value lead to less than 20% of the frequency change, this value can be - * changed without resetting the PLL. The Numerator and Denominator can not be - * changed at the same time for incremental frequency changed. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15 -/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13 -/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007 -/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_VCO_NUMER field value from a register. */ -#define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) -/* Produces a ALT_CLKMGR_SDRPLL_VCO_NUMER register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) - -/* - * Field : Denominator (N) - denom - * - * Denominator in VCO output frequency equation. For incremental frequency change, - * if the new value lead to less than 20% of the frequency change, this value can - * be changed without resetting the PLL. The Numerator and Denominator can not be - * changed at the same time for incremental frequency changed. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21 -/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6 -/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff -/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_VCO_DENOM field value from a register. */ -#define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) -/* Produces a ALT_CLKMGR_SDRPLL_VCO_DENOM register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) - -/* - * Field : Clock Source - ssrc - * - * Controls the VCO input clock source. The PLL must by bypassed to eosc1_clk - * before changing this field. - * - * Qsys and user documenation refer to f2s_sdram_ref_clk as f2h_sdram_ref_clk. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:------------------ - * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 | 0x0 | eosc1_clk - * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 | 0x1 | eosc2_clk - * ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF | 0x2 | f2s_sdram_ref_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC - * - * eosc1_clk - */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC - * - * eosc2_clk - */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1 -/* - * Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC - * - * f2s_sdram_ref_clk - */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23 -/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2 -/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff -/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_VCO_SSRC field value from a register. */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22) -/* Produces a ALT_CLKMGR_SDRPLL_VCO_SSRC register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000) - -/* - * Field : SDRAM All Output Counter Reset - outresetall - * - * Before releasing Bypass, All Output Counter Reset must be set and cleared by - * software for correct clock operation. - * - * If '1', Reset phase multiplexer and output counter state. So that after the - * assertion all the clocks output are start from rising edge align. - * - * If '0', phase multiplexer and output counter state not reset and no change to - * the phase of the clock outputs. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24 -/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff -/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL field value from a register. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) -/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) - -/* - * Field : Output Counter Reset - outreset - * - * Resets the individual PLL output counter. - * - * For software to change the PLL output counter without producing glitches on the - * respective clock, SW must set the VCO register respective Output Counter Reset - * bit. Software then polls the respective Output Counter Reset Acknowledge bit in - * the Output Counter Reset Ack Status Register. Software then writes the - * appropriate counter register, and then clears the respective VCO register Output - * Counter Reset bit. - * - * LSB 'outreset[0]' corresponds to PLL output clock C0, etc. - * - * If set to '1', reset output divider, no clock output from counter. - * - * If set to '0', counter is not reset. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30 -/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6 -/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff -/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRST field value from a register. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) -/* Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) - -/* - * Field : External Regulator Input Select - regextsel - * - * If set to '1', the external regulator is selected for the PLL. - * - * If set to '0', the internal regulator is slected. - * - * It is strongly recommended to select the external regulator while the PLL is not - * enabled (in reset), and then disable the external regulater once the PLL - * becomes enabled. Software should simulateously update the 'Enable' bit and the - * 'External Regulator Input Select' in the same write access to the VCO register. - * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be - * set, and vice versa. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31 -/* The width in bits of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value. */ -#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff -/* The reset value of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field. */ -#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL field value from a register. */ -#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_SDRPLL_VCO. - */ -struct ALT_CLKMGR_SDRPLL_VCO_s -{ - uint32_t bgpwrdn : 1; /* BG PWRDN */ - uint32_t en : 1; /* Enable */ - uint32_t pwrdn : 1; /* Power down */ - uint32_t numer : 13; /* Numerator (M) */ - uint32_t denom : 6; /* Denominator (N) */ - uint32_t ssrc : 2; /* Clock Source */ - uint32_t outresetall : 1; /* SDRAM All Output Counter Reset */ - uint32_t outreset : 6; /* Output Counter Reset */ - uint32_t regextsel : 1; /* External Regulator Input Select */ -}; - -/* The typedef declaration for register ALT_CLKMGR_SDRPLL_VCO. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_VCO_s ALT_CLKMGR_SDRPLL_VCO_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_SDRPLL_VCO register from the beginning of the component. */ -#define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0 - -/* - * Register : SDRAM PLL VCO Advanced Control Register - ctrl - * - * Contains VCO control signals and other PLL control signals need to be - * controllable through register. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------ - * [0] | RW | 0x0 | Loop Bandwidth Adjust Enabled - * [12:1] | RW | 0x1 | Loop Bandwidth Adjust - * [13] | RW | 0x0 | Fast Locking Enable - * [14] | RW | 0x1 | Saturation Enable - * [31:15] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Loop Bandwidth Adjust Enabled - bwadjen - * - * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth - * Adjust field. - * - * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 - * value of the VCO Control Register. The M divided by 2 is the upper 12 bits - * (12:1) of the M field in the VCO register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB 0 -/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJEN field value from a register. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJEN register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Loop Bandwidth Adjust - bwadj - * - * Provides Loop Bandwidth Adjust value. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB 12 -/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH 12 -/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK 0x00001ffe -/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK 0xffffe001 -/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_BWADJ register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_CTL_BWADJ field value from a register. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1) -/* Produces a ALT_CLKMGR_SDRPLL_CTL_BWADJ register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe) - -/* - * Field : Fast Locking Enable - fasten - * - * Enables fast locking circuit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB 13 -/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */ -#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK 0x00002000 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value. */ -#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK 0xffffdfff -/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_FASTEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_CTL_FASTEN field value from a register. */ -#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_CLKMGR_SDRPLL_CTL_FASTEN register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : Saturation Enable - saten - * - * Enables saturation behavior. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB 14 -/* The width in bits of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */ -#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK 0x00004000 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_CTL_SATEN register field value. */ -#define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK 0xffffbfff -/* The reset value of the ALT_CLKMGR_SDRPLL_CTL_SATEN register field. */ -#define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_CTL_SATEN field value from a register. */ -#define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_CLKMGR_SDRPLL_CTL_SATEN register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_SDRPLL_CTL. - */ -struct ALT_CLKMGR_SDRPLL_CTL_s -{ - uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */ - uint32_t bwadj : 12; /* Loop Bandwidth Adjust */ - uint32_t fasten : 1; /* Fast Locking Enable */ - uint32_t saten : 1; /* Saturation Enable */ - uint32_t : 17; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_SDRPLL_CTL. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_CTL_s ALT_CLKMGR_SDRPLL_CTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_SDRPLL_CTL register from the beginning of the component. */ -#define ALT_CLKMGR_SDRPLL_CTL_OFST 0x4 - -/* - * Register : SDRAM PLL C0 Control Register for Clock ddr_dqs_clk - ddrdqsclk - * - * Contains settings that control clock ddr_dqs_clk generated from the C0 output of - * the SDRAM PLL. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [20:9] | RW | 0x0 | Phase Shift - * [31:21] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT field value from a register. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -/* - * Field : Phase Shift - phase - * - * Increment the phase of the VCO output by the value in this field multiplied by - * 45 degrees. The accumulated phase shift is the total shifted amount since the - * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco - * control register. In order to guarantee the phase shift to a known value, 'SDRAM - * clocks output phase align' bit should be asserted before programming this field. - * - * This field is only writeable by SW when it is zero. HW updates this field in - * real time as the phase adjustment is being made. SW may poll this field - * waiting for zero indicating the phase adjustment has completed by HW. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB 20 -/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH 12 -/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK 0x001ffe00 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK 0xffe001ff -/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE field value from a register. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) -/* Produces a ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. - */ -struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t phase : 12; /* Phase Shift */ - uint32_t : 11; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQSCLK. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s ALT_CLKMGR_SDRPLL_DDRDQSCLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register from the beginning of the component. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST 0x8 - -/* - * Register : SDRAM PLL C1 Control Register for Clock ddr_2x_dqs_clk - ddr2xdqsclk - * - * Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output - * of the SDRAM PLL. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [20:9] | RW | 0x0 | Phase Shift - * [31:21] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT field value from a register. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -/* - * Field : Phase Shift - phase - * - * Increment the phase of the VCO output by the value in this field multiplied by - * 45 degrees. The accumulated phase shift is the total shifted amount since the - * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco - * control register. In order to guarantee the phase shift to a known value, 'SDRAM - * clocks output phase align' bit should be asserted before programming this field. - * - * This field is only writeable by SW when it is zero. HW updates this field in - * real time as the phase adjustment is being made. SW may poll this field - * waiting for zero indicating the phase adjustment has completed by HW. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB 20 -/* The width in bits of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH 12 -/* The mask used to set the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK 0x001ffe00 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK 0xffe001ff -/* The reset value of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE field value from a register. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) -/* Produces a ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. - */ -struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t phase : 12; /* Phase Shift */ - uint32_t : 11; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDR2XDQSCLK. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register from the beginning of the component. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST 0xc - -/* - * Register : SDRAM PLL C2 Control Register for Clock ddr_dq_clk - ddrdqclk - * - * Contains settings that control clock ddr_dq_clk generated from the C2 output of - * the SDRAM PLL. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [20:9] | RW | 0x0 | Phase Shift - * [31:21] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT field value from a register. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -/* - * Field : Phase Shift - phase - * - * Increment the phase of the VCO output by the value in this field multiplied by - * 45 degrees. The accumulated phase shift is the total shifted amount since the - * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco - * control register. In order to guarantee the phase shift to a known value, 'SDRAM - * clocks output phase align' bit should be asserted before programming this field. - * - * This field is only writeable by SW when it is zero. HW updates this field in - * real time as the phase adjustment is being made. SW may poll this field - * waiting for zero indicating the phase adjustment has completed by HW. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20 -/* The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12 -/* The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff -/* The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE field value from a register. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) -/* Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. - */ -struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t phase : 12; /* Phase Shift */ - uint32_t : 11; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s ALT_CLKMGR_SDRPLL_DDRDQCLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQCLK register from the beginning of the component. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10 - -/* - * Register : SDRAM PLL C5 Control Register for Clock s2f_user2_clk - s2fuser2clk - * - * Contains settings that control clock s2f_user2_clk generated from the C5 output - * of the SDRAM PLL. - * - * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------ - * [8:0] | RW | 0x1 | Counter - * [20:9] | RW | 0x0 | Phase Shift - * [31:21] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Counter - cnt - * - * Divides the VCO frequency by the value+1 in this field. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB 8 -/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH 9 -/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK 0x000001ff -/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK 0xfffffe00 -/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT field value from a register. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) -/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff) - -/* - * Field : Phase Shift - phase - * - * Increment the phase of the VCO output by the value in this field multiplied by - * 45 degrees. The accumulated phase shift is the total shifted amount since the - * last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco - * control register. In order to guarantee the phase shift to a known value, 'SDRAM - * clocks output phase align' bit should be asserted before programming this field. - * - * This field is only writeable by SW when it is zero. HW updates this field in - * real time as the phase adjustment is being made. SW may poll this field - * waiting for zero indicating the phase adjustment has completed by HW. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB 20 -/* The width in bits of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH 12 -/* The mask used to set the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK 0x001ffe00 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK 0xffe001ff -/* The reset value of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE field value from a register. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) -/* Produces a ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. - */ -struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s -{ - uint32_t cnt : 9; /* Counter */ - uint32_t phase : 12; /* Phase Shift */ - uint32_t : 11; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_SDRPLL_S2FUSER2CLK. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register from the beginning of the component. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST 0x14 - -/* - * Register : Enable Register - en - * - * Contains fields that control the SDRAM Clock Group enables generated from the - * SDRAM PLL clock outputs. - * - * 1: The clock is enabled. - * - * 0: The clock is disabled. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------- - * [0] | RW | 0x1 | ddr_dqs_clk Enable - * [1] | RW | 0x1 | ddr_2x_dqs_clk Enable - * [2] | RW | 0x1 | ddr_dq_clk Enable - * [3] | RW | 0x1 | s2f_user2_clk Enable - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : ddr_dqs_clk Enable - ddrdqsclk - * - * Enables clock ddr_dqs_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB 0 -/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK 0x00000001 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK 0xfffffffe -/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK field value from a register. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : ddr_2x_dqs_clk Enable - ddr2xdqsclk - * - * Enables clock ddr_2x_dqs_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB 1 -/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */ -#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK 0x00000002 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value. */ -#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK 0xfffffffd -/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK field value from a register. */ -#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : ddr_dq_clk Enable - ddrdqclk - * - * Enables clock ddr_dq_clk output - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB 2 -/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK 0x00000004 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK 0xfffffffb -/* The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK field value from a register. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : s2f_user2_clk Enable - s2fuser2clk - * - * Enables clock s2f_user2_clk output. - * - * Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB 3 -/* The width in bits of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH 1 -/* The mask used to set the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */ -#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK 0x00000008 -/* The mask used to clear the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value. */ -#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field. */ -#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET 0x1 -/* Extracts the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK field value from a register. */ -#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_SDRPLL_EN. - */ -struct ALT_CLKMGR_SDRPLL_EN_s -{ - uint32_t ddrdqsclk : 1; /* ddr_dqs_clk Enable */ - uint32_t ddr2xdqsclk : 1; /* ddr_2x_dqs_clk Enable */ - uint32_t ddrdqclk : 1; /* ddr_dq_clk Enable */ - uint32_t s2fuser2clk : 1; /* s2f_user2_clk Enable */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_SDRPLL_EN. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_EN_s ALT_CLKMGR_SDRPLL_EN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_SDRPLL_EN register from the beginning of the component. */ -#define ALT_CLKMGR_SDRPLL_EN_OFST 0x18 - -/* - * Register : SDRAM PLL Output Counter Reset Ack Status Register - stat - * - * Contains Output Clock Counter Reset acknowledge status. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [5:0] | R | 0x0 | Output Counter Reset Acknowledge - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Output Counter Reset Acknowledge - outresetack - * - * These read only bits per PLL output indicate that the PLL has received the - * Output Reset Counter request and has gracefully stopped the respective PLL - * output clock. - * - * For software to change the PLL output counter without producing glitches on the - * respective clock, SW must set the VCO register respective Output Counter Reset - * bit. Software then polls the respective Output Counter Reset Acknowledge bit in - * the Output Counter Reset Ack Status Register. Software then writes the - * appropriate counter register, and then clears the respective VCO register Output - * Counter Reset bit. - * - * The reset value of this bit is applied on a cold reset; warm reset has no affect - * on this bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:------------------------------------- - * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE | 0x0 | Idle - * ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK - * - * Idle - */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE 0x0 -/* - * Enumerated value for register field ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK - * - * Output Counter Acknowledge received. - */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB 5 -/* The width in bits of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH 6 -/* The mask used to set the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f -/* The mask used to clear the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value. */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0 -/* The reset value of the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field. */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET 0x0 -/* Extracts the ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK field value from a register. */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0) -/* Produces a ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK register field value suitable for setting the register. */ -#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_CLKMGR_SDRPLL_STAT. - */ -struct ALT_CLKMGR_SDRPLL_STAT_s -{ - const uint32_t outresetack : 6; /* Output Counter Reset Acknowledge */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_CLKMGR_SDRPLL_STAT. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_STAT_s ALT_CLKMGR_SDRPLL_STAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_CLKMGR_SDRPLL_STAT register from the beginning of the component. */ -#define ALT_CLKMGR_SDRPLL_STAT_OFST 0x1c - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_CLKMGR_SDRPLL. - */ -struct ALT_CLKMGR_SDRPLL_s -{ - volatile ALT_CLKMGR_SDRPLL_VCO_t vco; /* ALT_CLKMGR_SDRPLL_VCO */ - volatile ALT_CLKMGR_SDRPLL_CTL_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */ - volatile ALT_CLKMGR_SDRPLL_DDRDQSCLK_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */ - volatile ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */ - volatile ALT_CLKMGR_SDRPLL_DDRDQCLK_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */ - volatile ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */ - volatile ALT_CLKMGR_SDRPLL_EN_t en; /* ALT_CLKMGR_SDRPLL_EN */ - volatile ALT_CLKMGR_SDRPLL_STAT_t stat; /* ALT_CLKMGR_SDRPLL_STAT */ -}; - -/* The typedef declaration for register group ALT_CLKMGR_SDRPLL. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_s ALT_CLKMGR_SDRPLL_t; -/* The struct declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */ -struct ALT_CLKMGR_SDRPLL_raw_s -{ - volatile uint32_t vco; /* ALT_CLKMGR_SDRPLL_VCO */ - volatile uint32_t ctrl; /* ALT_CLKMGR_SDRPLL_CTL */ - volatile uint32_t ddrdqsclk; /* ALT_CLKMGR_SDRPLL_DDRDQSCLK */ - volatile uint32_t ddr2xdqsclk; /* ALT_CLKMGR_SDRPLL_DDR2XDQSCLK */ - volatile uint32_t ddrdqclk; /* ALT_CLKMGR_SDRPLL_DDRDQCLK */ - volatile uint32_t s2fuser2clk; /* ALT_CLKMGR_SDRPLL_S2FUSER2CLK */ - volatile uint32_t en; /* ALT_CLKMGR_SDRPLL_EN */ - volatile uint32_t stat; /* ALT_CLKMGR_SDRPLL_STAT */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_CLKMGR_SDRPLL. */ -typedef volatile struct ALT_CLKMGR_SDRPLL_raw_s ALT_CLKMGR_SDRPLL_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_CLKMGR. - */ -struct ALT_CLKMGR_s -{ - volatile ALT_CLKMGR_CTL_t ctrl; /* ALT_CLKMGR_CTL */ - volatile ALT_CLKMGR_BYPASS_t bypass; /* ALT_CLKMGR_BYPASS */ - volatile ALT_CLKMGR_INTER_t inter; /* ALT_CLKMGR_INTER */ - volatile ALT_CLKMGR_INTREN_t intren; /* ALT_CLKMGR_INTREN */ - volatile ALT_CLKMGR_DBCTL_t dbctrl; /* ALT_CLKMGR_DBCTL */ - volatile ALT_CLKMGR_STAT_t stat; /* ALT_CLKMGR_STAT */ - volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */ - volatile ALT_CLKMGR_MAINPLL_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */ - volatile ALT_CLKMGR_PERPLL_t perpllgrp; /* ALT_CLKMGR_PERPLL */ - volatile ALT_CLKMGR_SDRPLL_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */ - volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_CLKMGR. */ -typedef volatile struct ALT_CLKMGR_s ALT_CLKMGR_t; -/* The struct declaration for the raw register contents of register group ALT_CLKMGR. */ -struct ALT_CLKMGR_raw_s -{ - volatile uint32_t ctrl; /* ALT_CLKMGR_CTL */ - volatile uint32_t bypass; /* ALT_CLKMGR_BYPASS */ - volatile uint32_t inter; /* ALT_CLKMGR_INTER */ - volatile uint32_t intren; /* ALT_CLKMGR_INTREN */ - volatile uint32_t dbctrl; /* ALT_CLKMGR_DBCTL */ - volatile uint32_t stat; /* ALT_CLKMGR_STAT */ - volatile uint32_t _pad_0x18_0x3f[10]; /* *UNDEFINED* */ - volatile ALT_CLKMGR_MAINPLL_raw_t mainpllgrp; /* ALT_CLKMGR_MAINPLL */ - volatile ALT_CLKMGR_PERPLL_raw_t perpllgrp; /* ALT_CLKMGR_PERPLL */ - volatile ALT_CLKMGR_SDRPLL_raw_t sdrpllgrp; /* ALT_CLKMGR_SDRPLL */ - volatile uint32_t _pad_0xe0_0x200[72]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_CLKMGR. */ -typedef volatile struct ALT_CLKMGR_raw_s ALT_CLKMGR_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_CLKMGR_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h deleted file mode 100644 index 1425708983..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmanonsecure.h +++ /dev/null @@ -1,144 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_DMANONSECURE */ - -#ifndef __ALTERA_ALT_DMANONSECURE_H__ -#define __ALTERA_ALT_DMANONSECURE_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : nonsecure DMA Module Address Space - ALT_DMANONSECURE - * nonsecure DMA Module Address Space - * - * Address space allocated to the nonsecure DMA. For detailed information about the - * use of this address space, - * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click - * here[/url] to access the ARM documentation for the DMA-330. - * - */ -/* - * Register : Empty - reg - * - * Placeholder - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:------------ - * [31:0] | RW | Unknown | Empty - * - */ -/* - * Field : Empty - fld - * - * Placeholder - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ -#define ALT_DMANONSECURE_REG_FLD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_DMANONSECURE_REG_FLD register field. */ -#define ALT_DMANONSECURE_REG_FLD_MSB 31 -/* The width in bits of the ALT_DMANONSECURE_REG_FLD register field. */ -#define ALT_DMANONSECURE_REG_FLD_WIDTH 32 -/* The mask used to set the ALT_DMANONSECURE_REG_FLD register field value. */ -#define ALT_DMANONSECURE_REG_FLD_SET_MSK 0xffffffff -/* The mask used to clear the ALT_DMANONSECURE_REG_FLD register field value. */ -#define ALT_DMANONSECURE_REG_FLD_CLR_MSK 0x00000000 -/* The reset value of the ALT_DMANONSECURE_REG_FLD register field is UNKNOWN. */ -#define ALT_DMANONSECURE_REG_FLD_RESET 0x0 -/* Extracts the ALT_DMANONSECURE_REG_FLD field value from a register. */ -#define ALT_DMANONSECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_DMANONSECURE_REG_FLD register field value suitable for setting the register. */ -#define ALT_DMANONSECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_DMANONSECURE_REG. - */ -struct ALT_DMANONSECURE_REG_s -{ - uint32_t fld : 32; /* Empty */ -}; - -/* The typedef declaration for register ALT_DMANONSECURE_REG. */ -typedef volatile struct ALT_DMANONSECURE_REG_s ALT_DMANONSECURE_REG_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_DMANONSECURE_REG register from the beginning of the component. */ -#define ALT_DMANONSECURE_REG_OFST 0x0 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_DMANONSECURE. - */ -struct ALT_DMANONSECURE_s -{ - volatile ALT_DMANONSECURE_REG_t reg; /* ALT_DMANONSECURE_REG */ -}; - -/* The typedef declaration for register group ALT_DMANONSECURE. */ -typedef volatile struct ALT_DMANONSECURE_s ALT_DMANONSECURE_t; -/* The struct declaration for the raw register contents of register group ALT_DMANONSECURE. */ -struct ALT_DMANONSECURE_raw_s -{ - volatile uint32_t reg; /* ALT_DMANONSECURE_REG */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_DMANONSECURE. */ -typedef volatile struct ALT_DMANONSECURE_raw_s ALT_DMANONSECURE_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_DMANONSECURE_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h deleted file mode 100644 index 5941433268..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_dmasecure.h +++ /dev/null @@ -1,144 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_DMASECURE */ - -#ifndef __ALTERA_ALT_DMASECURE_H__ -#define __ALTERA_ALT_DMASECURE_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : secure DMA Module Address Space - ALT_DMASECURE - * secure DMA Module Address Space - * - * Address space allocated to the secure DMA. For detailed information about the - * use of this address space, - * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click - * here[/url] to access the ARM documentation for the DMA-330. - * - */ -/* - * Register : Empty - reg - * - * Placeholder - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:------------ - * [31:0] | RW | Unknown | Empty - * - */ -/* - * Field : Empty - fld - * - * Placeholder - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_DMASECURE_REG_FLD register field. */ -#define ALT_DMASECURE_REG_FLD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_DMASECURE_REG_FLD register field. */ -#define ALT_DMASECURE_REG_FLD_MSB 31 -/* The width in bits of the ALT_DMASECURE_REG_FLD register field. */ -#define ALT_DMASECURE_REG_FLD_WIDTH 32 -/* The mask used to set the ALT_DMASECURE_REG_FLD register field value. */ -#define ALT_DMASECURE_REG_FLD_SET_MSK 0xffffffff -/* The mask used to clear the ALT_DMASECURE_REG_FLD register field value. */ -#define ALT_DMASECURE_REG_FLD_CLR_MSK 0x00000000 -/* The reset value of the ALT_DMASECURE_REG_FLD register field is UNKNOWN. */ -#define ALT_DMASECURE_REG_FLD_RESET 0x0 -/* Extracts the ALT_DMASECURE_REG_FLD field value from a register. */ -#define ALT_DMASECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_DMASECURE_REG_FLD register field value suitable for setting the register. */ -#define ALT_DMASECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_DMASECURE_REG. - */ -struct ALT_DMASECURE_REG_s -{ - uint32_t fld : 32; /* Empty */ -}; - -/* The typedef declaration for register ALT_DMASECURE_REG. */ -typedef volatile struct ALT_DMASECURE_REG_s ALT_DMASECURE_REG_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_DMASECURE_REG register from the beginning of the component. */ -#define ALT_DMASECURE_REG_OFST 0x0 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_DMASECURE. - */ -struct ALT_DMASECURE_s -{ - volatile ALT_DMASECURE_REG_t reg; /* ALT_DMASECURE_REG */ -}; - -/* The typedef declaration for register group ALT_DMASECURE. */ -typedef volatile struct ALT_DMASECURE_s ALT_DMASECURE_t; -/* The struct declaration for the raw register contents of register group ALT_DMASECURE. */ -struct ALT_DMASECURE_raw_s -{ - volatile uint32_t reg; /* ALT_DMASECURE_REG */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_DMASECURE. */ -typedef volatile struct ALT_DMASECURE_raw_s ALT_DMASECURE_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_DMASECURE_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_gpio.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_gpio.h deleted file mode 100644 index 8bc4640161..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_gpio.h +++ /dev/null @@ -1,1991 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_GPIO */ - -#ifndef __ALTERA_ALT_GPIO_H__ -#define __ALTERA_ALT_GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : GPIO Module - ALT_GPIO - * GPIO Module - * - * Registers in the GPIO module - * - */ -/* - * Register : Port A Data Register - gpio_swporta_dr - * - * This GPIO Data register is used to input or output data - * - * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------ - * [28:0] | RW | 0x0 | Port A Data - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Port A Data - gpio_swporta_dr - * - * Values written to this register are output on the I/O signals of the GPIO Data - * Register, if the corresponding data direction bits for GPIO Data Direction Field - * are set to Output mode. The value read back is equal to the last value written - * to this register. - * - * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ -#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ -#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB 28 -/* The width in bits of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ -#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH 29 -/* The mask used to set the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */ -#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */ -#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */ -#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET 0x0 -/* Extracts the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */ -#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */ -#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_SWPORTA_DR. - */ -struct ALT_GPIO_SWPORTA_DR_s -{ - uint32_t gpio_swporta_dr : 29; /* Port A Data */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_SWPORTA_DR. */ -typedef volatile struct ALT_GPIO_SWPORTA_DR_s ALT_GPIO_SWPORTA_DR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_SWPORTA_DR register from the beginning of the component. */ -#define ALT_GPIO_SWPORTA_DR_OFST 0x0 -/* The address of the ALT_GPIO_SWPORTA_DR register. */ -#define ALT_GPIO_SWPORTA_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DR_OFST)) - -/* - * Register : Port A Data Direction Register - gpio_swporta_ddr - * - * This register establishes the direction of each corresponding GPIO Data Field - * Bit. - * - * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:---------------------------- - * [28:0] | RW | 0x0 | Port A Data Direction Field - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Port A Data Direction Field - gpio_swporta_ddr - * - * Values written to this register independently control the direction of the - * corresponding data bit in the Port A Data Register. - * - * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:----------------- - * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN | 0x0 | Input Direction - * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT | 0x1 | Output Direction - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR - * - * Input Direction - */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN 0x0 -/* - * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR - * - * Output Direction - */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB 28 -/* The width in bits of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH 29 -/* The mask used to set the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET 0x0 -/* Extracts the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */ -#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_SWPORTA_DDR. - */ -struct ALT_GPIO_SWPORTA_DDR_s -{ - uint32_t gpio_swporta_ddr : 29; /* Port A Data Direction Field */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_SWPORTA_DDR. */ -typedef volatile struct ALT_GPIO_SWPORTA_DDR_s ALT_GPIO_SWPORTA_DDR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_SWPORTA_DDR register from the beginning of the component. */ -#define ALT_GPIO_SWPORTA_DDR_OFST 0x4 -/* The address of the ALT_GPIO_SWPORTA_DDR register. */ -#define ALT_GPIO_SWPORTA_DDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DDR_OFST)) - -/* - * Register : Interrupt Enable Register - gpio_inten - * - * The Interrupt enable register allows interrupts for each bit of the Port A data - * register. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------- - * [28:0] | RW | 0x0 | Interrupt Enable Field - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Interrupt Enable Field - gpio_inten - * - * Allows each bit of Port A Data Register to be configured for interrupt - * capability. Interrupts are disabled on the corresponding bits of Port A Data - * Register if the corresponding data direction register is set to Output. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------|:------|:---------------------------- - * ALT_GPIO_INTEN_GPIO_INTEN_E_DIS | 0x0 | Disable Interrupt on Port A - * ALT_GPIO_INTEN_GPIO_INTEN_E_EN | 0x1 | Enable Interrupt on Port A - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN - * - * Disable Interrupt on Port A - */ -#define ALT_GPIO_INTEN_GPIO_INTEN_E_DIS 0x0 -/* - * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN - * - * Enable Interrupt on Port A - */ -#define ALT_GPIO_INTEN_GPIO_INTEN_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ -#define ALT_GPIO_INTEN_GPIO_INTEN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ -#define ALT_GPIO_INTEN_GPIO_INTEN_MSB 28 -/* The width in bits of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ -#define ALT_GPIO_INTEN_GPIO_INTEN_WIDTH 29 -/* The mask used to set the ALT_GPIO_INTEN_GPIO_INTEN register field value. */ -#define ALT_GPIO_INTEN_GPIO_INTEN_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_INTEN_GPIO_INTEN register field value. */ -#define ALT_GPIO_INTEN_GPIO_INTEN_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_INTEN_GPIO_INTEN register field. */ -#define ALT_GPIO_INTEN_GPIO_INTEN_RESET 0x0 -/* Extracts the ALT_GPIO_INTEN_GPIO_INTEN field value from a register. */ -#define ALT_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */ -#define ALT_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_INTEN. - */ -struct ALT_GPIO_INTEN_s -{ - uint32_t gpio_inten : 29; /* Interrupt Enable Field */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_INTEN. */ -typedef volatile struct ALT_GPIO_INTEN_s ALT_GPIO_INTEN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_INTEN register from the beginning of the component. */ -#define ALT_GPIO_INTEN_OFST 0x30 -/* The address of the ALT_GPIO_INTEN register. */ -#define ALT_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTEN_OFST)) - -/* - * Register : Interrupt Mask Register - gpio_intmask - * - * Controls which pins cause interrupts on Port A Data Register inputs. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:--------------------- - * [28:0] | RW | 0x0 | Interrupt Mask Field - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Interrupt Mask Field - gpio_intmask - * - * Controls whether an interrupt on Port A Data Register can generate an interrupt - * to the interrupt controller by not masking it. The unmasked status can be read - * as well as the resultant status after masking. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------- - * ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS | 0x0 | Interrupt bits are unmasked - * ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN | 0x1 | Mask Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK - * - * Interrupt bits are unmasked - */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS 0x0 -/* - * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK - * - * Mask Interrupt - */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_MSB 28 -/* The width in bits of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_WIDTH 29 -/* The mask used to set the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_RESET 0x0 -/* Extracts the ALT_GPIO_INTMSK_GPIO_INTMSK field value from a register. */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_INTMSK_GPIO_INTMSK register field value suitable for setting the register. */ -#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_INTMSK. - */ -struct ALT_GPIO_INTMSK_s -{ - uint32_t gpio_intmask : 29; /* Interrupt Mask Field */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_INTMSK. */ -typedef volatile struct ALT_GPIO_INTMSK_s ALT_GPIO_INTMSK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_INTMSK register from the beginning of the component. */ -#define ALT_GPIO_INTMSK_OFST 0x34 -/* The address of the ALT_GPIO_INTMSK register. */ -#define ALT_GPIO_INTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTMSK_OFST)) - -/* - * Register : Interrupt Level Register - gpio_inttype_level - * - * The interrupt level register defines the type of interrupt (edge or level). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:---------------------- - * [28:0] | RW | 0x0 | Interrupt Level Field - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Interrupt Level Field - gpio_inttype_level - * - * This field controls the type of interrupt that can occur on the Port A Data - * Register. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------------|:------|:---------------- - * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL | 0x0 | Level-sensitive - * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE | 0x1 | Edge-sensitive - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL - * - * Level-sensitive - */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL 0x0 -/* - * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL - * - * Edge-sensitive - */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB 28 -/* The width in bits of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH 29 -/* The mask used to set the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET 0x0 -/* Extracts the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */ -#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_INTTYPE_LEVEL. - */ -struct ALT_GPIO_INTTYPE_LEVEL_s -{ - uint32_t gpio_inttype_level : 29; /* Interrupt Level Field */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_INTTYPE_LEVEL. */ -typedef volatile struct ALT_GPIO_INTTYPE_LEVEL_s ALT_GPIO_INTTYPE_LEVEL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_INTTYPE_LEVEL register from the beginning of the component. */ -#define ALT_GPIO_INTTYPE_LEVEL_OFST 0x38 -/* The address of the ALT_GPIO_INTTYPE_LEVEL register. */ -#define ALT_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTTYPE_LEVEL_OFST)) - -/* - * Register : Interrupt Polarity Register - gpio_int_polarity - * - * Controls the Polarity of Interrupts that can occur on inputs of Port A Data - * Register - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------- - * [28:0] | RW | 0x0 | Polarity Control Field - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Polarity Control Field - gpio_int_polarity - * - * Controls the polarity of edge or level sensitivity that can occur on input of - * Port A Data Register. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:------------ - * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW | 0x0 | Active low - * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH | 0x1 | Active high - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL - * - * Active low - */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW 0x0 -/* - * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL - * - * Active high - */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_MSB 28 -/* The width in bits of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_WIDTH 29 -/* The mask used to set the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_RESET 0x0 -/* Extracts the ALT_GPIO_INT_POL_GPIO_INT_POL field value from a register. */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_INT_POL_GPIO_INT_POL register field value suitable for setting the register. */ -#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_INT_POL. - */ -struct ALT_GPIO_INT_POL_s -{ - uint32_t gpio_int_polarity : 29; /* Polarity Control Field */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_INT_POL. */ -typedef volatile struct ALT_GPIO_INT_POL_s ALT_GPIO_INT_POL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_INT_POL register from the beginning of the component. */ -#define ALT_GPIO_INT_POL_OFST 0x3c -/* The address of the ALT_GPIO_INT_POL register. */ -#define ALT_GPIO_INT_POL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INT_POL_OFST)) - -/* - * Register : Interrupt Status Register - gpio_intstatus - * - * The Interrupt status is reported for all Port A Data Register Bits. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------- - * [28:0] | RW | 0x0 | Interrupt Status Field - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Interrupt Status Field - gpio_intstatus - * - * Interrupt status of Port A Data Register. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------|:------|:------------ - * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT | 0x0 | Inactive - * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT | 0x1 | Active - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT - * - * Inactive - */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT 0x0 -/* - * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT - * - * Active - */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_MSB 28 -/* The width in bits of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_WIDTH 29 -/* The mask used to set the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_RESET 0x0 -/* Extracts the ALT_GPIO_INTSTAT_GPIO_INTSTAT field value from a register. */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value suitable for setting the register. */ -#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_INTSTAT. - */ -struct ALT_GPIO_INTSTAT_s -{ - uint32_t gpio_intstatus : 29; /* Interrupt Status Field */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_INTSTAT. */ -typedef volatile struct ALT_GPIO_INTSTAT_s ALT_GPIO_INTSTAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_INTSTAT register from the beginning of the component. */ -#define ALT_GPIO_INTSTAT_OFST 0x40 -/* The address of the ALT_GPIO_INTSTAT register. */ -#define ALT_GPIO_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTSTAT_OFST)) - -/* - * Register : Raw Interrupt Status Register - gpio_raw_intstatus - * - * This is the Raw Interrupt Status Register for Port A Data Register. It is used - * with the Interrupt Mask Register to allow interrupts from the Port A Data - * Register. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:--------------------------- - * [28:0] | RW | 0x0 | Raw Interrupt Status Field - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Raw Interrupt Status Field - gpio_raw_intstatus - * - * Raw interrupt of status of Port A Data Register (premasking bits) - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------------|:------|:------------ - * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT | 0x0 | Inactive - * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT | 0x1 | Active - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT - * - * Inactive - */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT 0x0 -/* - * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT - * - * Active - */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_MSB 28 -/* The width in bits of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_WIDTH 29 -/* The mask used to set the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_RESET 0x0 -/* Extracts the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT field value from a register. */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value suitable for setting the register. */ -#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_RAW_INTSTAT. - */ -struct ALT_GPIO_RAW_INTSTAT_s -{ - uint32_t gpio_raw_intstatus : 29; /* Raw Interrupt Status Field */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_RAW_INTSTAT. */ -typedef volatile struct ALT_GPIO_RAW_INTSTAT_s ALT_GPIO_RAW_INTSTAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_RAW_INTSTAT register from the beginning of the component. */ -#define ALT_GPIO_RAW_INTSTAT_OFST 0x44 -/* The address of the ALT_GPIO_RAW_INTSTAT register. */ -#define ALT_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_RAW_INTSTAT_OFST)) - -/* - * Register : Debounce Enable Register - gpio_debounce - * - * Debounces each IO Pin - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------------------- - * [28:0] | RW | 0x0 | ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : gpio_debounce - * - * Controls whether an external signal that is the source of an interrupt needs to - * be debounced to remove any spurious glitches. A signal must be valid for two - * periods of an external clock (gpio_db_clk) before it is internally processed. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------|:------|:---------------- - * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS | 0x0 | No debounce - * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN | 0x1 | Enable debounce - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE - * - * No debounce - */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS 0x0 -/* - * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE - * - * Enable debounce - */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB 28 -/* The width in bits of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH 29 -/* The mask used to set the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET 0x0 -/* Extracts the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */ -#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_DEBOUNCE. - */ -struct ALT_GPIO_DEBOUNCE_s -{ - uint32_t gpio_debounce : 29; /* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_DEBOUNCE. */ -typedef volatile struct ALT_GPIO_DEBOUNCE_s ALT_GPIO_DEBOUNCE_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_DEBOUNCE register from the beginning of the component. */ -#define ALT_GPIO_DEBOUNCE_OFST 0x48 -/* The address of the ALT_GPIO_DEBOUNCE register. */ -#define ALT_GPIO_DEBOUNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_DEBOUNCE_OFST)) - -/* - * Register : Clear Interrupt Register - gpio_porta_eoi - * - * Port A Data Register interrupt handling. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------------- - * [28:0] | W | 0x0 | Clears Edge Interrupts Field - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Clears Edge Interrupts Field - gpio_porta_eoi - * - * Controls the clearing of edge type interrupts from the Port A Data Register. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------------- - * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR | 0x0 | No interrupt clear - * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR | 0x1 | Clear interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI - * - * No interrupt clear - */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR 0x0 -/* - * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI - * - * Clear interrupt - */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB 28 -/* The width in bits of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH 29 -/* The mask used to set the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET 0x0 -/* Extracts the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */ -#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_PORTA_EOI. - */ -struct ALT_GPIO_PORTA_EOI_s -{ - uint32_t gpio_porta_eoi : 29; /* Clears Edge Interrupts Field */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_PORTA_EOI. */ -typedef volatile struct ALT_GPIO_PORTA_EOI_s ALT_GPIO_PORTA_EOI_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_PORTA_EOI register from the beginning of the component. */ -#define ALT_GPIO_PORTA_EOI_OFST 0x4c -/* The address of the ALT_GPIO_PORTA_EOI register. */ -#define ALT_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_PORTA_EOI_OFST)) - -/* - * Register : External Port A Register - gpio_ext_porta - * - * The external port register is used to input data to the metastability flops. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------- - * [28:0] | R | 0x0 | External Port Field - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : External Port Field - gpio_ext_porta - * - * When Port A Data Register is configured as Input, then reading this location - * reads the values on the signals. When the data direction of Port A Data Register - * is set as Output, reading this location reads Port A Data Register - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ -#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ -#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB 28 -/* The width in bits of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ -#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH 29 -/* The mask used to set the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */ -#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK 0x1fffffff -/* The mask used to clear the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */ -#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK 0xe0000000 -/* The reset value of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */ -#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET 0x0 -/* Extracts the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */ -#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x1fffffff) >> 0) -/* Produces a ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */ -#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x1fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_EXT_PORTA. - */ -struct ALT_GPIO_EXT_PORTA_s -{ - const uint32_t gpio_ext_porta : 29; /* External Port Field */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_EXT_PORTA. */ -typedef volatile struct ALT_GPIO_EXT_PORTA_s ALT_GPIO_EXT_PORTA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_EXT_PORTA register from the beginning of the component. */ -#define ALT_GPIO_EXT_PORTA_OFST 0x50 -/* The address of the ALT_GPIO_EXT_PORTA register. */ -#define ALT_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_EXT_PORTA_OFST)) - -/* - * Register : Synchronization Level Register - gpio_ls_sync - * - * The Synchronization level register is used to synchronize input with l4_mp_clk - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [0] | RW | 0x0 | Synchronization Level Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Synchronization Level Field - gpio_ls_sync - * - * The level-sensitive interrupts is synchronized to l4_mp_clk. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:-------------------------------- - * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0 | No synchronization to l4_mp_clk - * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC | 0x1 | Synchronize to l4_mp_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC - * - * No synchronization to l4_mp_clk - */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0 -/* - * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC - * - * Synchronize to l4_mp_clk - */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0 -/* The width in bits of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1 -/* The mask used to set the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001 -/* The mask used to clear the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe -/* The reset value of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0 -/* Extracts the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */ -#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_LS_SYNC. - */ -struct ALT_GPIO_LS_SYNC_s -{ - uint32_t gpio_ls_sync : 1; /* Synchronization Level Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_LS_SYNC. */ -typedef volatile struct ALT_GPIO_LS_SYNC_s ALT_GPIO_LS_SYNC_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_LS_SYNC register from the beginning of the component. */ -#define ALT_GPIO_LS_SYNC_OFST 0x60 -/* The address of the ALT_GPIO_LS_SYNC register. */ -#define ALT_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_LS_SYNC_OFST)) - -/* - * Register : ID Code Register - gpio_id_code - * - * GPIO ID code. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------- - * [31:0] | R | 0x0 | ID Code Field - * - */ -/* - * Field : ID Code Field - gpio_id_code - * - * Chip identification - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ -#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ -#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_MSB 31 -/* The width in bits of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ -#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH 32 -/* The mask used to set the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */ -#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */ -#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK 0x00000000 -/* The reset value of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */ -#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_RESET 0x0 -/* Extracts the ALT_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */ -#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */ -#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_ID_CODE. - */ -struct ALT_GPIO_ID_CODE_s -{ - const uint32_t gpio_id_code : 32; /* ID Code Field */ -}; - -/* The typedef declaration for register ALT_GPIO_ID_CODE. */ -typedef volatile struct ALT_GPIO_ID_CODE_s ALT_GPIO_ID_CODE_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_ID_CODE register from the beginning of the component. */ -#define ALT_GPIO_ID_CODE_OFST 0x64 -/* The address of the ALT_GPIO_ID_CODE register. */ -#define ALT_GPIO_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_ID_CODE_OFST)) - -/* - * Register : GPIO Version Register - gpio_ver_id_code - * - * GPIO Component Version - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:-----------|:------------------------------ - * [31:0] | R | 0x3230382a | ASCII Component Version Field - * - */ -/* - * Field : ASCII Component Version Field - gpio_ver_id_code - * - * ASCII value for each number in the version, followed by *. For example. - * 32_30_31_2A represents the version 2.01 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ -#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ -#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31 -/* The width in bits of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ -#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32 -/* The mask used to set the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ -#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */ -#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000 -/* The reset value of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */ -#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230382a -/* Extracts the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */ -#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */ -#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_VER_ID_CODE. - */ -struct ALT_GPIO_VER_ID_CODE_s -{ - const uint32_t gpio_ver_id_code : 32; /* ASCII Component Version Field */ -}; - -/* The typedef declaration for register ALT_GPIO_VER_ID_CODE. */ -typedef volatile struct ALT_GPIO_VER_ID_CODE_s ALT_GPIO_VER_ID_CODE_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_VER_ID_CODE register from the beginning of the component. */ -#define ALT_GPIO_VER_ID_CODE_OFST 0x6c -/* The address of the ALT_GPIO_VER_ID_CODE register. */ -#define ALT_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_VER_ID_CODE_OFST)) - -/* - * Register : Configuration Register 2 - gpio_config_reg2 - * - * Specifies the bit width of port A. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:---------------------- - * [4:0] | R | 0x1c | Port A Width (less 1) - * [9:5] | R | 0x7 | Port B Width (less 1) - * [14:10] | R | 0x7 | Port C Width (less 1) - * [19:15] | R | 0x7 | Port D Width (less 1) - * [31:20] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Port A Width (less 1) - encoded_id_pwidth_a - * - * Specifies the width of GPIO Port A. The value 28 represents the 29-bit width - * less one. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:-------------------------- - * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits - * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A - * - * Width (less 1) of 8 bits - */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7 -/* - * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A - * - * Width (less 1) of 29 bits - */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS 0x1c - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4 -/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5 -/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f -/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0 -/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0x1c -/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0) -/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f) - -/* - * Field : Port B Width (less 1) - encoded_id_pwidth_b - * - * Specifies the width of GPIO Port B. Ignored because there is no Port B in the - * GPIO. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:-------------------------- - * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits - * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B - * - * Width (less 1) of 8 bits - */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7 -/* - * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B - * - * Width (less 1) of 29 bits - */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS 0x1c - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9 -/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5 -/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0 -/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f -/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7 -/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5) -/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0) - -/* - * Field : Port C Width (less 1) - encoded_id_pwidth_c - * - * Specifies the width of GPIO Port C. Ignored because there is no Port C in the - * GPIO. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:-------------------------- - * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits - * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C - * - * Width (less 1) of 8 bits - */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7 -/* - * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C - * - * Width (less 1) of 29 bits - */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS 0x1c - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14 -/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5 -/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00 -/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff -/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7 -/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10) -/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00) - -/* - * Field : Port D Width (less 1) - encoded_id_pwidth_d - * - * Specifies the width of GPIO Port D. Ignored because there is no Port D in the - * GPIO. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:-------------------------- - * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits - * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D - * - * Width (less 1) of 8 bits - */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7 -/* - * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D - * - * Width (less 1) of 29 bits - */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS 0x1c - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19 -/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5 -/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000 -/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff -/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7 -/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15) -/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_CFG_REG2. - */ -struct ALT_GPIO_CFG_REG2_s -{ - const uint32_t encoded_id_pwidth_a : 5; /* Port A Width (less 1) */ - const uint32_t encoded_id_pwidth_b : 5; /* Port B Width (less 1) */ - const uint32_t encoded_id_pwidth_c : 5; /* Port C Width (less 1) */ - const uint32_t encoded_id_pwidth_d : 5; /* Port D Width (less 1) */ - uint32_t : 12; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_CFG_REG2. */ -typedef volatile struct ALT_GPIO_CFG_REG2_s ALT_GPIO_CFG_REG2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component. */ -#define ALT_GPIO_CFG_REG2_OFST 0x70 -/* The address of the ALT_GPIO_CFG_REG2 register. */ -#define ALT_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST)) - -/* - * Register : Configuration Register 1 - gpio_config_reg1 - * - * Reports settings of various GPIO configuration parameters - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:---------------------------------- - * [1:0] | R | 0x2 | APB DATA WIDTH - * [3:2] | R | 0x0 | NUM PORTS - * [4] | R | 0x1 | PORT A SINGLE CTL - * [5] | R | 0x1 | PORT B SINGLE CTL - * [6] | R | 0x1 | PORT C SINGLE CTL - * [7] | R | 0x1 | PORT D SINGLE CTL - * [8] | R | 0x0 | HW PORTA - * [11:9] | ??? | 0x0 | *UNDEFINED* - * [12] | R | 0x1 | Port A Interrupt Field - * [13] | R | 0x1 | Debounce Field - * [14] | R | 0x1 | Encoded GPIO Parameters Available - * [15] | R | 0x1 | ID Field - * [20:16] | R | 0x1f | Encoded ID Width Field - * [31:21] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : APB DATA WIDTH - apb_data_width - * - * Fixed to support an ABP data bus width of 32-bits. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------------|:------|:------------------------- - * ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH - * - * APB Data Width = 32-bits - */ -#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ -#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ -#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1 -/* The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ -#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2 -/* The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ -#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003 -/* The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */ -#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc -/* The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */ -#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2 -/* Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */ -#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : NUM PORTS - num_ports - * - * The value of this register is fixed at one port (Port A). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:------------------------- - * ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0 | Number of GPIO Ports = 1 - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS - * - * Number of GPIO Ports = 1 - */ -#define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ -#define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ -#define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3 -/* The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ -#define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2 -/* The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */ -#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c -/* The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */ -#define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3 -/* The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */ -#define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0 -/* Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register. */ -#define ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2) -/* Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c) - -/* - * Field : PORT A SINGLE CTL - porta_single_ctl - * - * Indicates the mode of operation of Port A to be software controlled only. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------|:------|:----------------------------------------- - * ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL - * - * Software Enabled Individual Port Control - */ -#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4 -/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1 -/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ -#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010 -/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */ -#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef -/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1 -/* Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */ -#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : PORT B SINGLE CTL - portb_single_ctl - * - * Indicates the mode of operation of Port B to be software controlled only. - * Ignored because there is no Port B in the GPIO. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------|:------|:----------------------------------------- - * ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL - * - * Software Enabled Individual Port Control - */ -#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5 -/* The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1 -/* The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ -#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020 -/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */ -#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf -/* The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1 -/* Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */ -#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : PORT C SINGLE CTL - portc_single_ctl - * - * Indicates the mode of operation of Port C to be software controlled only. - * Ignored because there is no Port C in the GPIO. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------|:------|:----------------------------------------- - * ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL - * - * Software Enabled Individual Port Control - */ -#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6 -/* The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1 -/* The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ -#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040 -/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */ -#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf -/* The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1 -/* Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */ -#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : PORT D SINGLE CTL - portd_single_ctl - * - * Indicates the mode of operation of Port D to be software controlled only. - * Ignored because there is no Port D in the GPIO. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------|:------|:----------------------------------------- - * ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL - * - * Software Enabled Individual Port Control - */ -#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7 -/* The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1 -/* The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ -#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080 -/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */ -#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f -/* The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */ -#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1 -/* Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */ -#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : HW PORTA - hw_porta - * - * The value is fixed to enable Port A configuration to be controlled by software - * only. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------|:------|:--------------------------------------- - * ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0 | Software Configuration Control Enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA - * - * Software Configuration Control Enabled - */ -#define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ -#define ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ -#define ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8 -/* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ -#define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1 -/* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */ -#define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100 -/* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */ -#define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff -/* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */ -#define ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0 -/* Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register. */ -#define ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Port A Interrupt Field - porta_intr - * - * The value of this field is fixed to allow interrupts on Port A. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:-------------------------- - * ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1 | Port A Interrupts Enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR - * - * Port A Interrupts Enabled - */ -#define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ -#define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ -#define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12 -/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ -#define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1 -/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */ -#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000 -/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */ -#define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff -/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */ -#define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1 -/* Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register. */ -#define ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000) - -/* - * Field : Debounce Field - debounce - * - * The value of this field is fixed to allow debouncing of the Port A signals. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:-------------------- - * ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA | 0x1 | Debounce is Enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE - * - * Debounce is Enabled - */ -#define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ -#define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ -#define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13 -/* The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ -#define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1 -/* The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */ -#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000 -/* The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */ -#define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff -/* The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */ -#define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1 -/* Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register. */ -#define ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : Encoded GPIO Parameters Available - add_encoded_params - * - * Fixed to allow the indentification of the Designware IP component. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------------|:------|:-------------------------- - * ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Enable IP indentification - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS - * - * Enable IP indentification - */ -#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ -#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ -#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14 -/* The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ -#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1 -/* The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ -#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000 -/* The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */ -#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff -/* The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */ -#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1 -/* Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */ -#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000) - -/* - * Field : ID Field - gpio_id - * - * Provides an ID code value - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:------------- - * ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE | 0x1 | GPIO ID Code - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID - * - * GPIO ID Code - */ -#define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ -#define ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ -#define ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15 -/* The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ -#define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1 -/* The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */ -#define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000 -/* The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */ -#define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff -/* The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */ -#define ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1 -/* Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register. */ -#define ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15) -/* Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000) - -/* - * Field : Encoded ID Width Field - encoded_id_width - * - * This value is fixed at 32 bits. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------------ - * ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f | Width of ID Field - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH - * - * Width of ID Field - */ -#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f - -/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ -#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ -#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20 -/* The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ -#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5 -/* The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ -#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000 -/* The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */ -#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff -/* The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */ -#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f -/* Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */ -#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16) -/* Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */ -#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_GPIO_CFG_REG1. - */ -struct ALT_GPIO_CFG_REG1_s -{ - const uint32_t apb_data_width : 2; /* APB DATA WIDTH */ - const uint32_t num_ports : 2; /* NUM PORTS */ - const uint32_t porta_single_ctl : 1; /* PORT A SINGLE CTL */ - const uint32_t portb_single_ctl : 1; /* PORT B SINGLE CTL */ - const uint32_t portc_single_ctl : 1; /* PORT C SINGLE CTL */ - const uint32_t portd_single_ctl : 1; /* PORT D SINGLE CTL */ - const uint32_t hw_porta : 1; /* HW PORTA */ - uint32_t : 3; /* *UNDEFINED* */ - const uint32_t porta_intr : 1; /* Port A Interrupt Field */ - const uint32_t debounce : 1; /* Debounce Field */ - const uint32_t add_encoded_params : 1; /* Encoded GPIO Parameters Available */ - const uint32_t gpio_id : 1; /* ID Field */ - const uint32_t encoded_id_width : 5; /* Encoded ID Width Field */ - uint32_t : 11; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_GPIO_CFG_REG1. */ -typedef volatile struct ALT_GPIO_CFG_REG1_s ALT_GPIO_CFG_REG1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component. */ -#define ALT_GPIO_CFG_REG1_OFST 0x74 -/* The address of the ALT_GPIO_CFG_REG1 register. */ -#define ALT_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_GPIO. - */ -struct ALT_GPIO_s -{ - volatile ALT_GPIO_SWPORTA_DR_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */ - volatile ALT_GPIO_SWPORTA_DDR_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */ - volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */ - volatile ALT_GPIO_INTEN_t gpio_inten; /* ALT_GPIO_INTEN */ - volatile ALT_GPIO_INTMSK_t gpio_intmask; /* ALT_GPIO_INTMSK */ - volatile ALT_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */ - volatile ALT_GPIO_INT_POL_t gpio_int_polarity; /* ALT_GPIO_INT_POL */ - volatile ALT_GPIO_INTSTAT_t gpio_intstatus; /* ALT_GPIO_INTSTAT */ - volatile ALT_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */ - volatile ALT_GPIO_DEBOUNCE_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */ - volatile ALT_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */ - volatile ALT_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */ - volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ - volatile ALT_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */ - volatile ALT_GPIO_ID_CODE_t gpio_id_code; /* ALT_GPIO_ID_CODE */ - volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */ - volatile ALT_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */ - volatile ALT_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */ - volatile ALT_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */ - volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_GPIO. */ -typedef volatile struct ALT_GPIO_s ALT_GPIO_t; -/* The struct declaration for the raw register contents of register group ALT_GPIO. */ -struct ALT_GPIO_raw_s -{ - volatile uint32_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */ - volatile uint32_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */ - volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */ - volatile uint32_t gpio_inten; /* ALT_GPIO_INTEN */ - volatile uint32_t gpio_intmask; /* ALT_GPIO_INTMSK */ - volatile uint32_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */ - volatile uint32_t gpio_int_polarity; /* ALT_GPIO_INT_POL */ - volatile uint32_t gpio_intstatus; /* ALT_GPIO_INTSTAT */ - volatile uint32_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */ - volatile uint32_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */ - volatile uint32_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */ - volatile uint32_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */ - volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */ - volatile uint32_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */ - volatile uint32_t gpio_id_code; /* ALT_GPIO_ID_CODE */ - volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */ - volatile uint32_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */ - volatile uint32_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */ - volatile uint32_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */ - volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_GPIO. */ -typedef volatile struct ALT_GPIO_raw_s ALT_GPIO_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_GPIO_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h deleted file mode 100644 index b50543a884..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_i2c.h +++ /dev/null @@ -1,5940 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_I2C */ - -#ifndef __ALTERA_ALT_I2C_H__ -#define __ALTERA_ALT_I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : I2C Module - ALT_I2C - * I2C Module - * - * Registers in the I2C module - * - */ -/* - * Register : Control Register - ic_con - * - * This register can be written only when the I2C is disabled, which corresponds to - * the Bit [0] of the Enable Register being set to 0. Writes at other times have no - * effect. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------- - * [0] | RW | 0x1 | Master Enable - * [2:1] | RW | 0x2 | Master Speed Control - * [3] | RW | 0x1 | Slave Address Size - * [4] | RW | 0x1 | Master Address Size - * [5] | RW | 0x1 | Restart Enable - * [6] | RW | 0x1 | Slave Disable - * [31:7] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Master Enable - master_mode - * - * This bit controls whether the i2c master is enabled. - * - * NOTE: Software should ensure that if this bit is written with '1', then bit 6 - * should also be written with a '1'. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:---------------- - * ALT_I2C_CON_MST_MOD_E_DIS | 0x0 | master disabled - * ALT_I2C_CON_MST_MOD_E_EN | 0x1 | master enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_CON_MST_MOD - * - * master disabled - */ -#define ALT_I2C_CON_MST_MOD_E_DIS 0x0 -/* - * Enumerated value for register field ALT_I2C_CON_MST_MOD - * - * master enabled - */ -#define ALT_I2C_CON_MST_MOD_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field. */ -#define ALT_I2C_CON_MST_MOD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field. */ -#define ALT_I2C_CON_MST_MOD_MSB 0 -/* The width in bits of the ALT_I2C_CON_MST_MOD register field. */ -#define ALT_I2C_CON_MST_MOD_WIDTH 1 -/* The mask used to set the ALT_I2C_CON_MST_MOD register field value. */ -#define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CON_MST_MOD register field value. */ -#define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CON_MST_MOD register field. */ -#define ALT_I2C_CON_MST_MOD_RESET 0x1 -/* Extracts the ALT_I2C_CON_MST_MOD field value from a register. */ -#define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register. */ -#define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Master Speed Control - speed - * - * These bits control at which speed the I2C operates, its setting is relevant only - * if one is operating the I2C in master mode. Hardware protects against illegal - * values being programmed by software. This field should be programmed only with - * standard or fast speed. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:--------------------------- - * ALT_I2C_CON_SPEED_E_STANDARD | 0x1 | standard mode (100 kbit/s) - * ALT_I2C_CON_SPEED_E_FAST | 0x2 | fast mode (400 kbit/s) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_CON_SPEED - * - * standard mode (100 kbit/s) - */ -#define ALT_I2C_CON_SPEED_E_STANDARD 0x1 -/* - * Enumerated value for register field ALT_I2C_CON_SPEED - * - * fast mode (400 kbit/s) - */ -#define ALT_I2C_CON_SPEED_E_FAST 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field. */ -#define ALT_I2C_CON_SPEED_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field. */ -#define ALT_I2C_CON_SPEED_MSB 2 -/* The width in bits of the ALT_I2C_CON_SPEED register field. */ -#define ALT_I2C_CON_SPEED_WIDTH 2 -/* The mask used to set the ALT_I2C_CON_SPEED register field value. */ -#define ALT_I2C_CON_SPEED_SET_MSK 0x00000006 -/* The mask used to clear the ALT_I2C_CON_SPEED register field value. */ -#define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9 -/* The reset value of the ALT_I2C_CON_SPEED register field. */ -#define ALT_I2C_CON_SPEED_RESET 0x2 -/* Extracts the ALT_I2C_CON_SPEED field value from a register. */ -#define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1) -/* Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register. */ -#define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006) - -/* - * Field : Slave Address Size - ic_10bitaddr_slave - * - * When acting as a slave, this bit controls whether the I2C responds to 7- or - * 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave - * Address Register are compared. The I2C responds will only respond to 10-bit - * addressing transfers that match the full 10 bits of the Slave Address register. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------------ - * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT | 0x0 | 7-bit addressing - * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT | 0x1 | 10-bit addressing - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV - * - * 7-bit addressing - */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 -/* - * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV - * - * 10-bit addressing - */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3 -/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1 -/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008 -/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1 -/* Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register. */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register. */ -#define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Master Address Size - ic_10bitaddr_master - * - * This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing - * mode when acting as a master. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------------ - * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT | 0x0 | 7-bit addressing - * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT | 0x1 | 10-bit addressing - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST - * - * 7-bit addressing - */ -#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 -/* - * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST - * - * 10-bit addressing - */ -#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ -#define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ -#define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4 -/* The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ -#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1 -/* The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ -#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010 -/* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value. */ -#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef -/* The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field. */ -#define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1 -/* Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register. */ -#define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register. */ -#define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Restart Enable - ic_restart_en - * - * Determines whether RESTART conditions may be sent when acting as a master. Some - * older slaves do not support handling RESTART conditions; however, RESTART - * conditions are used in several I2C operations. When RESTART is disabled, the - * master is prohibited from performing the following functions - * - * * Changing direction within a transfer (split), - * - * * Sending a START BYTE, - * - * * High-speed mode operation, - * - * * Combined format transfers in 7-bit addressing modes, - * - * * Read operation with a 10-bit address, - * - * * Sending multiple bytes per transfer, - * - * By replacing RESTART condition followed by a STOP and a subsequent START - * condition, split operations are broken down into multiple I2C transfers. If the - * above operations are performed, it will result in setting bit [6](tx_abort) of - * the Raw Interrupt Status Register. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------|:------|:----------------------- - * ALT_I2C_CON_IC_RESTART_EN_E_DIS | 0x0 | restart master disable - * ALT_I2C_CON_IC_RESTART_EN_E_EN | 0x1 | restart master enable - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN - * - * restart master disable - */ -#define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 -/* - * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN - * - * restart master enable - */ -#define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ -#define ALT_I2C_CON_IC_RESTART_EN_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */ -#define ALT_I2C_CON_IC_RESTART_EN_MSB 5 -/* The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field. */ -#define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1 -/* The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value. */ -#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020 -/* The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value. */ -#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf -/* The reset value of the ALT_I2C_CON_IC_RESTART_EN register field. */ -#define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1 -/* Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register. */ -#define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register. */ -#define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Slave Disable - ic_slave_disable - * - * This bit controls whether I2C has its slave disabled. The slave will be - * disabled, after reset. - * - * NOTE: Software should ensure that if this bit is written with 0, then bit [0] of - * this register should also be written with a 0. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:-------------- - * ALT_I2C_CON_IC_SLV_DIS_E_DIS | 0x1 | slave disable - * ALT_I2C_CON_IC_SLV_DIS_E_EN | 0x0 | slave enable - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS - * - * slave disable - */ -#define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 -/* - * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS - * - * slave enable - */ -#define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ -#define ALT_I2C_CON_IC_SLV_DIS_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */ -#define ALT_I2C_CON_IC_SLV_DIS_MSB 6 -/* The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field. */ -#define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1 -/* The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value. */ -#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040 -/* The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value. */ -#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf -/* The reset value of the ALT_I2C_CON_IC_SLV_DIS register field. */ -#define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1 -/* Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register. */ -#define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register. */ -#define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CON. - */ -struct ALT_I2C_CON_s -{ - uint32_t master_mode : 1; /* Master Enable */ - uint32_t speed : 2; /* Master Speed Control */ - uint32_t ic_10bitaddr_slave : 1; /* Slave Address Size */ - uint32_t ic_10bitaddr_master : 1; /* Master Address Size */ - uint32_t ic_restart_en : 1; /* Restart Enable */ - uint32_t ic_slave_disable : 1; /* Slave Disable */ - uint32_t : 25; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CON. */ -typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CON register from the beginning of the component. */ -#define ALT_I2C_CON_OFST 0x0 -/* The address of the ALT_I2C_CON register. */ -#define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST)) - -/* - * Register : Target Address Register - ic_tar - * - * This register can be written to only when the ic_enable register is set to 0. - * This register is 13 bits wide. All bits can be dynamically updated as long as - * any set of the following conditions are true, - * - * (Enable Register bit 0 is set to 0) or (Enable Register bit 0 is set to 1 AND - * (I2C is NOT engaged in any Master [tx, rx] operation [ic_status register - * mst_activity bit 5 is set to 0]) AND (I2C is enabled to operate in Master - * mode[ic_con bit[0] is set to one]) AND (there are NO entries in the TX FIFO - * Register [IC_STATUS bit [2] is set to 1]) - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------ - * [9:0] | RW | 0x55 | Master Target Address - * [10] | RW | 0x0 | General Call OR Start - * [11] | RW | 0x0 | Special - * [12] | RW | 0x1 | Master Addressing Bit Control - * [31:13] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Master Target Address - ic_tar - * - * This is the target address for any master transaction. When transmitting a - * General Call, these bits are ignored. To generate a START BYTE, the CPU needs to - * write only once into these bits. If the ic_tar and ic_sar are the same, loopback - * exists but the FIFOs are shared between master and slave, so full loopback is - * not feasible. Only one direction loopback mode is supported (simplex), not - * duplex. A master cannot transmit to itself; it can transmit to only a slave. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field. */ -#define ALT_I2C_TAR_IC_TAR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field. */ -#define ALT_I2C_TAR_IC_TAR_MSB 9 -/* The width in bits of the ALT_I2C_TAR_IC_TAR register field. */ -#define ALT_I2C_TAR_IC_TAR_WIDTH 10 -/* The mask used to set the ALT_I2C_TAR_IC_TAR register field value. */ -#define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff -/* The mask used to clear the ALT_I2C_TAR_IC_TAR register field value. */ -#define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00 -/* The reset value of the ALT_I2C_TAR_IC_TAR register field. */ -#define ALT_I2C_TAR_IC_TAR_RESET 0x55 -/* Extracts the ALT_I2C_TAR_IC_TAR field value from a register. */ -#define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0) -/* Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register. */ -#define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff) - -/* - * Field : General Call OR Start - gc_or_start - * - * If bit 11 (SPECIAL) of this Register is set to 1, then this bit indicates - * whether a General Call or START byte command is to be performed by the I2C or - * General Call Address after issuing a General Call, only writes may be performed. - * Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the Raw - * Interrupt_Status register. The I2C remains in General Call mode until the - * special bit value (bit 11) is cleared. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:------------- - * ALT_I2C_TAR_GC_OR_START_E_GENCALL | 0x0 | General Call - * ALT_I2C_TAR_GC_OR_START_E_STARTBYTE | 0x1 | START Byte - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_TAR_GC_OR_START - * - * General Call - */ -#define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0 -/* - * Enumerated value for register field ALT_I2C_TAR_GC_OR_START - * - * START Byte - */ -#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ -#define ALT_I2C_TAR_GC_OR_START_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field. */ -#define ALT_I2C_TAR_GC_OR_START_MSB 10 -/* The width in bits of the ALT_I2C_TAR_GC_OR_START register field. */ -#define ALT_I2C_TAR_GC_OR_START_WIDTH 1 -/* The mask used to set the ALT_I2C_TAR_GC_OR_START register field value. */ -#define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400 -/* The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value. */ -#define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff -/* The reset value of the ALT_I2C_TAR_GC_OR_START register field. */ -#define ALT_I2C_TAR_GC_OR_START_RESET 0x0 -/* Extracts the ALT_I2C_TAR_GC_OR_START field value from a register. */ -#define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register. */ -#define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : Special - special - * - * This bit indicates whether software performs a General Call or START BYTE - * command. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------|:------|:-------------------------------------------- - * ALT_I2C_TAR_SPECIAL_E_GENCALL | 0x0 | Ignore bit 10 gc_or_start and use ic_tar - * : | | normally - * ALT_I2C_TAR_SPECIAL_E_STARTBYTE | 0x1 | Perform special I2C command as specified in - * : | | gc_or_start - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_TAR_SPECIAL - * - * Ignore bit 10 gc_or_start and use ic_tar normally - */ -#define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0 -/* - * Enumerated value for register field ALT_I2C_TAR_SPECIAL - * - * Perform special I2C command as specified in gc_or_start - */ -#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field. */ -#define ALT_I2C_TAR_SPECIAL_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field. */ -#define ALT_I2C_TAR_SPECIAL_MSB 11 -/* The width in bits of the ALT_I2C_TAR_SPECIAL register field. */ -#define ALT_I2C_TAR_SPECIAL_WIDTH 1 -/* The mask used to set the ALT_I2C_TAR_SPECIAL register field value. */ -#define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800 -/* The mask used to clear the ALT_I2C_TAR_SPECIAL register field value. */ -#define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_I2C_TAR_SPECIAL register field. */ -#define ALT_I2C_TAR_SPECIAL_RESET 0x0 -/* Extracts the ALT_I2C_TAR_SPECIAL field value from a register. */ -#define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register. */ -#define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : Master Addressing Bit Control - ic_10bitaddr_master - * - * This bit controls whether the i2c starts its transfers in 7-bit or 10-bit - * addressing mode when acting as a master. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:---------------------- - * ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 | 0x0 | Master Address, 7bit - * ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 | 0x1 | Master Address, 10bit - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST - * - * Master Address, 7bit - */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0 -/* - * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST - * - * Master Address, 10bit - */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12 -/* The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1 -/* The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000 -/* The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff -/* The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1 -/* Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register. */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register. */ -#define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_TAR. - */ -struct ALT_I2C_TAR_s -{ - uint32_t ic_tar : 10; /* Master Target Address */ - uint32_t gc_or_start : 1; /* General Call OR Start */ - uint32_t special : 1; /* Special */ - uint32_t ic_10bitaddr_master : 1; /* Master Addressing Bit Control */ - uint32_t : 19; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_TAR. */ -typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_TAR register from the beginning of the component. */ -#define ALT_I2C_TAR_OFST 0x4 -/* The address of the ALT_I2C_TAR register. */ -#define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST)) - -/* - * Register : Slave Address Register - ic_sar - * - * Holds Address of Slave - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------- - * [9:0] | RW | 0x55 | Slave Address - * [31:10] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Slave Address - ic_sar - * - * The Slave Address register holds the slave address when the I2C is operating as - * a slave. For 7-bit addressing, only Field Bits [6:0] of the Slave Address - * Register are used. This register can be written only when the I2C interface is - * disabled, which corresponds to field bit 0 of the Enable Register being set to - * 0. Writes at other times have no effect. - * - * Note, the default values cannot be any of the reserved address locations: that - * is, - * - * 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not - * guaranteed if you program the Slave Address Register or Target Address Register - * to a reserved value. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_SAR_IC_SAR register field. */ -#define ALT_I2C_SAR_IC_SAR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_SAR_IC_SAR register field. */ -#define ALT_I2C_SAR_IC_SAR_MSB 9 -/* The width in bits of the ALT_I2C_SAR_IC_SAR register field. */ -#define ALT_I2C_SAR_IC_SAR_WIDTH 10 -/* The mask used to set the ALT_I2C_SAR_IC_SAR register field value. */ -#define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff -/* The mask used to clear the ALT_I2C_SAR_IC_SAR register field value. */ -#define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00 -/* The reset value of the ALT_I2C_SAR_IC_SAR register field. */ -#define ALT_I2C_SAR_IC_SAR_RESET 0x55 -/* Extracts the ALT_I2C_SAR_IC_SAR field value from a register. */ -#define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0) -/* Produces a ALT_I2C_SAR_IC_SAR register field value suitable for setting the register. */ -#define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_SAR. - */ -struct ALT_I2C_SAR_s -{ - uint32_t ic_sar : 10; /* Slave Address */ - uint32_t : 22; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_SAR. */ -typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_SAR register from the beginning of the component. */ -#define ALT_I2C_SAR_OFST 0x8 -/* The address of the ALT_I2C_SAR register. */ -#define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST)) - -/* - * Register : Tx Rx Data and Command Register - ic_data_cmd - * - * This is the register the CPU writes to when filling the TX FIFO. Reading from - * this register returns bytes from RX FIFO. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------------- - * [7:0] | RW | 0x0 | Tx Rx Data - * [8] | W | 0x0 | Master Read Write Control - * [9] | W | 0x0 | Generate Stop - * [10] | W | 0x0 | Generate Restart - * [31:11] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Tx Rx Data - dat - * - * This Field contains the data to be transmitted or received on the I2C bus. If - * you are writing to these bits and want to perform a read, bits 7:0 (dat) are - * ignored by the I2C. However, when you read from this register, these bits return - * the value of data received on the I2C interface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ -#define ALT_I2C_DATA_CMD_DAT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field. */ -#define ALT_I2C_DATA_CMD_DAT_MSB 7 -/* The width in bits of the ALT_I2C_DATA_CMD_DAT register field. */ -#define ALT_I2C_DATA_CMD_DAT_WIDTH 8 -/* The mask used to set the ALT_I2C_DATA_CMD_DAT register field value. */ -#define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff -/* The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value. */ -#define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00 -/* The reset value of the ALT_I2C_DATA_CMD_DAT register field. */ -#define ALT_I2C_DATA_CMD_DAT_RESET 0x0 -/* Extracts the ALT_I2C_DATA_CMD_DAT field value from a register. */ -#define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register. */ -#define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff) - -/* - * Field : Master Read Write Control - cmd - * - * This bit controls whether a read or a write is performed. This bit does not - * control the direction when the I2C acts as a slave. It controls only the - * direction when it acts as a master. When a command is entered in the TX FIFO, - * this bit distinguishes the write and read commands. In slave-receiver mode, this - * bit is a 'don't care' because writes to this register are not required. In - * slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted. - * When programming this bit, you should remember the following: attempting to - * perform a read operation after a General Call command has been sent results in a - * tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special - * in the Target Address Register has been cleared. If a '1' is written to this bit - * after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs. - * - * NOTE: It is possible that while attempting a master I2C read transfer on I2C, a - * RD_REQ interrupt may have occurred simultaneously due to a remote I2C master - * addressing I2C. In this type of scenario, I2C ignores the Data Cmd write, - * generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:------------- - * ALT_I2C_DATA_CMD_CMD_E_RD | 0x1 | Master Read - * ALT_I2C_DATA_CMD_CMD_E_WR | 0x0 | Master Write - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_DATA_CMD_CMD - * - * Master Read - */ -#define ALT_I2C_DATA_CMD_CMD_E_RD 0x1 -/* - * Enumerated value for register field ALT_I2C_DATA_CMD_CMD - * - * Master Write - */ -#define ALT_I2C_DATA_CMD_CMD_E_WR 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ -#define ALT_I2C_DATA_CMD_CMD_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field. */ -#define ALT_I2C_DATA_CMD_CMD_MSB 8 -/* The width in bits of the ALT_I2C_DATA_CMD_CMD register field. */ -#define ALT_I2C_DATA_CMD_CMD_WIDTH 1 -/* The mask used to set the ALT_I2C_DATA_CMD_CMD register field value. */ -#define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100 -/* The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value. */ -#define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff -/* The reset value of the ALT_I2C_DATA_CMD_CMD register field. */ -#define ALT_I2C_DATA_CMD_CMD_RESET 0x0 -/* Extracts the ALT_I2C_DATA_CMD_CMD field value from a register. */ -#define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register. */ -#define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Generate Stop - stop - * - * This bit controls whether a STOP is issued after the byte is sent or received. - * - * 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is - * empty. If the Tx FIFO is not empty, the master immediately tries to start a new - * transfer by issuing a START and arbitrating for the bus. - * - * 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO - * is empty. If the Tx FIFO is not empty, the master continues the current transfer - * by sending/receiving data bytes according to the value of the CMD bit. If the Tx - * FIFO is empty, the master holds the SCL line low and stalls the bus until a new - * command is available in the Tx FIFO. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------|:------|:------------------ - * ALT_I2C_DATA_CMD_STOP_E_STOP | 0x1 | Issue Stop - * ALT_I2C_DATA_CMD_STOP_E_NO_STOP | 0x0 | Do Not Issue Stop - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_DATA_CMD_STOP - * - * Issue Stop - */ -#define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1 -/* - * Enumerated value for register field ALT_I2C_DATA_CMD_STOP - * - * Do Not Issue Stop - */ -#define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ -#define ALT_I2C_DATA_CMD_STOP_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field. */ -#define ALT_I2C_DATA_CMD_STOP_MSB 9 -/* The width in bits of the ALT_I2C_DATA_CMD_STOP register field. */ -#define ALT_I2C_DATA_CMD_STOP_WIDTH 1 -/* The mask used to set the ALT_I2C_DATA_CMD_STOP register field value. */ -#define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200 -/* The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value. */ -#define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff -/* The reset value of the ALT_I2C_DATA_CMD_STOP register field. */ -#define ALT_I2C_DATA_CMD_STOP_RESET 0x0 -/* Extracts the ALT_I2C_DATA_CMD_STOP field value from a register. */ -#define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register. */ -#define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Generate Restart - restart - * - * This bit controls whether a RESTART is issued before the byte is sent or - * received. - * - * 1 = A RESTART is issued before the data is sent/received (according to the value - * of CMD), regardless of whether or not the transfer direction is changing from - * the previous command. - * - * 0 = A RESTART is issued only if the transfer direction is changing from the - * previous command. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------|:------|:---------------------------------- - * ALT_I2C_DATA_CMD_RESTART_E_RESTART | 0x1 | Issue Restart - * ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE | 0x0 | Issue Restart On Direction Change - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART - * - * Issue Restart - */ -#define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1 -/* - * Enumerated value for register field ALT_I2C_DATA_CMD_RESTART - * - * Issue Restart On Direction Change - */ -#define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ -#define ALT_I2C_DATA_CMD_RESTART_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */ -#define ALT_I2C_DATA_CMD_RESTART_MSB 10 -/* The width in bits of the ALT_I2C_DATA_CMD_RESTART register field. */ -#define ALT_I2C_DATA_CMD_RESTART_WIDTH 1 -/* The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value. */ -#define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400 -/* The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value. */ -#define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff -/* The reset value of the ALT_I2C_DATA_CMD_RESTART register field. */ -#define ALT_I2C_DATA_CMD_RESTART_RESET 0x0 -/* Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register. */ -#define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register. */ -#define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_DATA_CMD. - */ -struct ALT_I2C_DATA_CMD_s -{ - uint32_t dat : 8; /* Tx Rx Data */ - uint32_t cmd : 1; /* Master Read Write Control */ - uint32_t stop : 1; /* Generate Stop */ - uint32_t restart : 1; /* Generate Restart */ - uint32_t : 21; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_DATA_CMD. */ -typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component. */ -#define ALT_I2C_DATA_CMD_OFST 0x10 -/* The address of the ALT_I2C_DATA_CMD register. */ -#define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST)) - -/* - * Register : Std Spd Clock SCL HCNT Register - ic_ss_scl_hcnt - * - * This register sets the SCL clock high-period count for standard speed. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [15:0] | RW | 0x190 | Std Spd SCL High Period - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Std Spd SCL High Period - ic_ss_scl_hcnt - * - * This register must be set before any I2C bus transaction can take place to - * ensure proper I/O timing. This field sets the SCL clock high-period count for - * standard speed. This register can be written only when the I2C interface is - * disabled which corresponds to the Enable Register being set to 0. Writes at - * other times have no effect. The minimum valid value is 6; hardware prevents - * values less than this being written, and if attempted results in 6 being set. It - * is readable and writeable. - * - * NOTE: This register must not be programmed to a value higher than 65525, because - * I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter - * reaches a value of IC_SS_SCL_HCNT + 10. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ -#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ -#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 -/* The width in bits of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ -#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16 -/* The mask used to set the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ -#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */ -#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000 -/* The reset value of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */ -#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190 -/* Extracts the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */ -#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */ -#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_SS_SCL_HCNT. - */ -struct ALT_I2C_SS_SCL_HCNT_s -{ - uint32_t ic_ss_scl_hcnt : 16; /* Std Spd SCL High Period */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_SS_SCL_HCNT. */ -typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_SS_SCL_HCNT register from the beginning of the component. */ -#define ALT_I2C_SS_SCL_HCNT_OFST 0x14 -/* The address of the ALT_I2C_SS_SCL_HCNT register. */ -#define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST)) - -/* - * Register : Std Spd Clock SCL LCNT Register - ic_ss_scl_lcnt - * - * This register sets the SCL clock low-period count for standard speed - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------- - * [15:0] | RW | 0x1d6 | Std Spd SCL Low Period - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Std Spd SCL Low Period - ic_ss_scl_lcnt - * - * This register must be set before any I2C bus transaction can take place to - * ensure proper I/O timing. This field sets the SCL clock low period count for - * standard speed. This register can be written only when the I2C interface is - * disabled which corresponds to the Enable Register register being set to 0. - * Writes at other times have no effect. The minimum valid value is 8; hardware - * prevents values less than this from being written, and if attempted, results in - * 8 being set. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ -#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ -#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 -/* The width in bits of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ -#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16 -/* The mask used to set the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ -#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */ -#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000 -/* The reset value of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */ -#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6 -/* Extracts the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */ -#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */ -#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_SS_SCL_LCNT. - */ -struct ALT_I2C_SS_SCL_LCNT_s -{ - uint32_t ic_ss_scl_lcnt : 16; /* Std Spd SCL Low Period */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_SS_SCL_LCNT. */ -typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_SS_SCL_LCNT register from the beginning of the component. */ -#define ALT_I2C_SS_SCL_LCNT_OFST 0x18 -/* The address of the ALT_I2C_SS_SCL_LCNT register. */ -#define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST)) - -/* - * Register : Fast Spd Clock SCL HCNT Register - ic_fs_scl_hcnt - * - * This register sets the SCL clock high-period count for fast speed - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------- - * [15:0] | RW | 0x3c | Fast Spd SCL High Period - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Fast Spd SCL High Period - ic_fs_scl_hcnt - * - * This register must be set before any I2C bus transaction can take place to - * ensure proper I/O timing. This register sets the SCL clock high-period count for - * fast speed. It is used in high-speed mode to send the Master Code and START BYTE - * or General CALL. This register goes away and becomes read-only returning 0s if - * in Standard Speed Mode. This register can be written only when the I2C interface - * is disabled, which corresponds to the Enable Register being set to 0. Writes at - * other times have no effect. The minimum valid value is 6; hardware prevents - * values less than this from being written, and if attempted results in 6 being - * set. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ -#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ -#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 -/* The width in bits of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ -#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16 -/* The mask used to set the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ -#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */ -#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000 -/* The reset value of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */ -#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c -/* Extracts the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */ -#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */ -#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_FS_SCL_HCNT. - */ -struct ALT_I2C_FS_SCL_HCNT_s -{ - uint32_t ic_fs_scl_hcnt : 16; /* Fast Spd SCL High Period */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_FS_SCL_HCNT. */ -typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_FS_SCL_HCNT register from the beginning of the component. */ -#define ALT_I2C_FS_SCL_HCNT_OFST 0x1c -/* The address of the ALT_I2C_FS_SCL_HCNT register. */ -#define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST)) - -/* - * Register : Fast Spd Clock SCL LCNT Register - ic_fs_scl_lcnt - * - * This register sets the SCL clock low period count - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [15:0] | RW | 0x82 | Fast Spd SCL Low Period - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Fast Spd SCL Low Period - ic_fs_scl_lcnt - * - * This register must be set before any I2C bus transaction can take place to - * ensure proper I/O timing. This field sets the SCL clock low period count for - * fast speed. It is used in high-speed mode to send the Master Code and START BYTE - * or General CALL. This register can be written only when the I2C interface is - * disabled, which corresponds to the Enable Register being set to 0. Writes at - * other times have no effect.The minimum valid value is 8; hardware prevents - * values less than this being written, and if attempted results in 8 being set. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ -#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ -#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 -/* The width in bits of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ -#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16 -/* The mask used to set the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ -#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */ -#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000 -/* The reset value of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */ -#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82 -/* Extracts the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */ -#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */ -#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_FS_SCL_LCNT. - */ -struct ALT_I2C_FS_SCL_LCNT_s -{ - uint32_t ic_fs_scl_lcnt : 16; /* Fast Spd SCL Low Period */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_FS_SCL_LCNT. */ -typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_FS_SCL_LCNT register from the beginning of the component. */ -#define ALT_I2C_FS_SCL_LCNT_OFST 0x20 -/* The address of the ALT_I2C_FS_SCL_LCNT register. */ -#define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST)) - -/* - * Register : Interrupt Status Register - ic_intr_stat - * - * Each bit in this register has a corresponding mask bit in the Interrupt Mask - * Register. These bits are cleared by reading the matching Interrupt Clear - * Register. The unmasked raw versions of these bits are available in the Raw - * Interrupt Status Register. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------- - * [0] | R | 0x0 | Receiver Under - * [1] | R | 0x0 | Receiver Over - * [2] | R | 0x0 | Receive Full - * [3] | R | 0x0 | Interrupt Transmit Over - * [4] | R | 0x0 | Interrupt Transmit Empty - * [5] | R | 0x0 | Interrupt Read Request - * [6] | R | 0x0 | Interrupt TX Abort - * [7] | R | 0x0 | Interrupt RX Done - * [8] | R | 0x0 | Interrupt R_activity - * [9] | R | 0x0 | Interrupt Stop Detect - * [10] | R | 0x0 | Interrupt Start Detect - * [11] | R | 0x0 | Interrupt General Call - * [31:12] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Receiver Under - r_rx_under - * - * Set if the processor attempts to read the receive buffer when it is empty by - * reading from the Tx Rx Data and Command Register. If the module is disabled, - * Enable Register is set to 0, this bit keeps its level until the master or slave - * state machines go into idle, then this interrupt is cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ -#define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ -#define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0 -/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ -#define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ -#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */ -#define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */ -#define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register. */ -#define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Receiver Over - r_rx_over - * - * Set if the receive buffer is completely filled to 64 and an additional byte is - * received from an external I2C device. The I2C acknowledges this, but any data - * bytes received after the FIFO is full are lost. If the module is disabled, - * Enable Register bit[0] is set to 0 this bit keeps its level until the master or - * slave state machines go into idle, then this interrupt is cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ -#define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ -#define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1 -/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ -#define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ -#define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */ -#define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd -/* The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */ -#define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register. */ -#define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Receive Full - r_rx_full - * - * Set when the receive buffer reaches or goes above the Receive FIFO Threshold - * Value(rx_tl). It is automatically cleared by hardware when buffer level goes - * below the threshold. If the module is disabled, Bit [0] of the Enable Register - * set to 0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not - * full. So this bit is cleared once the Enable Register Bit 0 is programmed with a - * 0, regardless of the activity that continues. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ -#define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ -#define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2 -/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ -#define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ -#define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */ -#define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb -/* The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */ -#define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register. */ -#define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Interrupt Transmit Over - r_tx_over - * - * Set during transmit if the transmit buffer is filled to 64 and the processor - * attempts to issue another I2C command by writing to the Data and Command - * Register. When the module is disabled, this bit keeps its level until the master - * or slave state machines goes into idle, then interrupt is cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ -#define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ -#define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3 -/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ -#define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ -#define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */ -#define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */ -#define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register. */ -#define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Interrupt Transmit Empty - r_tx_empty - * - * This bit is set to 1 when the transmit buffer is at or below the threshold value - * set in the ic_tx_tl register. It is automatically cleared by hardware when the - * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX - * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data - * within it, so this bit is set to 1, provided there is activity in the master or - * slave state machines. When there is no longer activity, this bit is set to 0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ -#define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ -#define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4 -/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ -#define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ -#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */ -#define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef -/* The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */ -#define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register. */ -#define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Interrupt Read Request - r_rd_req - * - * This bit is set to 1 when i2c is acting as a slave and another I2C master is - * attempting to read data from I2C. The I2C holds the I2C bus in a wait state - * (SCL=0) until this interrupt is serviced, which means that the slave has been - * addressed by a remote master that is asking for data to be transferred. The - * processor must respond to this interrupt and then write the requested data to - * the IC_DATA_CMD register. This bit is set to 0 just after the processor reads - * the ic_clr_rd_req register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ -#define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ -#define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5 -/* The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ -#define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ -#define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */ -#define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf -/* The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */ -#define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register. */ -#define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Interrupt TX Abort - r_tx_abrt - * - * This bit indicates if I2C, as an I2C transmitter, is unable to complete the - * intended actions on the contents of the transmit FIFO. This situation can occur - * both as an I2C master or an I2C slave, and is referred to as a 'transmit - * abort'.When this bit is set to 1, the ic_tx_abrt_source register indicates the - * reason why the transmit abort takes places. - * - * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The - * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. - * Once this read is performed, the TX FIFO is then ready to accept more data bytes - * from the APB interface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ -#define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ -#define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6 -/* The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ -#define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ -#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */ -#define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf -/* The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */ -#define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register. */ -#define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Interrupt RX Done - r_rx_done - * - * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the - * master does not acknowledge a transmitted byte. This occurs on the last byte of - * the transmission, indicating that the transmission is done. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ -#define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ -#define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7 -/* The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ -#define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ -#define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */ -#define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f -/* The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */ -#define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register. */ -#define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : Interrupt R_activity - r_activity - * - * This bit captures I2C activity and stays set until it is cleared. There are four - * ways to clear it: - * - * * Disabling the I2C - * - * * Reading the ic_clr_activity register - * - * * Reading the ic_clr_intr register - * - * * I2C reset - * - * Once this bit is set, it stays set unless one of the four methods is used to - * clear it. Even if the I2C module is idle, this bit remains set until cleared, - * indicating that there was activity on the bus. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ -#define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ -#define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8 -/* The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ -#define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ -#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */ -#define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff -/* The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */ -#define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register. */ -#define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Interrupt Stop Detect - r_stop_det - * - * Indicates whether a STOP condition has occurred on the I2C interface regardless - * of whether I2C is operating in slave or master mode. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ -#define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ -#define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9 -/* The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ -#define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ -#define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */ -#define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff -/* The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */ -#define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register. */ -#define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Interrupt Start Detect - r_start_det - * - * Indicates whether a START or RESTART condition has occurred on the I2C interface - * regardless of whether I2C is operating in slave or master mode. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ -#define ALT_I2C_INTR_STAT_R_START_DET_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */ -#define ALT_I2C_INTR_STAT_R_START_DET_MSB 10 -/* The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field. */ -#define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value. */ -#define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value. */ -#define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff -/* The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field. */ -#define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register. */ -#define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : Interrupt General Call - r_gen_call - * - * Set only when a General Call address is received and it is acknowledged. It - * stays set until it is cleared either by disabling I2C or when the CPU reads bit - * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx - * buffer. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ -#define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ -#define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11 -/* The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ -#define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ -#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800 -/* The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */ -#define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */ -#define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0 -/* Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register. */ -#define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */ -#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_INTR_STAT. - */ -struct ALT_I2C_INTR_STAT_s -{ - const uint32_t r_rx_under : 1; /* Receiver Under */ - const uint32_t r_rx_over : 1; /* Receiver Over */ - const uint32_t r_rx_full : 1; /* Receive Full */ - const uint32_t r_tx_over : 1; /* Interrupt Transmit Over */ - const uint32_t r_tx_empty : 1; /* Interrupt Transmit Empty */ - const uint32_t r_rd_req : 1; /* Interrupt Read Request */ - const uint32_t r_tx_abrt : 1; /* Interrupt TX Abort */ - const uint32_t r_rx_done : 1; /* Interrupt RX Done */ - const uint32_t r_activity : 1; /* Interrupt R_activity */ - const uint32_t r_stop_det : 1; /* Interrupt Stop Detect */ - const uint32_t r_start_det : 1; /* Interrupt Start Detect */ - const uint32_t r_gen_call : 1; /* Interrupt General Call */ - uint32_t : 20; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_INTR_STAT. */ -typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component. */ -#define ALT_I2C_INTR_STAT_OFST 0x2c -/* The address of the ALT_I2C_INTR_STAT register. */ -#define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST)) - -/* - * Register : Interrupt Mask Register - ic_intr_mask - * - * These bits mask their corresponding interrupt status bits. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:---------------- - * [0] | RW | 0x1 | Mask RX Under - * [1] | RW | 0x1 | RX Buffer Over - * [2] | RW | 0x1 | RX Buffer Full - * [3] | RW | 0x1 | TX Buffer Over - * [4] | RW | 0x1 | TX Buffer Empty - * [5] | RW | 0x1 | Read Request - * [6] | RW | 0x1 | TX Abort - * [7] | RW | 0x1 | RX Done - * [8] | RW | 0x0 | Activity Bit - * [9] | RW | 0x0 | Stop Detect - * [10] | RW | 0x0 | Start Detect - * [11] | RW | 0x1 | General Call - * [31:12] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Mask RX Under - m_rx_under - * - * Set if the processor attempts to read the receive buffer when it is empty by - * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, - * this bit keeps its level until the master or slave state machines go into idle, - * and then this interrupt is cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ -#define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ -#define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0 -/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ -#define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ -#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */ -#define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */ -#define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1 -/* Extracts the ALT_I2C_INTR_MSK_M_RX_UNDER field value from a register. */ -#define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_INTR_MSK_M_RX_UNDER register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : RX Buffer Over - m_rx_over - * - * Set if the receive buffer is completely filled to 64 and an additional byte is - * received from an external I2C device. The I2C acknowledges this, but any data - * bytes received after the FIFO is full are lost. If the module is disabled - * ic_enable[0]=0, this bit keeps its level until the master or slave state - * machines go into idle, then this interrupt is cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ -#define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ -#define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1 -/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ -#define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ -#define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */ -#define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd -/* The reset value of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */ -#define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1 -/* Extracts the ALT_I2C_INTR_MSK_M_RX_OVER field value from a register. */ -#define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_I2C_INTR_MSK_M_RX_OVER register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : RX Buffer Full - m_rx_full - * - * Set when the receive buffer reaches or goes above the RX_TL threshold in the - * ic_rx_tl register. It is automatically cleared by hardware when buffer level - * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO - * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is - * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the - * activity that continues. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ -#define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ -#define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2 -/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ -#define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ -#define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */ -#define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb -/* The reset value of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */ -#define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1 -/* Extracts the ALT_I2C_INTR_MSK_M_RX_FULL field value from a register. */ -#define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_I2C_INTR_MSK_M_RX_FULL register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : TX Buffer Over - m_tx_over - * - * Set during transmit if the transmit buffer is filled to 64 and the processor - * attempts to issue another I2C command by writing to the ic_data_cmd register. - * When the module is disabled, this bit keeps its level until the master or slave - * state machines go into idle, then this interrupt is cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ -#define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ -#define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3 -/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ -#define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ -#define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */ -#define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */ -#define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1 -/* Extracts the ALT_I2C_INTR_MSK_M_TX_OVER field value from a register. */ -#define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_I2C_INTR_MSK_M_TX_OVER register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : TX Buffer Empty - m_tx_empty - * - * This bit is set to 1 when the transmit buffer is at or below the threshold value - * set in the ic_tx_tl register. It is automatically cleared by hardware when the - * buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX - * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data - * within it, so this bit is set to 1, provided there is activity in the master or - * slave state machines. When there is no longer activity, then this bit is set to - * 0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ -#define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ -#define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4 -/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ -#define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ -#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */ -#define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef -/* The reset value of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */ -#define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1 -/* Extracts the ALT_I2C_INTR_MSK_M_TX_EMPTY field value from a register. */ -#define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_I2C_INTR_MSK_M_TX_EMPTY register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Read Request - m_rd_req - * - * This bit is set to 1 when I2C is acting as a slave and another I2C master is - * attempting to read data from I2C. The I2C holds the I2C bus in a wait state - * (SCL=0) until this interrupt is serviced, which means that the slave has been - * addressed by a remote master that is asking for data to be transferred. The - * processor must respond to this interrupt and then write the requested data to - * the ic_data_cmd register. This bit is set to 0 just after the processor reads - * the ic_clr_rd_req register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ -#define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ -#define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5 -/* The width in bits of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ -#define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ -#define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */ -#define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf -/* The reset value of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */ -#define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1 -/* Extracts the ALT_I2C_INTR_MSK_M_RD_REQ field value from a register. */ -#define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_I2C_INTR_MSK_M_RD_REQ register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : TX Abort - m_tx_abrt - * - * This bit indicates if I2C, as an I2C transmitter, is unable to complete the - * intended actions on the contents of the transmit FIFO. This situation can occur - * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. - * When this bit is set to 1, the ic_tx_abrt_source register indicates the reason - * why the transmit abort takes places. - * - * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The - * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. - * Once this read is performed, the TX FIFO is then ready to accept more data bytes - * from the APB interface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ -#define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ -#define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6 -/* The width in bits of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ -#define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ -#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */ -#define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf -/* The reset value of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */ -#define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1 -/* Extracts the ALT_I2C_INTR_MSK_M_TX_ABRT field value from a register. */ -#define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_I2C_INTR_MSK_M_TX_ABRT register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : RX Done - m_rx_done - * - * When the I2C is acting as a slave-transmitter, this bit is set to 1, if the - * master does not acknowledge a transmitted byte. This occurs on the last byte of - * the transmission, indicating that the transmission is done. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ -#define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ -#define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7 -/* The width in bits of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ -#define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ -#define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */ -#define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f -/* The reset value of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */ -#define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1 -/* Extracts the ALT_I2C_INTR_MSK_M_RX_DONE field value from a register. */ -#define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_I2C_INTR_MSK_M_RX_DONE register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : Activity Bit - m_activity - * - * This bit captures i2c activity and stays set until it is cleared. There are four - * ways to clear it: - * - * * Disabling the i2c - * - * * Reading the ic_clr_activity register - * - * * Reading the ic_clr_intr register - * - * * System reset - * - * Once this bit is set, it stays set unless one of the four methods is used to - * clear it. Even if the I2C module is idle, this bit remains set until cleared, - * indicating that there was activity on the bus. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ -#define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ -#define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8 -/* The width in bits of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ -#define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ -#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */ -#define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff -/* The reset value of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */ -#define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0 -/* Extracts the ALT_I2C_INTR_MSK_M_ACTIVITY field value from a register. */ -#define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_I2C_INTR_MSK_M_ACTIVITY register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Stop Detect - m_stop_det - * - * Indicates whether a STOP condition has occurred on the I2C interface regardless - * of whether i2c is operating in slave or master mode. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ -#define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ -#define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9 -/* The width in bits of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ -#define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ -#define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */ -#define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff -/* The reset value of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */ -#define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0 -/* Extracts the ALT_I2C_INTR_MSK_M_STOP_DET field value from a register. */ -#define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_I2C_INTR_MSK_M_STOP_DET register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Start Detect - m_start_det - * - * Indicates whether a START or RESTART condition has occurred on the I2C interface - * regardless of whether I2C is operating in slave or master mode. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ -#define ALT_I2C_INTR_MSK_M_START_DET_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */ -#define ALT_I2C_INTR_MSK_M_START_DET_MSB 10 -/* The width in bits of the ALT_I2C_INTR_MSK_M_START_DET register field. */ -#define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_START_DET register field value. */ -#define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_START_DET register field value. */ -#define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff -/* The reset value of the ALT_I2C_INTR_MSK_M_START_DET register field. */ -#define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0 -/* Extracts the ALT_I2C_INTR_MSK_M_START_DET field value from a register. */ -#define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_I2C_INTR_MSK_M_START_DET register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : General Call - m_gen_call - * - * Set only when a General Call address is received and it is acknowledged. It - * stays set until it is cleared either by disabling I2C or when the CPU reads bit - * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx - * buffer. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ -#define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ -#define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11 -/* The width in bits of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ -#define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1 -/* The mask used to set the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ -#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800 -/* The mask used to clear the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */ -#define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */ -#define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1 -/* Extracts the ALT_I2C_INTR_MSK_M_GEN_CALL field value from a register. */ -#define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_I2C_INTR_MSK_M_GEN_CALL register field value suitable for setting the register. */ -#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_INTR_MSK. - */ -struct ALT_I2C_INTR_MSK_s -{ - uint32_t m_rx_under : 1; /* Mask RX Under */ - uint32_t m_rx_over : 1; /* RX Buffer Over */ - uint32_t m_rx_full : 1; /* RX Buffer Full */ - uint32_t m_tx_over : 1; /* TX Buffer Over */ - uint32_t m_tx_empty : 1; /* TX Buffer Empty */ - uint32_t m_rd_req : 1; /* Read Request */ - uint32_t m_tx_abrt : 1; /* TX Abort */ - uint32_t m_rx_done : 1; /* RX Done */ - uint32_t m_activity : 1; /* Activity Bit */ - uint32_t m_stop_det : 1; /* Stop Detect */ - uint32_t m_start_det : 1; /* Start Detect */ - uint32_t m_gen_call : 1; /* General Call */ - uint32_t : 20; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_INTR_MSK. */ -typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_INTR_MSK register from the beginning of the component. */ -#define ALT_I2C_INTR_MSK_OFST 0x30 -/* The address of the ALT_I2C_INTR_MSK register. */ -#define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST)) - -/* - * Register : Raw Interrupt Status Register - ic_raw_intr_stat - * - * Unlike the ic_intr_stat register, these bits are not masked so they always show - * the true status of the I2C. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:--------------------------- - * [0] | R | 0x0 | I2C Raw Interrupt RX Under - * [1] | R | 0x0 | Raw Interrupt RX Over - * [2] | R | 0x0 | Raw Interrupt RX Full - * [3] | R | 0x0 | Raw Interrupt TX Over - * [4] | R | 0x0 | Raw Interrupt TX Empty - * [5] | R | 0x0 | Raw Interrupt Read Request - * [6] | R | 0x0 | Raw Interrupt TX Abort - * [7] | R | 0x0 | Raw Interrupt RX Done - * [8] | R | 0x0 | Raw Interrupt Activity - * [9] | R | 0x0 | Raw Interrupt Stop Detect - * [10] | R | 0x0 | Raw Interrupt Start Detect - * [11] | R | 0x0 | Raw Interrupt General Call - * [31:12] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : I2C Raw Interrupt RX Under - rx_under - * - * Set if the processor attempts to read the receive buffer when it is empty by - * reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, - * this bit keeps its level until the master or slave state machines go into idle, - * then this interrupt is cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_UNDER field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Raw Interrupt RX Over - rx_over - * - * Set if the receive buffer is completely filled to 64 and an additional byte is - * received from an external I2C device. The I2C acknowledges this, but any data - * bytes received after the FIFO is full are lost. If the module is disabled - * ic_enable[0]=0), this bit keeps its level until the master or slave state - * machines go into then, this interrupt is cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd -/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_OVER field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_I2C_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Raw Interrupt RX Full - rx_full - * - * Set when the receive buffer reaches or goes above the RX_TL threshold in the - * ic_rx_tl register. It is automatically cleared by hardware when buffer level - * goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO - * is flushed and held in reset; therefore the RX FIFO is not full. So this bit is - * cleared once the ic_enable bit 0 is programmed with a 0, regardless of the - * activity that continues. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb -/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_FULL field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_I2C_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Raw Interrupt TX Over - tx_over - * - * Set during transmit if the transmit buffer is filled to 64 and the processor - * attempts to issue another I2C command by writing to the ic_data_cmd register. - * When the module is disabled, this bit keeps its level until the master or slave - * state machines go into idle, then this interrupt is cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ -#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */ -#define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_OVER field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_I2C_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Raw Interrupt TX Empty - tx_empty - * - * This bit is set to 1 when the transmit buffer is at or below the threshold value - * set in the ic_tx_tl register. It is automatically cleared by hardware when the - * buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX - * FIFO is flushed and held in reset. There the TX FIFO looks like it has no data - * within it, so this bit is set to 1, provided there is activity in the master or - * slave state machines. When there is no longer activity, then this bit is set to - * 0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ -#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */ -#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef -/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_EMPTY field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Raw Interrupt Read Request - rd_req - * - * This bit is set to 1 when I2C is acting as a slave and another I2C master is - * attempting to read data from I2C. The i2c holds the I2C bus in a wait state - * (SCL=0) until this interrupt is serviced, which means that the slave has been - * addressed by a remote master that is asking for data to be transferred. The - * processor must respond to this interrupt and then write the requested data to - * the ic_data_cmd register. This bit is set to 0 just after the processor reads - * the ic_clr_rd_req register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ -#define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ -#define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ -#define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf -/* The reset value of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */ -#define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_RD_REQ field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_I2C_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Raw Interrupt TX Abort - tx_abrt - * - * This bit indicates if I2C, as an I2C transmitter, is unable to complete the - * intended actions on the contents of the transmit FIFO. This situation can occur - * both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. - * When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason - * why the transmit abort takes places. - * - * NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The - * TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. - * Once this read is performed, the TX FIFO is then ready to accept more data bytes - * from the APB interface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ -#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */ -#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf -/* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */ -#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_TX_ABRT field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Raw Interrupt RX Done - rx_done - * - * When the I2C is acting as a slave-transmitter, this bit is set to 1 if the - * master does not acknowledge a transmitted byte. This occurs on the last byte of - * the transmission, indicating that the transmission is done. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */ -#define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f -/* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */ -#define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_RX_DONE field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_I2C_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : Raw Interrupt Activity - activity - * - * This bit captures i2c activity and stays set until it is cleared. There are four - * ways to clear it: - * - * * Disabling the I2C - * - * * Reading the ic_clr_activity register - * - * * Reading the ic_clr_intr register - * - * * System reset - * - * Once this bit is set, it stays set unless one of the four methods is used to - * clear it. Even if the i2c module is idle, this bit remains set until cleared, - * indicating that there was activity on the bus. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ -#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ -#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ -#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ -#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */ -#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff -/* The reset value of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */ -#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_ACTIVITY field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Raw Interrupt Stop Detect - stop_det - * - * Indicates whether a STOP condition has occurred on the I2C interface regardless - * of whether I2C is operating in slave or master mode. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ -#define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ -#define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ -#define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ -#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */ -#define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff -/* The reset value of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */ -#define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_STOP_DET field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_I2C_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Raw Interrupt Start Detect - start_det - * - * Indicates whether a START or RESTART condition has occurred on the I2C interface - * regardless of whether I2C is operating in slave or master mode. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ -#define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ -#define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ -#define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ -#define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */ -#define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff -/* The reset value of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */ -#define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_START_DET field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_I2C_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : Raw Interrupt General Call - gen_call - * - * Set only when a General Call address is received and it is acknowledged. It - * stays set until it is cleared either by disabling I2C or when the CPU reads bit - * 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx - * buffer. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ -#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ -#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11 -/* The width in bits of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ -#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1 -/* The mask used to set the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ -#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800 -/* The mask used to clear the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */ -#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */ -#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0 -/* Extracts the ALT_I2C_RAW_INTR_STAT_GEN_CALL field value from a register. */ -#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */ -#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_RAW_INTR_STAT. - */ -struct ALT_I2C_RAW_INTR_STAT_s -{ - const uint32_t rx_under : 1; /* I2C Raw Interrupt RX Under */ - const uint32_t rx_over : 1; /* Raw Interrupt RX Over */ - const uint32_t rx_full : 1; /* Raw Interrupt RX Full */ - const uint32_t tx_over : 1; /* Raw Interrupt TX Over */ - const uint32_t tx_empty : 1; /* Raw Interrupt TX Empty */ - const uint32_t rd_req : 1; /* Raw Interrupt Read Request */ - const uint32_t tx_abrt : 1; /* Raw Interrupt TX Abort */ - const uint32_t rx_done : 1; /* Raw Interrupt RX Done */ - const uint32_t activity : 1; /* Raw Interrupt Activity */ - const uint32_t stop_det : 1; /* Raw Interrupt Stop Detect */ - const uint32_t start_det : 1; /* Raw Interrupt Start Detect */ - const uint32_t gen_call : 1; /* Raw Interrupt General Call */ - uint32_t : 20; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_RAW_INTR_STAT. */ -typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_RAW_INTR_STAT register from the beginning of the component. */ -#define ALT_I2C_RAW_INTR_STAT_OFST 0x34 -/* The address of the ALT_I2C_RAW_INTR_STAT register. */ -#define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST)) - -/* - * Register : Receive FIFO Threshold Register - ic_rx_tl - * - * I2C Receive FIFO Threshold Register. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [7:0] | RW | 0x0 | Receive FIFO Threshold Level - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Receive FIFO Threshold Level - rx_tl - * - * Controls the level of entries (or above) that triggers the RX_FULL interrupt - * (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the - * additional restriction that hardware does not allow this value to be set to a - * value larger than the depth of the buffer. If an attempt is made to do that, the - * actual value set will be the maximum depth of the buffer. A value of 0 sets the - * threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ -#define ALT_I2C_RX_TL_RX_TL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RX_TL_RX_TL register field. */ -#define ALT_I2C_RX_TL_RX_TL_MSB 7 -/* The width in bits of the ALT_I2C_RX_TL_RX_TL register field. */ -#define ALT_I2C_RX_TL_RX_TL_WIDTH 8 -/* The mask used to set the ALT_I2C_RX_TL_RX_TL register field value. */ -#define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff -/* The mask used to clear the ALT_I2C_RX_TL_RX_TL register field value. */ -#define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00 -/* The reset value of the ALT_I2C_RX_TL_RX_TL register field. */ -#define ALT_I2C_RX_TL_RX_TL_RESET 0x0 -/* Extracts the ALT_I2C_RX_TL_RX_TL field value from a register. */ -#define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_I2C_RX_TL_RX_TL register field value suitable for setting the register. */ -#define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_RX_TL. - */ -struct ALT_I2C_RX_TL_s -{ - uint32_t rx_tl : 8; /* Receive FIFO Threshold Level */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_RX_TL. */ -typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_RX_TL register from the beginning of the component. */ -#define ALT_I2C_RX_TL_OFST 0x38 -/* The address of the ALT_I2C_RX_TL register. */ -#define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST)) - -/* - * Register : Transmit FIFO Threshold Level Register - ic_tx_tl - * - * Sets FIFO depth for Interrupt. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [7:0] | RW | 0x0 | Transmit FIFO Threshold Level - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Transmit FIFO Threshold Level - tx_tl - * - * Controls the level of entries (or below) that trigger the TX_EMPTY interrupt - * (bit 4 in ic_raw_intr_stat register). The valid range is 0-255, with the - * additional restriction that it may not be set to value larger than the depth of - * the buffer. If an attempt is made to do that, the actual value set will be the - * maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and - * a value of 255 sets the threshold for 255 entries. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ -#define ALT_I2C_TX_TL_TX_TL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_TL_TX_TL register field. */ -#define ALT_I2C_TX_TL_TX_TL_MSB 7 -/* The width in bits of the ALT_I2C_TX_TL_TX_TL register field. */ -#define ALT_I2C_TX_TL_TX_TL_WIDTH 8 -/* The mask used to set the ALT_I2C_TX_TL_TX_TL register field value. */ -#define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff -/* The mask used to clear the ALT_I2C_TX_TL_TX_TL register field value. */ -#define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00 -/* The reset value of the ALT_I2C_TX_TL_TX_TL register field. */ -#define ALT_I2C_TX_TL_TX_TL_RESET 0x0 -/* Extracts the ALT_I2C_TX_TL_TX_TL field value from a register. */ -#define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_I2C_TX_TL_TX_TL register field value suitable for setting the register. */ -#define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_TX_TL. - */ -struct ALT_I2C_TX_TL_s -{ - uint32_t tx_tl : 8; /* Transmit FIFO Threshold Level */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_TX_TL. */ -typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_TX_TL register from the beginning of the component. */ -#define ALT_I2C_TX_TL_OFST 0x3c -/* The address of the ALT_I2C_TX_TL register. */ -#define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST)) - -/* - * Register : Combined and Individual Interrupt Register - ic_clr_intr - * - * Controls Interrupts - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | R | 0x0 | Combined and Individual Interrupt Bits - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Combined and Individual Interrupt Bits - clr_intr - * - * Read this register to clear the combined interrupt, all individual interrupts, - * and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable - * interrupts but software clearable interrupts. Refer to Bit 9 of the - * ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ -#define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ -#define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0 -/* The width in bits of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ -#define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ -#define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_INTR_CLR_INTR register field value. */ -#define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_INTR_CLR_INTR register field. */ -#define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0 -/* Extracts the ALT_I2C_CLR_INTR_CLR_INTR field value from a register. */ -#define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_INTR_CLR_INTR register field value suitable for setting the register. */ -#define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_INTR. - */ -struct ALT_I2C_CLR_INTR_s -{ - const uint32_t clr_intr : 1; /* Combined and Individual Interrupt Bits */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_INTR. */ -typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_INTR register from the beginning of the component. */ -#define ALT_I2C_CLR_INTR_OFST 0x40 -/* The address of the ALT_I2C_CLR_INTR register. */ -#define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST)) - -/* - * Register : Rx Under Interrupt Register - ic_clr_rx_under - * - * Rx Under Interrupt Bits. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [0] | R | 0x0 | Clear Rx Under Interrupt Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Clear Rx Under Interrupt Bit - clr_rx_under - * - * Read this register to clear the RX_UNDER interrupt bit 0 of the ic_raw_intr_stat - * register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ -#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ -#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 -/* The width in bits of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ -#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ -#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */ -#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */ -#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 -/* Extracts the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */ -#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */ -#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_RX_UNDER. - */ -struct ALT_I2C_CLR_RX_UNDER_s -{ - const uint32_t clr_rx_under : 1; /* Clear Rx Under Interrupt Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_RX_UNDER. */ -typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_RX_UNDER register from the beginning of the component. */ -#define ALT_I2C_CLR_RX_UNDER_OFST 0x44 -/* The address of the ALT_I2C_CLR_RX_UNDER register. */ -#define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST)) - -/* - * Register : RX Over Interrupt Register - ic_clr_rx_over - * - * Clears Rx over Interrupt Bit - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------- - * [0] | R | 0x0 | RX Over Interrupt Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : RX Over Interrupt Bit - clr_rx_over - * - * Read this register to clear the RX_OVER interrupt bit 1 of the ic_raw_intr_stat - * register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ -#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ -#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0 -/* The width in bits of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ -#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ -#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */ -#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */ -#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 -/* Extracts the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER field value from a register. */ -#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */ -#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_RX_OVER. - */ -struct ALT_I2C_CLR_RX_OVER_s -{ - const uint32_t clr_rx_over : 1; /* RX Over Interrupt Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_RX_OVER. */ -typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_RX_OVER register from the beginning of the component. */ -#define ALT_I2C_CLR_RX_OVER_OFST 0x48 -/* The address of the ALT_I2C_CLR_RX_OVER register. */ -#define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST)) - -/* - * Register : TX Over Interrupt Register - ic_clr_tx_over - * - * Clears Over Interrupts - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------- - * [0] | R | 0x0 | TX Over Interrupt Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : TX Over Interrupt Bit - clr_tx_over - * - * Read this register to clear the TX_OVER interrupt (bit 3) of the - * ic_raw_intr_stat register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ -#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ -#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0 -/* The width in bits of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ -#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ -#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */ -#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */ -#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 -/* Extracts the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER field value from a register. */ -#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */ -#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_TX_OVER. - */ -struct ALT_I2C_CLR_TX_OVER_s -{ - const uint32_t clr_tx_over : 1; /* TX Over Interrupt Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_TX_OVER. */ -typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_TX_OVER register from the beginning of the component. */ -#define ALT_I2C_CLR_TX_OVER_OFST 0x4c -/* The address of the ALT_I2C_CLR_TX_OVER register. */ -#define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST)) - -/* - * Register : Interrupt Read Request Register - ic_clr_rd_req - * - * Clear RD_REQ Interrupt Register - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------ - * [0] | R | 0x0 | Interrupt Register Read Request Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Interrupt Register Read Request Bit - clr_rd_req - * - * Read this register to clear the RD_REQ interrupt (bit 5) of the ic_raw_intr_stat - * register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ -#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ -#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0 -/* The width in bits of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ -#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ -#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */ -#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */ -#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 -/* Extracts the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ field value from a register. */ -#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */ -#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_RD_REQ. - */ -struct ALT_I2C_CLR_RD_REQ_s -{ - const uint32_t clr_rd_req : 1; /* Interrupt Register Read Request Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_RD_REQ. */ -typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_RD_REQ register from the beginning of the component. */ -#define ALT_I2C_CLR_RD_REQ_OFST 0x50 -/* The address of the ALT_I2C_CLR_RD_REQ register. */ -#define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST)) - -/* - * Register : Tx Abort Interrupt Register - ic_clr_tx_abrt - * - * Clear TX_ABRT Interrupt - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------- - * [0] | R | 0x0 | Tx Abort Interrupt Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Tx Abort Interrupt Bit - clr_tx_abort - * - * Read this register to clear the TX_ABRT interrupt (bit 6) of the - * ic_raw_intr_stat register, and the ic_tx_abrt_source register. This also - * releases the TX FIFO from the flushed/reset state, allowing more writes to the - * TX FIFO. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to - * clearing ic_tx_abrt_source. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ -#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ -#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0 -/* The width in bits of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ -#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ -#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */ -#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */ -#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0 -/* Extracts the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT field value from a register. */ -#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value suitable for setting the register. */ -#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_TX_ABRT. - */ -struct ALT_I2C_CLR_TX_ABRT_s -{ - const uint32_t clr_tx_abort : 1; /* Tx Abort Interrupt Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_TX_ABRT. */ -typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_TX_ABRT register from the beginning of the component. */ -#define ALT_I2C_CLR_TX_ABRT_OFST 0x54 -/* The address of the ALT_I2C_CLR_TX_ABRT register. */ -#define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST)) - -/* - * Register : Rx Done Interrupt Register - ic_clr_rx_done - * - * Clear RX_DONE Interrupt Register - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------- - * [0] | R | 0x0 | RX_DONE Interrupt Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : RX_DONE Interrupt Bit - clr_rx_done - * - * Read this register to clear the RX_DONE interrupt (bit 7) of the - * ic_raw_intr_stat register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ -#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ -#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0 -/* The width in bits of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ -#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ -#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */ -#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */ -#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 -/* Extracts the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE field value from a register. */ -#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */ -#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_RX_DONE. - */ -struct ALT_I2C_CLR_RX_DONE_s -{ - const uint32_t clr_rx_done : 1; /* RX_DONE Interrupt Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_RX_DONE. */ -typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_RX_DONE register from the beginning of the component. */ -#define ALT_I2C_CLR_RX_DONE_OFST 0x58 -/* The address of the ALT_I2C_CLR_RX_DONE register. */ -#define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST)) - -/* - * Register : Activity Interrupt Register - ic_clr_activity - * - * Clears ACTIVITY Interrupt - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------- - * [0] | R | 0x0 | Activity Interrupt Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Activity Interrupt Bit - clr_activity - * - * Reading this register clears the ACTIVITY interrupt if the I2C is not active - * anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt - * bit continues to be set. It is automatically cleared by hardware if the module - * is disabled and if there is no further activity on the bus. The value read from - * this register to get status of the ACTIVITY interrupt (bit 8) of the - * ic_raw_intr_stat register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ -#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ -#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 -/* The width in bits of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ -#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ -#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */ -#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */ -#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 -/* Extracts the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */ -#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */ -#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_ACTIVITY. - */ -struct ALT_I2C_CLR_ACTIVITY_s -{ - const uint32_t clr_activity : 1; /* Activity Interrupt Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_ACTIVITY. */ -typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_ACTIVITY register from the beginning of the component. */ -#define ALT_I2C_CLR_ACTIVITY_OFST 0x5c -/* The address of the ALT_I2C_CLR_ACTIVITY register. */ -#define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST)) - -/* - * Register : Stop Detect Interrupt Register - ic_clr_stop_det - * - * Clear Interrupts. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------- - * [0] | R | 0x0 | Stop Detect Interrupt Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Stop Detect Interrupt Bit - clr_stop_det - * - * Read this register to clear the clr_stop_det interrupt (bit 9) of the - * ic_raw_intr_stat register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ -#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ -#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0 -/* The width in bits of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ -#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ -#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */ -#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */ -#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 -/* Extracts the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET field value from a register. */ -#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */ -#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_STOP_DET. - */ -struct ALT_I2C_CLR_STOP_DET_s -{ - const uint32_t clr_stop_det : 1; /* Stop Detect Interrupt Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_STOP_DET. */ -typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_STOP_DET register from the beginning of the component. */ -#define ALT_I2C_CLR_STOP_DET_OFST 0x60 -/* The address of the ALT_I2C_CLR_STOP_DET register. */ -#define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST)) - -/* - * Register : Start Detect Interrupt Register - ic_clr_start_det - * - * Clears START_DET Interrupt - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------- - * [0] | R | 0x0 | Start Detect Interrupt Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Start Detect Interrupt Bit - clr_start_det - * - * Read this register to clear the start_det interrupt (bit 10) of the - * ic_raw_intr_stat register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ -#define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ -#define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0 -/* The width in bits of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ -#define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ -#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */ -#define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */ -#define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0 -/* Extracts the ALT_I2C_CLR_START_DET_CLR_START_DET field value from a register. */ -#define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */ -#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_START_DET. - */ -struct ALT_I2C_CLR_START_DET_s -{ - const uint32_t clr_start_det : 1; /* Start Detect Interrupt Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_START_DET. */ -typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_START_DET register from the beginning of the component. */ -#define ALT_I2C_CLR_START_DET_OFST 0x64 -/* The address of the ALT_I2C_CLR_START_DET register. */ -#define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST)) - -/* - * Register : GEN CALL Interrupt Register - ic_clr_gen_call - * - * Clear GEN_CALL Interrupt Register - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------- - * [0] | R | 0x0 | GEN CALL Interrupt Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GEN CALL Interrupt Bit - clr_gen_call - * - * Read this register to clear the GEN_CALL interrupt (bit 11) of ic_raw_intr_stat - * register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ -#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ -#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 -/* The width in bits of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ -#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1 -/* The mask used to set the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ -#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */ -#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */ -#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 -/* Extracts the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */ -#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */ -#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_CLR_GEN_CALL. - */ -struct ALT_I2C_CLR_GEN_CALL_s -{ - const uint32_t clr_gen_call : 1; /* GEN CALL Interrupt Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_CLR_GEN_CALL. */ -typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_CLR_GEN_CALL register from the beginning of the component. */ -#define ALT_I2C_CLR_GEN_CALL_OFST 0x68 -/* The address of the ALT_I2C_CLR_GEN_CALL register. */ -#define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST)) - -/* - * Register : Enable Register - ic_enable - * - * Enable and disable i2c operation - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------- - * [0] | RW | 0x0 | Enable Bit - * [1] | RW | 0x0 | TX abort Bit - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Enable Bit - enable - * - * Controls whether the I2C is enabled. Software can disable I2C while it is - * active. However, it is important that care be taken to ensure that I2C is - * disabled properly. When the I2C is disabled, the following occurs: - * - * The TX FIFO and RX FIFO get flushed. Status bits in the IC_INTR_STAT register - * are still active until I2C goes into IDLE state. If the module is transmitting, - * it stops as well as deletes the contents of the transmit buffer after the - * current transfer is complete. If the module is receiving, the I2C stops the - * current transfer at the end of the current byte and does not acknowledge the - * transfer. The l4_sp_clk synchronizes pclk and ic_clk. The register - * ic_enable_status is added to allow software to determine when the hardware has - * completely shutdown in response to the IC_ENABLE register being set from 1 to 0. - * Only one register is required to be monitored. Procedure for Disabling I2C - * - * 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling - * period for the highest I2C transfer speed used in the system and supported by - * I2C. For example, if the highest I2C transfer mode is 400 kb/s, then this - * ti2c_poll is 25us. - * - * 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any - * repeated polling operation exceeds this maximum value, an error is reported. 3. - * Execute a blocking thread/process/function that prevents any further I2C master - * transactions to be started by software, but allows any pending transfers to be - * completed. - * - * 4. The variable POLL_COUNT is initialized to zero. 5. Set IC_ENABLE to 0. - * - * 6. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment - * POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant - * error code. - * - * 7. If IC_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the - * previous step. Otherwise, exit with a relevant success code. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------|:------|:----------------------------------------------- - * ALT_I2C_EN_EN_E_DIS | 0x0 | Disables i2c. TX and RX FIFOs are held in an - * : | | erased state - * ALT_I2C_EN_EN_E_EN | 0x1 | Enables i2c. Software can disable i2c while it - * : | | is active - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_EN_EN - * - * Disables i2c. TX and RX FIFOs are held in an erased state - */ -#define ALT_I2C_EN_EN_E_DIS 0x0 -/* - * Enumerated value for register field ALT_I2C_EN_EN - * - * Enables i2c. Software can disable i2c while it is active - */ -#define ALT_I2C_EN_EN_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_EN register field. */ -#define ALT_I2C_EN_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_EN register field. */ -#define ALT_I2C_EN_EN_MSB 0 -/* The width in bits of the ALT_I2C_EN_EN register field. */ -#define ALT_I2C_EN_EN_WIDTH 1 -/* The mask used to set the ALT_I2C_EN_EN register field value. */ -#define ALT_I2C_EN_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_EN_EN register field value. */ -#define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_EN_EN register field. */ -#define ALT_I2C_EN_EN_RESET 0x0 -/* Extracts the ALT_I2C_EN_EN field value from a register. */ -#define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_EN_EN register field value suitable for setting the register. */ -#define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : TX abort Bit - txabort - * - * Write 1 does a TX abort. Self cleared on abort completion - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_TXABT register field. */ -#define ALT_I2C_EN_TXABT_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_TXABT register field. */ -#define ALT_I2C_EN_TXABT_MSB 1 -/* The width in bits of the ALT_I2C_EN_TXABT register field. */ -#define ALT_I2C_EN_TXABT_WIDTH 1 -/* The mask used to set the ALT_I2C_EN_TXABT register field value. */ -#define ALT_I2C_EN_TXABT_SET_MSK 0x00000002 -/* The mask used to clear the ALT_I2C_EN_TXABT register field value. */ -#define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd -/* The reset value of the ALT_I2C_EN_TXABT register field. */ -#define ALT_I2C_EN_TXABT_RESET 0x0 -/* Extracts the ALT_I2C_EN_TXABT field value from a register. */ -#define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_I2C_EN_TXABT register field value suitable for setting the register. */ -#define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_EN. - */ -struct ALT_I2C_EN_s -{ - uint32_t enable : 1; /* Enable Bit */ - uint32_t txabort : 1; /* TX abort Bit */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_EN. */ -typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_EN register from the beginning of the component. */ -#define ALT_I2C_EN_OFST 0x6c -/* The address of the ALT_I2C_EN register. */ -#define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST)) - -/* - * Register : Status Register - ic_status - * - * This is a read-only register used to indicate the current transfer status and - * FIFO status. The status register may be read at any time. None of the bits in - * this register request an interrupt.When the I2C is disabled by writing 0 in bit - * 0 of the ic_enable register: - * - * * Bits 1 and 2 are set to 1 - * - * * Bits 3 and 4 are set to 0 - * - * When the master or slave state machines goes to idle - * - * * Bits 5 and 6 are set to 0 - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [0] | R | 0x0 | Activity Status Bit - * [1] | R | 0x1 | TX FIFO Not Full Bit - * [2] | R | 0x1 | TX FIFO Empty Bit - * [3] | R | 0x0 | RX FIFO Empty Bit - * [4] | R | 0x0 | RX FIFO Full Bit - * [5] | R | 0x0 | Master FSM Activity Status Bit - * [6] | R | 0x0 | Slave FSM Activity Status Bit - * [31:7] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Activity Status Bit - activity - * - * I2C Activity. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ -#define ALT_I2C_STAT_ACTIVITY_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_ACTIVITY register field. */ -#define ALT_I2C_STAT_ACTIVITY_MSB 0 -/* The width in bits of the ALT_I2C_STAT_ACTIVITY register field. */ -#define ALT_I2C_STAT_ACTIVITY_WIDTH 1 -/* The mask used to set the ALT_I2C_STAT_ACTIVITY register field value. */ -#define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_STAT_ACTIVITY register field value. */ -#define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_STAT_ACTIVITY register field. */ -#define ALT_I2C_STAT_ACTIVITY_RESET 0x0 -/* Extracts the ALT_I2C_STAT_ACTIVITY field value from a register. */ -#define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_STAT_ACTIVITY register field value suitable for setting the register. */ -#define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : TX FIFO Not Full Bit - tfnf - * - * Transmit Fifo Full - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:-------------------------- - * ALT_I2C_STAT_TFNF_E_FULL | 0x0 | Transmit FIFO is full - * ALT_I2C_STAT_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_STAT_TFNF - * - * Transmit FIFO is full - */ -#define ALT_I2C_STAT_TFNF_E_FULL 0x0 -/* - * Enumerated value for register field ALT_I2C_STAT_TFNF - * - * Transmit FIFO is not full - */ -#define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFNF register field. */ -#define ALT_I2C_STAT_TFNF_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFNF register field. */ -#define ALT_I2C_STAT_TFNF_MSB 1 -/* The width in bits of the ALT_I2C_STAT_TFNF register field. */ -#define ALT_I2C_STAT_TFNF_WIDTH 1 -/* The mask used to set the ALT_I2C_STAT_TFNF register field value. */ -#define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002 -/* The mask used to clear the ALT_I2C_STAT_TFNF register field value. */ -#define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd -/* The reset value of the ALT_I2C_STAT_TFNF register field. */ -#define ALT_I2C_STAT_TFNF_RESET 0x1 -/* Extracts the ALT_I2C_STAT_TFNF field value from a register. */ -#define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_I2C_STAT_TFNF register field value suitable for setting the register. */ -#define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : TX FIFO Empty Bit - tfe - * - * Transmit FIFO Empty. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:--------------------------- - * ALT_I2C_STAT_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty - * ALT_I2C_STAT_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_STAT_TFE - * - * Transmit FIFO is not empty - */ -#define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0 -/* - * Enumerated value for register field ALT_I2C_STAT_TFE - * - * Transmit FIFO is empty - */ -#define ALT_I2C_STAT_TFE_E_EMPTY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFE register field. */ -#define ALT_I2C_STAT_TFE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFE register field. */ -#define ALT_I2C_STAT_TFE_MSB 2 -/* The width in bits of the ALT_I2C_STAT_TFE register field. */ -#define ALT_I2C_STAT_TFE_WIDTH 1 -/* The mask used to set the ALT_I2C_STAT_TFE register field value. */ -#define ALT_I2C_STAT_TFE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_I2C_STAT_TFE register field value. */ -#define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_I2C_STAT_TFE register field. */ -#define ALT_I2C_STAT_TFE_RESET 0x1 -/* Extracts the ALT_I2C_STAT_TFE field value from a register. */ -#define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_I2C_STAT_TFE register field value suitable for setting the register. */ -#define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : RX FIFO Empty Bit - rfne - * - * Receive FIFO Not Empty. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:-------------------------- - * ALT_I2C_STAT_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty - * ALT_I2C_STAT_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_STAT_RFNE - * - * Receive FIFO is empty - */ -#define ALT_I2C_STAT_RFNE_E_EMPTY 0x0 -/* - * Enumerated value for register field ALT_I2C_STAT_RFNE - * - * Receive FIFO is not empty - */ -#define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFNE register field. */ -#define ALT_I2C_STAT_RFNE_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFNE register field. */ -#define ALT_I2C_STAT_RFNE_MSB 3 -/* The width in bits of the ALT_I2C_STAT_RFNE register field. */ -#define ALT_I2C_STAT_RFNE_WIDTH 1 -/* The mask used to set the ALT_I2C_STAT_RFNE register field value. */ -#define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008 -/* The mask used to clear the ALT_I2C_STAT_RFNE register field value. */ -#define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_I2C_STAT_RFNE register field. */ -#define ALT_I2C_STAT_RFNE_RESET 0x0 -/* Extracts the ALT_I2C_STAT_RFNE field value from a register. */ -#define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_I2C_STAT_RFNE register field value suitable for setting the register. */ -#define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : RX FIFO Full Bit - rff - * - * Receive FIFO Completely Full. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:------------------------- - * ALT_I2C_STAT_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full - * ALT_I2C_STAT_RFF_E_FULL | 0x1 | Receive FIFO is full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_STAT_RFF - * - * Receive FIFO is not full - */ -#define ALT_I2C_STAT_RFF_E_NOTFULL 0x0 -/* - * Enumerated value for register field ALT_I2C_STAT_RFF - * - * Receive FIFO is full - */ -#define ALT_I2C_STAT_RFF_E_FULL 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFF register field. */ -#define ALT_I2C_STAT_RFF_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFF register field. */ -#define ALT_I2C_STAT_RFF_MSB 4 -/* The width in bits of the ALT_I2C_STAT_RFF register field. */ -#define ALT_I2C_STAT_RFF_WIDTH 1 -/* The mask used to set the ALT_I2C_STAT_RFF register field value. */ -#define ALT_I2C_STAT_RFF_SET_MSK 0x00000010 -/* The mask used to clear the ALT_I2C_STAT_RFF register field value. */ -#define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef -/* The reset value of the ALT_I2C_STAT_RFF register field. */ -#define ALT_I2C_STAT_RFF_RESET 0x0 -/* Extracts the ALT_I2C_STAT_RFF field value from a register. */ -#define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_I2C_STAT_RFF register field value suitable for setting the register. */ -#define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Master FSM Activity Status Bit - mst_activity - * - * When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is - * set. Note:IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and - * MST_ACTIVITY bits. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:------------------------------------------------ - * ALT_I2C_STAT_MST_ACTIVITY_E_IDLE | 0x0 | Master FSM is in IDLE state. Master part of i2c - * : | | is not Active - * ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE | 0x1 | Master FSM is not in IDLE state. Master part of - * : | | i2c is Active - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY - * - * Master FSM is in IDLE state. Master part of i2c is not Active - */ -#define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0 -/* - * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY - * - * Master FSM is not in IDLE state. Master part of i2c is Active - */ -#define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ -#define ALT_I2C_STAT_MST_ACTIVITY_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */ -#define ALT_I2C_STAT_MST_ACTIVITY_MSB 5 -/* The width in bits of the ALT_I2C_STAT_MST_ACTIVITY register field. */ -#define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1 -/* The mask used to set the ALT_I2C_STAT_MST_ACTIVITY register field value. */ -#define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020 -/* The mask used to clear the ALT_I2C_STAT_MST_ACTIVITY register field value. */ -#define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf -/* The reset value of the ALT_I2C_STAT_MST_ACTIVITY register field. */ -#define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0 -/* Extracts the ALT_I2C_STAT_MST_ACTIVITY field value from a register. */ -#define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_I2C_STAT_MST_ACTIVITY register field value suitable for setting the register. */ -#define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Slave FSM Activity Status Bit - slv_activity - * - * Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in - * the IDLE state, this bit is set. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:------------------------------------------------- - * ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE | 0x0 | Slave FSM is in IDLE state so the Slave part of - * : | | i2c is not Active - * ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE | 0x1 | Slave FSM is not in IDLE state so the Slave part - * : | | of i2c is Active - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY - * - * Slave FSM is in IDLE state so the Slave part of i2c is not Active - */ -#define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0 -/* - * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY - * - * Slave FSM is not in IDLE state so the Slave part of i2c is Active - */ -#define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ -#define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ -#define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6 -/* The width in bits of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ -#define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1 -/* The mask used to set the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ -#define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040 -/* The mask used to clear the ALT_I2C_STAT_SLV_ACTIVITY register field value. */ -#define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf -/* The reset value of the ALT_I2C_STAT_SLV_ACTIVITY register field. */ -#define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0 -/* Extracts the ALT_I2C_STAT_SLV_ACTIVITY field value from a register. */ -#define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_I2C_STAT_SLV_ACTIVITY register field value suitable for setting the register. */ -#define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_STAT. - */ -struct ALT_I2C_STAT_s -{ - const uint32_t activity : 1; /* Activity Status Bit */ - const uint32_t tfnf : 1; /* TX FIFO Not Full Bit */ - const uint32_t tfe : 1; /* TX FIFO Empty Bit */ - const uint32_t rfne : 1; /* RX FIFO Empty Bit */ - const uint32_t rff : 1; /* RX FIFO Full Bit */ - const uint32_t mst_activity : 1; /* Master FSM Activity Status Bit */ - const uint32_t slv_activity : 1; /* Slave FSM Activity Status Bit */ - uint32_t : 25; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_STAT. */ -typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_STAT register from the beginning of the component. */ -#define ALT_I2C_STAT_OFST 0x70 -/* The address of the ALT_I2C_STAT register. */ -#define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST)) - -/* - * Register : Transmit FIFO Level Register - ic_txflr - * - * This register contains the number of valid data entries in the transmit FIFO - * buffer. It is cleared whenever: - * - * * The I2C is disabled - * - * * There is a transmit abort that is, TX_ABRT bit is set in the ic_raw_intr_stat - * register. The slave bulk transmit mode is aborted The register increments - * whenever data is placed into the transmit FIFO and decrements when data is - * taken from the transmit FIFO. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------ - * [6:0] | R | 0x0 | Transmit FIFO Level Bit - * [31:7] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Transmit FIFO Level Bit - txflr - * - * Transmit FIFO Level.Contains the number of valid data entries in the transmit - * FIFO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ -#define ALT_I2C_TXFLR_TXFLR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TXFLR_TXFLR register field. */ -#define ALT_I2C_TXFLR_TXFLR_MSB 6 -/* The width in bits of the ALT_I2C_TXFLR_TXFLR register field. */ -#define ALT_I2C_TXFLR_TXFLR_WIDTH 7 -/* The mask used to set the ALT_I2C_TXFLR_TXFLR register field value. */ -#define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f -/* The mask used to clear the ALT_I2C_TXFLR_TXFLR register field value. */ -#define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80 -/* The reset value of the ALT_I2C_TXFLR_TXFLR register field. */ -#define ALT_I2C_TXFLR_TXFLR_RESET 0x0 -/* Extracts the ALT_I2C_TXFLR_TXFLR field value from a register. */ -#define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0) -/* Produces a ALT_I2C_TXFLR_TXFLR register field value suitable for setting the register. */ -#define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_TXFLR. - */ -struct ALT_I2C_TXFLR_s -{ - const uint32_t txflr : 7; /* Transmit FIFO Level Bit */ - uint32_t : 25; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_TXFLR. */ -typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_TXFLR register from the beginning of the component. */ -#define ALT_I2C_TXFLR_OFST 0x74 -/* The address of the ALT_I2C_TXFLR register. */ -#define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST)) - -/* - * Register : Receive FIFO Level Register - ic_rxflr - * - * This register contains the number of valid data entries in the receive FIFO - * buffer. It is cleared whenever: - * - * * The I2C is disabled - * - * * Whenever there is a transmit abort caused by any of the events tracked in - * ic_tx_abrt_source The register increments whenever data is placed into the - * receive FIFO and decrements when data is taken from the receive FIFO. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------- - * [6:0] | R | 0x0 | Receive FIFO Level Bit - * [31:7] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Receive FIFO Level Bit - rxflr - * - * Receive FIFO Level. Contains the number of valid data entries in the receive - * FIFO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ -#define ALT_I2C_RXFLR_RXFLR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_RXFLR_RXFLR register field. */ -#define ALT_I2C_RXFLR_RXFLR_MSB 6 -/* The width in bits of the ALT_I2C_RXFLR_RXFLR register field. */ -#define ALT_I2C_RXFLR_RXFLR_WIDTH 7 -/* The mask used to set the ALT_I2C_RXFLR_RXFLR register field value. */ -#define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f -/* The mask used to clear the ALT_I2C_RXFLR_RXFLR register field value. */ -#define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80 -/* The reset value of the ALT_I2C_RXFLR_RXFLR register field. */ -#define ALT_I2C_RXFLR_RXFLR_RESET 0x0 -/* Extracts the ALT_I2C_RXFLR_RXFLR field value from a register. */ -#define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0) -/* Produces a ALT_I2C_RXFLR_RXFLR register field value suitable for setting the register. */ -#define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_RXFLR. - */ -struct ALT_I2C_RXFLR_s -{ - const uint32_t rxflr : 7; /* Receive FIFO Level Bit */ - uint32_t : 25; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_RXFLR. */ -typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_RXFLR register from the beginning of the component. */ -#define ALT_I2C_RXFLR_OFST 0x78 -/* The address of the ALT_I2C_RXFLR register. */ -#define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST)) - -/* - * Register : SDA Hold Register - ic_sda_hold - * - * This register controls the amount of time delay (in terms of number of l4_sp_clk - * clock periods) introduced in the falling edge of SCL, relative to SDA changing, - * when I2C services a read request in a slave-transmitter operation. The relevant - * I2C requirement is thd:DAT as detailed in the I2C Bus Specification. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------- - * [15:0] | RW | 0x1 | SDA Hold Bit - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : SDA Hold Bit - ic_sda_hold - * - * Program to a minimum 0f 300ns. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ -#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ -#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15 -/* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ -#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16 -/* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ -#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value. */ -#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000 -/* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field. */ -#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1 -/* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_HOLD field value from a register. */ -#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_I2C_SDA_HOLD_IC_SDA_HOLD register field value suitable for setting the register. */ -#define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_SDA_HOLD. - */ -struct ALT_I2C_SDA_HOLD_s -{ - uint32_t ic_sda_hold : 16; /* SDA Hold Bit */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_SDA_HOLD. */ -typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_SDA_HOLD register from the beginning of the component. */ -#define ALT_I2C_SDA_HOLD_OFST 0x7c -/* The address of the ALT_I2C_SDA_HOLD register. */ -#define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST)) - -/* - * Register : Transmit Abort Source Register - ic_tx_abrt_source - * - * This register has 16 bits that indicate the source of the TX_ABRT bit. Except - * for Bit 9, this register is cleared whenever the ic_clr_tx_abrt register or the - * ic_clr_intr register is read. To clear Bit 9, the source of the - * abrt_sbyte_norstrt must be fixed first; RESTART must be enabled (ic_con[5]=1), - * the special bit must be cleared (ic_tar[11]), or the gc_or_start bit must be - * cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then - * this bit can be cleared in the same manner as other bits in this register. If - * the source of the abrt_sbyte_norstrt is not fixed before attempting to clear - * this bit, Bit 9 clears for one cycle and is then re-asserted. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------------------- - * [0] | RW | 0x0 | Master Abort 7 Bit Address - * [1] | RW | 0x0 | Master Abort 10 Bit Address Byte 1 - * [2] | RW | 0x0 | Master Abort 10 Bit Address Byte 2 - * [3] | RW | 0x0 | Master Abort TX Noack Bit - * [4] | RW | 0x0 | Master Abort GC Noack Bit - * [5] | RW | 0x0 | Master Abort GC Read Bit - * [6] | RW | 0x0 | Master HS MC Ack - * [7] | RW | 0x0 | Master Abort START Byte - * [8] | RW | 0x0 | Master HS Restart Disabled - * [9] | RW | 0x0 | Master Abort START No Restart - * [10] | RW | 0x0 | Master Abort 10 Bit No Restart - * [11] | RW | 0x0 | Master Oper Master Dis - * [12] | RW | 0x0 | Master Abort Arbitration Lost - * [13] | RW | 0x0 | Slave Abort Flush TXFIFO - * [14] | RW | 0x0 | Slave Abort Arbitration Lost - * [15] | RW | 0x0 | Slave Abort Read TX - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Master Abort 7 Bit Address - abrt_7b_addr_noack - * - * Master is in 7-bit addressing mode and the address sent was not acknowledged by - * any slave. Role of i2c: Master-Transmitter or Master-Receiver - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Master Abort 10 Bit Address Byte 1 - abrt_10addr1_noack - * - * Master is in 10-bit address mode and the first 10-bit address byte was not - * acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Master Abort 10 Bit Address Byte 2 - abrt_10addr2_noack - * - * Master is in 10-bit address mode and the second address byte of the 10-bit - * address was not acknowledged by any slave. Role of i2c: Master-Transmitter or - * Master-Receiver - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Master Abort TX Noack Bit - abrt_txdata_noack - * - * This is a master-mode only bit. Master has received an acknowledgement for the - * address, but when it sent data byte(s) following the address, it did not receive - * an acknowledge from the remote slave(s). Role of i2c: Master-Transmitter - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Master Abort GC Noack Bit - abrt_gcall_noack - * - * i2c in master mode sent a General Call and no slave on the bus acknowledged the - * General Call. Role of i2c: Master-Transmitter - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Master Abort GC Read Bit - abrt_gcall_read - * - * i2c in master mode sent a General Call but the user programmed the byte - * following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to - * 1). Role of i2c: Master-Transmitter - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Master HS MC Ack - abrt_hs_ackdet - * - * Master is in High Speed mode and the High Speed Master code was acknowledged - * (wrong behavior). Role of i2c: Master - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Master Abort START Byte - abrt_sbyte_ackdet - * - * Master has sent a START Byte and the START Byte was acknowledged (wrong - * behavior). Role of i2c: Master - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : Master HS Restart Disabled - abrt_hs_norstrt - * - * The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is - * trying to use the master to transfer data in High Speed mode. Role of i2c: - * Master-Transmitter or Master-Receiver - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Master Abort START No Restart - abrt_sbyte_norstrt - * - * To clear Bit 9, the source of then abrt_sbyte_norstrt must be fixed first; - * restart must be enabled (ic_con[5]=1), the SPECIAL bit must be cleared - * (ic_tar[11]), or the GC_OR_START bit must be cleared (ic_tar[10]). Once the - * source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the - * same manner as other bits in this register. If the source of the - * abrt_sbyte_norstrt is not fixed before attempting to clear this bit, bit 9 - * clears for one cycle and then gets reasserted. 1: The restart is disabled - * (IC_RESTART_EN bit (ic_con[5]) =0) and the user is trying to send a START Byte. - * Role of I2C: Master - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Master Abort 10 Bit No Restart - abrt_10b_rd_norstrt - * - * The restart is disabled (ic_restart_en bit (ic_con[5]) =0) and the master sends - * a read command in 10-bit addressing mode. Role of I2C: Master-Receiver - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : Master Oper Master Dis - abrt_master_dis - * - * User tries to initiate a Master operation with the Master mode disabled. Role of - * I2C: Master-Transmitter or Master-Receiver - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : Master Abort Arbitration Lost - arb_lost - * - * Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the - * slave transmitter has lost arbitration. Note: I2C can be both master and slave - * at the same time. Role of i2c: Master-Transmitter or Slave-Transmitter - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ -#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ -#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ -#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */ -#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000) - -/* - * Field : Slave Abort Flush TXFIFO - abrt_slvflush_txfifo - * - * Slave has received a read command and some data exists in the TX FIFO so the - * slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Role of I2C: - * Slave-Transmitter - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : Slave Abort Arbitration Lost - abrt_slv_arblost - * - * Slave lost the bus while transmitting data to a remote master. - * IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never - * 'owns' the bus, something could go wrong on the bus. This is a fail safe check. - * For instance, during a data transmission at the low-to-high transition of SCL, - * if what is on the data bus is not what is supposed to be transmitted, then i2c - * no longer own the bus. Role of I2C: Slave-Transmitter - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000) - -/* - * Field : Slave Abort Read TX - abrt_slvrd_intx - * - * When the processor side responds to a slave mode request for data to be - * transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD - * register. Role of I2C: Slave-Transmitter - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15 -/* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1 -/* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000 -/* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff -/* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0 -/* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15) -/* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register. */ -#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_TX_ABRT_SRC. - */ -struct ALT_I2C_TX_ABRT_SRC_s -{ - uint32_t abrt_7b_addr_noack : 1; /* Master Abort 7 Bit Address */ - uint32_t abrt_10addr1_noack : 1; /* Master Abort 10 Bit Address Byte 1 */ - uint32_t abrt_10addr2_noack : 1; /* Master Abort 10 Bit Address Byte 2 */ - uint32_t abrt_txdata_noack : 1; /* Master Abort TX Noack Bit */ - uint32_t abrt_gcall_noack : 1; /* Master Abort GC Noack Bit */ - uint32_t abrt_gcall_read : 1; /* Master Abort GC Read Bit */ - uint32_t abrt_hs_ackdet : 1; /* Master HS MC Ack */ - uint32_t abrt_sbyte_ackdet : 1; /* Master Abort START Byte */ - uint32_t abrt_hs_norstrt : 1; /* Master HS Restart Disabled */ - uint32_t abrt_sbyte_norstrt : 1; /* Master Abort START No Restart */ - uint32_t abrt_10b_rd_norstrt : 1; /* Master Abort 10 Bit No Restart */ - uint32_t abrt_master_dis : 1; /* Master Oper Master Dis */ - uint32_t arb_lost : 1; /* Master Abort Arbitration Lost */ - uint32_t abrt_slvflush_txfifo : 1; /* Slave Abort Flush TXFIFO */ - uint32_t abrt_slv_arblost : 1; /* Slave Abort Arbitration Lost */ - uint32_t abrt_slvrd_intx : 1; /* Slave Abort Read TX */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_TX_ABRT_SRC. */ -typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component. */ -#define ALT_I2C_TX_ABRT_SRC_OFST 0x80 -/* The address of the ALT_I2C_TX_ABRT_SRC register. */ -#define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST)) - -/* - * Register : Generate Slave Data NACK - ic_slv_data_nack_only - * - * The register is used to generate a NACK for the data part of a transfer when i2c - * is acting as a slave-receiver. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------ - * [0] | RW | 0x0 | Generate Nack Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Generate Nack Bit - nack - * - * This Bit control Nack generation - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------|:------|:-------------------------------------- - * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE | 0x1 | Generate NACK after data byte receive - * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM | 0x0 | Generate NACK/ACK normally - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK - * - * Generate NACK after data byte receive - */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1 -/* - * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK - * - * Generate NACK/ACK normally - */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0 -/* The width in bits of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1 -/* The mask used to set the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 -/* Extracts the ALT_I2C_SLV_DATA_NACK_ONLY_NACK field value from a register. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. - */ -struct ALT_I2C_SLV_DATA_NACK_ONLY_s -{ - uint32_t nack : 1; /* Generate Nack Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. */ -typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_SLV_DATA_NACK_ONLY register from the beginning of the component. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84 -/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register. */ -#define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST)) - -/* - * Register : DMA Control - ic_dma_cr - * - * The register is used to enable the DMA Controller interface operation. There is - * a separate bit for transmit and receive. This can be programmed regardless of - * the state of IC_ENABLE. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------ - * [0] | RW | 0x0 | Receive DMA Enable Bit - * [1] | RW | 0x0 | Transmit DMA Enable Bit - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Receive DMA Enable Bit - rdmae - * - * This bit enables/disables the receive FIFO DMA channel. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:-------------------- - * ALT_I2C_DMA_CR_RDMAE_E_DIS | 0x0 | Receive DMA disable - * ALT_I2C_DMA_CR_RDMAE_E_EN | 0x1 | Receive DMA enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE - * - * Receive DMA disable - */ -#define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0 -/* - * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE - * - * Receive DMA enabled - */ -#define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ -#define ALT_I2C_DMA_CR_RDMAE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */ -#define ALT_I2C_DMA_CR_RDMAE_MSB 0 -/* The width in bits of the ALT_I2C_DMA_CR_RDMAE register field. */ -#define ALT_I2C_DMA_CR_RDMAE_WIDTH 1 -/* The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value. */ -#define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value. */ -#define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_DMA_CR_RDMAE register field. */ -#define ALT_I2C_DMA_CR_RDMAE_RESET 0x0 -/* Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register. */ -#define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register. */ -#define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Transmit DMA Enable Bit - tdmae - * - * This bit enables/disables the transmit FIFO DMA channel. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:--------------------- - * ALT_I2C_DMA_CR_TDMAE_E_DIS | 0x0 | Transmit DMA disable - * ALT_I2C_DMA_CR_TDMAE_E_EN | 0x1 | Transmit DMA enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE - * - * Transmit DMA disable - */ -#define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0 -/* - * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE - * - * Transmit DMA enabled - */ -#define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ -#define ALT_I2C_DMA_CR_TDMAE_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */ -#define ALT_I2C_DMA_CR_TDMAE_MSB 1 -/* The width in bits of the ALT_I2C_DMA_CR_TDMAE register field. */ -#define ALT_I2C_DMA_CR_TDMAE_WIDTH 1 -/* The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value. */ -#define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002 -/* The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value. */ -#define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd -/* The reset value of the ALT_I2C_DMA_CR_TDMAE register field. */ -#define ALT_I2C_DMA_CR_TDMAE_RESET 0x0 -/* Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register. */ -#define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register. */ -#define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_DMA_CR. - */ -struct ALT_I2C_DMA_CR_s -{ - uint32_t rdmae : 1; /* Receive DMA Enable Bit */ - uint32_t tdmae : 1; /* Transmit DMA Enable Bit */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_DMA_CR. */ -typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component. */ -#define ALT_I2C_DMA_CR_OFST 0x88 -/* The address of the ALT_I2C_DMA_CR register. */ -#define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST)) - -/* - * Register : DMA Transmit Data Level - ic_dma_tdlr - * - * This register supports DMA Transmit Operation. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [5:0] | RW | 0x0 | DMA Transmit Data Level Bit - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : DMA Transmit Data Level Bit - dmatdl - * - * This bit field controls the level at which a DMA request is made by the transmit - * logic. It is equal to the watermark level; that is, the i2c_dma_tx_req signal is - * generated when the number of valid data entries in the transmit FIFO is equal to - * or below this field value, and TDMAE = 1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ -#define ALT_I2C_DMA_TDLR_DMATDL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */ -#define ALT_I2C_DMA_TDLR_DMATDL_MSB 5 -/* The width in bits of the ALT_I2C_DMA_TDLR_DMATDL register field. */ -#define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6 -/* The mask used to set the ALT_I2C_DMA_TDLR_DMATDL register field value. */ -#define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f -/* The mask used to clear the ALT_I2C_DMA_TDLR_DMATDL register field value. */ -#define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0 -/* The reset value of the ALT_I2C_DMA_TDLR_DMATDL register field. */ -#define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0 -/* Extracts the ALT_I2C_DMA_TDLR_DMATDL field value from a register. */ -#define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0) -/* Produces a ALT_I2C_DMA_TDLR_DMATDL register field value suitable for setting the register. */ -#define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_DMA_TDLR. - */ -struct ALT_I2C_DMA_TDLR_s -{ - uint32_t dmatdl : 6; /* DMA Transmit Data Level Bit */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_DMA_TDLR. */ -typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_DMA_TDLR register from the beginning of the component. */ -#define ALT_I2C_DMA_TDLR_OFST 0x8c -/* The address of the ALT_I2C_DMA_TDLR register. */ -#define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST)) - -/* - * Register : Receive Data Level - ic_dma_rdlr - * - * DMA Control Signals Interface. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------ - * [5:0] | RW | 0x0 | Receive Data Level Bits - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Receive Data Level Bits - dmardl - * - * This bit field controls the level at which a DMA request is made by the receive - * logic. The watermark level \= DMARDL+1; that is, dma_rx_req is generated when - * the number of valid data entries in the receive FIFO is equal to or more than - * this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then - * dma_rx_req is asserted when or more data entries are present in the receive - * FIFO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ -#define ALT_I2C_DMA_RDLR_DMARDL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */ -#define ALT_I2C_DMA_RDLR_DMARDL_MSB 5 -/* The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field. */ -#define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6 -/* The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value. */ -#define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f -/* The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value. */ -#define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0 -/* The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field. */ -#define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0 -/* Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register. */ -#define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0) -/* Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register. */ -#define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_DMA_RDLR. - */ -struct ALT_I2C_DMA_RDLR_s -{ - uint32_t dmardl : 6; /* Receive Data Level Bits */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_DMA_RDLR. */ -typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component. */ -#define ALT_I2C_DMA_RDLR_OFST 0x90 -/* The address of the ALT_I2C_DMA_RDLR register. */ -#define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST)) - -/* - * Register : SDA Setup Register - ic_sda_setup - * - * This register controls the amount of time delay (in terms of number of l4_sp_clk - * clock periods) introduced in the rising edge of SCL relative to SDA changing by - * holding SCL low when I2C services a read request while operating as a slave- - * transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the - * I2C Bus Specification. This register must be programmed with a value equal to or - * greater than 2. - * - * Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * - * (l4_sp_clk)], so if the user requires 10 l4_sp_clk periods of setup time, they - * should program a value of 11. The IC_SDA_SETUP register is only used by the I2C - * when operating as a slave transmitter. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------- - * [7:0] | RW | 0x64 | SDA Setup Value - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : SDA Setup Value - sda_setup - * - * It is recommended that if the required delay is 1000ns, then for an l4_sp_clk - * frequency of 10 MHz, ic_sda_setup should be programmed to a value of 11. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ -#define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ -#define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7 -/* The width in bits of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ -#define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8 -/* The mask used to set the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ -#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff -/* The mask used to clear the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */ -#define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00 -/* The reset value of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */ -#define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64 -/* Extracts the ALT_I2C_SDA_SETUP_SDA_SETUP field value from a register. */ -#define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_I2C_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */ -#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_SDA_SETUP. - */ -struct ALT_I2C_SDA_SETUP_s -{ - uint32_t sda_setup : 8; /* SDA Setup Value */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_SDA_SETUP. */ -typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_SDA_SETUP register from the beginning of the component. */ -#define ALT_I2C_SDA_SETUP_OFST 0x94 -/* The address of the ALT_I2C_SDA_SETUP register. */ -#define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST)) - -/* - * Register : ACK General Call - ic_ack_general_call - * - * The register controls whether i2c responds with a ACK or NACK when it receives - * an I2C General Call address. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------- - * [0] | RW | 0x1 | ACK General Call Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : ACK General Call Bit - ack_gen_call - * - * When an ACK is asserted, (by asserting i2c_out_data) when it receives a General - * call. Otherwise, i2c responds with a NACK (by negating i2c_out_data). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------|:------|:------------------------- - * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK | 0x0 | I2C responds with a NACK - * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK | 0x1 | I2C responds with an ACK - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL - * - * I2C responds with a NACK - */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0 -/* - * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL - * - * I2C responds with an ACK - */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 -/* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1 -/* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 -/* Extracts the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */ -#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_ACK_GENERAL_CALL. - */ -struct ALT_I2C_ACK_GENERAL_CALL_s -{ - uint32_t ack_gen_call : 1; /* ACK General Call Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_ACK_GENERAL_CALL. */ -typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_ACK_GENERAL_CALL register from the beginning of the component. */ -#define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98 -/* The address of the ALT_I2C_ACK_GENERAL_CALL register. */ -#define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST)) - -/* - * Register : Enable Status Register - ic_enable_status - * - * This register is used to report the i2c hardware status when the IC_ENABLE - * register is set from 1 to 0; that is, when i2c is disabled. If IC_ENABLE has - * been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE - * has been set to 0, bits 2:1 are only valid as soon as bit 0 is read as '0'. - * - * Note: When ic_enable has been written with '0' a delay occurs for bit 0 to be - * read as '0' because disabling the i2c depends on I2C bus activities. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [0] | R | 0x0 | Enable Status Bit - * [1] | R | 0x0 | Slave Disabled While Busy Bit - * [2] | R | 0x0 | Slave Received Data Lost Bit - * [31:3] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Enable Status Bit - ic_en - * - * This bit always reflects the value driven on the output port ic_en. Not used in - * current application. When read as 1, i2c is deemed to be in an enabled state. - * When read as 0, i2c is deemed completely inactive. NOTE: The CPU can safely read - * this bit anytime. When this bit is read as 0, the CPU can safely read - * slv_rx_data_lost (bit 2) and slv_disabled_while_busy (bit 1). - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ -#define ALT_I2C_EN_STAT_IC_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */ -#define ALT_I2C_EN_STAT_IC_EN_MSB 0 -/* The width in bits of the ALT_I2C_EN_STAT_IC_EN register field. */ -#define ALT_I2C_EN_STAT_IC_EN_WIDTH 1 -/* The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value. */ -#define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value. */ -#define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_I2C_EN_STAT_IC_EN register field. */ -#define ALT_I2C_EN_STAT_IC_EN_RESET 0x0 -/* Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register. */ -#define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register. */ -#define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Slave Disabled While Busy Bit - slv_disabled_while_busy - * - * This bit indicates if a potential or active Slave operation has been aborted due - * to the setting of the ic_enable register from 1 to 0. This bit is set when the - * CPU writes a 0 to the ic_enable register while: (a) I2C is receiving the address - * byte of the Slave-Transmitter operation from a remote master; OR, (b) address - * and data bytes of the Slave-Receiver operation from a remote master. When read - * as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, - * irrespective of whether the I2C address matches the slave address set in i2c - * (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 - * but has not taken effect. NOTE: If the remote I2C master terminates the transfer - * with a STOP condition before the i2c has a chance to NACK a transfer, and - * IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as - * 0, i2c is deemed to have been disabled when there is master activity, or when - * the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) - * is read as 0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ -#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ -#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1 -/* The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ -#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1 -/* The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ -#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002 -/* The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */ -#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd -/* The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */ -#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0 -/* Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register. */ -#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register. */ -#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Slave Received Data Lost Bit - slv_rx_data_lost - * - * This bit indicates if a Slave-Receiver operation has been aborted with at least - * one data byte received from an I2C transfer due to the setting of IC ENABLE from - * 1 to 0. When read as 1, i2c is deemed to have been actively engaged in an - * aborted I2C transfer (with matching address) and the data phase of the I2C - * transfer has been entered, even though a data byte has been responded with a - * NACK. NOTE: If the remote I2C master terminates the transfer with a STOP - * condition before the i2c has a chance to NACK a transfer, and ic_enable has been - * set to 0, then this bit is also set to 1. When read as 0, i2c is deemed to have - * been disabled without being actively involved in the data phase of a Slave- - * Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is - * read as 0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ -#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ -#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2 -/* The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ -#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1 -/* The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ -#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004 -/* The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */ -#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb -/* The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */ -#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0 -/* Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register. */ -#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register. */ -#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_EN_STAT. - */ -struct ALT_I2C_EN_STAT_s -{ - const uint32_t ic_en : 1; /* Enable Status Bit */ - const uint32_t slv_disabled_while_busy : 1; /* Slave Disabled While Busy Bit */ - const uint32_t slv_rx_data_lost : 1; /* Slave Received Data Lost Bit */ - uint32_t : 29; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_EN_STAT. */ -typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component. */ -#define ALT_I2C_EN_STAT_OFST 0x9c -/* The address of the ALT_I2C_EN_STAT register. */ -#define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST)) - -/* - * Register : SS and FS Spike Suppression Limit Register - ic_fs_spklen - * - * This register is used to store the duration, measured in ic_clk cycles, of the - * longest spike that is filtered out by the spike suppression logic when the - * component is operating in SS or FS modes. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [7:0] | RW | 0x2 | Spike Suppression Limit Register - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Spike Suppression Limit Register - spklen - * - * This register must be set before any I2C bus transaction can take place to - * ensure stable operation. This register sets the duration, measured in ic_clk - * cycles, of the longest spike in the SCL or SDA lines that are filtered out by - * the spike suppression logic. This register can be written only when the I2C - * interface is disabled, which corresponds to the IC_ENABLE register being set to - * 0. Writes at other times have no effect. The minimum valid value is 1; hardware - * prevents values less than this being written, and if attempted results in 2 - * being set. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ -#define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ -#define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7 -/* The width in bits of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ -#define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8 -/* The mask used to set the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ -#define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff -/* The mask used to clear the ALT_I2C_FS_SPKLEN_SPKLEN register field value. */ -#define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00 -/* The reset value of the ALT_I2C_FS_SPKLEN_SPKLEN register field. */ -#define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2 -/* Extracts the ALT_I2C_FS_SPKLEN_SPKLEN field value from a register. */ -#define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_I2C_FS_SPKLEN_SPKLEN register field value suitable for setting the register. */ -#define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_FS_SPKLEN. - */ -struct ALT_I2C_FS_SPKLEN_s -{ - uint32_t spklen : 8; /* Spike Suppression Limit Register */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_FS_SPKLEN. */ -typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_FS_SPKLEN register from the beginning of the component. */ -#define ALT_I2C_FS_SPKLEN_OFST 0xa0 -/* The address of the ALT_I2C_FS_SPKLEN register. */ -#define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST)) - -/* - * Register : Component Parameter Register 1 - ic_comp_param_1 - * - * This is a constant read-only register that contains encoded information about - * the component's parameter settings. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [1:0] | R | 0x2 | APB Data Width Register - * [3:2] | R | 0x2 | Max Speed Mode - * [4] | R | 0x0 | CNT Registers Access - * [5] | R | 0x1 | Intr IO - * [6] | R | 0x1 | Has DMA - * [7] | R | 0x1 | Add Encoded Params - * [15:8] | R | 0x3f | Rx Buffer Depth - * [23:16] | R | 0x3f | Tx Buffer Depth - * [31:24] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : APB Data Width Register - apb_data_width - * - * Sets the APB Data Width. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------------|:------|:-------------------------- - * ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH - * - * APB Data Width is 32 Bits - */ -#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ -#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ -#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 -/* The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ -#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2 -/* The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ -#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003 -/* The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */ -#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc -/* The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */ -#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2 -/* Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */ -#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */ -#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : Max Speed Mode - max_speed_mode - * - * The value of this field determines the maximum i2c bus interface speed. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:----------------------- - * ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST | 0x2 | Fast Mode (400 kbit/s) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD - * - * Fast Mode (400 kbit/s) - */ -#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ -#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ -#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3 -/* The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ -#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2 -/* The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ -#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c -/* The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */ -#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3 -/* The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */ -#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2 -/* Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register. */ -#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2) -/* Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register. */ -#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c) - -/* - * Field : CNT Registers Access - hc_count_values - * - * This makes the *CNT registers readable and writable. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:-------------------------- - * ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR | 0x0 | *CNT registers read/write - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES - * - * * CNT registers read/write - */ -#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ -#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ -#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 -/* The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ -#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1 -/* The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ -#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010 -/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */ -#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef -/* The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */ -#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 -/* Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */ -#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */ -#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Intr IO - intr_io - * - * All interrupt sources are combined in to a single output. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:-------------------------- - * ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | Combined Interrupt Output - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO - * - * Combined Interrupt Output - */ -#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ -#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ -#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5 -/* The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ -#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1 -/* The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ -#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020 -/* The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */ -#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf -/* The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */ -#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1 -/* Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register. */ -#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */ -#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Has DMA - has_dma - * - * This configures the inclusion of DMA handshaking interface signals. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:------------ - * ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT | 0x1 | Has DMA - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA - * - * Has DMA - */ -#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ -#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ -#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6 -/* The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ -#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1 -/* The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ -#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040 -/* The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */ -#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf -/* The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */ -#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1 -/* Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register. */ -#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */ -#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Add Encoded Params - add_encoded_params - * - * By adding in the encoded parameters, this gives firmware an easy and quick way - * of identifying the DesignWare component within an I/O memory map. Some critical - * design-time options determine how a driver should interact with the peripheral. - * There is a minimal area overhead by including these parameters. Allows a single - * driver to be developed for each component which will be self-configurable. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------------|:------|:------------------- - * ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Add Encoded Params - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS - * - * Add Encoded Params - */ -#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ -#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ -#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7 -/* The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ -#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1 -/* The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ -#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080 -/* The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */ -#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f -/* The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */ -#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1 -/* Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register. */ -#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register. */ -#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : Rx Buffer Depth - rx_buffer_depth - * - * Sets Rx FIFO Depth. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------------|:------|:------------------------- - * ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Rx Fifo Depth 64 Entries - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH - * - * Rx Fifo Depth 64 Entries - */ -#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ -#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ -#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15 -/* The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ -#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8 -/* The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ -#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00 -/* The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */ -#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff -/* The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */ -#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f -/* Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register. */ -#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8) -/* Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register. */ -#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00) - -/* - * Field : Tx Buffer Depth - tx_buffer_depth - * - * Sets Tx FIFO Depth. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------------|:------|:--------------------------- - * ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Tx Buffer Depth 64 Entries - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH - * - * Tx Buffer Depth 64 Entries - */ -#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40 - -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ -#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ -#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23 -/* The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ -#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8 -/* The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ -#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000 -/* The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */ -#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff -/* The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */ -#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f -/* Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register. */ -#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16) -/* Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register. */ -#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_COMP_PARAM_1. - */ -struct ALT_I2C_COMP_PARAM_1_s -{ - const uint32_t apb_data_width : 2; /* APB Data Width Register */ - const uint32_t max_speed_mode : 2; /* Max Speed Mode */ - const uint32_t hc_count_values : 1; /* CNT Registers Access */ - const uint32_t intr_io : 1; /* Intr IO */ - const uint32_t has_dma : 1; /* Has DMA */ - const uint32_t add_encoded_params : 1; /* Add Encoded Params */ - const uint32_t rx_buffer_depth : 8; /* Rx Buffer Depth */ - const uint32_t tx_buffer_depth : 8; /* Tx Buffer Depth */ - uint32_t : 8; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_I2C_COMP_PARAM_1. */ -typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component. */ -#define ALT_I2C_COMP_PARAM_1_OFST 0xf4 -/* The address of the ALT_I2C_COMP_PARAM_1 register. */ -#define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST)) - -/* - * Register : Component Version Register - ic_comp_version - * - * Describes the version of the I2C - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:-----------|:-------------------------- - * [31:0] | R | 0x3132302a | Component Parameter Value - * - */ -/* - * Field : Component Parameter Value - ic_comp_version - * - * Specifies I2C release number (encoded as 4 ASCII characters) - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------|:-----------|:-------------- - * ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A | 0x3132302a | Version 1.20a - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_I2C_COMP_VER_IC_COMP_VER - * - * Version 1.20a - */ -#define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a - -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ -#define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ -#define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31 -/* The width in bits of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ -#define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32 -/* The mask used to set the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ -#define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff -/* The mask used to clear the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */ -#define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000 -/* The reset value of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */ -#define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a -/* Extracts the ALT_I2C_COMP_VER_IC_COMP_VER field value from a register. */ -#define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_I2C_COMP_VER_IC_COMP_VER register field value suitable for setting the register. */ -#define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_COMP_VER. - */ -struct ALT_I2C_COMP_VER_s -{ - const uint32_t ic_comp_version : 32; /* Component Parameter Value */ -}; - -/* The typedef declaration for register ALT_I2C_COMP_VER. */ -typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_COMP_VER register from the beginning of the component. */ -#define ALT_I2C_COMP_VER_OFST 0xf8 -/* The address of the ALT_I2C_COMP_VER register. */ -#define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST)) - -/* - * Register : Component Type Register - ic_comp_type - * - * Describes a unique ASCII value - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:-----------|:---------------------- - * [31:0] | R | 0x44570140 | Component Type Number - * - */ -/* - * Field : Component Type Number - ic_comp_type - * - * Designware Component Type number = 0x44_57_01_40. This assigned unique hex value - * is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit - * unsigned number. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ -#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ -#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31 -/* The width in bits of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ -#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32 -/* The mask used to set the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ -#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */ -#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000 -/* The reset value of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */ -#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 -/* Extracts the ALT_I2C_COMP_TYPE_IC_COMP_TYPE field value from a register. */ -#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */ -#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_I2C_COMP_TYPE. - */ -struct ALT_I2C_COMP_TYPE_s -{ - const uint32_t ic_comp_type : 32; /* Component Type Number */ -}; - -/* The typedef declaration for register ALT_I2C_COMP_TYPE. */ -typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_I2C_COMP_TYPE register from the beginning of the component. */ -#define ALT_I2C_COMP_TYPE_OFST 0xfc -/* The address of the ALT_I2C_COMP_TYPE register. */ -#define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_I2C. - */ -struct ALT_I2C_s -{ - volatile ALT_I2C_CON_t ic_con; /* ALT_I2C_CON */ - volatile ALT_I2C_TAR_t ic_tar; /* ALT_I2C_TAR */ - volatile ALT_I2C_SAR_t ic_sar; /* ALT_I2C_SAR */ - volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ - volatile ALT_I2C_DATA_CMD_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ - volatile ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ - volatile ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ - volatile ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ - volatile ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ - volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ - volatile ALT_I2C_INTR_STAT_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ - volatile ALT_I2C_INTR_MSK_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ - volatile ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ - volatile ALT_I2C_RX_TL_t ic_rx_tl; /* ALT_I2C_RX_TL */ - volatile ALT_I2C_TX_TL_t ic_tx_tl; /* ALT_I2C_TX_TL */ - volatile ALT_I2C_CLR_INTR_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ - volatile ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ - volatile ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ - volatile ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ - volatile ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ - volatile ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ - volatile ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ - volatile ALT_I2C_CLR_ACTIVITY_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ - volatile ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ - volatile ALT_I2C_CLR_START_DET_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ - volatile ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ - volatile ALT_I2C_EN_t ic_enable; /* ALT_I2C_EN */ - volatile ALT_I2C_STAT_t ic_status; /* ALT_I2C_STAT */ - volatile ALT_I2C_TXFLR_t ic_txflr; /* ALT_I2C_TXFLR */ - volatile ALT_I2C_RXFLR_t ic_rxflr; /* ALT_I2C_RXFLR */ - volatile ALT_I2C_SDA_HOLD_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ - volatile ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ - volatile ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ - volatile ALT_I2C_DMA_CR_t ic_dma_cr; /* ALT_I2C_DMA_CR */ - volatile ALT_I2C_DMA_TDLR_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ - volatile ALT_I2C_DMA_RDLR_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ - volatile ALT_I2C_SDA_SETUP_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ - volatile ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ - volatile ALT_I2C_EN_STAT_t ic_enable_status; /* ALT_I2C_EN_STAT */ - volatile ALT_I2C_FS_SPKLEN_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ - volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ - volatile ALT_I2C_COMP_PARAM_1_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ - volatile ALT_I2C_COMP_VER_t ic_comp_version; /* ALT_I2C_COMP_VER */ - volatile ALT_I2C_COMP_TYPE_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ -}; - -/* The typedef declaration for register group ALT_I2C. */ -typedef volatile struct ALT_I2C_s ALT_I2C_t; -/* The struct declaration for the raw register contents of register group ALT_I2C. */ -struct ALT_I2C_raw_s -{ - volatile uint32_t ic_con; /* ALT_I2C_CON */ - volatile uint32_t ic_tar; /* ALT_I2C_TAR */ - volatile uint32_t ic_sar; /* ALT_I2C_SAR */ - volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ - volatile uint32_t ic_data_cmd; /* ALT_I2C_DATA_CMD */ - volatile uint32_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */ - volatile uint32_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */ - volatile uint32_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */ - volatile uint32_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */ - volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */ - volatile uint32_t ic_intr_stat; /* ALT_I2C_INTR_STAT */ - volatile uint32_t ic_intr_mask; /* ALT_I2C_INTR_MSK */ - volatile uint32_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */ - volatile uint32_t ic_rx_tl; /* ALT_I2C_RX_TL */ - volatile uint32_t ic_tx_tl; /* ALT_I2C_TX_TL */ - volatile uint32_t ic_clr_intr; /* ALT_I2C_CLR_INTR */ - volatile uint32_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */ - volatile uint32_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */ - volatile uint32_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */ - volatile uint32_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */ - volatile uint32_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */ - volatile uint32_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */ - volatile uint32_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */ - volatile uint32_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */ - volatile uint32_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */ - volatile uint32_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */ - volatile uint32_t ic_enable; /* ALT_I2C_EN */ - volatile uint32_t ic_status; /* ALT_I2C_STAT */ - volatile uint32_t ic_txflr; /* ALT_I2C_TXFLR */ - volatile uint32_t ic_rxflr; /* ALT_I2C_RXFLR */ - volatile uint32_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */ - volatile uint32_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */ - volatile uint32_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */ - volatile uint32_t ic_dma_cr; /* ALT_I2C_DMA_CR */ - volatile uint32_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */ - volatile uint32_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */ - volatile uint32_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */ - volatile uint32_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */ - volatile uint32_t ic_enable_status; /* ALT_I2C_EN_STAT */ - volatile uint32_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */ - volatile uint32_t _pad_0xa4_0xf3[20]; /* *UNDEFINED* */ - volatile uint32_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */ - volatile uint32_t ic_comp_version; /* ALT_I2C_COMP_VER */ - volatile uint32_t ic_comp_type; /* ALT_I2C_COMP_TYPE */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_I2C. */ -typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_I2C_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_l3.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_l3.h deleted file mode 100644 index 12e6f21b89..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_l3.h +++ /dev/null @@ -1,6299 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_L3 */ - -#ifndef __ALTERA_ALT_L3_H__ -#define __ALTERA_ALT_L3_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : L3 (NIC-301) GPV Registers - ALT_L3 - * L3 (NIC-301) GPV Registers - * - * Registers to control L3 interconnect settings - * - */ -/* - * Register : Remap - remap - * - * The L3 interconnect has separate address maps for the various L3 Masters. - * Generally, the addresses are the same for most masters. However, the sparse - * interconnect of the L3 switch causes some masters to have holes in their memory - * maps. The remap bits are not mutually exclusive. Each bit can be set - * independently and in combinations. Priority for the bits is determined by the - * bit offset: lower offset bits take precedence over higher offset bits. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [0] | W | 0x0 | MPU at 0x0 - * [1] | W | 0x0 | Non-MPU at 0x0 - * [2] | ??? | 0x0 | *UNDEFINED* - * [3] | W | 0x0 | HPS2FPGA AXI Bridge Visibility - * [4] | W | 0x0 | LWHPS2FPGA AXI Bridge Visibility - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : MPU at 0x0 - mpuzero - * - * Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or - * On-chip RAM. This field only has an effect on the MPU L3 master. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------|:------|:------------------------------------------------- - * ALT_L3_REMAP_MPUZERO_E_BOOTROM | 0x0 | Maps the Boot ROM to address 0x0 for the MPU L3 - * : | | master. Note that the Boot ROM is also always - * : | | mapped to address 0xfffd_0000 for the MPU L3 - * : | | master independent of this field's value. - * ALT_L3_REMAP_MPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the MPU - * : | | L3 master. Note that the On-chip RAM is also - * : | | always mapped to address 0xffff_0000 for the MPU - * : | | L3 master independent of this field's value. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_REMAP_MPUZERO - * - * Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM - * is also always mapped to address 0xfffd_0000 for the MPU L3 master independent - * of this field's value. - */ -#define ALT_L3_REMAP_MPUZERO_E_BOOTROM 0x0 -/* - * Enumerated value for register field ALT_L3_REMAP_MPUZERO - * - * Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip - * RAM is also always mapped to address 0xffff_0000 for the MPU L3 master - * independent of this field's value. - */ -#define ALT_L3_REMAP_MPUZERO_E_OCRAM 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_MPUZERO register field. */ -#define ALT_L3_REMAP_MPUZERO_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_MPUZERO register field. */ -#define ALT_L3_REMAP_MPUZERO_MSB 0 -/* The width in bits of the ALT_L3_REMAP_MPUZERO register field. */ -#define ALT_L3_REMAP_MPUZERO_WIDTH 1 -/* The mask used to set the ALT_L3_REMAP_MPUZERO register field value. */ -#define ALT_L3_REMAP_MPUZERO_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_REMAP_MPUZERO register field value. */ -#define ALT_L3_REMAP_MPUZERO_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_REMAP_MPUZERO register field. */ -#define ALT_L3_REMAP_MPUZERO_RESET 0x0 -/* Extracts the ALT_L3_REMAP_MPUZERO field value from a register. */ -#define ALT_L3_REMAP_MPUZERO_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_REMAP_MPUZERO register field value suitable for setting the register. */ -#define ALT_L3_REMAP_MPUZERO_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Non-MPU at 0x0 - nonmpuzero - * - * Controls whether address 0x0 for the non-MPU L3 masters is mapped to the SDRAM - * or On-chip RAM. This field only has an effect on the non-MPU L3 masters. The - * non-MPU L3 masters are the DMA controllers (standalone and those built-in to - * peripherals), the FPGA2HPS AXI Bridge, and the DAP. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------|:------|:------------------------------------------------- - * ALT_L3_REMAP_NONMPUZERO_E_SDRAM | 0x0 | Maps the SDRAM to address 0x0 for the non-MPU L3 - * : | | masters. - * ALT_L3_REMAP_NONMPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the non- - * : | | MPU L3 masters. Note that the On-chip RAM is - * : | | also always mapped to address 0xffff_0000 for - * : | | the non-MPU L3 masters independent of this - * : | | field's value. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO - * - * Maps the SDRAM to address 0x0 for the non-MPU L3 masters. - */ -#define ALT_L3_REMAP_NONMPUZERO_E_SDRAM 0x0 -/* - * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO - * - * Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the - * On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3 - * masters independent of this field's value. - */ -#define ALT_L3_REMAP_NONMPUZERO_E_OCRAM 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */ -#define ALT_L3_REMAP_NONMPUZERO_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */ -#define ALT_L3_REMAP_NONMPUZERO_MSB 1 -/* The width in bits of the ALT_L3_REMAP_NONMPUZERO register field. */ -#define ALT_L3_REMAP_NONMPUZERO_WIDTH 1 -/* The mask used to set the ALT_L3_REMAP_NONMPUZERO register field value. */ -#define ALT_L3_REMAP_NONMPUZERO_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_REMAP_NONMPUZERO register field value. */ -#define ALT_L3_REMAP_NONMPUZERO_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_REMAP_NONMPUZERO register field. */ -#define ALT_L3_REMAP_NONMPUZERO_RESET 0x0 -/* Extracts the ALT_L3_REMAP_NONMPUZERO field value from a register. */ -#define ALT_L3_REMAP_NONMPUZERO_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_REMAP_NONMPUZERO register field value suitable for setting the register. */ -#define ALT_L3_REMAP_NONMPUZERO_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : HPS2FPGA AXI Bridge Visibility - hps2fpga - * - * Controls whether the HPS2FPGA AXI Bridge is visible to L3 masters or not. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:------------------------------------------------ - * ALT_L3_REMAP_H2F_E_INVISIBLE | 0x0 | The HPS2FPGA AXI Bridge is not visible to L3 - * : | | masters. Accesses to the associated address - * : | | range return an AXI decode error to the master. - * ALT_L3_REMAP_H2F_E_VISIBLE | 0x1 | The HPS2FPGA AXI Bridge is visible to L3 - * : | | masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_REMAP_H2F - * - * The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated - * address range return an AXI decode error to the master. - */ -#define ALT_L3_REMAP_H2F_E_INVISIBLE 0x0 -/* - * Enumerated value for register field ALT_L3_REMAP_H2F - * - * The HPS2FPGA AXI Bridge is visible to L3 masters. - */ -#define ALT_L3_REMAP_H2F_E_VISIBLE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_H2F register field. */ -#define ALT_L3_REMAP_H2F_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_H2F register field. */ -#define ALT_L3_REMAP_H2F_MSB 3 -/* The width in bits of the ALT_L3_REMAP_H2F register field. */ -#define ALT_L3_REMAP_H2F_WIDTH 1 -/* The mask used to set the ALT_L3_REMAP_H2F register field value. */ -#define ALT_L3_REMAP_H2F_SET_MSK 0x00000008 -/* The mask used to clear the ALT_L3_REMAP_H2F register field value. */ -#define ALT_L3_REMAP_H2F_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_L3_REMAP_H2F register field. */ -#define ALT_L3_REMAP_H2F_RESET 0x0 -/* Extracts the ALT_L3_REMAP_H2F field value from a register. */ -#define ALT_L3_REMAP_H2F_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_L3_REMAP_H2F register field value suitable for setting the register. */ -#define ALT_L3_REMAP_H2F_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : LWHPS2FPGA AXI Bridge Visibility - lwhps2fpga - * - * Controls whether the Lightweight HPS2FPGA AXI Bridge is visible to L3 masters or - * not. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------|:------|:------------------------------------------------ - * ALT_L3_REMAP_LWH2F_E_INVISIBLE | 0x0 | The LWHPS2FPGA AXI Bridge is not visible to L3 - * : | | masters. Accesses to the associated address - * : | | range return an AXI decode error to the master. - * ALT_L3_REMAP_LWH2F_E_VISIBLE | 0x1 | The LWHPS2FPGA AXI Bridge is visible to L3 - * : | | masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_REMAP_LWH2F - * - * The LWHPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the - * associated address range return an AXI decode error to the master. - */ -#define ALT_L3_REMAP_LWH2F_E_INVISIBLE 0x0 -/* - * Enumerated value for register field ALT_L3_REMAP_LWH2F - * - * The LWHPS2FPGA AXI Bridge is visible to L3 masters. - */ -#define ALT_L3_REMAP_LWH2F_E_VISIBLE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_LWH2F register field. */ -#define ALT_L3_REMAP_LWH2F_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_LWH2F register field. */ -#define ALT_L3_REMAP_LWH2F_MSB 4 -/* The width in bits of the ALT_L3_REMAP_LWH2F register field. */ -#define ALT_L3_REMAP_LWH2F_WIDTH 1 -/* The mask used to set the ALT_L3_REMAP_LWH2F register field value. */ -#define ALT_L3_REMAP_LWH2F_SET_MSK 0x00000010 -/* The mask used to clear the ALT_L3_REMAP_LWH2F register field value. */ -#define ALT_L3_REMAP_LWH2F_CLR_MSK 0xffffffef -/* The reset value of the ALT_L3_REMAP_LWH2F register field. */ -#define ALT_L3_REMAP_LWH2F_RESET 0x0 -/* Extracts the ALT_L3_REMAP_LWH2F field value from a register. */ -#define ALT_L3_REMAP_LWH2F_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_L3_REMAP_LWH2F register field value suitable for setting the register. */ -#define ALT_L3_REMAP_LWH2F_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_REMAP. - */ -struct ALT_L3_REMAP_s -{ - uint32_t mpuzero : 1; /* MPU at 0x0 */ - uint32_t nonmpuzero : 1; /* Non-MPU at 0x0 */ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t hps2fpga : 1; /* HPS2FPGA AXI Bridge Visibility */ - uint32_t lwhps2fpga : 1; /* LWHPS2FPGA AXI Bridge Visibility */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_REMAP. */ -typedef volatile struct ALT_L3_REMAP_s ALT_L3_REMAP_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_REMAP register from the beginning of the component. */ -#define ALT_L3_REMAP_OFST 0x0 - -/* - * Register Group : Security Register Group - ALT_L3_SECGRP - * Security Register Group - * - * Registers that control slave security. - * - */ -/* - * Register : L4 Main Peripherals Security - l4main - * - * Controls security settings for L4 Main peripherals. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------ - * [0] | W | 0x0 | SPI Slave 0 Security - * [1] | W | 0x0 | SPI Slave 1 Security - * [2] | W | 0x0 | DMA Secure Security - * [3] | W | 0x0 | DMA Non-secure Security - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : SPI Slave 0 Security - spis0 - * - * Controls whether secure or non-secure masters can access the SPI Slave 0 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ -#define ALT_L3_SEC_L4MAIN_SPIS0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ -#define ALT_L3_SEC_L4MAIN_SPIS0_MSB 0 -/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ -#define ALT_L3_SEC_L4MAIN_SPIS0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */ -#define ALT_L3_SEC_L4MAIN_SPIS0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */ -#define ALT_L3_SEC_L4MAIN_SPIS0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */ -#define ALT_L3_SEC_L4MAIN_SPIS0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MAIN_SPIS0 field value from a register. */ -#define ALT_L3_SEC_L4MAIN_SPIS0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_L4MAIN_SPIS0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MAIN_SPIS0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : SPI Slave 1 Security - spis1 - * - * Controls whether secure or non-secure masters can access the SPI Slave 1 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ -#define ALT_L3_SEC_L4MAIN_SPIS1_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ -#define ALT_L3_SEC_L4MAIN_SPIS1_MSB 1 -/* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ -#define ALT_L3_SEC_L4MAIN_SPIS1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */ -#define ALT_L3_SEC_L4MAIN_SPIS1_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */ -#define ALT_L3_SEC_L4MAIN_SPIS1_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */ -#define ALT_L3_SEC_L4MAIN_SPIS1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MAIN_SPIS1 field value from a register. */ -#define ALT_L3_SEC_L4MAIN_SPIS1_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_SEC_L4MAIN_SPIS1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MAIN_SPIS1_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : DMA Secure Security - dmasecure - * - * Controls whether secure or non-secure masters can access the DMA Secure slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_MSB 2 -/* The width in bits of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MAIN_DMASECURE field value from a register. */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_L3_SEC_L4MAIN_DMASECURE register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MAIN_DMASECURE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : DMA Non-secure Security - dmanonsecure - * - * Controls whether secure or non-secure masters can access the DMA Non-secure - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_MSB 3 -/* The width in bits of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET_MSK 0x00000008 -/* The mask used to clear the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MAIN_DMANONSECURE field value from a register. */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_L3_SEC_L4MAIN_DMANONSECURE register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET(value) (((value) << 3) & 0x00000008) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_L4MAIN. - */ -struct ALT_L3_SEC_L4MAIN_s -{ - uint32_t spis0 : 1; /* SPI Slave 0 Security */ - uint32_t spis1 : 1; /* SPI Slave 1 Security */ - uint32_t dmasecure : 1; /* DMA Secure Security */ - uint32_t dmanonsecure : 1; /* DMA Non-secure Security */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_L4MAIN. */ -typedef volatile struct ALT_L3_SEC_L4MAIN_s ALT_L3_SEC_L4MAIN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_L4MAIN register from the beginning of the component. */ -#define ALT_L3_SEC_L4MAIN_OFST 0x0 - -/* - * Register : L4 SP Peripherals Security - l4sp - * - * Controls security settings for L4 SP peripherals. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------- - * [0] | W | 0x0 | SDRAM Registers Security - * [1] | W | 0x0 | SP Timer 0 Security - * [2] | W | 0x0 | I2C0 Security - * [3] | W | 0x0 | I2C1 Security - * [4] | W | 0x0 | I2C2 (EMAC 0) Security - * [5] | W | 0x0 | I2C3 (EMAC 1) Security - * [6] | W | 0x0 | UART 0 Security - * [7] | W | 0x0 | UART 1 Security - * [8] | W | 0x0 | CAN 0 Security - * [9] | W | 0x0 | CAN 1 Security - * [10] | W | 0x0 | SP Timer 1 Security - * [31:11] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : SDRAM Registers Security - sdrregs - * - * Controls whether secure or non-secure masters can access the SDRAM Registers - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_SDRREGS_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */ -#define ALT_L3_SEC_L4SP_SDRREGS_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */ -#define ALT_L3_SEC_L4SP_SDRREGS_MSB 0 -/* The width in bits of the ALT_L3_SEC_L4SP_SDRREGS register field. */ -#define ALT_L3_SEC_L4SP_SDRREGS_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_SDRREGS register field value. */ -#define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_L4SP_SDRREGS register field value. */ -#define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_L4SP_SDRREGS register field. */ -#define ALT_L3_SEC_L4SP_SDRREGS_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_SDRREGS field value from a register. */ -#define ALT_L3_SEC_L4SP_SDRREGS_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_L4SP_SDRREGS register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_SDRREGS_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : SP Timer 0 Security - sptimer0 - * - * Controls whether secure or non-secure masters can access the SP Timer 0 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_SPTMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ -#define ALT_L3_SEC_L4SP_SPTMR0_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ -#define ALT_L3_SEC_L4SP_SPTMR0_MSB 1 -/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ -#define ALT_L3_SEC_L4SP_SPTMR0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR0 register field value. */ -#define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR0 register field value. */ -#define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_SEC_L4SP_SPTMR0 register field. */ -#define ALT_L3_SEC_L4SP_SPTMR0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_SPTMR0 field value from a register. */ -#define ALT_L3_SEC_L4SP_SPTMR0_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_SEC_L4SP_SPTMR0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_SPTMR0_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : I2C0 Security - i2c0 - * - * Controls whether secure or non-secure masters can access the I2C0 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_I2C0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_I2C0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_I2C0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */ -#define ALT_L3_SEC_L4SP_I2C0_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */ -#define ALT_L3_SEC_L4SP_I2C0_MSB 2 -/* The width in bits of the ALT_L3_SEC_L4SP_I2C0 register field. */ -#define ALT_L3_SEC_L4SP_I2C0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_I2C0 register field value. */ -#define ALT_L3_SEC_L4SP_I2C0_SET_MSK 0x00000004 -/* The mask used to clear the ALT_L3_SEC_L4SP_I2C0 register field value. */ -#define ALT_L3_SEC_L4SP_I2C0_CLR_MSK 0xfffffffb -/* The reset value of the ALT_L3_SEC_L4SP_I2C0 register field. */ -#define ALT_L3_SEC_L4SP_I2C0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_I2C0 field value from a register. */ -#define ALT_L3_SEC_L4SP_I2C0_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_L3_SEC_L4SP_I2C0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_I2C0_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : I2C1 Security - i2c1 - * - * Controls whether secure or non-secure masters can access the I2C1 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_I2C1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_I2C1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_I2C1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */ -#define ALT_L3_SEC_L4SP_I2C1_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */ -#define ALT_L3_SEC_L4SP_I2C1_MSB 3 -/* The width in bits of the ALT_L3_SEC_L4SP_I2C1 register field. */ -#define ALT_L3_SEC_L4SP_I2C1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_I2C1 register field value. */ -#define ALT_L3_SEC_L4SP_I2C1_SET_MSK 0x00000008 -/* The mask used to clear the ALT_L3_SEC_L4SP_I2C1 register field value. */ -#define ALT_L3_SEC_L4SP_I2C1_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_L3_SEC_L4SP_I2C1 register field. */ -#define ALT_L3_SEC_L4SP_I2C1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_I2C1 field value from a register. */ -#define ALT_L3_SEC_L4SP_I2C1_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_L3_SEC_L4SP_I2C1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_I2C1_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : I2C2 (EMAC 0) Security - i2c2 - * - * Controls whether secure or non-secure masters can access the I2C2 (EMAC 0) - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_I2C2_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_I2C2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_I2C2_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */ -#define ALT_L3_SEC_L4SP_I2C2_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */ -#define ALT_L3_SEC_L4SP_I2C2_MSB 4 -/* The width in bits of the ALT_L3_SEC_L4SP_I2C2 register field. */ -#define ALT_L3_SEC_L4SP_I2C2_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_I2C2 register field value. */ -#define ALT_L3_SEC_L4SP_I2C2_SET_MSK 0x00000010 -/* The mask used to clear the ALT_L3_SEC_L4SP_I2C2 register field value. */ -#define ALT_L3_SEC_L4SP_I2C2_CLR_MSK 0xffffffef -/* The reset value of the ALT_L3_SEC_L4SP_I2C2 register field. */ -#define ALT_L3_SEC_L4SP_I2C2_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_I2C2 field value from a register. */ -#define ALT_L3_SEC_L4SP_I2C2_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_L3_SEC_L4SP_I2C2 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_I2C2_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : I2C3 (EMAC 1) Security - i2c3 - * - * Controls whether secure or non-secure masters can access the I2C3 (EMAC 1) - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_I2C3_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_I2C3_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_I2C3_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */ -#define ALT_L3_SEC_L4SP_I2C3_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */ -#define ALT_L3_SEC_L4SP_I2C3_MSB 5 -/* The width in bits of the ALT_L3_SEC_L4SP_I2C3 register field. */ -#define ALT_L3_SEC_L4SP_I2C3_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_I2C3 register field value. */ -#define ALT_L3_SEC_L4SP_I2C3_SET_MSK 0x00000020 -/* The mask used to clear the ALT_L3_SEC_L4SP_I2C3 register field value. */ -#define ALT_L3_SEC_L4SP_I2C3_CLR_MSK 0xffffffdf -/* The reset value of the ALT_L3_SEC_L4SP_I2C3 register field. */ -#define ALT_L3_SEC_L4SP_I2C3_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_I2C3 field value from a register. */ -#define ALT_L3_SEC_L4SP_I2C3_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_L3_SEC_L4SP_I2C3 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_I2C3_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : UART 0 Security - uart0 - * - * Controls whether secure or non-secure masters can access the UART 0 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_UART0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_UART0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_UART0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_UART0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_UART0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_UART0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */ -#define ALT_L3_SEC_L4SP_UART0_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */ -#define ALT_L3_SEC_L4SP_UART0_MSB 6 -/* The width in bits of the ALT_L3_SEC_L4SP_UART0 register field. */ -#define ALT_L3_SEC_L4SP_UART0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_UART0 register field value. */ -#define ALT_L3_SEC_L4SP_UART0_SET_MSK 0x00000040 -/* The mask used to clear the ALT_L3_SEC_L4SP_UART0 register field value. */ -#define ALT_L3_SEC_L4SP_UART0_CLR_MSK 0xffffffbf -/* The reset value of the ALT_L3_SEC_L4SP_UART0 register field. */ -#define ALT_L3_SEC_L4SP_UART0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_UART0 field value from a register. */ -#define ALT_L3_SEC_L4SP_UART0_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_L3_SEC_L4SP_UART0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_UART0_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : UART 1 Security - uart1 - * - * Controls whether secure or non-secure masters can access the UART 1 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_UART1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_UART1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_UART1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_UART1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_UART1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_UART1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */ -#define ALT_L3_SEC_L4SP_UART1_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */ -#define ALT_L3_SEC_L4SP_UART1_MSB 7 -/* The width in bits of the ALT_L3_SEC_L4SP_UART1 register field. */ -#define ALT_L3_SEC_L4SP_UART1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_UART1 register field value. */ -#define ALT_L3_SEC_L4SP_UART1_SET_MSK 0x00000080 -/* The mask used to clear the ALT_L3_SEC_L4SP_UART1 register field value. */ -#define ALT_L3_SEC_L4SP_UART1_CLR_MSK 0xffffff7f -/* The reset value of the ALT_L3_SEC_L4SP_UART1 register field. */ -#define ALT_L3_SEC_L4SP_UART1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_UART1 field value from a register. */ -#define ALT_L3_SEC_L4SP_UART1_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_L3_SEC_L4SP_UART1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_UART1_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : CAN 0 Security - can0 - * - * Controls whether secure or non-secure masters can access the CAN 0 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_CAN0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_CAN0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_CAN0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */ -#define ALT_L3_SEC_L4SP_CAN0_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */ -#define ALT_L3_SEC_L4SP_CAN0_MSB 8 -/* The width in bits of the ALT_L3_SEC_L4SP_CAN0 register field. */ -#define ALT_L3_SEC_L4SP_CAN0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_CAN0 register field value. */ -#define ALT_L3_SEC_L4SP_CAN0_SET_MSK 0x00000100 -/* The mask used to clear the ALT_L3_SEC_L4SP_CAN0 register field value. */ -#define ALT_L3_SEC_L4SP_CAN0_CLR_MSK 0xfffffeff -/* The reset value of the ALT_L3_SEC_L4SP_CAN0 register field. */ -#define ALT_L3_SEC_L4SP_CAN0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_CAN0 field value from a register. */ -#define ALT_L3_SEC_L4SP_CAN0_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_L3_SEC_L4SP_CAN0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_CAN0_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : CAN 1 Security - can1 - * - * Controls whether secure or non-secure masters can access the CAN 1 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_CAN1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_CAN1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_CAN1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */ -#define ALT_L3_SEC_L4SP_CAN1_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */ -#define ALT_L3_SEC_L4SP_CAN1_MSB 9 -/* The width in bits of the ALT_L3_SEC_L4SP_CAN1 register field. */ -#define ALT_L3_SEC_L4SP_CAN1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_CAN1 register field value. */ -#define ALT_L3_SEC_L4SP_CAN1_SET_MSK 0x00000200 -/* The mask used to clear the ALT_L3_SEC_L4SP_CAN1 register field value. */ -#define ALT_L3_SEC_L4SP_CAN1_CLR_MSK 0xfffffdff -/* The reset value of the ALT_L3_SEC_L4SP_CAN1 register field. */ -#define ALT_L3_SEC_L4SP_CAN1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_CAN1 field value from a register. */ -#define ALT_L3_SEC_L4SP_CAN1_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_L3_SEC_L4SP_CAN1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_CAN1_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : SP Timer 1 Security - sptimer1 - * - * Controls whether secure or non-secure masters can access the SP Timer 1 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SP_SPTMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ -#define ALT_L3_SEC_L4SP_SPTMR1_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ -#define ALT_L3_SEC_L4SP_SPTMR1_MSB 10 -/* The width in bits of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ -#define ALT_L3_SEC_L4SP_SPTMR1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SP_SPTMR1 register field value. */ -#define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK 0x00000400 -/* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR1 register field value. */ -#define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK 0xfffffbff -/* The reset value of the ALT_L3_SEC_L4SP_SPTMR1 register field. */ -#define ALT_L3_SEC_L4SP_SPTMR1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SP_SPTMR1 field value from a register. */ -#define ALT_L3_SEC_L4SP_SPTMR1_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_L3_SEC_L4SP_SPTMR1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SP_SPTMR1_SET(value) (((value) << 10) & 0x00000400) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_L4SP. - */ -struct ALT_L3_SEC_L4SP_s -{ - uint32_t sdrregs : 1; /* SDRAM Registers Security */ - uint32_t sptimer0 : 1; /* SP Timer 0 Security */ - uint32_t i2c0 : 1; /* I2C0 Security */ - uint32_t i2c1 : 1; /* I2C1 Security */ - uint32_t i2c2 : 1; /* I2C2 (EMAC 0) Security */ - uint32_t i2c3 : 1; /* I2C3 (EMAC 1) Security */ - uint32_t uart0 : 1; /* UART 0 Security */ - uint32_t uart1 : 1; /* UART 1 Security */ - uint32_t can0 : 1; /* CAN 0 Security */ - uint32_t can1 : 1; /* CAN 1 Security */ - uint32_t sptimer1 : 1; /* SP Timer 1 Security */ - uint32_t : 21; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_L4SP. */ -typedef volatile struct ALT_L3_SEC_L4SP_s ALT_L3_SEC_L4SP_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_L4SP register from the beginning of the component. */ -#define ALT_L3_SEC_L4SP_OFST 0x4 - -/* - * Register : L4 MP Peripherals Security - l4mp - * - * Controls security settings for L4 MP peripherals. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------- - * [0] | W | 0x0 | FPGA Manager Register Security - * [1] | W | 0x0 | DAP Security - * [2] | W | 0x0 | QSPI Registers Security - * [3] | W | 0x0 | SDMMC Security - * [4] | W | 0x0 | EMAC 0 Security - * [5] | W | 0x0 | EMAC 1 Security - * [6] | W | 0x0 | ACP ID Mapper Security - * [7] | W | 0x0 | GPIO 0 Security - * [8] | W | 0x0 | GPIO 1 Security - * [9] | W | 0x0 | GPIO 2 Security - * [31:10] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : FPGA Manager Register Security - fpgamgrregs - * - * Controls whether secure or non-secure masters can access the FPGA Manager - * Register slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ -#define ALT_L3_SEC_L4MP_FPGAMGR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ -#define ALT_L3_SEC_L4MP_FPGAMGR_MSB 0 -/* The width in bits of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ -#define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_FPGAMGR register field value. */ -#define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_L4MP_FPGAMGR register field value. */ -#define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_L4MP_FPGAMGR register field. */ -#define ALT_L3_SEC_L4MP_FPGAMGR_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_FPGAMGR field value from a register. */ -#define ALT_L3_SEC_L4MP_FPGAMGR_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_L4MP_FPGAMGR register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_FPGAMGR_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : DAP Security - dap - * - * Controls whether secure or non-secure masters can access the DAP slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_DAP_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_DAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_DAP - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_DAP_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_DAP - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_DAP_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_DAP register field. */ -#define ALT_L3_SEC_L4MP_DAP_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_DAP register field. */ -#define ALT_L3_SEC_L4MP_DAP_MSB 1 -/* The width in bits of the ALT_L3_SEC_L4MP_DAP register field. */ -#define ALT_L3_SEC_L4MP_DAP_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_DAP register field value. */ -#define ALT_L3_SEC_L4MP_DAP_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_SEC_L4MP_DAP register field value. */ -#define ALT_L3_SEC_L4MP_DAP_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_SEC_L4MP_DAP register field. */ -#define ALT_L3_SEC_L4MP_DAP_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_DAP field value from a register. */ -#define ALT_L3_SEC_L4MP_DAP_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_SEC_L4MP_DAP register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_DAP_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : QSPI Registers Security - qspiregs - * - * Controls whether secure or non-secure masters can access the QSPI Registers - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_QSPI_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_QSPI_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_QSPI_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */ -#define ALT_L3_SEC_L4MP_QSPI_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */ -#define ALT_L3_SEC_L4MP_QSPI_MSB 2 -/* The width in bits of the ALT_L3_SEC_L4MP_QSPI register field. */ -#define ALT_L3_SEC_L4MP_QSPI_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_QSPI register field value. */ -#define ALT_L3_SEC_L4MP_QSPI_SET_MSK 0x00000004 -/* The mask used to clear the ALT_L3_SEC_L4MP_QSPI register field value. */ -#define ALT_L3_SEC_L4MP_QSPI_CLR_MSK 0xfffffffb -/* The reset value of the ALT_L3_SEC_L4MP_QSPI register field. */ -#define ALT_L3_SEC_L4MP_QSPI_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_QSPI field value from a register. */ -#define ALT_L3_SEC_L4MP_QSPI_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_L3_SEC_L4MP_QSPI register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_QSPI_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : SDMMC Security - sdmmc - * - * Controls whether secure or non-secure masters can access the SDMMC slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_SDMMC_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_SDMMC_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */ -#define ALT_L3_SEC_L4MP_SDMMC_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */ -#define ALT_L3_SEC_L4MP_SDMMC_MSB 3 -/* The width in bits of the ALT_L3_SEC_L4MP_SDMMC register field. */ -#define ALT_L3_SEC_L4MP_SDMMC_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_SDMMC register field value. */ -#define ALT_L3_SEC_L4MP_SDMMC_SET_MSK 0x00000008 -/* The mask used to clear the ALT_L3_SEC_L4MP_SDMMC register field value. */ -#define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_L3_SEC_L4MP_SDMMC register field. */ -#define ALT_L3_SEC_L4MP_SDMMC_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_SDMMC field value from a register. */ -#define ALT_L3_SEC_L4MP_SDMMC_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_L3_SEC_L4MP_SDMMC register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_SDMMC_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : EMAC 0 Security - emac0 - * - * Controls whether secure or non-secure masters can access the EMAC 0 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_EMAC0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_EMAC0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */ -#define ALT_L3_SEC_L4MP_EMAC0_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */ -#define ALT_L3_SEC_L4MP_EMAC0_MSB 4 -/* The width in bits of the ALT_L3_SEC_L4MP_EMAC0 register field. */ -#define ALT_L3_SEC_L4MP_EMAC0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_EMAC0 register field value. */ -#define ALT_L3_SEC_L4MP_EMAC0_SET_MSK 0x00000010 -/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC0 register field value. */ -#define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK 0xffffffef -/* The reset value of the ALT_L3_SEC_L4MP_EMAC0 register field. */ -#define ALT_L3_SEC_L4MP_EMAC0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_EMAC0 field value from a register. */ -#define ALT_L3_SEC_L4MP_EMAC0_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_L3_SEC_L4MP_EMAC0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_EMAC0_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : EMAC 1 Security - emac1 - * - * Controls whether secure or non-secure masters can access the EMAC 1 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_EMAC1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_EMAC1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */ -#define ALT_L3_SEC_L4MP_EMAC1_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */ -#define ALT_L3_SEC_L4MP_EMAC1_MSB 5 -/* The width in bits of the ALT_L3_SEC_L4MP_EMAC1 register field. */ -#define ALT_L3_SEC_L4MP_EMAC1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_EMAC1 register field value. */ -#define ALT_L3_SEC_L4MP_EMAC1_SET_MSK 0x00000020 -/* The mask used to clear the ALT_L3_SEC_L4MP_EMAC1 register field value. */ -#define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK 0xffffffdf -/* The reset value of the ALT_L3_SEC_L4MP_EMAC1 register field. */ -#define ALT_L3_SEC_L4MP_EMAC1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_EMAC1 field value from a register. */ -#define ALT_L3_SEC_L4MP_EMAC1_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_L3_SEC_L4MP_EMAC1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_EMAC1_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : ACP ID Mapper Security - acpidmap - * - * Controls whether secure or non-secure masters can access the ACP ID Mapper - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_MSB 6 -/* The width in bits of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK 0x00000040 -/* The mask used to clear the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK 0xffffffbf -/* The reset value of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_ACPIDMAP field value from a register. */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_L3_SEC_L4MP_ACPIDMAP register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_ACPIDMAP_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : GPIO 0 Security - gpio0 - * - * Controls whether secure or non-secure masters can access the GPIO 0 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_GPIO0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_GPIO0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */ -#define ALT_L3_SEC_L4MP_GPIO0_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */ -#define ALT_L3_SEC_L4MP_GPIO0_MSB 7 -/* The width in bits of the ALT_L3_SEC_L4MP_GPIO0 register field. */ -#define ALT_L3_SEC_L4MP_GPIO0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_GPIO0 register field value. */ -#define ALT_L3_SEC_L4MP_GPIO0_SET_MSK 0x00000080 -/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO0 register field value. */ -#define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK 0xffffff7f -/* The reset value of the ALT_L3_SEC_L4MP_GPIO0 register field. */ -#define ALT_L3_SEC_L4MP_GPIO0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_GPIO0 field value from a register. */ -#define ALT_L3_SEC_L4MP_GPIO0_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_L3_SEC_L4MP_GPIO0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_GPIO0_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : GPIO 1 Security - gpio1 - * - * Controls whether secure or non-secure masters can access the GPIO 1 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_GPIO1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_GPIO1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */ -#define ALT_L3_SEC_L4MP_GPIO1_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */ -#define ALT_L3_SEC_L4MP_GPIO1_MSB 8 -/* The width in bits of the ALT_L3_SEC_L4MP_GPIO1 register field. */ -#define ALT_L3_SEC_L4MP_GPIO1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_GPIO1 register field value. */ -#define ALT_L3_SEC_L4MP_GPIO1_SET_MSK 0x00000100 -/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO1 register field value. */ -#define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK 0xfffffeff -/* The reset value of the ALT_L3_SEC_L4MP_GPIO1 register field. */ -#define ALT_L3_SEC_L4MP_GPIO1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_GPIO1 field value from a register. */ -#define ALT_L3_SEC_L4MP_GPIO1_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_L3_SEC_L4MP_GPIO1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_GPIO1_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : GPIO 2 Security - gpio2 - * - * Controls whether secure or non-secure masters can access the GPIO 2 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4MP_GPIO2_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4MP_GPIO2_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */ -#define ALT_L3_SEC_L4MP_GPIO2_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */ -#define ALT_L3_SEC_L4MP_GPIO2_MSB 9 -/* The width in bits of the ALT_L3_SEC_L4MP_GPIO2 register field. */ -#define ALT_L3_SEC_L4MP_GPIO2_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4MP_GPIO2 register field value. */ -#define ALT_L3_SEC_L4MP_GPIO2_SET_MSK 0x00000200 -/* The mask used to clear the ALT_L3_SEC_L4MP_GPIO2 register field value. */ -#define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK 0xfffffdff -/* The reset value of the ALT_L3_SEC_L4MP_GPIO2 register field. */ -#define ALT_L3_SEC_L4MP_GPIO2_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4MP_GPIO2 field value from a register. */ -#define ALT_L3_SEC_L4MP_GPIO2_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_L3_SEC_L4MP_GPIO2 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4MP_GPIO2_SET(value) (((value) << 9) & 0x00000200) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_L4MP. - */ -struct ALT_L3_SEC_L4MP_s -{ - uint32_t fpgamgrregs : 1; /* FPGA Manager Register Security */ - uint32_t dap : 1; /* DAP Security */ - uint32_t qspiregs : 1; /* QSPI Registers Security */ - uint32_t sdmmc : 1; /* SDMMC Security */ - uint32_t emac0 : 1; /* EMAC 0 Security */ - uint32_t emac1 : 1; /* EMAC 1 Security */ - uint32_t acpidmap : 1; /* ACP ID Mapper Security */ - uint32_t gpio0 : 1; /* GPIO 0 Security */ - uint32_t gpio1 : 1; /* GPIO 1 Security */ - uint32_t gpio2 : 1; /* GPIO 2 Security */ - uint32_t : 22; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_L4MP. */ -typedef volatile struct ALT_L3_SEC_L4MP_s ALT_L3_SEC_L4MP_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_L4MP register from the beginning of the component. */ -#define ALT_L3_SEC_L4MP_OFST 0x8 - -/* - * Register : L4 OSC1 Peripherals Security - l4osc1 - * - * Controls security settings for L4 OSC1 peripherals. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [0] | W | 0x0 | L4 Watchdog Timer 0 Security - * [1] | W | 0x0 | L4 Watchdog Timer 0 Security - * [2] | W | 0x0 | Clock Manager Security - * [3] | W | 0x0 | Reset Manager Security - * [4] | W | 0x0 | System Manager Security - * [5] | W | 0x0 | OSC1 Timer 0 Security - * [6] | W | 0x0 | OSC1 Timer 1 Security - * [31:7] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : L4 Watchdog Timer 0 Security - l4wd0 - * - * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ -#define ALT_L3_SEC_L4OSC1_L4WD0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ -#define ALT_L3_SEC_L4OSC1_L4WD0_MSB 0 -/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ -#define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */ -#define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */ -#define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */ -#define ALT_L3_SEC_L4OSC1_L4WD0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4OSC1_L4WD0 field value from a register. */ -#define ALT_L3_SEC_L4OSC1_L4WD0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_L4OSC1_L4WD0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4OSC1_L4WD0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : L4 Watchdog Timer 0 Security - l4wd1 - * - * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ -#define ALT_L3_SEC_L4OSC1_L4WD1_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ -#define ALT_L3_SEC_L4OSC1_L4WD1_MSB 1 -/* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ -#define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */ -#define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */ -#define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */ -#define ALT_L3_SEC_L4OSC1_L4WD1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4OSC1_L4WD1 field value from a register. */ -#define ALT_L3_SEC_L4OSC1_L4WD1_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_SEC_L4OSC1_L4WD1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4OSC1_L4WD1_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Clock Manager Security - clkmgr - * - * Controls whether secure or non-secure masters can access the Clock Manager - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_MSB 2 -/* The width in bits of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK 0x00000004 -/* The mask used to clear the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK 0xfffffffb -/* The reset value of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4OSC1_CLKMGR field value from a register. */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_L3_SEC_L4OSC1_CLKMGR register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4OSC1_CLKMGR_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Reset Manager Security - rstmgr - * - * Controls whether secure or non-secure masters can access the Reset Manager - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_MSB 3 -/* The width in bits of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4OSC1_RSTMGR field value from a register. */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_L3_SEC_L4OSC1_RSTMGR register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4OSC1_RSTMGR_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : System Manager Security - sysmgr - * - * Controls whether secure or non-secure masters can access the System Manager - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_MSB 4 -/* The width in bits of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK 0xffffffef -/* The reset value of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4OSC1_SYSMGR field value from a register. */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_L3_SEC_L4OSC1_SYSMGR register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4OSC1_SYSMGR_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : OSC1 Timer 0 Security - osc1timer0 - * - * Controls whether secure or non-secure masters can access the OSC1 Timer 0 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB 5 -/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK 0x00000020 -/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK 0xffffffdf -/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR0 field value from a register. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : OSC1 Timer 1 Security - osc1timer1 - * - * Controls whether secure or non-secure masters can access the OSC1 Timer 1 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB 6 -/* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK 0x00000040 -/* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK 0xffffffbf -/* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR1 field value from a register. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET(value) (((value) << 6) & 0x00000040) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_L4OSC1. - */ -struct ALT_L3_SEC_L4OSC1_s -{ - uint32_t l4wd0 : 1; /* L4 Watchdog Timer 0 Security */ - uint32_t l4wd1 : 1; /* L4 Watchdog Timer 0 Security */ - uint32_t clkmgr : 1; /* Clock Manager Security */ - uint32_t rstmgr : 1; /* Reset Manager Security */ - uint32_t sysmgr : 1; /* System Manager Security */ - uint32_t osc1timer0 : 1; /* OSC1 Timer 0 Security */ - uint32_t osc1timer1 : 1; /* OSC1 Timer 1 Security */ - uint32_t : 25; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_L4OSC1. */ -typedef volatile struct ALT_L3_SEC_L4OSC1_s ALT_L3_SEC_L4OSC1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_L4OSC1 register from the beginning of the component. */ -#define ALT_L3_SEC_L4OSC1_OFST 0xc - -/* - * Register : L4 SPIM Peripherals Security - l4spim - * - * Controls security settings for L4 SPIM peripherals. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------- - * [0] | W | 0x0 | SPI Master 0 Security - * [1] | W | 0x0 | SPI Master 1 Security - * [2] | W | 0x0 | Scan Manager Security - * [31:3] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : SPI Master 0 Security - spim0 - * - * Controls whether secure or non-secure masters can access the SPI Master 0 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ -#define ALT_L3_SEC_L4SPIM_SPIM0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ -#define ALT_L3_SEC_L4SPIM_SPIM0_MSB 0 -/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ -#define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */ -#define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */ -#define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */ -#define ALT_L3_SEC_L4SPIM_SPIM0_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SPIM_SPIM0 field value from a register. */ -#define ALT_L3_SEC_L4SPIM_SPIM0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_L4SPIM_SPIM0 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SPIM_SPIM0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : SPI Master 1 Security - spim1 - * - * Controls whether secure or non-secure masters can access the SPI Master 1 slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1 - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1 - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ -#define ALT_L3_SEC_L4SPIM_SPIM1_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ -#define ALT_L3_SEC_L4SPIM_SPIM1_MSB 1 -/* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ -#define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */ -#define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */ -#define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */ -#define ALT_L3_SEC_L4SPIM_SPIM1_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SPIM_SPIM1 field value from a register. */ -#define ALT_L3_SEC_L4SPIM_SPIM1_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_SEC_L4SPIM_SPIM1 register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SPIM_SPIM1_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Scan Manager Security - scanmgr - * - * Controls whether secure or non-secure masters can access the Scan Manager slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_MSB 2 -/* The width in bits of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK 0x00000004 -/* The mask used to clear the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK 0xfffffffb -/* The reset value of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_RESET 0x0 -/* Extracts the ALT_L3_SEC_L4SPIM_SCANMGR field value from a register. */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_L3_SEC_L4SPIM_SCANMGR register field value suitable for setting the register. */ -#define ALT_L3_SEC_L4SPIM_SCANMGR_SET(value) (((value) << 2) & 0x00000004) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_L4SPIM. - */ -struct ALT_L3_SEC_L4SPIM_s -{ - uint32_t spim0 : 1; /* SPI Master 0 Security */ - uint32_t spim1 : 1; /* SPI Master 1 Security */ - uint32_t scanmgr : 1; /* Scan Manager Security */ - uint32_t : 29; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_L4SPIM. */ -typedef volatile struct ALT_L3_SEC_L4SPIM_s ALT_L3_SEC_L4SPIM_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_L4SPIM register from the beginning of the component. */ -#define ALT_L3_SEC_L4SPIM_OFST 0x10 - -/* - * Register : STM Peripheral Security - stm - * - * Controls security settings for STM peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------- - * [0] | W | 0x0 | STM Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : STM Security - s - * - * Controls whether secure or non-secure masters can access the STM slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_STM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_STM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_STM_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_STM_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_STM_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_STM_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_STM_S register field. */ -#define ALT_L3_SEC_STM_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_STM_S register field. */ -#define ALT_L3_SEC_STM_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_STM_S register field. */ -#define ALT_L3_SEC_STM_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_STM_S register field value. */ -#define ALT_L3_SEC_STM_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_STM_S register field value. */ -#define ALT_L3_SEC_STM_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_STM_S register field. */ -#define ALT_L3_SEC_STM_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_STM_S field value from a register. */ -#define ALT_L3_SEC_STM_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_STM_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_STM_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_STM. - */ -struct ALT_L3_SEC_STM_s -{ - uint32_t s : 1; /* STM Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_STM. */ -typedef volatile struct ALT_L3_SEC_STM_s ALT_L3_SEC_STM_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_STM register from the beginning of the component. */ -#define ALT_L3_SEC_STM_OFST 0x14 - -/* - * Register : LWHPS2FPGA AXI Bridge Registers Peripheral Security - lwhps2fpgaregs - * - * Controls security settings for LWHPS2FPGA AXI Bridge Registers peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------------------- - * [0] | W | 0x0 | LWHPS2FPGA AXI Bridge Registers Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : LWHPS2FPGA AXI Bridge Registers Security - s - * - * Controls whether secure or non-secure masters can access the LWHPS2FPGA AXI - * Bridge Registers slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_LWH2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_LWH2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_LWH2F_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_LWH2F_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_LWH2F_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_LWH2F_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_LWH2F_S register field. */ -#define ALT_L3_SEC_LWH2F_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_LWH2F_S register field. */ -#define ALT_L3_SEC_LWH2F_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_LWH2F_S register field. */ -#define ALT_L3_SEC_LWH2F_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_LWH2F_S register field value. */ -#define ALT_L3_SEC_LWH2F_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_LWH2F_S register field value. */ -#define ALT_L3_SEC_LWH2F_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_LWH2F_S register field. */ -#define ALT_L3_SEC_LWH2F_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_LWH2F_S field value from a register. */ -#define ALT_L3_SEC_LWH2F_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_LWH2F_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_LWH2F_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_LWH2F. - */ -struct ALT_L3_SEC_LWH2F_s -{ - uint32_t s : 1; /* LWHPS2FPGA AXI Bridge Registers Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_LWH2F. */ -typedef volatile struct ALT_L3_SEC_LWH2F_s ALT_L3_SEC_LWH2F_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_LWH2F register from the beginning of the component. */ -#define ALT_L3_SEC_LWH2F_OFST 0x18 - -/* - * Register : USB1 Registers Peripheral Security - usb1 - * - * Controls security settings for USB1 Registers peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------ - * [0] | W | 0x0 | USB1 Registers Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : USB1 Registers Security - s - * - * Controls whether secure or non-secure masters can access the USB1 Registers - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_USB1_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_USB1_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_USB1_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_USB1_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_USB1_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_USB1_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB1_S register field. */ -#define ALT_L3_SEC_USB1_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB1_S register field. */ -#define ALT_L3_SEC_USB1_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_USB1_S register field. */ -#define ALT_L3_SEC_USB1_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_USB1_S register field value. */ -#define ALT_L3_SEC_USB1_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_USB1_S register field value. */ -#define ALT_L3_SEC_USB1_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_USB1_S register field. */ -#define ALT_L3_SEC_USB1_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_USB1_S field value from a register. */ -#define ALT_L3_SEC_USB1_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_USB1_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_USB1_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_USB1. - */ -struct ALT_L3_SEC_USB1_s -{ - uint32_t s : 1; /* USB1 Registers Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_USB1. */ -typedef volatile struct ALT_L3_SEC_USB1_s ALT_L3_SEC_USB1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_USB1 register from the beginning of the component. */ -#define ALT_L3_SEC_USB1_OFST 0x20 - -/* - * Register : NAND Flash Controller Data Peripheral Security - nanddata - * - * Controls security settings for NAND Flash Controller Data peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------ - * [0] | W | 0x0 | NAND Flash Controller Data Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : NAND Flash Controller Data Security - s - * - * Controls whether secure or non-secure masters can access the NAND Flash - * Controller Data slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_NANDDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_NANDDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_NANDDATA_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_NANDDATA_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_NANDDATA_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_NANDDATA_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NANDDATA_S register field. */ -#define ALT_L3_SEC_NANDDATA_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NANDDATA_S register field. */ -#define ALT_L3_SEC_NANDDATA_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_NANDDATA_S register field. */ -#define ALT_L3_SEC_NANDDATA_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_NANDDATA_S register field value. */ -#define ALT_L3_SEC_NANDDATA_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_NANDDATA_S register field value. */ -#define ALT_L3_SEC_NANDDATA_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_NANDDATA_S register field. */ -#define ALT_L3_SEC_NANDDATA_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_NANDDATA_S field value from a register. */ -#define ALT_L3_SEC_NANDDATA_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_NANDDATA_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_NANDDATA_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_NANDDATA. - */ -struct ALT_L3_SEC_NANDDATA_s -{ - uint32_t s : 1; /* NAND Flash Controller Data Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_NANDDATA. */ -typedef volatile struct ALT_L3_SEC_NANDDATA_s ALT_L3_SEC_NANDDATA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_NANDDATA register from the beginning of the component. */ -#define ALT_L3_SEC_NANDDATA_OFST 0x24 - -/* - * Register : USB0 Registers Peripheral Security - usb0 - * - * Controls security settings for USB0 Registers peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------ - * [0] | W | 0x0 | USB0 Registers Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : USB0 Registers Security - s - * - * Controls whether secure or non-secure masters can access the USB0 Registers - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_USB0_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_USB0_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_USB0_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_USB0_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_USB0_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_USB0_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB0_S register field. */ -#define ALT_L3_SEC_USB0_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB0_S register field. */ -#define ALT_L3_SEC_USB0_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_USB0_S register field. */ -#define ALT_L3_SEC_USB0_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_USB0_S register field value. */ -#define ALT_L3_SEC_USB0_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_USB0_S register field value. */ -#define ALT_L3_SEC_USB0_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_USB0_S register field. */ -#define ALT_L3_SEC_USB0_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_USB0_S field value from a register. */ -#define ALT_L3_SEC_USB0_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_USB0_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_USB0_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_USB0. - */ -struct ALT_L3_SEC_USB0_s -{ - uint32_t s : 1; /* USB0 Registers Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_USB0. */ -typedef volatile struct ALT_L3_SEC_USB0_s ALT_L3_SEC_USB0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_USB0 register from the beginning of the component. */ -#define ALT_L3_SEC_USB0_OFST 0x78 - -/* - * Register : NAND Flash Controller Registers Peripheral Security - nandregs - * - * Controls security settings for NAND Flash Controller Registers peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------------------- - * [0] | W | 0x0 | NAND Flash Controller Registers Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : NAND Flash Controller Registers Security - s - * - * Controls whether secure or non-secure masters can access the NAND Flash - * Controller Registers slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_NAND_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_NAND_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_NAND_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_NAND_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_NAND_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_NAND_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NAND_S register field. */ -#define ALT_L3_SEC_NAND_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NAND_S register field. */ -#define ALT_L3_SEC_NAND_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_NAND_S register field. */ -#define ALT_L3_SEC_NAND_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_NAND_S register field value. */ -#define ALT_L3_SEC_NAND_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_NAND_S register field value. */ -#define ALT_L3_SEC_NAND_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_NAND_S register field. */ -#define ALT_L3_SEC_NAND_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_NAND_S field value from a register. */ -#define ALT_L3_SEC_NAND_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_NAND_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_NAND_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_NAND. - */ -struct ALT_L3_SEC_NAND_s -{ - uint32_t s : 1; /* NAND Flash Controller Registers Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_NAND. */ -typedef volatile struct ALT_L3_SEC_NAND_s ALT_L3_SEC_NAND_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_NAND register from the beginning of the component. */ -#define ALT_L3_SEC_NAND_OFST 0x7c - -/* - * Register : QSPI Flash Controller Data Peripheral Security - qspidata - * - * Controls security settings for QSPI Flash Controller Data peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------ - * [0] | W | 0x0 | QSPI Flash Controller Data Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : QSPI Flash Controller Data Security - s - * - * Controls whether secure or non-secure masters can access the QSPI Flash - * Controller Data slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_QSPIDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_QSPIDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_QSPIDATA_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_QSPIDATA_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */ -#define ALT_L3_SEC_QSPIDATA_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */ -#define ALT_L3_SEC_QSPIDATA_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_QSPIDATA_S register field. */ -#define ALT_L3_SEC_QSPIDATA_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_QSPIDATA_S register field value. */ -#define ALT_L3_SEC_QSPIDATA_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_QSPIDATA_S register field value. */ -#define ALT_L3_SEC_QSPIDATA_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_QSPIDATA_S register field. */ -#define ALT_L3_SEC_QSPIDATA_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_QSPIDATA_S field value from a register. */ -#define ALT_L3_SEC_QSPIDATA_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_QSPIDATA_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_QSPIDATA_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_QSPIDATA. - */ -struct ALT_L3_SEC_QSPIDATA_s -{ - uint32_t s : 1; /* QSPI Flash Controller Data Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_QSPIDATA. */ -typedef volatile struct ALT_L3_SEC_QSPIDATA_s ALT_L3_SEC_QSPIDATA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_QSPIDATA register from the beginning of the component. */ -#define ALT_L3_SEC_QSPIDATA_OFST 0x80 - -/* - * Register : FPGA Manager Data Peripheral Security - fpgamgrdata - * - * Controls security settings for FPGA Manager Data peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------- - * [0] | W | 0x0 | FPGA Manager Data Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : FPGA Manager Data Security - s - * - * Controls whether secure or non-secure masters can access the FPGA Manager Data - * slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ -#define ALT_L3_SEC_FPGAMGRDATA_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ -#define ALT_L3_SEC_FPGAMGRDATA_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ -#define ALT_L3_SEC_FPGAMGRDATA_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_FPGAMGRDATA_S register field value. */ -#define ALT_L3_SEC_FPGAMGRDATA_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_FPGAMGRDATA_S register field value. */ -#define ALT_L3_SEC_FPGAMGRDATA_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_FPGAMGRDATA_S register field. */ -#define ALT_L3_SEC_FPGAMGRDATA_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_FPGAMGRDATA_S field value from a register. */ -#define ALT_L3_SEC_FPGAMGRDATA_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_FPGAMGRDATA_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_FPGAMGRDATA_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_FPGAMGRDATA. - */ -struct ALT_L3_SEC_FPGAMGRDATA_s -{ - uint32_t s : 1; /* FPGA Manager Data Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_FPGAMGRDATA. */ -typedef volatile struct ALT_L3_SEC_FPGAMGRDATA_s ALT_L3_SEC_FPGAMGRDATA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_FPGAMGRDATA register from the beginning of the component. */ -#define ALT_L3_SEC_FPGAMGRDATA_OFST 0x84 - -/* - * Register : HPS2FPGA AXI Bridge Registers Peripheral Security - hps2fpgaregs - * - * Controls security settings for HPS2FPGA AXI Bridge Registers peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | W | 0x0 | HPS2FPGA AXI Bridge Registers Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : HPS2FPGA AXI Bridge Registers Security - s - * - * Controls whether secure or non-secure masters can access the HPS2FPGA AXI Bridge - * Registers slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_H2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_H2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_H2F_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_H2F_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_H2F_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_H2F_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_H2F_S register field. */ -#define ALT_L3_SEC_H2F_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_H2F_S register field. */ -#define ALT_L3_SEC_H2F_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_H2F_S register field. */ -#define ALT_L3_SEC_H2F_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_H2F_S register field value. */ -#define ALT_L3_SEC_H2F_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_H2F_S register field value. */ -#define ALT_L3_SEC_H2F_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_H2F_S register field. */ -#define ALT_L3_SEC_H2F_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_H2F_S field value from a register. */ -#define ALT_L3_SEC_H2F_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_H2F_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_H2F_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_H2F. - */ -struct ALT_L3_SEC_H2F_s -{ - uint32_t s : 1; /* HPS2FPGA AXI Bridge Registers Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_H2F. */ -typedef volatile struct ALT_L3_SEC_H2F_s ALT_L3_SEC_H2F_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_H2F register from the beginning of the component. */ -#define ALT_L3_SEC_H2F_OFST 0x88 - -/* - * Register : MPU ACP Peripheral Security - acp - * - * Controls security settings for MPU ACP peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------- - * [0] | W | 0x0 | MPU ACP Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : MPU ACP Security - s - * - * Controls whether secure or non-secure masters can access the MPU ACP slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_ACP_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_ACP_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_ACP_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_ACP_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_ACP_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_ACP_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ACP_S register field. */ -#define ALT_L3_SEC_ACP_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ACP_S register field. */ -#define ALT_L3_SEC_ACP_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_ACP_S register field. */ -#define ALT_L3_SEC_ACP_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_ACP_S register field value. */ -#define ALT_L3_SEC_ACP_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_ACP_S register field value. */ -#define ALT_L3_SEC_ACP_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_ACP_S register field. */ -#define ALT_L3_SEC_ACP_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_ACP_S field value from a register. */ -#define ALT_L3_SEC_ACP_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_ACP_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_ACP_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_ACP. - */ -struct ALT_L3_SEC_ACP_s -{ - uint32_t s : 1; /* MPU ACP Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_ACP. */ -typedef volatile struct ALT_L3_SEC_ACP_s ALT_L3_SEC_ACP_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_ACP register from the beginning of the component. */ -#define ALT_L3_SEC_ACP_OFST 0x8c - -/* - * Register : ROM Peripheral Security - rom - * - * Controls security settings for ROM peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------- - * [0] | W | 0x0 | ROM Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : ROM Security - s - * - * Controls whether secure or non-secure masters can access the ROM slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_ROM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_ROM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_ROM_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_ROM_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_ROM_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_ROM_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ROM_S register field. */ -#define ALT_L3_SEC_ROM_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ROM_S register field. */ -#define ALT_L3_SEC_ROM_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_ROM_S register field. */ -#define ALT_L3_SEC_ROM_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_ROM_S register field value. */ -#define ALT_L3_SEC_ROM_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_ROM_S register field value. */ -#define ALT_L3_SEC_ROM_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_ROM_S register field. */ -#define ALT_L3_SEC_ROM_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_ROM_S field value from a register. */ -#define ALT_L3_SEC_ROM_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_ROM_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_ROM_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_ROM. - */ -struct ALT_L3_SEC_ROM_s -{ - uint32_t s : 1; /* ROM Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_ROM. */ -typedef volatile struct ALT_L3_SEC_ROM_s ALT_L3_SEC_ROM_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_ROM register from the beginning of the component. */ -#define ALT_L3_SEC_ROM_OFST 0x90 - -/* - * Register : On-chip RAM Peripheral Security - ocram - * - * Controls security settings for On-chip RAM peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------- - * [0] | W | 0x0 | On-chip RAM Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : On-chip RAM Security - s - * - * Controls whether secure or non-secure masters can access the On-chip RAM slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_OCRAM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_OCRAM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_OCRAM_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_OCRAM_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_OCRAM_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_OCRAM_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_OCRAM_S register field. */ -#define ALT_L3_SEC_OCRAM_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_OCRAM_S register field. */ -#define ALT_L3_SEC_OCRAM_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_OCRAM_S register field. */ -#define ALT_L3_SEC_OCRAM_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_OCRAM_S register field value. */ -#define ALT_L3_SEC_OCRAM_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_OCRAM_S register field value. */ -#define ALT_L3_SEC_OCRAM_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_OCRAM_S register field. */ -#define ALT_L3_SEC_OCRAM_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_OCRAM_S field value from a register. */ -#define ALT_L3_SEC_OCRAM_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_OCRAM_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_OCRAM_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_OCRAM. - */ -struct ALT_L3_SEC_OCRAM_s -{ - uint32_t s : 1; /* On-chip RAM Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_OCRAM. */ -typedef volatile struct ALT_L3_SEC_OCRAM_s ALT_L3_SEC_OCRAM_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_OCRAM register from the beginning of the component. */ -#define ALT_L3_SEC_OCRAM_OFST 0x94 - -/* - * Register : SDRAM Data Peripheral Security - sdrdata - * - * Controls security settings for SDRAM Data peripheral. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------- - * [0] | W | 0x0 | SDRAM Data Security - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : SDRAM Data Security - s - * - * Controls whether secure or non-secure masters can access the SDRAM Data slave. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------------------------- - * ALT_L3_SEC_SDRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure - * : | | master. - * ALT_L3_SEC_SDRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or - * : | | non-secure masters. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_SEC_SDRDATA_S - * - * The slave can only be accessed by a secure master. - */ -#define ALT_L3_SEC_SDRDATA_S_E_SECURE 0x0 -/* - * Enumerated value for register field ALT_L3_SEC_SDRDATA_S - * - * The slave can only be accessed by a secure or non-secure masters. - */ -#define ALT_L3_SEC_SDRDATA_S_E_NONSECURE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_SEC_SDRDATA_S register field. */ -#define ALT_L3_SEC_SDRDATA_S_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_SEC_SDRDATA_S register field. */ -#define ALT_L3_SEC_SDRDATA_S_MSB 0 -/* The width in bits of the ALT_L3_SEC_SDRDATA_S register field. */ -#define ALT_L3_SEC_SDRDATA_S_WIDTH 1 -/* The mask used to set the ALT_L3_SEC_SDRDATA_S register field value. */ -#define ALT_L3_SEC_SDRDATA_S_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_SEC_SDRDATA_S register field value. */ -#define ALT_L3_SEC_SDRDATA_S_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_SEC_SDRDATA_S register field. */ -#define ALT_L3_SEC_SDRDATA_S_RESET 0x0 -/* Extracts the ALT_L3_SEC_SDRDATA_S field value from a register. */ -#define ALT_L3_SEC_SDRDATA_S_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_SEC_SDRDATA_S register field value suitable for setting the register. */ -#define ALT_L3_SEC_SDRDATA_S_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_SEC_SDRDATA. - */ -struct ALT_L3_SEC_SDRDATA_s -{ - uint32_t s : 1; /* SDRAM Data Security */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_SEC_SDRDATA. */ -typedef volatile struct ALT_L3_SEC_SDRDATA_s ALT_L3_SEC_SDRDATA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_SEC_SDRDATA register from the beginning of the component. */ -#define ALT_L3_SEC_SDRDATA_OFST 0x98 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SECGRP. - */ -struct ALT_L3_SECGRP_s -{ - volatile ALT_L3_SEC_L4MAIN_t l4main; /* ALT_L3_SEC_L4MAIN */ - volatile ALT_L3_SEC_L4SP_t l4sp; /* ALT_L3_SEC_L4SP */ - volatile ALT_L3_SEC_L4MP_t l4mp; /* ALT_L3_SEC_L4MP */ - volatile ALT_L3_SEC_L4OSC1_t l4osc1; /* ALT_L3_SEC_L4OSC1 */ - volatile ALT_L3_SEC_L4SPIM_t l4spim; /* ALT_L3_SEC_L4SPIM */ - volatile ALT_L3_SEC_STM_t stm; /* ALT_L3_SEC_STM */ - volatile ALT_L3_SEC_LWH2F_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */ - volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ - volatile ALT_L3_SEC_USB1_t usb1; /* ALT_L3_SEC_USB1 */ - volatile ALT_L3_SEC_NANDDATA_t nanddata; /* ALT_L3_SEC_NANDDATA */ - volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */ - volatile ALT_L3_SEC_USB0_t usb0; /* ALT_L3_SEC_USB0 */ - volatile ALT_L3_SEC_NAND_t nandregs; /* ALT_L3_SEC_NAND */ - volatile ALT_L3_SEC_QSPIDATA_t qspidata; /* ALT_L3_SEC_QSPIDATA */ - volatile ALT_L3_SEC_FPGAMGRDATA_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */ - volatile ALT_L3_SEC_H2F_t hps2fpgaregs; /* ALT_L3_SEC_H2F */ - volatile ALT_L3_SEC_ACP_t acp; /* ALT_L3_SEC_ACP */ - volatile ALT_L3_SEC_ROM_t rom; /* ALT_L3_SEC_ROM */ - volatile ALT_L3_SEC_OCRAM_t ocram; /* ALT_L3_SEC_OCRAM */ - volatile ALT_L3_SEC_SDRDATA_t sdrdata; /* ALT_L3_SEC_SDRDATA */ -}; - -/* The typedef declaration for register group ALT_L3_SECGRP. */ -typedef volatile struct ALT_L3_SECGRP_s ALT_L3_SECGRP_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SECGRP. */ -struct ALT_L3_SECGRP_raw_s -{ - volatile uint32_t l4main; /* ALT_L3_SEC_L4MAIN */ - volatile uint32_t l4sp; /* ALT_L3_SEC_L4SP */ - volatile uint32_t l4mp; /* ALT_L3_SEC_L4MP */ - volatile uint32_t l4osc1; /* ALT_L3_SEC_L4OSC1 */ - volatile uint32_t l4spim; /* ALT_L3_SEC_L4SPIM */ - volatile uint32_t stm; /* ALT_L3_SEC_STM */ - volatile uint32_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */ - volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */ - volatile uint32_t usb1; /* ALT_L3_SEC_USB1 */ - volatile uint32_t nanddata; /* ALT_L3_SEC_NANDDATA */ - volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */ - volatile uint32_t usb0; /* ALT_L3_SEC_USB0 */ - volatile uint32_t nandregs; /* ALT_L3_SEC_NAND */ - volatile uint32_t qspidata; /* ALT_L3_SEC_QSPIDATA */ - volatile uint32_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */ - volatile uint32_t hps2fpgaregs; /* ALT_L3_SEC_H2F */ - volatile uint32_t acp; /* ALT_L3_SEC_ACP */ - volatile uint32_t rom; /* ALT_L3_SEC_ROM */ - volatile uint32_t ocram; /* ALT_L3_SEC_OCRAM */ - volatile uint32_t sdrdata; /* ALT_L3_SEC_SDRDATA */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SECGRP. */ -typedef volatile struct ALT_L3_SECGRP_raw_s ALT_L3_SECGRP_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : ID Register Group - ALT_L3_IDGRP - * ID Register Group - * - * Contains registers that identify the ARM NIC-301 IP Core. - * - */ -/* - * Register : Peripheral ID4 Register - periph_id_4 - * - * JEP106 continuation code - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------- - * [7:0] | R | 0x4 | Peripheral ID4 - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Peripheral ID4 - periph_id_4 - * - * JEP106 continuation code - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ -#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ -#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7 -/* The width in bits of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ -#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8 -/* The mask used to set the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ -#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff -/* The mask used to clear the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */ -#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00 -/* The reset value of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */ -#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4 -/* Extracts the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */ -#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */ -#define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_ID_PERIPH_ID_4. - */ -struct ALT_L3_ID_PERIPH_ID_4_s -{ - const uint32_t periph_id_4 : 8; /* Peripheral ID4 */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_4. */ -typedef volatile struct ALT_L3_ID_PERIPH_ID_4_s ALT_L3_ID_PERIPH_ID_4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_ID_PERIPH_ID_4 register from the beginning of the component. */ -#define ALT_L3_ID_PERIPH_ID_4_OFST 0xfd0 - -/* - * Register : Peripheral ID0 Register - periph_id_0 - * - * Peripheral ID0 - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------ - * [7:0] | R | 0x1 | Part Number [7:0] - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Part Number [7:0] - pn7to0 - * - * Part Number [7:0] - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ -#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ -#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_MSB 7 -/* The width in bits of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ -#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_WIDTH 8 -/* The mask used to set the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */ -#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff -/* The mask used to clear the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */ -#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00 -/* The reset value of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */ -#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_RESET 0x1 -/* Extracts the ALT_L3_ID_PERIPH_ID_0_PN7TO0 field value from a register. */ -#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */ -#define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_ID_PERIPH_ID_0. - */ -struct ALT_L3_ID_PERIPH_ID_0_s -{ - const uint32_t pn7to0 : 8; /* Part Number [7:0] */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_0. */ -typedef volatile struct ALT_L3_ID_PERIPH_ID_0_s ALT_L3_ID_PERIPH_ID_0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_ID_PERIPH_ID_0 register from the beginning of the component. */ -#define ALT_L3_ID_PERIPH_ID_0_OFST 0xfe0 - -/* - * Register : Peripheral ID1 Register - periph_id_1 - * - * Peripheral ID1 - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8] - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8 - * - * JEP106[3:0], Part Number [11:8] - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ -#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ -#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7 -/* The width in bits of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ -#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8 -/* The mask used to set the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ -#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff -/* The mask used to clear the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */ -#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00 -/* The reset value of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */ -#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3 -/* Extracts the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */ -#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */ -#define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_ID_PERIPH_ID_1. - */ -struct ALT_L3_ID_PERIPH_ID_1_s -{ - const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_1. */ -typedef volatile struct ALT_L3_ID_PERIPH_ID_1_s ALT_L3_ID_PERIPH_ID_1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_ID_PERIPH_ID_1 register from the beginning of the component. */ -#define ALT_L3_ID_PERIPH_ID_1_OFST 0xfe4 - -/* - * Register : Peripheral ID2 Register - periph_id_2 - * - * Peripheral ID2 - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4] - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4 - * - * Revision, JEP106 code flag, JEP106[6:4] - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ -#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ -#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7 -/* The width in bits of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ -#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8 -/* The mask used to set the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ -#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff -/* The mask used to clear the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */ -#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00 -/* The reset value of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */ -#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b -/* Extracts the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */ -#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */ -#define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_ID_PERIPH_ID_2. - */ -struct ALT_L3_ID_PERIPH_ID_2_s -{ - const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_2. */ -typedef volatile struct ALT_L3_ID_PERIPH_ID_2_s ALT_L3_ID_PERIPH_ID_2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_ID_PERIPH_ID_2 register from the beginning of the component. */ -#define ALT_L3_ID_PERIPH_ID_2_OFST 0xfe8 - -/* - * Register : Peripheral ID3 Register - periph_id_3 - * - * Peripheral ID3 - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------- - * [3:0] | R | 0x0 | Customer Model Number - * [7:4] | R | 0x0 | Revision - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Customer Model Number - cust_mod_num - * - * Customer Model Number - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ -#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ -#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3 -/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ -#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4 -/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ -#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f -/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */ -#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */ -#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0 -/* Extracts the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */ -#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */ -#define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f) - -/* - * Field : Revision - rev_and - * - * Revision - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ -#define ALT_L3_ID_PERIPH_ID_3_REV_AND_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ -#define ALT_L3_ID_PERIPH_ID_3_REV_AND_MSB 7 -/* The width in bits of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ -#define ALT_L3_ID_PERIPH_ID_3_REV_AND_WIDTH 4 -/* The mask used to set the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */ -#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0 -/* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */ -#define ALT_L3_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f -/* The reset value of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */ -#define ALT_L3_ID_PERIPH_ID_3_REV_AND_RESET 0x0 -/* Extracts the ALT_L3_ID_PERIPH_ID_3_REV_AND field value from a register. */ -#define ALT_L3_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4) -/* Produces a ALT_L3_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */ -#define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_ID_PERIPH_ID_3. - */ -struct ALT_L3_ID_PERIPH_ID_3_s -{ - const uint32_t cust_mod_num : 4; /* Customer Model Number */ - const uint32_t rev_and : 4; /* Revision */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_ID_PERIPH_ID_3. */ -typedef volatile struct ALT_L3_ID_PERIPH_ID_3_s ALT_L3_ID_PERIPH_ID_3_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_ID_PERIPH_ID_3 register from the beginning of the component. */ -#define ALT_L3_ID_PERIPH_ID_3_OFST 0xfec - -/* - * Register : Component ID0 Register - comp_id_0 - * - * Component ID0 - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [7:0] | R | 0xd | Preamble - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Preamble - preamble - * - * Preamble - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_0_PREAMBLE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_0_PREAMBLE_MSB 7 -/* The width in bits of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_0_PREAMBLE_WIDTH 8 -/* The mask used to set the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */ -#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff -/* The mask used to clear the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */ -#define ALT_L3_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00 -/* The reset value of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_0_PREAMBLE_RESET 0xd -/* Extracts the ALT_L3_ID_COMP_ID_0_PREAMBLE field value from a register. */ -#define ALT_L3_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_L3_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */ -#define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_ID_COMP_ID_0. - */ -struct ALT_L3_ID_COMP_ID_0_s -{ - const uint32_t preamble : 8; /* Preamble */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_ID_COMP_ID_0. */ -typedef volatile struct ALT_L3_ID_COMP_ID_0_s ALT_L3_ID_COMP_ID_0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_ID_COMP_ID_0 register from the beginning of the component. */ -#define ALT_L3_ID_COMP_ID_0_OFST 0xff0 - -/* - * Register : Component ID1 Register - comp_id_1 - * - * Component ID1 - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------- - * [7:0] | R | 0xf0 | Generic IP component class, Preamble - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Generic IP component class, Preamble - genipcompcls_preamble - * - * Generic IP component class, Preamble - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7 -/* The width in bits of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8 -/* The mask used to set the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ -#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff -/* The mask used to clear the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */ -#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00 -/* The reset value of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0 -/* Extracts the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */ -#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */ -#define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_ID_COMP_ID_1. - */ -struct ALT_L3_ID_COMP_ID_1_s -{ - const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_ID_COMP_ID_1. */ -typedef volatile struct ALT_L3_ID_COMP_ID_1_s ALT_L3_ID_COMP_ID_1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_ID_COMP_ID_1 register from the beginning of the component. */ -#define ALT_L3_ID_COMP_ID_1_OFST 0xff4 - -/* - * Register : Component ID2 Register - comp_id_2 - * - * Component ID2 - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [7:0] | R | 0x5 | Preamble - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Preamble - preamble - * - * Preamble - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_2_PREAMBLE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_2_PREAMBLE_MSB 7 -/* The width in bits of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_2_PREAMBLE_WIDTH 8 -/* The mask used to set the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */ -#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff -/* The mask used to clear the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */ -#define ALT_L3_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00 -/* The reset value of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_2_PREAMBLE_RESET 0x5 -/* Extracts the ALT_L3_ID_COMP_ID_2_PREAMBLE field value from a register. */ -#define ALT_L3_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_L3_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */ -#define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_ID_COMP_ID_2. - */ -struct ALT_L3_ID_COMP_ID_2_s -{ - const uint32_t preamble : 8; /* Preamble */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_ID_COMP_ID_2. */ -typedef volatile struct ALT_L3_ID_COMP_ID_2_s ALT_L3_ID_COMP_ID_2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_ID_COMP_ID_2 register from the beginning of the component. */ -#define ALT_L3_ID_COMP_ID_2_OFST 0xff8 - -/* - * Register : Component ID3 Register - comp_id_3 - * - * Component ID3 - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [7:0] | R | 0xb1 | Preamble - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Preamble - preamble - * - * Preamble - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_3_PREAMBLE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_3_PREAMBLE_MSB 7 -/* The width in bits of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_3_PREAMBLE_WIDTH 8 -/* The mask used to set the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */ -#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff -/* The mask used to clear the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */ -#define ALT_L3_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00 -/* The reset value of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */ -#define ALT_L3_ID_COMP_ID_3_PREAMBLE_RESET 0xb1 -/* Extracts the ALT_L3_ID_COMP_ID_3_PREAMBLE field value from a register. */ -#define ALT_L3_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_L3_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */ -#define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_ID_COMP_ID_3. - */ -struct ALT_L3_ID_COMP_ID_3_s -{ - const uint32_t preamble : 8; /* Preamble */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_ID_COMP_ID_3. */ -typedef volatile struct ALT_L3_ID_COMP_ID_3_s ALT_L3_ID_COMP_ID_3_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_ID_COMP_ID_3 register from the beginning of the component. */ -#define ALT_L3_ID_COMP_ID_3_OFST 0xffc - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_IDGRP. - */ -struct ALT_L3_IDGRP_s -{ - volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ - volatile ALT_L3_ID_PERIPH_ID_4_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */ - volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ - volatile ALT_L3_ID_PERIPH_ID_0_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */ - volatile ALT_L3_ID_PERIPH_ID_1_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */ - volatile ALT_L3_ID_PERIPH_ID_2_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */ - volatile ALT_L3_ID_PERIPH_ID_3_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */ - volatile ALT_L3_ID_COMP_ID_0_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */ - volatile ALT_L3_ID_COMP_ID_1_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */ - volatile ALT_L3_ID_COMP_ID_2_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */ - volatile ALT_L3_ID_COMP_ID_3_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */ -}; - -/* The typedef declaration for register group ALT_L3_IDGRP. */ -typedef volatile struct ALT_L3_IDGRP_s ALT_L3_IDGRP_t; -/* The struct declaration for the raw register contents of register group ALT_L3_IDGRP. */ -struct ALT_L3_IDGRP_raw_s -{ - volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */ - volatile uint32_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */ - volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */ - volatile uint32_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */ - volatile uint32_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */ - volatile uint32_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */ - volatile uint32_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */ - volatile uint32_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */ - volatile uint32_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */ - volatile uint32_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */ - volatile uint32_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_IDGRP. */ -typedef volatile struct ALT_L3_IDGRP_raw_s ALT_L3_IDGRP_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Master Register Group - ALT_L3_MSTGRP - * Master Register Group - * - * Registers associated with master interfaces in the L3 Interconnect. Note that a - * master in the L3 Interconnect connects to a slave in a module. - * - */ -/* - * Register Group : L4 MAIN - ALT_L3_MST_L4MAIN - * L4 MAIN - * - * Registers associated with the L4 MAIN master. This master is used to access the - * APB slaves on the L4 MAIN bus. - * - */ -/* - * Register : Bus Matrix Issuing Functionality Modification Register - fn_mod_bm_iss - * - * Sets the issuing capability of the preceding switch arbitration scheme to - * multiple or single outstanding transactions. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------ - * [0] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_RD - * [1] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_WR - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : rd - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:------------------------------------------- - * ALT_L3_FN_MOD_BM_ISS_RD_E_MULT | 0x0 | Multiple outstanding read transactions - * ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD - * - * Multiple outstanding read transactions - */ -#define ALT_L3_FN_MOD_BM_ISS_RD_E_MULT 0x0 -/* - * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD - * - * Only a single outstanding read transaction - */ -#define ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ -#define ALT_L3_FN_MOD_BM_ISS_RD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ -#define ALT_L3_FN_MOD_BM_ISS_RD_MSB 0 -/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ -#define ALT_L3_FN_MOD_BM_ISS_RD_WIDTH 1 -/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_RD register field value. */ -#define ALT_L3_FN_MOD_BM_ISS_RD_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_RD register field value. */ -#define ALT_L3_FN_MOD_BM_ISS_RD_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_FN_MOD_BM_ISS_RD register field. */ -#define ALT_L3_FN_MOD_BM_ISS_RD_RESET 0x0 -/* Extracts the ALT_L3_FN_MOD_BM_ISS_RD field value from a register. */ -#define ALT_L3_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_FN_MOD_BM_ISS_RD register field value suitable for setting the register. */ -#define ALT_L3_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : wr - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:-------------------------------------------- - * ALT_L3_FN_MOD_BM_ISS_WR_E_MULT | 0x0 | Multiple outstanding write transactions - * ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR - * - * Multiple outstanding write transactions - */ -#define ALT_L3_FN_MOD_BM_ISS_WR_E_MULT 0x0 -/* - * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR - * - * Only a single outstanding write transaction - */ -#define ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ -#define ALT_L3_FN_MOD_BM_ISS_WR_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ -#define ALT_L3_FN_MOD_BM_ISS_WR_MSB 1 -/* The width in bits of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ -#define ALT_L3_FN_MOD_BM_ISS_WR_WIDTH 1 -/* The mask used to set the ALT_L3_FN_MOD_BM_ISS_WR register field value. */ -#define ALT_L3_FN_MOD_BM_ISS_WR_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_WR register field value. */ -#define ALT_L3_FN_MOD_BM_ISS_WR_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_FN_MOD_BM_ISS_WR register field. */ -#define ALT_L3_FN_MOD_BM_ISS_WR_RESET 0x0 -/* Extracts the ALT_L3_FN_MOD_BM_ISS_WR field value from a register. */ -#define ALT_L3_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_FN_MOD_BM_ISS_WR register field value suitable for setting the register. */ -#define ALT_L3_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_FN_MOD_BM_ISS. - */ -struct ALT_L3_FN_MOD_BM_ISS_s -{ - uint32_t rd : 1; /* ALT_L3_FN_MOD_BM_ISS_RD */ - uint32_t wr : 1; /* ALT_L3_FN_MOD_BM_ISS_WR */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_FN_MOD_BM_ISS. */ -typedef volatile struct ALT_L3_FN_MOD_BM_ISS_s ALT_L3_FN_MOD_BM_ISS_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_FN_MOD_BM_ISS register from the beginning of the component. */ -#define ALT_L3_FN_MOD_BM_ISS_OFST 0x8 -/* The address of the ALT_L3_FN_MOD_BM_ISS register. */ -#define ALT_L3_FN_MOD_BM_ISS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_BM_ISS_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_L4MAIN. - */ -struct ALT_L3_MST_L4MAIN_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for register group ALT_L3_MST_L4MAIN. */ -typedef volatile struct ALT_L3_MST_L4MAIN_s ALT_L3_MST_L4MAIN_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */ -struct ALT_L3_MST_L4MAIN_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */ -typedef volatile struct ALT_L3_MST_L4MAIN_raw_s ALT_L3_MST_L4MAIN_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : L4 SP - ALT_L3_MST_L4SP - * L4 SP - * - * Registers associated with the L4 SP master. This master is used to access the - * APB slaves on the L4 SP bus. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_L4SP. - */ -struct ALT_L3_MST_L4SP_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for register group ALT_L3_MST_L4SP. */ -typedef volatile struct ALT_L3_MST_L4SP_s ALT_L3_MST_L4SP_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SP. */ -struct ALT_L3_MST_L4SP_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SP. */ -typedef volatile struct ALT_L3_MST_L4SP_raw_s ALT_L3_MST_L4SP_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : L4 MP - ALT_L3_MST_L4MP - * L4 MP - * - * Registers associated with the L4 MP master. This master is used to access the - * APB slaves on the L4 MP bus. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_L4MP. - */ -struct ALT_L3_MST_L4MP_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for register group ALT_L3_MST_L4MP. */ -typedef volatile struct ALT_L3_MST_L4MP_s ALT_L3_MST_L4MP_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MP. */ -struct ALT_L3_MST_L4MP_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MP. */ -typedef volatile struct ALT_L3_MST_L4MP_raw_s ALT_L3_MST_L4MP_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : L4 OSC1 - ALT_L3_MST_L4OSC1 - * L4 OSC1 - * - * Registers associated with the L4 OSC1 master. This master is used to access the - * APB slaves on the L4 OSC1 bus. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_L4OSC1. - */ -struct ALT_L3_MST_L4OSC1_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for register group ALT_L3_MST_L4OSC1. */ -typedef volatile struct ALT_L3_MST_L4OSC1_s ALT_L3_MST_L4OSC1_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */ -struct ALT_L3_MST_L4OSC1_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */ -typedef volatile struct ALT_L3_MST_L4OSC1_raw_s ALT_L3_MST_L4OSC1_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : L4 SPIM - ALT_L3_MST_L4SPIM - * L4 SPIM - * - * Registers associated with the L4 SPIM master. This master is used to access the - * APB slaves on the L4 SPIM bus. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_L4SPIM. - */ -struct ALT_L3_MST_L4SPIM_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for register group ALT_L3_MST_L4SPIM. */ -typedef volatile struct ALT_L3_MST_L4SPIM_s ALT_L3_MST_L4SPIM_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */ -struct ALT_L3_MST_L4SPIM_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */ -typedef volatile struct ALT_L3_MST_L4SPIM_raw_s ALT_L3_MST_L4SPIM_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : STM - ALT_L3_MST_STM - * STM - * - * Registers associated with the STM master. This master is used to access the STM - * AXI slave. - * - */ -/* - * Register : Issuing Functionality Modification Register - fn_mod - * - * Sets the block issuing capability to multiple or single outstanding - * transactions. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------- - * [0] | RW | 0x0 | ALT_L3_FN_MOD_RD - * [1] | RW | 0x0 | ALT_L3_FN_MOD_WR - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : rd - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:------------------------------------------- - * ALT_L3_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions - * ALT_L3_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_FN_MOD_RD - * - * Multiple outstanding read transactions - */ -#define ALT_L3_FN_MOD_RD_E_MULT 0x0 -/* - * Enumerated value for register field ALT_L3_FN_MOD_RD - * - * Only a single outstanding read transaction - */ -#define ALT_L3_FN_MOD_RD_E_SINGLE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_RD register field. */ -#define ALT_L3_FN_MOD_RD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_RD register field. */ -#define ALT_L3_FN_MOD_RD_MSB 0 -/* The width in bits of the ALT_L3_FN_MOD_RD register field. */ -#define ALT_L3_FN_MOD_RD_WIDTH 1 -/* The mask used to set the ALT_L3_FN_MOD_RD register field value. */ -#define ALT_L3_FN_MOD_RD_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_FN_MOD_RD register field value. */ -#define ALT_L3_FN_MOD_RD_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_FN_MOD_RD register field. */ -#define ALT_L3_FN_MOD_RD_RESET 0x0 -/* Extracts the ALT_L3_FN_MOD_RD field value from a register. */ -#define ALT_L3_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_FN_MOD_RD register field value suitable for setting the register. */ -#define ALT_L3_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : wr - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:-------------------------------------------- - * ALT_L3_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions - * ALT_L3_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_FN_MOD_WR - * - * Multiple outstanding write transactions - */ -#define ALT_L3_FN_MOD_WR_E_MULT 0x0 -/* - * Enumerated value for register field ALT_L3_FN_MOD_WR - * - * Only a single outstanding write transaction - */ -#define ALT_L3_FN_MOD_WR_E_SINGLE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_WR register field. */ -#define ALT_L3_FN_MOD_WR_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_WR register field. */ -#define ALT_L3_FN_MOD_WR_MSB 1 -/* The width in bits of the ALT_L3_FN_MOD_WR register field. */ -#define ALT_L3_FN_MOD_WR_WIDTH 1 -/* The mask used to set the ALT_L3_FN_MOD_WR register field value. */ -#define ALT_L3_FN_MOD_WR_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_FN_MOD_WR register field value. */ -#define ALT_L3_FN_MOD_WR_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_FN_MOD_WR register field. */ -#define ALT_L3_FN_MOD_WR_RESET 0x0 -/* Extracts the ALT_L3_FN_MOD_WR field value from a register. */ -#define ALT_L3_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_FN_MOD_WR register field value suitable for setting the register. */ -#define ALT_L3_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_FN_MOD. - */ -struct ALT_L3_FN_MOD_s -{ - uint32_t rd : 1; /* ALT_L3_FN_MOD_RD */ - uint32_t wr : 1; /* ALT_L3_FN_MOD_WR */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_FN_MOD. */ -typedef volatile struct ALT_L3_FN_MOD_s ALT_L3_FN_MOD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_FN_MOD register from the beginning of the component. */ -#define ALT_L3_FN_MOD_OFST 0x108 -/* The address of the ALT_L3_FN_MOD register. */ -#define ALT_L3_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_STM. - */ -struct ALT_L3_MST_STM_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_MST_STM. */ -typedef volatile struct ALT_L3_MST_STM_s ALT_L3_MST_STM_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_STM. */ -struct ALT_L3_MST_STM_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_STM. */ -typedef volatile struct ALT_L3_MST_STM_raw_s ALT_L3_MST_STM_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : LWHPS2FPGA - ALT_L3_MST_LWH2F - * LWHPS2FPGA - * - * Registers associated with the LWHPS2FPGA AXI Bridge master. This master is used - * to access the LWHPS2FPGA AXI Bridge slave. This slave is used to access the - * registers for all 3 AXI bridges and to access slaves in the FPGA connected to - * the LWHPS2FPGA AXI Bridge. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_LWH2F. - */ -struct ALT_L3_MST_LWH2F_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_MST_LWH2F. */ -typedef volatile struct ALT_L3_MST_LWH2F_s ALT_L3_MST_LWH2F_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */ -struct ALT_L3_MST_LWH2F_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */ -typedef volatile struct ALT_L3_MST_LWH2F_raw_s ALT_L3_MST_LWH2F_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : USB1 - ALT_L3_MST_USB1 - * USB1 - * - * Registers associated with the USB1 master. This master is used to access the - * registers in USB1. - * - */ -/* - * Register : AHB Control Register - ahb_cntl - * - * Sets the block issuing capability to one outstanding transaction. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------- - * [0] | RW | 0x0 | ALT_L3_AHB_CNTL_DECERR_EN - * [1] | RW | 0x0 | ALT_L3_AHB_CNTL_FORCE_INCR - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : decerr_en - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------|:------|:------------------------------------------------- - * ALT_L3_AHB_CNTL_DECERR_EN_E_DIS | 0x0 | No DECERR response. - * ALT_L3_AHB_CNTL_DECERR_EN_E_EN | 0x1 | If the AHB protocol conversion function receives - * : | | an unaligned address or a write data beat - * : | | without all the byte strobes set, creates a - * : | | DECERR response. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN - * - * No DECERR response. - */ -#define ALT_L3_AHB_CNTL_DECERR_EN_E_DIS 0x0 -/* - * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN - * - * If the AHB protocol conversion function receives an unaligned address or a write - * data beat without all the byte strobes set, creates a DECERR response. - */ -#define ALT_L3_AHB_CNTL_DECERR_EN_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ -#define ALT_L3_AHB_CNTL_DECERR_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ -#define ALT_L3_AHB_CNTL_DECERR_EN_MSB 0 -/* The width in bits of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ -#define ALT_L3_AHB_CNTL_DECERR_EN_WIDTH 1 -/* The mask used to set the ALT_L3_AHB_CNTL_DECERR_EN register field value. */ -#define ALT_L3_AHB_CNTL_DECERR_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_AHB_CNTL_DECERR_EN register field value. */ -#define ALT_L3_AHB_CNTL_DECERR_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_AHB_CNTL_DECERR_EN register field. */ -#define ALT_L3_AHB_CNTL_DECERR_EN_RESET 0x0 -/* Extracts the ALT_L3_AHB_CNTL_DECERR_EN field value from a register. */ -#define ALT_L3_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_AHB_CNTL_DECERR_EN register field value suitable for setting the register. */ -#define ALT_L3_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : force_incr - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:------------------------------------------------- - * ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS | 0x0 | Multiple outstanding write transactions - * ALT_L3_AHB_CNTL_FORCE_INCR_E_EN | 0x1 | If a beat is received that has no write data - * : | | strobes set, that write data beat is replaced - * : | | with an IDLE beat. Also, causes all transactions - * : | | that are to be output to the AHB domain to be an - * : | | undefined length INCR. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR - * - * Multiple outstanding write transactions - */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS 0x0 -/* - * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR - * - * If a beat is received that has no write data strobes set, that write data beat - * is replaced with an IDLE beat. Also, causes all transactions that are to be - * output to the AHB domain to be an undefined length INCR. - */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_MSB 1 -/* The width in bits of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_WIDTH 1 -/* The mask used to set the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_RESET 0x0 -/* Extracts the ALT_L3_AHB_CNTL_FORCE_INCR field value from a register. */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_AHB_CNTL_FORCE_INCR register field value suitable for setting the register. */ -#define ALT_L3_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_AHB_CNTL. - */ -struct ALT_L3_AHB_CNTL_s -{ - uint32_t decerr_en : 1; /* ALT_L3_AHB_CNTL_DECERR_EN */ - uint32_t force_incr : 1; /* ALT_L3_AHB_CNTL_FORCE_INCR */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_AHB_CNTL. */ -typedef volatile struct ALT_L3_AHB_CNTL_s ALT_L3_AHB_CNTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_AHB_CNTL register from the beginning of the component. */ -#define ALT_L3_AHB_CNTL_OFST 0x44 -/* The address of the ALT_L3_AHB_CNTL register. */ -#define ALT_L3_AHB_CNTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_AHB_CNTL_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_USB1. - */ -struct ALT_L3_MST_USB1_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ - volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ -}; - -/* The typedef declaration for register group ALT_L3_MST_USB1. */ -typedef volatile struct ALT_L3_MST_USB1_s ALT_L3_MST_USB1_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB1. */ -struct ALT_L3_MST_USB1_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ - volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB1. */ -typedef volatile struct ALT_L3_MST_USB1_raw_s ALT_L3_MST_USB1_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : NANDDATA - ALT_L3_MST_NANDDATA - * NANDDATA - * - * Registers associated with the NANDDATA master. This master is used to access - * data in the NAND flash controller. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_NANDDATA. - */ -struct ALT_L3_MST_NANDDATA_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_MST_NANDDATA. */ -typedef volatile struct ALT_L3_MST_NANDDATA_s ALT_L3_MST_NANDDATA_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */ -struct ALT_L3_MST_NANDDATA_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */ -typedef volatile struct ALT_L3_MST_NANDDATA_raw_s ALT_L3_MST_NANDDATA_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : USB0 - ALT_L3_MST_USB0 - * USB0 - * - * Registers associated with the USB0 master. This master is used to access the - * registers in USB0. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_USB0. - */ -struct ALT_L3_MST_USB0_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ - volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ -}; - -/* The typedef declaration for register group ALT_L3_MST_USB0. */ -typedef volatile struct ALT_L3_MST_USB0_s ALT_L3_MST_USB0_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_USB0. */ -struct ALT_L3_MST_USB0_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ - volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB0. */ -typedef volatile struct ALT_L3_MST_USB0_raw_s ALT_L3_MST_USB0_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : NANDREGS - ALT_L3_MST_NAND - * NANDREGS - * - * Registers associated with the NANDREGS master. This master is used to access the - * registers in the NAND flash controller. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_NAND. - */ -struct ALT_L3_MST_NAND_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_MST_NAND. */ -typedef volatile struct ALT_L3_MST_NAND_s ALT_L3_MST_NAND_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_NAND. */ -struct ALT_L3_MST_NAND_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_NAND. */ -typedef volatile struct ALT_L3_MST_NAND_raw_s ALT_L3_MST_NAND_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : QSPIDATA - ALT_L3_MST_QSPIDATA - * QSPIDATA - * - * Registers associated with the QSPIDATA master. This master is used to access - * data in the QSPI flash controller. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_QSPIDATA. - */ -struct ALT_L3_MST_QSPIDATA_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ - volatile ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */ -}; - -/* The typedef declaration for register group ALT_L3_MST_QSPIDATA. */ -typedef volatile struct ALT_L3_MST_QSPIDATA_s ALT_L3_MST_QSPIDATA_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */ -struct ALT_L3_MST_QSPIDATA_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */ - volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */ -typedef volatile struct ALT_L3_MST_QSPIDATA_raw_s ALT_L3_MST_QSPIDATA_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : FPGAMGRDATA - ALT_L3_MST_FPGAMGRDATA - * FPGAMGRDATA - * - * Registers associated with the FPGAMGRDATA master. This master is used to send - * FPGA configuration image data to the FPGA Manager. - * - */ -/* - * Register : Write Tidemark - wr_tidemark - * - * Controls the release of the transaction in the write data FIFO. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [3:0] | RW | 0x4 | Level - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Level - level - * - * Stalls the transaction in the write data FIFO until the number of occupied slots - * in the write data FIFO exceeds the level. Note that the transaction is released - * before this level is achieved if the network receives the WLAST beat or the - * write FIFO becomes full. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ -#define ALT_L3_WR_TIDEMARK_LEVEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ -#define ALT_L3_WR_TIDEMARK_LEVEL_MSB 3 -/* The width in bits of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ -#define ALT_L3_WR_TIDEMARK_LEVEL_WIDTH 4 -/* The mask used to set the ALT_L3_WR_TIDEMARK_LEVEL register field value. */ -#define ALT_L3_WR_TIDEMARK_LEVEL_SET_MSK 0x0000000f -/* The mask used to clear the ALT_L3_WR_TIDEMARK_LEVEL register field value. */ -#define ALT_L3_WR_TIDEMARK_LEVEL_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_L3_WR_TIDEMARK_LEVEL register field. */ -#define ALT_L3_WR_TIDEMARK_LEVEL_RESET 0x4 -/* Extracts the ALT_L3_WR_TIDEMARK_LEVEL field value from a register. */ -#define ALT_L3_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_L3_WR_TIDEMARK_LEVEL register field value suitable for setting the register. */ -#define ALT_L3_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_WR_TIDEMARK. - */ -struct ALT_L3_WR_TIDEMARK_s -{ - uint32_t level : 4; /* Level */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_WR_TIDEMARK. */ -typedef volatile struct ALT_L3_WR_TIDEMARK_s ALT_L3_WR_TIDEMARK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_WR_TIDEMARK register from the beginning of the component. */ -#define ALT_L3_WR_TIDEMARK_OFST 0x40 -/* The address of the ALT_L3_WR_TIDEMARK register. */ -#define ALT_L3_WR_TIDEMARK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_TIDEMARK_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_FPGAMGRDATA. - */ -struct ALT_L3_MST_FPGAMGRDATA_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ - volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ - volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_MST_FPGAMGRDATA. */ -typedef volatile struct ALT_L3_MST_FPGAMGRDATA_s ALT_L3_MST_FPGAMGRDATA_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */ -struct ALT_L3_MST_FPGAMGRDATA_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ - volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ - volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */ -typedef volatile struct ALT_L3_MST_FPGAMGRDATA_raw_s ALT_L3_MST_FPGAMGRDATA_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : HPS2FPGA - ALT_L3_MST_H2F - * HPS2FPGA - * - * Registers associated with the HPS2FPGA AXI Bridge master. This master is used to - * access the HPS2FPGA AXI Bridge slave. This slave is used to access slaves in the - * FPGA connected to the HPS2FPGA AXI Bridge. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_H2F. - */ -struct ALT_L3_MST_H2F_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ - volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ - volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_MST_H2F. */ -typedef volatile struct ALT_L3_MST_H2F_s ALT_L3_MST_H2F_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_H2F. */ -struct ALT_L3_MST_H2F_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ - volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ - volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_H2F. */ -typedef volatile struct ALT_L3_MST_H2F_raw_s ALT_L3_MST_H2F_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : ACP - ALT_L3_MST_ACP - * ACP - * - * Registers associated with the ACP master. This master is used to access the MPU - * ACP slave via the ACP ID Mapper. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_ACP. - */ -struct ALT_L3_MST_ACP_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_MST_ACP. */ -typedef volatile struct ALT_L3_MST_ACP_s ALT_L3_MST_ACP_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_ACP. */ -struct ALT_L3_MST_ACP_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ACP. */ -typedef volatile struct ALT_L3_MST_ACP_raw_s ALT_L3_MST_ACP_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Boot ROM - ALT_L3_MST_ROM - * Boot ROM - * - * Registers associated with the Boot ROM master. This master is used to access the - * contents of the Boot ROM. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_ROM. - */ -struct ALT_L3_MST_ROM_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_MST_ROM. */ -typedef volatile struct ALT_L3_MST_ROM_s ALT_L3_MST_ROM_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_ROM. */ -struct ALT_L3_MST_ROM_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_ROM. */ -typedef volatile struct ALT_L3_MST_ROM_raw_s ALT_L3_MST_ROM_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : On-chip RAM - ALT_L3_MST_OCRAM - * On-chip RAM - * - * Registers associated with the On-chip RAM master. This master is used to access - * the contents of the On-chip RAM. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MST_OCRAM. - */ -struct ALT_L3_MST_OCRAM_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ - volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ - volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_MST_OCRAM. */ -typedef volatile struct ALT_L3_MST_OCRAM_s ALT_L3_MST_OCRAM_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */ -struct ALT_L3_MST_OCRAM_raw_s -{ - volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */ - volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */ - volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ - volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */ -typedef volatile struct ALT_L3_MST_OCRAM_raw_s ALT_L3_MST_OCRAM_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_MSTGRP. - */ -struct ALT_L3_MSTGRP_s -{ - volatile ALT_L3_MST_L4MAIN_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */ - volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_L4SP_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */ - volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_L4MP_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */ - volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_L4OSC1_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */ - volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_L4SPIM_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */ - volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_STM_t mastergrp_stm; /* ALT_L3_MST_STM */ - volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_LWH2F_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */ - volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */ - volatile ALT_L3_MST_USB1_t mastergrp_usb1; /* ALT_L3_MST_USB1 */ - volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */ - volatile ALT_L3_MST_NANDDATA_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */ - volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */ - volatile ALT_L3_MST_USB0_t mastergrp_usb0; /* ALT_L3_MST_USB0 */ - volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */ - volatile ALT_L3_MST_NAND_t mastergrp_nandregs; /* ALT_L3_MST_NAND */ - volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_QSPIDATA_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */ - volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */ - volatile ALT_L3_MST_FPGAMGRDATA_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */ - volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_H2F_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */ - volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_ACP_t mastergrp_acp; /* ALT_L3_MST_ACP */ - volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_ROM_t mastergrp_rom; /* ALT_L3_MST_ROM */ - volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_OCRAM_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */ -}; - -/* The typedef declaration for register group ALT_L3_MSTGRP. */ -typedef volatile struct ALT_L3_MSTGRP_s ALT_L3_MSTGRP_t; -/* The struct declaration for the raw register contents of register group ALT_L3_MSTGRP. */ -struct ALT_L3_MSTGRP_raw_s -{ - volatile ALT_L3_MST_L4MAIN_raw_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */ - volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_L4SP_raw_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */ - volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_L4MP_raw_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */ - volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_L4OSC1_raw_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */ - volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_L4SPIM_raw_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */ - volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */ - volatile ALT_L3_MST_STM_raw_t mastergrp_stm; /* ALT_L3_MST_STM */ - volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_LWH2F_raw_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */ - volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */ - volatile ALT_L3_MST_USB1_raw_t mastergrp_usb1; /* ALT_L3_MST_USB1 */ - volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */ - volatile ALT_L3_MST_NANDDATA_raw_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */ - volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */ - volatile ALT_L3_MST_USB0_raw_t mastergrp_usb0; /* ALT_L3_MST_USB0 */ - volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */ - volatile ALT_L3_MST_NAND_raw_t mastergrp_nandregs; /* ALT_L3_MST_NAND */ - volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_QSPIDATA_raw_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */ - volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */ - volatile ALT_L3_MST_FPGAMGRDATA_raw_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */ - volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_H2F_raw_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */ - volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_ACP_raw_t mastergrp_acp; /* ALT_L3_MST_ACP */ - volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_ROM_raw_t mastergrp_rom; /* ALT_L3_MST_ROM */ - volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_MST_OCRAM_raw_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_MSTGRP. */ -typedef volatile struct ALT_L3_MSTGRP_raw_s ALT_L3_MSTGRP_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Slave Register Group - ALT_L3_SLVGRP - * Slave Register Group - * - * Registers associated with slave interfaces. - * - */ -/* - * Register Group : DAP - ALT_L3_SLV_DAP - * DAP - * - * Registers associated with the DAP slave interface. This slave is used by the DAP - * to access slaves attached to the L3/L4 Interconnect. - * - */ -/* - * Register : Functionality Modification 2 Register - fn_mod2 - * - * Controls bypass merge of upsizing/downsizing. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------- - * [0] | RW | 0x0 | Bypass Merge - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Bypass Merge - bypass_merge - * - * Controls bypass merge of upsizing/downsizing. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------|:------|:------------------------------------------------- - * ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER | 0x0 | The network can alter transactions. - * ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1 | The network does not alter any transactions that - * : | | could pass through the upsizer legally without - * : | | alteration. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE - * - * The network can alter transactions. - */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0 -/* - * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE - * - * The network does not alter any transactions that could pass through the upsizer - * legally without alteration. - */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_MSB 0 -/* The width in bits of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_WIDTH 1 -/* The mask used to set the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_RESET 0x0 -/* Extracts the ALT_L3_FN_MOD2_BYPASS_MERGE field value from a register. */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */ -#define ALT_L3_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_FN_MOD2. - */ -struct ALT_L3_FN_MOD2_s -{ - uint32_t bypass_merge : 1; /* Bypass Merge */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_FN_MOD2. */ -typedef volatile struct ALT_L3_FN_MOD2_s ALT_L3_FN_MOD2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_FN_MOD2 register from the beginning of the component. */ -#define ALT_L3_FN_MOD2_OFST 0x24 -/* The address of the ALT_L3_FN_MOD2 register. */ -#define ALT_L3_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD2_OFST)) - -/* - * Register : Functionality Modification AHB Register - fn_mod_ahb - * - * Controls how AHB-lite burst transactions are converted to AXI tranactions. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------- - * [0] | RW | 0x0 | Read Increment Override - * [1] | RW | 0x0 | Write Increment Override - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Read Increment Override - rd_incr_override - * - * Controls how AHB-lite read burst transactions are converted to AXI tranactions. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------|:------|:---------------------------------------------- - * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite read - * : | | bursts to AXI transactions in accordance with - * : | | the default behavior as specified in the ARM - * : | | NIC-301 documentation. - * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite read - * : | | bursts to AXI single transactions. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE - * - * The L3 Interconnect converts AHB-lite read bursts to AXI transactions in - * accordance with the default behavior as specified in the ARM NIC-301 - * documentation. - */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT 0x0 -/* - * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE - * - * The L3 Interconnect converts AHB-lite read bursts to AXI single transactions. - */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_MSB 0 -/* The width in bits of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_WIDTH 1 -/* The mask used to set the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET_MSK 0x00000001 -/* The mask used to clear the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_CLR_MSK 0xfffffffe -/* The reset value of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_RESET 0x0 -/* Extracts the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE field value from a register. */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value suitable for setting the register. */ -#define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Write Increment Override - wr_incr_override - * - * Controls how AHB-lite write burst transactions are converted to AXI tranactions. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------|:------|:---------------------------------------------- - * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite write - * : | | bursts to AXI transactions in accordance with - * : | | the default behavior as specified in the ARM - * : | | NIC-301 documentation. - * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite write - * : | | bursts to AXI single transactions. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE - * - * The L3 Interconnect converts AHB-lite write bursts to AXI transactions in - * accordance with the default behavior as specified in the ARM NIC-301 - * documentation. - */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT 0x0 -/* - * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE - * - * The L3 Interconnect converts AHB-lite write bursts to AXI single transactions. - */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_MSB 1 -/* The width in bits of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_WIDTH 1 -/* The mask used to set the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET_MSK 0x00000002 -/* The mask used to clear the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_CLR_MSK 0xfffffffd -/* The reset value of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_RESET 0x0 -/* Extracts the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE field value from a register. */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value suitable for setting the register. */ -#define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_FN_MOD_AHB. - */ -struct ALT_L3_FN_MOD_AHB_s -{ - uint32_t rd_incr_override : 1; /* Read Increment Override */ - uint32_t wr_incr_override : 1; /* Write Increment Override */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_FN_MOD_AHB. */ -typedef volatile struct ALT_L3_FN_MOD_AHB_s ALT_L3_FN_MOD_AHB_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_FN_MOD_AHB register from the beginning of the component. */ -#define ALT_L3_FN_MOD_AHB_OFST 0x28 -/* The address of the ALT_L3_FN_MOD_AHB register. */ -#define ALT_L3_FN_MOD_AHB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_AHB_OFST)) - -/* - * Register : Read Channel QoS Value - read_qos - * - * QoS (Quality of Service) value for the read channel. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [3:0] | RW | 0x0 | Priority - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Priority - pri - * - * QoS (Quality of Service) value for the read channel. A higher value has a higher - * priority. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_RD_QOS_PRI register field. */ -#define ALT_L3_RD_QOS_PRI_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_RD_QOS_PRI register field. */ -#define ALT_L3_RD_QOS_PRI_MSB 3 -/* The width in bits of the ALT_L3_RD_QOS_PRI register field. */ -#define ALT_L3_RD_QOS_PRI_WIDTH 4 -/* The mask used to set the ALT_L3_RD_QOS_PRI register field value. */ -#define ALT_L3_RD_QOS_PRI_SET_MSK 0x0000000f -/* The mask used to clear the ALT_L3_RD_QOS_PRI register field value. */ -#define ALT_L3_RD_QOS_PRI_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_L3_RD_QOS_PRI register field. */ -#define ALT_L3_RD_QOS_PRI_RESET 0x0 -/* Extracts the ALT_L3_RD_QOS_PRI field value from a register. */ -#define ALT_L3_RD_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_L3_RD_QOS_PRI register field value suitable for setting the register. */ -#define ALT_L3_RD_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_RD_QOS. - */ -struct ALT_L3_RD_QOS_s -{ - uint32_t pri : 4; /* Priority */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_RD_QOS. */ -typedef volatile struct ALT_L3_RD_QOS_s ALT_L3_RD_QOS_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_RD_QOS register from the beginning of the component. */ -#define ALT_L3_RD_QOS_OFST 0x100 -/* The address of the ALT_L3_RD_QOS register. */ -#define ALT_L3_RD_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_RD_QOS_OFST)) - -/* - * Register : Write Channel QoS Value - write_qos - * - * QoS (Quality of Service) value for the write channel. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [3:0] | RW | 0x0 | Priority - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Priority - pri - * - * QoS (Quality of Service) value for the write channel. A higher value has a - * higher priority. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_L3_WR_QOS_PRI register field. */ -#define ALT_L3_WR_QOS_PRI_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_L3_WR_QOS_PRI register field. */ -#define ALT_L3_WR_QOS_PRI_MSB 3 -/* The width in bits of the ALT_L3_WR_QOS_PRI register field. */ -#define ALT_L3_WR_QOS_PRI_WIDTH 4 -/* The mask used to set the ALT_L3_WR_QOS_PRI register field value. */ -#define ALT_L3_WR_QOS_PRI_SET_MSK 0x0000000f -/* The mask used to clear the ALT_L3_WR_QOS_PRI register field value. */ -#define ALT_L3_WR_QOS_PRI_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_L3_WR_QOS_PRI register field. */ -#define ALT_L3_WR_QOS_PRI_RESET 0x0 -/* Extracts the ALT_L3_WR_QOS_PRI field value from a register. */ -#define ALT_L3_WR_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_L3_WR_QOS_PRI register field value suitable for setting the register. */ -#define ALT_L3_WR_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_L3_WR_QOS. - */ -struct ALT_L3_WR_QOS_s -{ - uint32_t pri : 4; /* Priority */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_L3_WR_QOS. */ -typedef volatile struct ALT_L3_WR_QOS_s ALT_L3_WR_QOS_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_L3_WR_QOS register from the beginning of the component. */ -#define ALT_L3_WR_QOS_OFST 0x104 -/* The address of the ALT_L3_WR_QOS register. */ -#define ALT_L3_WR_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_QOS_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_DAP. - */ -struct ALT_L3_SLV_DAP_s -{ - volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD2_t fn_mod2; /* ALT_L3_FN_MOD2 */ - volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ - volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_DAP. */ -typedef volatile struct ALT_L3_SLV_DAP_s ALT_L3_SLV_DAP_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DAP. */ -struct ALT_L3_SLV_DAP_raw_s -{ - volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */ - volatile uint32_t fn_mod2; /* ALT_L3_FN_MOD2 */ - volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ - volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DAP. */ -typedef volatile struct ALT_L3_SLV_DAP_raw_s ALT_L3_SLV_DAP_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : MPU - ALT_L3_SLV_MPU - * MPU - * - * Registers associated with the MPU slave interface. This slave is used by the MPU - * to access slaves attached to the L3/L4 Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_MPU. - */ -struct ALT_L3_SLV_MPU_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_MPU. */ -typedef volatile struct ALT_L3_SLV_MPU_s ALT_L3_SLV_MPU_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_MPU. */ -struct ALT_L3_SLV_MPU_raw_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_MPU. */ -typedef volatile struct ALT_L3_SLV_MPU_raw_s ALT_L3_SLV_MPU_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : SDMMC - ALT_L3_SLV_SDMMC - * SDMMC - * - * Registers associated with the SDMMC slave interface. This slave is used by the - * DMA controller built into the SDMMC to access slaves attached to the L3/L4 - * Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_SDMMC. - */ -struct ALT_L3_SLV_SDMMC_s -{ - volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ - volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_SDMMC. */ -typedef volatile struct ALT_L3_SLV_SDMMC_s ALT_L3_SLV_SDMMC_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */ -struct ALT_L3_SLV_SDMMC_raw_s -{ - volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ - volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */ -typedef volatile struct ALT_L3_SLV_SDMMC_raw_s ALT_L3_SLV_SDMMC_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : DMA - ALT_L3_SLV_DMA - * DMA - * - * Registers associated with the DMA Controller slave interface. This slave is used - * by the DMA Controller to access slaves attached to the L3/L4 Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_DMA. - */ -struct ALT_L3_SLV_DMA_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_DMA. */ -typedef volatile struct ALT_L3_SLV_DMA_s ALT_L3_SLV_DMA_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_DMA. */ -struct ALT_L3_SLV_DMA_raw_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DMA. */ -typedef volatile struct ALT_L3_SLV_DMA_raw_s ALT_L3_SLV_DMA_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : FPGA2HPS - ALT_L3_SLV_F2H - * FPGA2HPS - * - * Registers associated with the FPGA2HPS AXI Bridge slave interface. This slave is - * used by the FPGA2HPS AXI Bridge to access slaves attached to the L3/L4 - * Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_F2H. - */ -struct ALT_L3_SLV_F2H_s -{ - volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */ - volatile ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ - volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_F2H. */ -typedef volatile struct ALT_L3_SLV_F2H_s ALT_L3_SLV_F2H_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_F2H. */ -struct ALT_L3_SLV_F2H_raw_s -{ - volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */ - volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */ - volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_F2H. */ -typedef volatile struct ALT_L3_SLV_F2H_raw_s ALT_L3_SLV_F2H_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : ETR - ALT_L3_SLV_ETR - * ETR - * - * Registers associated with the ETR (TMC) slave interface. This slave is used by - * the ETR to access slaves attached to the L3/L4 Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_ETR. - */ -struct ALT_L3_SLV_ETR_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_ETR. */ -typedef volatile struct ALT_L3_SLV_ETR_s ALT_L3_SLV_ETR_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_ETR. */ -struct ALT_L3_SLV_ETR_raw_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_ETR. */ -typedef volatile struct ALT_L3_SLV_ETR_raw_s ALT_L3_SLV_ETR_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : EMAC0 - ALT_L3_SLV_EMAC0 - * EMAC0 - * - * Registers associated with the EMAC0 slave interface. This slave is used by the - * DMA controller built into the EMAC0 to access slaves attached to the L3/L4 - * Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_EMAC0. - */ -struct ALT_L3_SLV_EMAC0_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_EMAC0. */ -typedef volatile struct ALT_L3_SLV_EMAC0_s ALT_L3_SLV_EMAC0_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */ -struct ALT_L3_SLV_EMAC0_raw_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */ -typedef volatile struct ALT_L3_SLV_EMAC0_raw_s ALT_L3_SLV_EMAC0_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : EMAC1 - ALT_L3_SLV_EMAC1 - * EMAC1 - * - * Registers associated with the EMAC1 slave interface. This slave is used by the - * DMA controller built into the EMAC1 to access slaves attached to the L3/L4 - * Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_EMAC1. - */ -struct ALT_L3_SLV_EMAC1_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_EMAC1. */ -typedef volatile struct ALT_L3_SLV_EMAC1_s ALT_L3_SLV_EMAC1_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */ -struct ALT_L3_SLV_EMAC1_raw_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */ -typedef volatile struct ALT_L3_SLV_EMAC1_raw_s ALT_L3_SLV_EMAC1_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : USB0 - ALT_L3_SLV_USB0 - * USB0 - * - * Registers associated with the USB0 slave interface. This slave is used by the - * DMA controller built into the USB0 to access slaves attached to the L3/L4 - * Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_USB0. - */ -struct ALT_L3_SLV_USB0_s -{ - volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ - volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_USB0. */ -typedef volatile struct ALT_L3_SLV_USB0_s ALT_L3_SLV_USB0_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB0. */ -struct ALT_L3_SLV_USB0_raw_s -{ - volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ - volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB0. */ -typedef volatile struct ALT_L3_SLV_USB0_raw_s ALT_L3_SLV_USB0_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : NAND - ALT_L3_SLV_NAND - * NAND - * - * Registers associated with the NAND slave interface. This slave is used by the - * DMA controller built into the NAND flash controller to access slaves attached to - * the L3/L4 Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_NAND. - */ -struct ALT_L3_SLV_NAND_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_NAND. */ -typedef volatile struct ALT_L3_SLV_NAND_s ALT_L3_SLV_NAND_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_NAND. */ -struct ALT_L3_SLV_NAND_raw_s -{ - volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_NAND. */ -typedef volatile struct ALT_L3_SLV_NAND_raw_s ALT_L3_SLV_NAND_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : USB1 - ALT_L3_SLV_USB1 - * USB1 - * - * Registers associated with the USB1 slave interface. This slave is used by the - * DMA controller built into the USB1 to access slaves attached to the L3/L4 - * Interconnect. - * - */ -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLV_USB1. - */ -struct ALT_L3_SLV_USB1_s -{ - volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ - volatile ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ - volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ - volatile ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */ - volatile ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */ - volatile ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for register group ALT_L3_SLV_USB1. */ -typedef volatile struct ALT_L3_SLV_USB1_s ALT_L3_SLV_USB1_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB1. */ -struct ALT_L3_SLV_USB1_raw_s -{ - volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */ - volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */ - volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */ - volatile uint32_t read_qos; /* ALT_L3_RD_QOS */ - volatile uint32_t write_qos; /* ALT_L3_WR_QOS */ - volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB1. */ -typedef volatile struct ALT_L3_SLV_USB1_raw_s ALT_L3_SLV_USB1_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3_SLVGRP. - */ -struct ALT_L3_SLVGRP_s -{ - volatile ALT_L3_SLV_DAP_t slavegrp_dap; /* ALT_L3_SLV_DAP */ - volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_MPU_t slavegrp_mpu; /* ALT_L3_SLV_MPU */ - volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_SDMMC_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */ - volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_DMA_t slavegrp_dma; /* ALT_L3_SLV_DMA */ - volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_F2H_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */ - volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_ETR_t slavegrp_etr; /* ALT_L3_SLV_ETR */ - volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_EMAC0_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */ - volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_EMAC1_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */ - volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_USB0_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */ - volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_NAND_t slavegrp_nand; /* ALT_L3_SLV_NAND */ - volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_USB1_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */ -}; - -/* The typedef declaration for register group ALT_L3_SLVGRP. */ -typedef volatile struct ALT_L3_SLVGRP_s ALT_L3_SLVGRP_t; -/* The struct declaration for the raw register contents of register group ALT_L3_SLVGRP. */ -struct ALT_L3_SLVGRP_raw_s -{ - volatile ALT_L3_SLV_DAP_raw_t slavegrp_dap; /* ALT_L3_SLV_DAP */ - volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_MPU_raw_t slavegrp_mpu; /* ALT_L3_SLV_MPU */ - volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_SDMMC_raw_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */ - volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_DMA_raw_t slavegrp_dma; /* ALT_L3_SLV_DMA */ - volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_F2H_raw_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */ - volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_ETR_raw_t slavegrp_etr; /* ALT_L3_SLV_ETR */ - volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_EMAC0_raw_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */ - volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_EMAC1_raw_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */ - volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_USB0_raw_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */ - volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_NAND_raw_t slavegrp_nand; /* ALT_L3_SLV_NAND */ - volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */ - volatile ALT_L3_SLV_USB1_raw_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3_SLVGRP. */ -typedef volatile struct ALT_L3_SLVGRP_raw_s ALT_L3_SLVGRP_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_L3. - */ -struct ALT_L3_s -{ - volatile ALT_L3_REMAP_t remap; /* ALT_L3_REMAP */ - volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ - volatile ALT_L3_SECGRP_t secgrp; /* ALT_L3_SECGRP */ - volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */ - volatile ALT_L3_IDGRP_t idgrp; /* ALT_L3_IDGRP */ - volatile ALT_L3_MSTGRP_t mastergrp; /* ALT_L3_MSTGRP */ - volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */ - volatile ALT_L3_SLVGRP_t slavegrp; /* ALT_L3_SLVGRP */ - volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_L3. */ -typedef volatile struct ALT_L3_s ALT_L3_t; -/* The struct declaration for the raw register contents of register group ALT_L3. */ -struct ALT_L3_raw_s -{ - volatile uint32_t remap; /* ALT_L3_REMAP */ - volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */ - volatile ALT_L3_SECGRP_raw_t secgrp; /* ALT_L3_SECGRP */ - volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */ - volatile ALT_L3_IDGRP_raw_t idgrp; /* ALT_L3_IDGRP */ - volatile ALT_L3_MSTGRP_raw_t mastergrp; /* ALT_L3_MSTGRP */ - volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */ - volatile ALT_L3_SLVGRP_raw_t slavegrp; /* ALT_L3_SLVGRP */ - volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_L3. */ -typedef volatile struct ALT_L3_raw_s ALT_L3_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_L3_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h deleted file mode 100644 index cbec31b76f..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspi.h +++ /dev/null @@ -1,5951 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_QSPI */ - -#ifndef __ALTERA_ALT_QSPI_H__ -#define __ALTERA_ALT_QSPI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : QSPI Flash Controller Module Registers - ALT_QSPI - * QSPI Flash Controller Module Registers - * - * Registers in the QSPI Flash Controller module accessible via its APB slave - * - */ -/* - * Register : QSPI Configuration Register - cfg - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------------------- - * [0] | RW | 0x0 | QSPI Enable - * [1] | RW | 0x0 | Clock Polarity - * [2] | RW | 0x0 | Select Clock Phase - * [6:3] | ??? | 0x0 | *UNDEFINED* - * [7] | RW | 0x0 | Enable Direct Access Controller - * [8] | RW | 0x0 | Legacy IP Mode Enable - * [9] | RW | 0x0 | Peripheral select decode - * [13:10] | RW | 0x0 | Peripheral Chip Select Lines - * [14] | RW | 0x0 | Write Protect Flash Pin - * [15] | RW | 0x0 | Enable DMA Peripheral Interface - * [16] | RW | 0x0 | Enable AHB Address Re-mapping - * [17] | RW | 0x0 | Enter XIP Mode on next READ - * [18] | RW | 0x0 | Enter XIP Mode Immediately - * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor - * [30:23] | ??? | 0x0 | *UNDEFINED* - * [31] | R | 0x0 | Serial interface and QSPI pipeline is IDLE - * - */ -/* - * Field : QSPI Enable - en - * - * If this bit is disabled, the QSPI will finish the current transfer of the data - * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output - * enables are inactive and all pins are set to input mode. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------|:------|:----------------- - * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI - * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_EN - * - * Disable the QSPI - */ -#define ALT_QSPI_CFG_EN_E_DIS 0x0 -/* - * Enumerated value for register field ALT_QSPI_CFG_EN - * - * Enable the QSPI - */ -#define ALT_QSPI_CFG_EN_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */ -#define ALT_QSPI_CFG_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */ -#define ALT_QSPI_CFG_EN_MSB 0 -/* The width in bits of the ALT_QSPI_CFG_EN register field. */ -#define ALT_QSPI_CFG_EN_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_EN register field value. */ -#define ALT_QSPI_CFG_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_QSPI_CFG_EN register field value. */ -#define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_QSPI_CFG_EN register field. */ -#define ALT_QSPI_CFG_EN_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_EN field value from a register. */ -#define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Clock Polarity - selclkpol - * - * Controls spiclk modes of operation. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:---------------------------- - * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low - * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL - * - * SPI clock is quiescent low - */ -#define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL - * - * SPI clock is quiescent high - */ -#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ -#define ALT_QSPI_CFG_SELCLKPOL_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */ -#define ALT_QSPI_CFG_SELCLKPOL_MSB 1 -/* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */ -#define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */ -#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002 -/* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */ -#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd -/* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */ -#define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */ -#define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Select Clock Phase - selclkphase - * - * Selects whether the clock is in an active or inactive phase outside the SPI - * word. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:--------------------------- - * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low - * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE - * - * SPI clock is quiescent low - */ -#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0 -/* - * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE - * - * Clock Inactive - */ -#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ -#define ALT_QSPI_CFG_SELCLKPHASE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */ -#define ALT_QSPI_CFG_SELCLKPHASE_MSB 2 -/* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */ -#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */ -#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */ -#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */ -#define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */ -#define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Enable Direct Access Controller - endiracc - * - * If disabled, the Direct Access Controller becomes inactive once the current - * transfer of the data word (FF_W) is complete. When the Direct Access Controller - * and Indirect Access Controller are both disabled, all AHB requests are completed - * with an error response. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:--------------------------- - * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl - * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC - * - * Disable Direct Access Ctrl - */ -#define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0 -/* - * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC - * - * Enable Direct Access Ctrl - */ -#define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ -#define ALT_QSPI_CFG_ENDIRACC_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */ -#define ALT_QSPI_CFG_ENDIRACC_MSB 7 -/* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */ -#define ALT_QSPI_CFG_ENDIRACC_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */ -#define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080 -/* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */ -#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f -/* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */ -#define ALT_QSPI_CFG_ENDIRACC_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */ -#define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : Legacy IP Mode Enable - enlegacyip - * - * This bit can select the Direct Access Controller/Indirect Access Controller or - * legacy mode.If legacy mode is selected, any write to the controller via the AHB - * interface is serialized and sent to the FLASH device. Any valid AHB read will - * pop the internal RX-FIFO, retrieving data that was forwarded by the external - * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and - * controlled via the HSIZE input. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:-------------------------------------- - * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode - * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP - * - * Legacy Mode - */ -#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP - * - * Use Direct/Indirect Access Controller - */ -#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ -#define ALT_QSPI_CFG_ENLEGACYIP_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */ -#define ALT_QSPI_CFG_ENLEGACYIP_MSB 8 -/* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */ -#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */ -#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100 -/* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */ -#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff -/* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */ -#define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */ -#define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Peripheral select decode - perseldec - * - * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The - * qspi_n_ss_out[3:0] output signals are controlled. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------- - * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode - * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0] - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC - * - * Select external 4-to-16 decode - */ -#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC - * - * Selects 1 of 4 qspi_n_ss_out[3:0] - */ -#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ -#define ALT_QSPI_CFG_PERSELDEC_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */ -#define ALT_QSPI_CFG_PERSELDEC_MSB 9 -/* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */ -#define ALT_QSPI_CFG_PERSELDEC_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */ -#define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200 -/* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */ -#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff -/* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */ -#define ALT_QSPI_CFG_PERSELDEC_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */ -#define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Peripheral Chip Select Lines - percslines - * - * Peripheral chip select line output decode type. As per perseldec, if perseldec = - * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The - * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0] - * require an external 4 to 16 decoder. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ -#define ALT_QSPI_CFG_PERCSLINES_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */ -#define ALT_QSPI_CFG_PERCSLINES_MSB 13 -/* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */ -#define ALT_QSPI_CFG_PERCSLINES_WIDTH 4 -/* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */ -#define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00 -/* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */ -#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff -/* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */ -#define ALT_QSPI_CFG_PERCSLINES_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */ -#define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10) -/* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00) - -/* - * Field : Write Protect Flash Pin - wp - * - * This bit controls the write protect pin of the flash devices. The signal - * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as - * necessary. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:---------------------- - * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect - * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_WP - * - * Enable Write Protect - */ -#define ALT_QSPI_CFG_WP_E_WRPROTON 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_WP - * - * Disable Write Protect - */ -#define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */ -#define ALT_QSPI_CFG_WP_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */ -#define ALT_QSPI_CFG_WP_MSB 14 -/* The width in bits of the ALT_QSPI_CFG_WP register field. */ -#define ALT_QSPI_CFG_WP_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_WP register field value. */ -#define ALT_QSPI_CFG_WP_SET_MSK 0x00004000 -/* The mask used to clear the ALT_QSPI_CFG_WP register field value. */ -#define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff -/* The reset value of the ALT_QSPI_CFG_WP register field. */ -#define ALT_QSPI_CFG_WP_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_WP field value from a register. */ -#define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000) - -/* - * Field : Enable DMA Peripheral Interface - endma - * - * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer - * requests via the DMA peripheral interface. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------|:------|:----------------- - * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode - * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_ENDMA - * - * Enable DMA Mode - */ -#define ALT_QSPI_CFG_ENDMA_E_EN 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_ENDMA - * - * Disable DMA Mode - */ -#define ALT_QSPI_CFG_ENDMA_E_DIS 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */ -#define ALT_QSPI_CFG_ENDMA_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */ -#define ALT_QSPI_CFG_ENDMA_MSB 15 -/* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */ -#define ALT_QSPI_CFG_ENDMA_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */ -#define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000 -/* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */ -#define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff -/* The reset value of the ALT_QSPI_CFG_ENDMA register field. */ -#define ALT_QSPI_CFG_ENDMA_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */ -#define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15) -/* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000) - -/* - * Field : Enable AHB Address Re-mapping - enahbremap - * - * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted - * and sent to the FLASH device as (address + N), where N is the value stored in - * the remap address register. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:----------------------- - * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping - * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP - * - * Enable AHB Re-mapping - */ -#define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP - * - * Disable AHB Re-mapping - */ -#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ -#define ALT_QSPI_CFG_ENAHBREMAP_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */ -#define ALT_QSPI_CFG_ENAHBREMAP_MSB 16 -/* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */ -#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */ -#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000 -/* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */ -#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff -/* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */ -#define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */ -#define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16) -/* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000) - -/* - * Field : Enter XIP Mode on next READ - enterxipnextrd - * - * If XIP is enabled, then setting to disabled will cause the controller to exit - * XIP mode on the next READ instruction. If XIP is disabled, then setting to - * enabled will inform the controller that the device is ready to enter XIP on the - * next READ instruction. The controller will therefore send the appropriate - * command sequence, including mode bits to cause the device to enter XIP mode. Use - * this register after the controller has ensured the FLASH device has been - * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit - * should be set to 0. This will take effect in the attached device only AFTER the - * next READ instruction is executed. Software should therefore ensure that at - * least one READ instruction is requested after resetting this bit before it can - * be sure XIP mode in the device is exited. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------------------- - * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction - * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD - * - * Enter XIP Mode on next READ instruction - */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD - * - * Exit XIP Mode on next READ instruction - */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17 -/* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000 -/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff -/* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17) -/* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000) - -/* - * Field : Enter XIP Mode Immediately - enterxipimm - * - * If XIP is enabled, then setting to disabled will cause the controller to exit - * XIP mode on the next READ instruction. If XIP is disabled, then setting enable - * will operate the device in XIP mode immediately. Use this register when the - * external device wakes up in XIP mode (as per the contents of its non- volatile - * configuration register). The controller will assume the next READ instruction - * will be passed to the device as an XIP instruction, and therefore will not - * require the READ opcode to be transferred. Note: To exit XIP mode, this bit - * should be set to 0. This will take effect in the attached device only after the - * next READ instruction is executed. Software therefore should ensure that at - * least one READ instruction is requested after resetting this bit in order to be - * sure that XIP mode is exited. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------|:------|:--------------------------------------- - * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately - * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM - * - * Enter XIP Mode immediately - */ -#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM - * - * Exit XIP Mode on next READ instruction - */ -#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ -#define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ -#define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18 -/* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ -#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ -#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000 -/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */ -#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff -/* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */ -#define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */ -#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18) -/* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000) - -/* - * Field : Master Mode Baud Rate Divisor - bauddiv - * - * SPI baud rate = ref_clk / (2 * baud_rate_divisor) - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:----------------- - * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30 - * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32 - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/2 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/4 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/6 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/8 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/10 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/12 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/14 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/16 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/18 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/20 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9 -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/22 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/24 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/26 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/28 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/30 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe -/* - * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV - * - * Baud Rate Div/32 - */ -#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ -#define ALT_QSPI_CFG_BAUDDIV_LSB 19 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */ -#define ALT_QSPI_CFG_BAUDDIV_MSB 22 -/* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */ -#define ALT_QSPI_CFG_BAUDDIV_WIDTH 4 -/* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */ -#define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000 -/* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */ -#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff -/* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */ -#define ALT_QSPI_CFG_BAUDDIV_RESET 0xf -/* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */ -#define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19) -/* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000) - -/* - * Field : Serial interface and QSPI pipeline is IDLE - idle - * - * This is a STATUS read-only bit. Note this is a retimed signal, so there will be - * some inherent delay on the generation of this status signal. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:-------------- - * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode - * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_CFG_IDLE - * - * Idle Mode - */ -#define ALT_QSPI_CFG_IDLE_E_SET 0x1 -/* - * Enumerated value for register field ALT_QSPI_CFG_IDLE - * - * Non-Idle Mode - */ -#define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */ -#define ALT_QSPI_CFG_IDLE_LSB 31 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */ -#define ALT_QSPI_CFG_IDLE_MSB 31 -/* The width in bits of the ALT_QSPI_CFG_IDLE register field. */ -#define ALT_QSPI_CFG_IDLE_WIDTH 1 -/* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */ -#define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000 -/* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */ -#define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff -/* The reset value of the ALT_QSPI_CFG_IDLE register field. */ -#define ALT_QSPI_CFG_IDLE_RESET 0x0 -/* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */ -#define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31) -/* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */ -#define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_CFG. - */ -struct ALT_QSPI_CFG_s -{ - uint32_t en : 1; /* QSPI Enable */ - uint32_t selclkpol : 1; /* Clock Polarity */ - uint32_t selclkphase : 1; /* Select Clock Phase */ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t endiracc : 1; /* Enable Direct Access Controller */ - uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */ - uint32_t perseldec : 1; /* Peripheral select decode */ - uint32_t percslines : 4; /* Peripheral Chip Select Lines */ - uint32_t wp : 1; /* Write Protect Flash Pin */ - uint32_t endma : 1; /* Enable DMA Peripheral Interface */ - uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */ - uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */ - uint32_t enterxipimm : 1; /* Enter XIP Mode Immediately */ - uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */ - uint32_t : 8; /* *UNDEFINED* */ - const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */ -}; - -/* The typedef declaration for register ALT_QSPI_CFG. */ -typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */ -#define ALT_QSPI_CFG_OFST 0x0 - -/* - * Register : Device Read Instruction Register - devrd - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:---------------------------- - * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode - * [9:8] | RW | 0x0 | Instruction Transfer Width - * [11:10] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | Address Transfer Width - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [17:16] | RW | 0x0 | Data Transfer Width - * [19:18] | ??? | 0x0 | *UNDEFINED* - * [20] | RW | 0x0 | Mode Bit Enable - * [23:21] | ??? | 0x0 | *UNDEFINED* - * [28:24] | RW | 0x0 | Dummy Read Clock Cycles - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Read Opcode in non-XIP mode - rdopcode - * - * Read Opcode to use when not in XIP mode - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------- - * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode - * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE - * - * Read Opcode in Non-XIP mode - */ -#define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 -/* - * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE - * - * Fast Read in Non-XIP mode - */ -#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ -#define ALT_QSPI_DEVRD_RDOPCODE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */ -#define ALT_QSPI_DEVRD_RDOPCODE_MSB 7 -/* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */ -#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8 -/* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */ -#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff -/* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */ -#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00 -/* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */ -#define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3 -/* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */ -#define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */ -#define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff) - -/* - * Field : Instruction Transfer Width - instwidth - * - * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions - * sent to SPI flash device (not just read instructions). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:------------------------------------------------- - * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all - * : | | SPI flash devices. - * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1. - * : | | Supported by all SPI flash devices that support - * : | | the Dual SP (DIO-SPI) Protocol. - * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and - * : | | DQ3. Supported by all SPI flash devices that - * : | | support the Quad SP (QIO-SPI) Protocol. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH - * - * Instruction transferred on DQ0. Supported by all SPI flash devices. - */ -#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 -/* - * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH - * - * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that - * support the Dual SP (DIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 -/* - * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH - * - * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash - * devices that support the Quad SP (QIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ -#define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ -#define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9 -/* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ -#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2 -/* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ -#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300 -/* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */ -#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff -/* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */ -#define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0 -/* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */ -#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8) -/* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */ -#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300) - -/* - * Field : Address Transfer Width - addrwidth - * - * Sets read address transfer width (1, 2, or 4 bits). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:------------------------------------------------- - * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by - * : | | all SPI flash devices - * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. - * : | | Supported by some SPI flash devices that support - * : | | the Extended SPI Protocol and by all SPI flash - * : | | devices that support the Dual SP (DIO-SPI) - * : | | Protocol. - * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and - * : | | DQ3. Supported by some SPI flash devices that - * : | | support the Extended SPI Protocol and by all SPI - * : | | flash devices that support the Quad SP (QIO-SPI) - * : | | Protocol. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH - * - * Read address transferred on DQ0. Supported by all SPI flash devices - */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 -/* - * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH - * - * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices - * that support the Extended SPI Protocol and by all SPI flash devices that support - * the Dual SP (DIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 -/* - * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH - * - * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash - * devices that support the Extended SPI Protocol and by all SPI flash devices that - * support the Quad SP (QIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13 -/* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2 -/* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000 -/* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff -/* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0 -/* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */ -#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Data Transfer Width - datawidth - * - * Sets read data transfer width (1, 2, or 4 bits). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:------------------------------------------------- - * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all - * : | | SPI flash devices - * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported - * : | | by some SPI flash devices that support the - * : | | Extended SPI Protocol and by all SPI flash - * : | | devices that support the Dual SP (DIO-SPI) - * : | | Protocol. - * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. - * : | | Supported by some SPI flash devices that support - * : | | the Extended SPI Protocol and by all SPI flash - * : | | devices that support the Quad SP (QIO-SPI) - * : | | Protocol. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH - * - * Read data transferred on DQ0. Supported by all SPI flash devices - */ -#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 -/* - * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH - * - * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that - * support the Extended SPI Protocol and by all SPI flash devices that support the - * Dual SP (DIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 -/* - * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH - * - * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash - * devices that support the Extended SPI Protocol and by all SPI flash devices that - * support the Quad SP (QIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ -#define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ -#define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17 -/* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ -#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2 -/* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ -#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000 -/* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */ -#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff -/* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */ -#define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0 -/* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */ -#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) -/* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */ -#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) - -/* - * Field : Mode Bit Enable - enmodebits - * - * If this bit is set, the mode bits as defined in the Mode Bit Configuration - * register are sent following the address bytes. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:------------------------------- - * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order - * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS - * - * No Order - */ -#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 -/* - * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS - * - * Mode Bits follow address bytes - */ -#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ -#define ALT_QSPI_DEVRD_ENMODBITS_LSB 20 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */ -#define ALT_QSPI_DEVRD_ENMODBITS_MSB 20 -/* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */ -#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1 -/* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */ -#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000 -/* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */ -#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff -/* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */ -#define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0 -/* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */ -#define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20) -/* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */ -#define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000) - -/* - * Field : Dummy Read Clock Cycles - dummyrdclks - * - * Number of dummy clock cycles required by device for read instruction. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ -#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ -#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28 -/* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ -#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5 -/* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ -#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000 -/* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */ -#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff -/* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */ -#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0 -/* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */ -#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24) -/* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */ -#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_DEVRD. - */ -struct ALT_QSPI_DEVRD_s -{ - uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */ - uint32_t instwidth : 2; /* Instruction Transfer Width */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t addrwidth : 2; /* Address Transfer Width */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t datawidth : 2; /* Data Transfer Width */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t enmodebits : 1; /* Mode Bit Enable */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_DEVRD. */ -typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */ -#define ALT_QSPI_DEVRD_OFST 0x4 - -/* - * Register : Device Write Instruction Register - devwr - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------- - * [7:0] | RW | 0x2 | Write Opcode - * [11:8] | ??? | 0x0 | *UNDEFINED* - * [13:12] | RW | 0x0 | Address Transfer Width - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [17:16] | RW | 0x0 | Data Transfer Width - * [23:18] | ??? | 0x0 | *UNDEFINED* - * [28:24] | RW | 0x0 | Dummy Write Clock Cycles - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Write Opcode - wropcode - * - * Write Opcode - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ -#define ALT_QSPI_DEVWR_WROPCODE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */ -#define ALT_QSPI_DEVWR_WROPCODE_MSB 7 -/* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */ -#define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8 -/* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */ -#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff -/* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */ -#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00 -/* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */ -#define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2 -/* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */ -#define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */ -#define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff) - -/* - * Field : Address Transfer Width - addrwidth - * - * Sets write address transfer width (1, 2, or 4 bits). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:------------------------------------------------- - * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by - * : | | all SPI flash devices - * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1. - * : | | Supported by some SPI flash devices that support - * : | | the Extended SPI Protocol and by all SPI flash - * : | | devices that support the Dual SP (DIO-SPI) - * : | | Protocol. - * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and - * : | | DQ3. Supported by some SPI flash devices that - * : | | support the Extended SPI Protocol and by all SPI - * : | | flash devices that support the Quad SP (QIO-SPI) - * : | | Protocol. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH - * - * Write address transferred on DQ0. Supported by all SPI flash devices - */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0 -/* - * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH - * - * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices - * that support the Extended SPI Protocol and by all SPI flash devices that support - * the Dual SP (DIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1 -/* - * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH - * - * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash - * devices that support the Extended SPI Protocol and by all SPI flash devices that - * support the Quad SP (QIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13 -/* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2 -/* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000 -/* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff -/* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0 -/* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) -/* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */ -#define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) - -/* - * Field : Data Transfer Width - datawidth - * - * Sets write data transfer width (1, 2, or 4 bits). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:------------------------------------------------- - * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all - * : | | SPI flash devices - * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported - * : | | by some SPI flash devices that support the - * : | | Extended SPI Protocol and by all SPI flash - * : | | devices that support the Dual SP (DIO-SPI) - * : | | Protocol. - * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3. - * : | | Supported by some SPI flash devices that support - * : | | the Extended SPI Protocol and by all SPI flash - * : | | devices that support the Quad SP (QIO-SPI) - * : | | Protocol. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH - * - * Write data transferred on DQ0. Supported by all SPI flash devices - */ -#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0 -/* - * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH - * - * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that - * support the Extended SPI Protocol and by all SPI flash devices that support the - * Dual SP (DIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1 -/* - * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH - * - * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash - * devices that support the Extended SPI Protocol and by all SPI flash devices that - * support the Quad SP (QIO-SPI) Protocol. - */ -#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ -#define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ -#define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17 -/* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ -#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2 -/* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ -#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000 -/* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */ -#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff -/* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */ -#define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0 -/* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */ -#define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) -/* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */ -#define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) - -/* - * Field : Dummy Write Clock Cycles - dummywrclks - * - * Number of dummy clock cycles required by device for write instruction. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ -#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ -#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28 -/* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ -#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5 -/* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ -#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000 -/* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */ -#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff -/* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */ -#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0 -/* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */ -#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24) -/* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */ -#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_DEVWR. - */ -struct ALT_QSPI_DEVWR_s -{ - uint32_t wropcode : 8; /* Write Opcode */ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t addrwidth : 2; /* Address Transfer Width */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t datawidth : 2; /* Data Transfer Width */ - uint32_t : 6; /* *UNDEFINED* */ - uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_DEVWR. */ -typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */ -#define ALT_QSPI_DEVWR_OFST 0x8 - -/* - * Register : QSPI Device Delay Register - delay - * - * This register is used to introduce relative delays into the generation of the - * master output signals. All timings are defined in cycles of the qspi_clk. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------------------------- - * [7:0] | RW | 0x0 | Clock Delay with qspi_n_ss_out - * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit - * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation - * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert - * - */ -/* - * Field : Clock Delay with qspi_n_ss_out - init - * - * Delay in master reference clocks between setting qspi_n_ss_out low and first bit - * transfer. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */ -#define ALT_QSPI_DELAY_INIT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */ -#define ALT_QSPI_DELAY_INIT_MSB 7 -/* The width in bits of the ALT_QSPI_DELAY_INIT register field. */ -#define ALT_QSPI_DELAY_INIT_WIDTH 8 -/* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */ -#define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff -/* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */ -#define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00 -/* The reset value of the ALT_QSPI_DELAY_INIT register field. */ -#define ALT_QSPI_DELAY_INIT_RESET 0x0 -/* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */ -#define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */ -#define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff) - -/* - * Field : Clock Delay for Last Transaction Bit - after - * - * Delay in master reference clocks between last bit of current transaction and - * deasserting the device chip select (qspi_n_ss_out). By default, the chip select - * will be deasserted on the cycle following the completion of the current - * transaction. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */ -#define ALT_QSPI_DELAY_AFTER_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */ -#define ALT_QSPI_DELAY_AFTER_MSB 15 -/* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */ -#define ALT_QSPI_DELAY_AFTER_WIDTH 8 -/* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */ -#define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00 -/* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */ -#define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff -/* The reset value of the ALT_QSPI_DELAY_AFTER register field. */ -#define ALT_QSPI_DELAY_AFTER_RESET 0x0 -/* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */ -#define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8) -/* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */ -#define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00) - -/* - * Field : Clock Delay for Chip Select Deactivation - btwn - * - * Delay in master reference clocks between one chip select being de-activated and - * the activation of another. This is used to ensure a quiet period between the - * selection of two different slaves and requires the transmit FIFO to be empty. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */ -#define ALT_QSPI_DELAY_BTWN_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */ -#define ALT_QSPI_DELAY_BTWN_MSB 23 -/* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */ -#define ALT_QSPI_DELAY_BTWN_WIDTH 8 -/* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */ -#define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000 -/* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */ -#define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff -/* The reset value of the ALT_QSPI_DELAY_BTWN register field. */ -#define ALT_QSPI_DELAY_BTWN_RESET 0x0 -/* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */ -#define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16) -/* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */ -#define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000) - -/* - * Field : Clock Delay for Chip Select Deassert - nss - * - * Delay in master reference clocks for the length that the master mode chip select - * outputs are de-asserted between transactions. The minimum delay is always - * qspi_sck_out period to ensure the chip select is never re-asserted within an - * qspi_sck_out period. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */ -#define ALT_QSPI_DELAY_NSS_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */ -#define ALT_QSPI_DELAY_NSS_MSB 31 -/* The width in bits of the ALT_QSPI_DELAY_NSS register field. */ -#define ALT_QSPI_DELAY_NSS_WIDTH 8 -/* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */ -#define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000 -/* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */ -#define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff -/* The reset value of the ALT_QSPI_DELAY_NSS register field. */ -#define ALT_QSPI_DELAY_NSS_RESET 0x0 -/* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */ -#define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24) -/* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */ -#define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_DELAY. - */ -struct ALT_QSPI_DELAY_s -{ - uint32_t init : 8; /* Clock Delay with qspi_n_ss_out */ - uint32_t after : 8; /* Clock Delay for Last Transaction Bit */ - uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */ - uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */ -}; - -/* The typedef declaration for register ALT_QSPI_DELAY. */ -typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */ -#define ALT_QSPI_DELAY_OFST 0xc - -/* - * Register : Read Data Capture Register - rddatacap - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [0] | RW | 0x1 | Bypass - * [4:1] | RW | 0x0 | Read Delay - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Bypass - byp - * - * Controls bypass of the adapted loopback clock circuit - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:------------------------------ - * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0 | No Bypass - * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x1 | Bypass loopback clock circuit - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP - * - * No Bypass - */ -#define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0 -/* - * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP - * - * Bypass loopback clock circuit - */ -#define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ -#define ALT_QSPI_RDDATACAP_BYP_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */ -#define ALT_QSPI_RDDATACAP_BYP_MSB 0 -/* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */ -#define ALT_QSPI_RDDATACAP_BYP_WIDTH 1 -/* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */ -#define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001 -/* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */ -#define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe -/* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */ -#define ALT_QSPI_RDDATACAP_BYP_RESET 0x1 -/* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */ -#define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */ -#define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Read Delay - delay - * - * Delay the read data capturing logic by the programmed number of qspi_clk cycles - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ -#define ALT_QSPI_RDDATACAP_DELAY_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */ -#define ALT_QSPI_RDDATACAP_DELAY_MSB 4 -/* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */ -#define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4 -/* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */ -#define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e -/* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */ -#define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1 -/* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */ -#define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0 -/* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */ -#define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1) -/* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */ -#define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_RDDATACAP. - */ -struct ALT_QSPI_RDDATACAP_s -{ - uint32_t byp : 1; /* Bypass */ - uint32_t delay : 4; /* Read Delay */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_RDDATACAP. */ -typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */ -#define ALT_QSPI_RDDATACAP_OFST 0x10 - -/* - * Register : Device Size Register - devsz - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------------------- - * [3:0] | RW | 0x2 | Number of address Bytes - * [15:4] | RW | 0x100 | Number of Bytes per Device Page - * [20:16] | RW | 0x10 | Number of Bytes per Block - * [31:21] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Number of address Bytes - numaddrbytes - * - * Number of address bytes. A value of 0 indicates 1 byte. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ -#define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ -#define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3 -/* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ -#define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4 -/* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ -#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f -/* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */ -#define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */ -#define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2 -/* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */ -#define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */ -#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f) - -/* - * Field : Number of Bytes per Device Page - bytesperdevicepage - * - * Number of bytes per device page. This is required by the controller for - * performing FLASH writes up to and across page boundaries. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ -#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ -#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15 -/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ -#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12 -/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ -#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0 -/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */ -#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f -/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */ -#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100 -/* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */ -#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4) -/* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */ -#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0) - -/* - * Field : Number of Bytes per Block - bytespersubsector - * - * Number of bytes per Block. This is required by the controller for performing the - * write protection logic. The number of bytes per block must be a power of 2 - * number. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ -#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ -#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20 -/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ -#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5 -/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ -#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000 -/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */ -#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff -/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */ -#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10 -/* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */ -#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16) -/* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */ -#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_DEVSZ. - */ -struct ALT_QSPI_DEVSZ_s -{ - uint32_t numaddrbytes : 4; /* Number of address Bytes */ - uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */ - uint32_t bytespersubsector : 5; /* Number of Bytes per Block */ - uint32_t : 11; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_DEVSZ. */ -typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */ -#define ALT_QSPI_DEVSZ_OFST 0x14 - -/* - * Register : SRAM Partition Register - srampart - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [6:0] | RW | 0x40 | Indirect Read Partition Size - * [31:7] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Indirect Read Partition Size - addr - * - * Defines the size of the indirect read partition in the SRAM, in units of SRAM - * locations. By default, half of the SRAM is reserved for indirect read operations - * and half for indirect write operations. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ -#define ALT_QSPI_SRAMPART_ADDR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */ -#define ALT_QSPI_SRAMPART_ADDR_MSB 6 -/* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */ -#define ALT_QSPI_SRAMPART_ADDR_WIDTH 7 -/* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */ -#define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f -/* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */ -#define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80 -/* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */ -#define ALT_QSPI_SRAMPART_ADDR_RESET 0x40 -/* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */ -#define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0) -/* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */ -#define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_SRAMPART. - */ -struct ALT_QSPI_SRAMPART_s -{ - uint32_t addr : 7; /* Indirect Read Partition Size */ - uint32_t : 25; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_SRAMPART. */ -typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */ -#define ALT_QSPI_SRAMPART_OFST 0x18 - -/* - * Register : Indirect AHB Address Trigger Register - indaddrtrig - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------- - * [31:0] | RW | 0x0 | Trigger Address - * - */ -/* - * Field : Trigger Address - addr - * - * This is the base address that will be used by the AHB controller. When the - * incoming AHB read access address matches a range of addresses from this trigger - * address to the trigger address + 15, then the AHB request will be completed by - * fetching data from the Indirect Controllers SRAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ -#define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ -#define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31 -/* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ -#define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32 -/* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ -#define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */ -#define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */ -#define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0 -/* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */ -#define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */ -#define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_INDADDRTRIG. - */ -struct ALT_QSPI_INDADDRTRIG_s -{ - uint32_t addr : 32; /* Trigger Address */ -}; - -/* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */ -typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */ -#define ALT_QSPI_INDADDRTRIG_OFST 0x1c - -/* - * Register : DMA Peripheral Register - dmaper - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------- - * [3:0] | RW | 0x0 | Number of Single Bytes - * [7:4] | ??? | 0x0 | *UNDEFINED* - * [11:8] | RW | 0x0 | Number of Burst Bytes - * [31:12] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Number of Single Bytes - numsglreqbytes - * - * Number of bytes in a single type request on the DMA peripheral request. A - * programmed value of 0 represents a single byte. This should be setup before - * starting the indirect read or write operation. The actual number of bytes used - * is 2**(value in this register) which will simplify implementation. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ -#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ -#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3 -/* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ -#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4 -/* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ -#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f -/* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */ -#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */ -#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0 -/* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */ -#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */ -#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f) - -/* - * Field : Number of Burst Bytes - numburstreqbytes - * - * Number of bytes in a burst type request on the DMA peripheral request. A - * programmed value of 0 represents a single byte. This should be setup before - * starting the indirect read or write operation. The actual number of bytes used - * is 2**(value in this register) which will simplify implementation. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ -#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ -#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11 -/* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ -#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4 -/* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ -#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00 -/* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */ -#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff -/* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */ -#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0 -/* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */ -#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8) -/* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */ -#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_DMAPER. - */ -struct ALT_QSPI_DMAPER_s -{ - uint32_t numsglreqbytes : 4; /* Number of Single Bytes */ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */ - uint32_t : 20; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_DMAPER. */ -typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */ -#define ALT_QSPI_DMAPER_OFST 0x20 - -/* - * Register : Remap Address Register - remapaddr - * - * This register is used to remap an incoming AHB address to a different address - * used by the FLASH device. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------- - * [31:0] | RW | 0x0 | Remap Address Offset - * - */ -/* - * Field : Remap Address Offset - value - * - * This offset is added to the incoming AHB address to determine the address used - * by the FLASH device. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ -#define ALT_QSPI_REMAPADDR_VALUE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */ -#define ALT_QSPI_REMAPADDR_VALUE_MSB 31 -/* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */ -#define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32 -/* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */ -#define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */ -#define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */ -#define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0 -/* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */ -#define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */ -#define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_REMAPADDR. - */ -struct ALT_QSPI_REMAPADDR_s -{ - uint32_t value : 32; /* Remap Address Offset */ -}; - -/* The typedef declaration for register ALT_QSPI_REMAPADDR. */ -typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */ -#define ALT_QSPI_REMAPADDR_OFST 0x24 - -/* - * Register : Mode Bit Register - modebit - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [7:0] | RW | 0x0 | Mode - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Mode - mode - * - * These are the 8 mode bits that are sent to the device following the address - * bytes if mode bit transmission has been enabled. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */ -#define ALT_QSPI_MODBIT_MOD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */ -#define ALT_QSPI_MODBIT_MOD_MSB 7 -/* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */ -#define ALT_QSPI_MODBIT_MOD_WIDTH 8 -/* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */ -#define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff -/* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */ -#define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00 -/* The reset value of the ALT_QSPI_MODBIT_MOD register field. */ -#define ALT_QSPI_MODBIT_MOD_RESET 0x0 -/* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */ -#define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */ -#define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_MODBIT. - */ -struct ALT_QSPI_MODBIT_s -{ - uint32_t mode : 8; /* Mode */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_MODBIT. */ -typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */ -#define ALT_QSPI_MODBIT_OFST 0x28 - -/* - * Register : SRAM Fill Register - sramfill - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------------------------------------------- - * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - * - */ -/* - * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ -#define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ -#define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15 -/* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ -#define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16 -/* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ -#define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */ -#define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000 -/* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */ -#define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0 -/* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */ -#define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */ -#define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff) - -/* - * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ -#define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ -#define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31 -/* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ -#define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16 -/* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ -#define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000 -/* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */ -#define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff -/* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */ -#define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0 -/* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */ -#define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16) -/* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */ -#define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_SRAMFILL. - */ -struct ALT_QSPI_SRAMFILL_s -{ - const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */ - const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */ -}; - -/* The typedef declaration for register ALT_QSPI_SRAMFILL. */ -typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */ -#define ALT_QSPI_SRAMFILL_OFST 0x2c - -/* - * Register : TX Threshold Register - txthresh - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [3:0] | RW | 0x1 | Level - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Level - level - * - * Defines the level at which the transmit FIFO not full interrupt is generated - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ -#define ALT_QSPI_TXTHRESH_LEVEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */ -#define ALT_QSPI_TXTHRESH_LEVEL_MSB 3 -/* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */ -#define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4 -/* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */ -#define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f -/* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */ -#define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */ -#define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1 -/* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */ -#define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */ -#define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_TXTHRESH. - */ -struct ALT_QSPI_TXTHRESH_s -{ - uint32_t level : 4; /* Level */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_TXTHRESH. */ -typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */ -#define ALT_QSPI_TXTHRESH_OFST 0x30 - -/* - * Register : RX Threshold Register - rxthresh - * - * Device Instruction Register - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [3:0] | RW | 0x1 | Level - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Level - level - * - * Defines the level at which the receive FIFO not empty interrupt is generated - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ -#define ALT_QSPI_RXTHRESH_LEVEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */ -#define ALT_QSPI_RXTHRESH_LEVEL_MSB 3 -/* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */ -#define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4 -/* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */ -#define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f -/* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */ -#define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */ -#define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1 -/* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */ -#define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */ -#define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_RXTHRESH. - */ -struct ALT_QSPI_RXTHRESH_s -{ - uint32_t level : 4; /* Level */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_RXTHRESH. */ -typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */ -#define ALT_QSPI_RXTHRESH_OFST 0x34 - -/* - * Register : Interrupt Status Register - irqstat - * - * The status fields in this register are set when the described event occurs and - * the interrupt is enabled in the mask register. When any of these bit fields are - * set, the interrupt output is asserted high. The fields are each cleared by - * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when - * legacy SPI mode is active. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------------ - * [0] | ??? | 0x0 | *UNDEFINED* - * [1] | RW | 0x0 | Underflow Detected - * [2] | RW | 0x0 | Indirect Operation Complete - * [3] | RW | 0x0 | Indirect Read Reject - * [4] | RW | 0x0 | Protected Area Write Attempt - * [5] | RW | 0x0 | Illegal AHB Access Detected - * [6] | RW | 0x0 | Transfer Watermark Reached - * [7] | RW | 0x0 | Receive Overflow - * [8] | RW | 0x1 | Transmit FIFO Compared to Threshold - * [9] | RW | 0x0 | Transmit FIFO Full - * [10] | RW | 0x0 | Receive FIFO Compared to Threshold - * [11] | RW | 0x0 | Receive FIFO Full - * [12] | RW | 0x0 | Indirect Read Partition overflow - * [31:13] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Underflow Detected - underflowdet - * - * An underflow is detected when an attempt to transfer data is made when the - * transmit FIFO is empty. This may occur when the AHB write data is being supplied - * too slowly to keep up with the requested write operation. This bit is reset only - * by a system reset and cleared only when the register is read. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------- - * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow - * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET - * - * Underflow - */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET - * - * No Underflow - */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1 -/* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002 -/* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd -/* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Indirect Operation Complete - indopdone - * - * Controller has completed last triggered indirect operation - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation - * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE - * - * Completed Indirect Operation - */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE - * - * No Indirect Operation - */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2 -/* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Indirect Read Reject - indrdreject - * - * Indirect operation was requested but could not be accepted. Two indirect - * operations already in storage. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested - * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT - * - * Indirect Operation Requested - */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT - * - * No Indirect Operation - */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3 -/* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008 -/* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Protected Area Write Attempt - protwrattempt - * - * Write to protected area was attempted and rejected. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:-------------------------------- - * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area - * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT - * - * Write Attempt to protected area - */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT - * - * No Write Attempt - */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4 -/* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010 -/* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef -/* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Illegal AHB Access Detected - illegalacc - * - * Illegal AHB access has been detected. AHB wrapping bursts and the use of - * SPLIT/RETRY accesses will cause this error interrupt to trigger. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:----------------------- - * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt - * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC - * - * Illegal AHB attempt - */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC - * - * No Illegal AHB attempt - */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5 -/* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020 -/* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf -/* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Transfer Watermark Reached - indxfrlvl - * - * Indirect Transfer Watermark Level Reached - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:----------------------- - * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached - * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL - * - * Water level reached - */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL - * - * No water level reached - */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6 -/* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040 -/* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf -/* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Receive Overflow - rxover - * - * This should only occur in Legacy SPI mode. Set if an attempt is made to push the - * RX FIFO when it is full. This bit is reset only by a system reset and cleared - * only when this register is read. If a new push to the RX FIFO occurs coincident - * with a register read this flag will remain set. 0 : no overflow has been - * detected. 1 : an overflow has occurred. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:-------------------- - * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow - * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER - * - * Receive Overflow - */ -#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER - * - * No Receive Overflow - */ -#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ -#define ALT_QSPI_IRQSTAT_RXOVER_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */ -#define ALT_QSPI_IRQSTAT_RXOVER_MSB 7 -/* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */ -#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */ -#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080 -/* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */ -#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f -/* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */ -#define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */ -#define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : Transmit FIFO Compared to Threshold - txthreshcmp - * - * Indicates the number of entries in the transmit FIFO with respect to the - * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries - * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP - * - * FIFO has > TXTHRESH entries - */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP - * - * FIFO has <= TXTHRESH entries - */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8 -/* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100 -/* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff -/* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1 -/* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Transmit FIFO Full - txfull - * - * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy - * mode. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:----------------------- - * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full - * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL - * - * Transmit FIFO Not Full - */ -#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL - * - * Transmit FIFO Full - */ -#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ -#define ALT_QSPI_IRQSTAT_TXFULL_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */ -#define ALT_QSPI_IRQSTAT_TXFULL_MSB 9 -/* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */ -#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */ -#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200 -/* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */ -#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff -/* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */ -#define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */ -#define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Receive FIFO Compared to Threshold - rxthreshcmp - * - * Indicates the number of entries in the receive FIFO with respect to the - * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries - * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP - * - * FIFO has <= RXTHRESH entries - */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP - * - * FIFO has > RXTHRESH entries - */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10 -/* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400 -/* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff -/* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : Receive FIFO Full - rxfull - * - * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy - * mode. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------- - * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full - * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL - * - * Receive FIFO Not Full - */ -#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL - * - * Receive FIFO Full - */ -#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ -#define ALT_QSPI_IRQSTAT_RXFULL_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */ -#define ALT_QSPI_IRQSTAT_RXFULL_MSB 11 -/* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */ -#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */ -#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800 -/* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */ -#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */ -#define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */ -#define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : Indirect Read Partition overflow - indsramfull - * - * Indirect Read Partition of SRAM is full and unable to immediately complete - * indirect operation - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------|:------|:----------------- - * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full - * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL - * - * SRAM is full - */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1 -/* - * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL - * - * SRAM is not full - */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12 -/* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000 -/* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff -/* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0 -/* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */ -#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_IRQSTAT. - */ -struct ALT_QSPI_IRQSTAT_s -{ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t underflowdet : 1; /* Underflow Detected */ - uint32_t indopdone : 1; /* Indirect Operation Complete */ - uint32_t indrdreject : 1; /* Indirect Read Reject */ - uint32_t protwrattempt : 1; /* Protected Area Write Attempt */ - uint32_t illegalacc : 1; /* Illegal AHB Access Detected */ - uint32_t indxfrlvl : 1; /* Transfer Watermark Reached */ - uint32_t rxover : 1; /* Receive Overflow */ - uint32_t txthreshcmp : 1; /* Transmit FIFO Compared to Threshold */ - uint32_t txfull : 1; /* Transmit FIFO Full */ - uint32_t rxthreshcmp : 1; /* Receive FIFO Compared to Threshold */ - uint32_t rxfull : 1; /* Receive FIFO Full */ - uint32_t indsramfull : 1; /* Indirect Read Partition overflow */ - uint32_t : 19; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_IRQSTAT. */ -typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */ -#define ALT_QSPI_IRQSTAT_OFST 0x40 - -/* - * Register : Interrupt Mask - irqmask - * - * If disabled, the interrupt for the corresponding interrupt status register bit - * is disabled. If enabled, the interrupt for the corresponding interrupt status - * register bit is enabled. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------------------------- - * [0] | ??? | 0x0 | *UNDEFINED* - * [1] | RW | 0x0 | Underflow Detected Mask - * [2] | RW | 0x0 | Mask - * [3] | RW | 0x0 | Indirect Read Reject Mask - * [4] | RW | 0x0 | Protected Area Write Attempt Mask - * [5] | RW | 0x0 | Illegal Access Detected Mask - * [6] | RW | 0x0 | Transfer Watermark Breach Mask - * [7] | RW | 0x0 | Receive Overflow Mask - * [8] | RW | 0x0 | Transmit FIFO Threshold Compare Mask - * [9] | RW | 0x0 | Transmit FIFO Full Mask - * [10] | RW | 0x0 | Receive FIFO Threshold Compare Mask - * [11] | RW | 0x0 | Receive FIFO full Mask - * [12] | RW | 0x0 | Indirect Read Partition overflow mask - * [31:13] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Underflow Detected Mask - underflowdet - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1 -/* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002 -/* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd -/* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Mask - indopdone - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ -#define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ -#define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2 -/* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ -#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ -#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */ -#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */ -#define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */ -#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Indirect Read Reject Mask - indrdreject - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3 -/* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008 -/* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Protected Area Write Attempt Mask - protwrattempt - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4 -/* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010 -/* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef -/* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Illegal Access Detected Mask - illegalacc - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5 -/* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020 -/* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf -/* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Transfer Watermark Breach Mask - indxfrlvl - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6 -/* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040 -/* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf -/* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Receive Overflow Mask - rxover - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ -#define ALT_QSPI_IRQMSK_RXOVER_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */ -#define ALT_QSPI_IRQMSK_RXOVER_MSB 7 -/* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */ -#define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */ -#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080 -/* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */ -#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f -/* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */ -#define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */ -#define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8 -/* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100 -/* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff -/* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Transmit FIFO Full Mask - txfull - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ -#define ALT_QSPI_IRQMSK_TXFULL_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */ -#define ALT_QSPI_IRQMSK_TXFULL_MSB 9 -/* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */ -#define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */ -#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200 -/* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */ -#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff -/* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */ -#define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */ -#define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10 -/* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400 -/* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff -/* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : Receive FIFO full Mask - rxfull - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ -#define ALT_QSPI_IRQMSK_RXFULL_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */ -#define ALT_QSPI_IRQMSK_RXFULL_MSB 11 -/* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */ -#define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */ -#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800 -/* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */ -#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */ -#define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */ -#define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : Indirect Read Partition overflow mask - indsramfull - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:----------------------------- - * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking - * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL - * - * Disable Interrupt by Masking - */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0 -/* - * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL - * - * Enable Interrupt - */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12 -/* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1 -/* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000 -/* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff -/* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0 -/* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */ -#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_IRQMSK. - */ -struct ALT_QSPI_IRQMSK_s -{ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t underflowdet : 1; /* Underflow Detected Mask */ - uint32_t indopdone : 1; /* Mask */ - uint32_t indrdreject : 1; /* Indirect Read Reject Mask */ - uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */ - uint32_t illegalacc : 1; /* Illegal Access Detected Mask */ - uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */ - uint32_t rxover : 1; /* Receive Overflow Mask */ - uint32_t txthreshcmp : 1; /* Transmit FIFO Threshold Compare Mask */ - uint32_t txfull : 1; /* Transmit FIFO Full Mask */ - uint32_t rxthreshcmp : 1; /* Receive FIFO Threshold Compare Mask */ - uint32_t rxfull : 1; /* Receive FIFO full Mask */ - uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */ - uint32_t : 19; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_IRQMSK. */ -typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */ -#define ALT_QSPI_IRQMSK_OFST 0x44 - -/* - * Register : Lower Write Protection Register - lowwrprot - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------- - * [31:0] | RW | 0x0 | Block Number - * - */ -/* - * Field : Block Number - subsector - * - * The block number that defines the lower block in the range of blocks that is to - * be locked from writing. The definition of a block in terms of number of bytes is - * programmable via the Device Size Configuration register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ -#define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ -#define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31 -/* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ -#define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32 -/* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ -#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */ -#define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */ -#define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0 -/* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */ -#define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */ -#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_LOWWRPROT. - */ -struct ALT_QSPI_LOWWRPROT_s -{ - uint32_t subsector : 32; /* Block Number */ -}; - -/* The typedef declaration for register ALT_QSPI_LOWWRPROT. */ -typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */ -#define ALT_QSPI_LOWWRPROT_OFST 0x50 - -/* - * Register : Upper Write Protection Register - uppwrprot - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------- - * [31:0] | RW | 0x0 | Block Number - * - */ -/* - * Field : Block Number - subsector - * - * The block number that defines the upper block in the range of blocks that is to - * be locked from writing. The definition of a block in terms of number of bytes is - * programmable via the Device Size Configuration register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ -#define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ -#define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31 -/* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ -#define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32 -/* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ -#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */ -#define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */ -#define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0 -/* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */ -#define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */ -#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_UPPWRPROT. - */ -struct ALT_QSPI_UPPWRPROT_s -{ - uint32_t subsector : 32; /* Block Number */ -}; - -/* The typedef declaration for register ALT_QSPI_UPPWRPROT. */ -typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */ -#define ALT_QSPI_UPPWRPROT_OFST 0x54 - -/* - * Register : Write Protection Register - wrprot - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [0] | RW | 0x0 | Write Protection Inversion Bit - * [1] | RW | 0x0 | Write Protection Enable Bit - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Write Protection Inversion Bit - inv - * - * When enabled, the protection region defined in the lower and upper write - * protection registers is inverted meaning it is the region that the system is - * permitted to write to. When disabled, the protection region defined in the lower - * and upper write protection registers is the region that the system is not - * permitted to write to. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:------------------------- - * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed - * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_WRPROT_INV - * - * Write Region allowed - */ -#define ALT_QSPI_WRPROT_INV_E_EN 0x1 -/* - * Enumerated value for register field ALT_QSPI_WRPROT_INV - * - * Write Region not allowed - */ -#define ALT_QSPI_WRPROT_INV_E_DIS 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */ -#define ALT_QSPI_WRPROT_INV_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */ -#define ALT_QSPI_WRPROT_INV_MSB 0 -/* The width in bits of the ALT_QSPI_WRPROT_INV register field. */ -#define ALT_QSPI_WRPROT_INV_WIDTH 1 -/* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */ -#define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001 -/* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */ -#define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe -/* The reset value of the ALT_QSPI_WRPROT_INV register field. */ -#define ALT_QSPI_WRPROT_INV_RESET 0x0 -/* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */ -#define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */ -#define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Write Protection Enable Bit - en - * - * When enabled, any AHB write access with an address within the protection region - * defined in the lower and upper write protection registers is rejected. An AHB - * error response is generated and an interrupt source triggered. When disabled, - * the protection region is disabled. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------|:------|:--------------------------- - * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected - * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_WRPROT_EN - * - * AHB Write Access rejected - */ -#define ALT_QSPI_WRPROT_EN_E_EN 0x1 -/* - * Enumerated value for register field ALT_QSPI_WRPROT_EN - * - * Protection Region Disabled - */ -#define ALT_QSPI_WRPROT_EN_E_DIS 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */ -#define ALT_QSPI_WRPROT_EN_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */ -#define ALT_QSPI_WRPROT_EN_MSB 1 -/* The width in bits of the ALT_QSPI_WRPROT_EN register field. */ -#define ALT_QSPI_WRPROT_EN_WIDTH 1 -/* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */ -#define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002 -/* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */ -#define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd -/* The reset value of the ALT_QSPI_WRPROT_EN register field. */ -#define ALT_QSPI_WRPROT_EN_RESET 0x0 -/* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */ -#define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */ -#define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_WRPROT. - */ -struct ALT_QSPI_WRPROT_s -{ - uint32_t inv : 1; /* Write Protection Inversion Bit */ - uint32_t en : 1; /* Write Protection Enable Bit */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_WRPROT. */ -typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */ -#define ALT_QSPI_WRPROT_OFST 0x58 - -/* - * Register : Indirect Read Transfer Register - indrd - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:-------------------------------- - * [0] | RW | 0x0 | Start Indirect Read - * [1] | RW | 0x0 | Cancel Indirect Read - * [2] | R | Unknown | Indirect Read Status - * [3] | RW | Unknown | SRAM Full - * [4] | R | Unknown | Queued Indirect Read Operations - * [5] | RW | Unknown | Indirect Completion Status - * [7:6] | R | Unknown | Completed Indirect Operations - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Start Indirect Read - start - * - * When this bit is enabled, it will trigger an indirect read operation. The - * assumption is that the indirect start address and the indirect number of bytes - * register is setup before triggering the indirect read operation. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:---------------------- - * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read - * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDRD_START - * - * Trigger Indirect Read - */ -#define ALT_QSPI_INDRD_START_E_END 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDRD_START - * - * No Indirect Read - */ -#define ALT_QSPI_INDRD_START_E_DISD 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */ -#define ALT_QSPI_INDRD_START_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */ -#define ALT_QSPI_INDRD_START_MSB 0 -/* The width in bits of the ALT_QSPI_INDRD_START register field. */ -#define ALT_QSPI_INDRD_START_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDRD_START register field value. */ -#define ALT_QSPI_INDRD_START_SET_MSK 0x00000001 -/* The mask used to clear the ALT_QSPI_INDRD_START register field value. */ -#define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe -/* The reset value of the ALT_QSPI_INDRD_START register field. */ -#define ALT_QSPI_INDRD_START_RESET 0x0 -/* Extracts the ALT_QSPI_INDRD_START field value from a register. */ -#define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */ -#define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Cancel Indirect Read - cancel - * - * This bit will cancel all ongoing indirect read operations. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:---------------------------- - * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read - * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDRD_CANCEL - * - * Cancel Indirect Read - */ -#define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDRD_CANCEL - * - * Do Not Cancel Indirect Read - */ -#define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ -#define ALT_QSPI_INDRD_CANCEL_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */ -#define ALT_QSPI_INDRD_CANCEL_MSB 1 -/* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */ -#define ALT_QSPI_INDRD_CANCEL_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */ -#define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002 -/* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */ -#define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd -/* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */ -#define ALT_QSPI_INDRD_CANCEL_RESET 0x0 -/* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */ -#define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */ -#define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Indirect Read Status - rd_status - * - * Indirect read operation in progress (status) - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:------------------------------ - * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress - * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT - * - * Read Operation in progress - */ -#define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT - * - * No read operation in progress - */ -#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ -#define ALT_QSPI_INDRD_RD_STAT_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */ -#define ALT_QSPI_INDRD_RD_STAT_MSB 2 -/* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */ -#define ALT_QSPI_INDRD_RD_STAT_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */ -#define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004 -/* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */ -#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb -/* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */ -#define ALT_QSPI_INDRD_RD_STAT_RESET 0x0 -/* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */ -#define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */ -#define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : SRAM Full - sram_full - * - * SRAM full and unable to immediately complete an indirect operation. Write a 1 to - * this field to clear it. ; indirect operation (status) - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:----------------------------------- - * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation - * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL - * - * Sram Full- Cant complete operation - */ -#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL - * - * SRram Not Full - */ -#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ -#define ALT_QSPI_INDRD_SRAM_FULL_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */ -#define ALT_QSPI_INDRD_SRAM_FULL_MSB 3 -/* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */ -#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */ -#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008 -/* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */ -#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */ -#define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0 -/* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */ -#define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */ -#define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Queued Indirect Read Operations - rd_queued - * - * Two indirect read operations have been queued - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:--------------------- - * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read - * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED - * - * Queued Indirect Read - */ -#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED - * - * No Queued Read - */ -#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ -#define ALT_QSPI_INDRD_RD_QUEUED_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */ -#define ALT_QSPI_INDRD_RD_QUEUED_MSB 4 -/* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */ -#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */ -#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010 -/* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */ -#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef -/* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */ -#define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0 -/* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */ -#define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */ -#define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Indirect Completion Status - ind_ops_done_status - * - * This field is set to 1 when an indirect operation has completed. Write a 1 to - * this field to clear it. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------------------------- - * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation - * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT - * - * Indirect Op Complete operation - */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT - * - * Indirect Op Not Complete - */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5 -/* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020 -/* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf -/* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0 -/* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */ -#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Completed Indirect Operations - num_ind_ops_done - * - * This field contains the number of indirect operations which have been completed. - * This is used in conjunction with the indirect completion status field (bit 5). - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ -#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ -#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7 -/* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */ -#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2 -/* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ -#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0 -/* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */ -#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f -/* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */ -#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0 -/* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */ -#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6) -/* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */ -#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_INDRD. - */ -struct ALT_QSPI_INDRD_s -{ - uint32_t start : 1; /* Start Indirect Read */ - uint32_t cancel : 1; /* Cancel Indirect Read */ - const uint32_t rd_status : 1; /* Indirect Read Status */ - uint32_t sram_full : 1; /* SRAM Full */ - const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */ - uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */ - const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_INDRD. */ -typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */ -#define ALT_QSPI_INDRD_OFST 0x60 - -/* - * Register : Indirect Read Transfer Watermark Register - indrdwater - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------- - * [31:0] | RW | 0x0 | Watermark Value - * - */ -/* - * Field : Watermark Value - level - * - * This represents the minimum fill level of the SRAM before a DMA peripheral - * access is permitted. When the SRAM fill level passes the watermark, an interrupt - * is also generated. This field can be disabled by writing a value of all zeroes. - * The units of this register are BYTES - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ -#define ALT_QSPI_INDRDWATER_LEVEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */ -#define ALT_QSPI_INDRDWATER_LEVEL_MSB 31 -/* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */ -#define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32 -/* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */ -#define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */ -#define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */ -#define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0 -/* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */ -#define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */ -#define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_INDRDWATER. - */ -struct ALT_QSPI_INDRDWATER_s -{ - uint32_t level : 32; /* Watermark Value */ -}; - -/* The typedef declaration for register ALT_QSPI_INDRDWATER. */ -typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */ -#define ALT_QSPI_INDRDWATER_OFST 0x64 - -/* - * Register : Indirect Read Transfer Start Address Register - indrdstaddr - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [31:0] | RW | 0x0 | Start Address of Indirect Access - * - */ -/* - * Field : Start Address of Indirect Access - addr - * - * This is the start address from which the indirect access will commence its READ - * operation. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ -#define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ -#define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31 -/* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ -#define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32 -/* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ -#define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */ -#define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */ -#define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0 -/* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */ -#define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */ -#define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_INDRDSTADDR. - */ -struct ALT_QSPI_INDRDSTADDR_s -{ - uint32_t addr : 32; /* Start Address of Indirect Access */ -}; - -/* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */ -typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */ -#define ALT_QSPI_INDRDSTADDR_OFST 0x68 - -/* - * Register : Indirect Read Transfer Number Bytes Register - indrdcnt - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------- - * [31:0] | RW | 0x0 | Indirect Count - * - */ -/* - * Field : Indirect Count - value - * - * This is the number of bytes that the indirect access will consume. This can be - * bigger than the configured size of SRAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ -#define ALT_QSPI_INDRDCNT_VALUE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */ -#define ALT_QSPI_INDRDCNT_VALUE_MSB 31 -/* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */ -#define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32 -/* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */ -#define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */ -#define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */ -#define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0 -/* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */ -#define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */ -#define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_INDRDCNT. - */ -struct ALT_QSPI_INDRDCNT_s -{ - uint32_t value : 32; /* Indirect Count */ -}; - -/* The typedef declaration for register ALT_QSPI_INDRDCNT. */ -typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */ -#define ALT_QSPI_INDRDCNT_OFST 0x6c - -/* - * Register : Indirect Write Transfer Register - indwr - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:--------------------------------- - * [0] | RW | 0x0 | Start Indirect Write - * [1] | RW | 0x0 | Cancel Indirect Write - * [2] | R | Unknown | Indirect Write Status - * [3] | R | 0x0 | Reserved - * [4] | R | Unknown | Queued Indirect Write Operations - * [5] | RW | Unknown | Indirect Completion Status - * [7:6] | R | Unknown | Completed Indirect Operations - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Start Indirect Write - start - * - * Writing a 1 to this bit will trigger an indirect write operation. The assumption - * is that the indirect start address and the indirect number of bytes register is - * setup before triggering the indirect write operation. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:--------------------------------- - * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation - * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDWR_START - * - * Trigger indirect write operation - */ -#define ALT_QSPI_INDWR_START_E_END 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDWR_START - * - * No Action - */ -#define ALT_QSPI_INDWR_START_E_DISD 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */ -#define ALT_QSPI_INDWR_START_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */ -#define ALT_QSPI_INDWR_START_MSB 0 -/* The width in bits of the ALT_QSPI_INDWR_START register field. */ -#define ALT_QSPI_INDWR_START_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDWR_START register field value. */ -#define ALT_QSPI_INDWR_START_SET_MSK 0x00000001 -/* The mask used to clear the ALT_QSPI_INDWR_START register field value. */ -#define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe -/* The reset value of the ALT_QSPI_INDWR_START register field. */ -#define ALT_QSPI_INDWR_START_RESET 0x0 -/* Extracts the ALT_QSPI_INDWR_START field value from a register. */ -#define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */ -#define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Cancel Indirect Write - cancel - * - * Writing a 1 to this bit will cancel all ongoing indirect write operations. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:-------------------------------- - * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation - * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDWR_CANCEL - * - * Cancel Indirect write operation - */ -#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDWR_CANCEL - * - * No Action - */ -#define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ -#define ALT_QSPI_INDWR_CANCEL_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */ -#define ALT_QSPI_INDWR_CANCEL_MSB 1 -/* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */ -#define ALT_QSPI_INDWR_CANCEL_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */ -#define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002 -/* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */ -#define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd -/* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */ -#define ALT_QSPI_INDWR_CANCEL_RESET 0x0 -/* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */ -#define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */ -#define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Indirect Write Status - rdstat - * - * Indirect write operation in progress (status) - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:------------------------- - * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation - * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT - * - * Indirect write operation - */ -#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT - * - * No Action - */ -#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ -#define ALT_QSPI_INDWR_RDSTAT_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */ -#define ALT_QSPI_INDWR_RDSTAT_MSB 2 -/* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */ -#define ALT_QSPI_INDWR_RDSTAT_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */ -#define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004 -/* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */ -#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb -/* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */ -#define ALT_QSPI_INDWR_RDSTAT_RESET 0x0 -/* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */ -#define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */ -#define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Reserved - sramfull - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ -#define ALT_QSPI_INDWR_SRAMFULL_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */ -#define ALT_QSPI_INDWR_SRAMFULL_MSB 3 -/* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */ -#define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */ -#define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008 -/* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */ -#define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */ -#define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0 -/* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */ -#define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */ -#define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Queued Indirect Write Operations - rdqueued - * - * Two indirect write operations have been queued - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:----------------------------- - * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation - * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED - * - * Two Indirect write operation - */ -#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED - * - * No Action - */ -#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ -#define ALT_QSPI_INDWR_RDQUEUED_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */ -#define ALT_QSPI_INDWR_RDQUEUED_MSB 4 -/* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */ -#define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */ -#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010 -/* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */ -#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef -/* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */ -#define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0 -/* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */ -#define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */ -#define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Indirect Completion Status - inddone - * - * This field is set to 1 when an indirect operation has completed. Write a 1 to - * this field to clear it. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:----------------------------- - * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed - * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_INDWR_INDDONE - * - * Indirect operation completed - */ -#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1 -/* - * Enumerated value for register field ALT_QSPI_INDWR_INDDONE - * - * No Action - */ -#define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ -#define ALT_QSPI_INDWR_INDDONE_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */ -#define ALT_QSPI_INDWR_INDDONE_MSB 5 -/* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */ -#define ALT_QSPI_INDWR_INDDONE_WIDTH 1 -/* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */ -#define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020 -/* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */ -#define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf -/* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */ -#define ALT_QSPI_INDWR_INDDONE_RESET 0x0 -/* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */ -#define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */ -#define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Completed Indirect Operations - indcnt - * - * This field contains the count of indirect operations which have been completed. - * This is used in conjunction with the indirect completion status field (bit 5). - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ -#define ALT_QSPI_INDWR_INDCNT_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */ -#define ALT_QSPI_INDWR_INDCNT_MSB 7 -/* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */ -#define ALT_QSPI_INDWR_INDCNT_WIDTH 2 -/* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */ -#define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0 -/* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */ -#define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f -/* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */ -#define ALT_QSPI_INDWR_INDCNT_RESET 0x0 -/* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */ -#define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6) -/* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */ -#define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_INDWR. - */ -struct ALT_QSPI_INDWR_s -{ - uint32_t start : 1; /* Start Indirect Write */ - uint32_t cancel : 1; /* Cancel Indirect Write */ - const uint32_t rdstat : 1; /* Indirect Write Status */ - const uint32_t sramfull : 1; /* Reserved */ - const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */ - uint32_t inddone : 1; /* Indirect Completion Status */ - const uint32_t indcnt : 2; /* Completed Indirect Operations */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_INDWR. */ -typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */ -#define ALT_QSPI_INDWR_OFST 0x70 - -/* - * Register : Indirect Write Transfer Watermark Register - indwrwater - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:-----------|:---------------- - * [31:0] | RW | 0xffffffff | Watermark Value - * - */ -/* - * Field : Watermark Value - level - * - * This represents the maximum fill level of the SRAM before a DMA peripheral - * access is permitted. When the SRAM fill level falls below the watermark, an - * interrupt is also generated. This field can be disabled by writing a value of - * all ones. The units of this register are bytes. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ -#define ALT_QSPI_INDWRWATER_LEVEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */ -#define ALT_QSPI_INDWRWATER_LEVEL_MSB 31 -/* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */ -#define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32 -/* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */ -#define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */ -#define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */ -#define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff -/* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */ -#define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */ -#define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_INDWRWATER. - */ -struct ALT_QSPI_INDWRWATER_s -{ - uint32_t level : 32; /* Watermark Value */ -}; - -/* The typedef declaration for register ALT_QSPI_INDWRWATER. */ -typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */ -#define ALT_QSPI_INDWRWATER_OFST 0x74 - -/* - * Register : Indirect Write Transfer Start Address Register - indwrstaddr - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------- - * [31:0] | RW | 0x0 | Start of Indirect Access - * - */ -/* - * Field : Start of Indirect Access - addr - * - * This is the start address from which the indirect access will commence its write - * operation. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ -#define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ -#define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31 -/* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ -#define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32 -/* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ -#define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */ -#define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */ -#define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0 -/* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */ -#define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */ -#define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_INDWRSTADDR. - */ -struct ALT_QSPI_INDWRSTADDR_s -{ - uint32_t addr : 32; /* Start of Indirect Access */ -}; - -/* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */ -typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */ -#define ALT_QSPI_INDWRSTADDR_OFST 0x78 - -/* - * Register : Indirect Write Transfer Count Register - indwrcnt - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------- - * [31:0] | RW | 0x0 | Indirect Number of Bytes - * - */ -/* - * Field : Indirect Number of Bytes - value - * - * This is the number of bytes that the indirect access will consume. This can be - * bigger than the configured size of SRAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ -#define ALT_QSPI_INDWRCNT_VALUE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */ -#define ALT_QSPI_INDWRCNT_VALUE_MSB 31 -/* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */ -#define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32 -/* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */ -#define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */ -#define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */ -#define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0 -/* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */ -#define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */ -#define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_INDWRCNT. - */ -struct ALT_QSPI_INDWRCNT_s -{ - uint32_t value : 32; /* Indirect Number of Bytes */ -}; - -/* The typedef declaration for register ALT_QSPI_INDWRCNT. */ -typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */ -#define ALT_QSPI_INDWRCNT_OFST 0x7c - -/* - * Register : Flash Command Register - flashcmd - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:--------------------------- - * [0] | RW | 0x0 | Execute Command - * [1] | R | 0x0 | Command Execution Status - * [6:2] | ??? | 0x0 | *UNDEFINED* - * [11:7] | RW | 0x0 | Number of Dummy Bytes - * [14:12] | RW | 0x0 | Number of Write Data Bytes - * [15] | RW | 0x0 | Write Data Enable - * [17:16] | RW | 0x0 | Number of Address Bytes - * [18] | RW | 0x0 | Mode Bit Enable - * [19] | RW | 0x0 | Command Address Enable - * [22:20] | RW | 0x0 | Number of Read Data Bytes - * [23] | RW | 0x0 | Read Data Enable - * [31:24] | RW | 0x0 | Command Opcode - * - */ -/* - * Field : Execute Command - execcmd - * - * Execute the command. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:---------------- - * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command - * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD - * - * Execute Command - */ -#define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD - * - * No Action - */ -#define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ -#define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ -#define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0 -/* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ -#define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1 -/* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ -#define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001 -/* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */ -#define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe -/* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */ -#define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */ -#define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Command Execution Status - cmdexecstat - * - * Command execution in progress. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:------------------------- - * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status - * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT - * - * Command Execution Status - */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT - * - * No Action - */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1 -/* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1 -/* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002 -/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd -/* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Number of Dummy Bytes - numdummybytes - * - * Set to the number of dummy bytes required This should be setup before triggering - * the command via the execute field of this register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11 -/* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5 -/* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ -#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80 -/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */ -#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f -/* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */ -#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7) -/* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80) - -/* - * Field : Number of Write Data Bytes - numwrdatabytes - * - * Up to 8 Data bytes may be written using this command. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------- - * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte - * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte - * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte - * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte - * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte - * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte - * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte - * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES - * - * Write 1 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES - * - * Write 2 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES - * - * Write 3 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES - * - * Write 4 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES - * - * Write 5 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES - * - * Write 6 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES - * - * Write 7 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES - * - * Write 8 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14 -/* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3 -/* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000 -/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff -/* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12) -/* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000) - -/* - * Field : Write Data Enable - enwrdata - * - * Set to 1 if the command specified in the command opcode field requires write - * data bytes to be sent to the device. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:---------------------------------- - * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes - * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA - * - * Command requires write data bytes - */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA - * - * No Action - */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15 -/* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1 -/* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000 -/* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff -/* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15) -/* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000) - -/* - * Field : Number of Address Bytes - numaddrbytes - * - * Set to the number of address bytes required (the address itself is programmed in - * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the - * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address - * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:---------------------- - * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte - * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes - * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes - * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES - * - * Write 1 Address Byte - */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES - * - * Write 2 Address Bytes - */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES - * - * Write 3 Address Bytes - */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES - * - * Write 4 Address Bytes - */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17 -/* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2 -/* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000 -/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff -/* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16) -/* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000) - -/* - * Field : Mode Bit Enable - enmodebit - * - * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration - * register are sent following the address bytes. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:------------------------------- - * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes - * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT - * - * Mode Bit follows address bytes - */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT - * - * No Action - */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18 -/* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1 -/* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000 -/* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff -/* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18) -/* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000) - -/* - * Field : Command Address Enable - encmdaddr - * - * If enabled, the command specified in bits 31:24 requires an address. This should - * be setup before triggering the command via writing a 1 to the execute field. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:--------------------------------------- - * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address - * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR - * - * Command in bits 31:24 requires address - */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR - * - * No Action - */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19 -/* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1 -/* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000 -/* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff -/* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19) -/* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000) - -/* - * Field : Number of Read Data Bytes - numrddatabytes - * - * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for - * 8 bytes. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------ - * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte - * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte - * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte - * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte - * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte - * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte - * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte - * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES - * - * Read 1 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES - * - * Read 2 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES - * - * Read 3 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES - * - * Read 4 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES - * - * Read 5 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES - * - * Read 6 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES - * - * Read 7 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES - * - * Read 8 Byte - */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22 -/* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3 -/* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000 -/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff -/* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20) -/* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000) - -/* - * Field : Read Data Enable - enrddata - * - * If enabled, the command specified in the command opcode field (bits 31:24) - * requires read data bytes to be received from the device. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:--------------------------- - * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data - * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA - * - * Command Requires read data - */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1 -/* - * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA - * - * No Action - */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23 -/* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1 -/* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000 -/* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff -/* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23) -/* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000) - -/* - * Field : Command Opcode - cmdopcode - * - * The command opcode field should be setup before triggering the command. For - * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of - * this register launches the command. NOTE : Using this approach to issue commands - * to the device will make use of the instruction type of the device instruction - * configuration register. If this field is set to 2'b00, then the command opcode, - * command address, command dummy bytes and command data will all be transferred in - * a serial fashion. If this field is set to 2'b01, then the command opcode, - * command address, command dummy bytes and command data will all be transferred in - * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command - * opcode, command address, command dummy bytes and command data will all be - * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ -#define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ -#define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31 -/* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ -#define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8 -/* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ -#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000 -/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */ -#define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff -/* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */ -#define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */ -#define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24) -/* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_FLSHCMD. - */ -struct ALT_QSPI_FLSHCMD_s -{ - uint32_t execcmd : 1; /* Execute Command */ - const uint32_t cmdexecstat : 1; /* Command Execution Status */ - uint32_t : 5; /* *UNDEFINED* */ - uint32_t numdummybytes : 5; /* Number of Dummy Bytes */ - uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */ - uint32_t enwrdata : 1; /* Write Data Enable */ - uint32_t numaddrbytes : 2; /* Number of Address Bytes */ - uint32_t enmodebit : 1; /* Mode Bit Enable */ - uint32_t encmdaddr : 1; /* Command Address Enable */ - uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */ - uint32_t enrddata : 1; /* Read Data Enable */ - uint32_t cmdopcode : 8; /* Command Opcode */ -}; - -/* The typedef declaration for register ALT_QSPI_FLSHCMD. */ -typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */ -#define ALT_QSPI_FLSHCMD_OFST 0x90 - -/* - * Register : Flash Command Address Registers - flashcmdaddr - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------- - * [31:0] | RW | 0x0 | Command Address - * - */ -/* - * Field : Command Address - addr - * - * This should be setup before triggering the command with execute field (bit 0) of - * the Flash Command Control register. It is the address used by the command - * specified in the opcode field (bits 31:24) of the Flash Command Control - * register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ -#define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ -#define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31 -/* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ -#define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32 -/* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ -#define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */ -#define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */ -#define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */ -#define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_FLSHCMDADDR. - */ -struct ALT_QSPI_FLSHCMDADDR_s -{ - uint32_t addr : 32; /* Command Address */ -}; - -/* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */ -typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */ -#define ALT_QSPI_FLSHCMDADDR_OFST 0x94 - -/* - * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [31:0] | RW | 0x0 | Command Read Data (Lower byte) - * - */ -/* - * Field : Command Read Data (Lower byte) - data - * - * This is the data that is returned by the flash device for any status or - * configuration read operation carried out by triggering the event in the control - * register. The register will be valid when the polling bit in the control - * register is low. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ -#define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ -#define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31 -/* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ -#define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32 -/* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ -#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */ -#define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */ -#define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */ -#define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO. - */ -struct ALT_QSPI_FLSHCMDRDDATALO_s -{ - uint32_t data : 32; /* Command Read Data (Lower byte) */ -}; - -/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */ -typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */ -#define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0 - -/* - * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup - * - * Device Instruction Register - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [31:0] | RW | 0x0 | Command Read Data (Upper byte) - * - */ -/* - * Field : Command Read Data (Upper byte) - data - * - * This is the data that is returned by the FLASH device for any status or - * configuration read operation carried out by triggering the event in the control - * register. The register will be valid when the polling bit in the control - * register is low. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31 -/* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32 -/* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP. - */ -struct ALT_QSPI_FLSHCMDRDDATAUP_s -{ - uint32_t data : 32; /* Command Read Data (Upper byte) */ -}; - -/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */ -typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4 - -/* - * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [31:0] | RW | 0x0 | Command Write Data Lower Byte - * - */ -/* - * Field : Command Write Data Lower Byte - data - * - * This is the command write data lower byte. This should be setup before - * triggering the command with execute field (bit 0) of the Flash Command Control - * register. It is the data that is to be written to the flash for any status or - * configuration write operation carried out by triggering the event in the Flash - * Command Control register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ -#define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ -#define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31 -/* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ -#define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32 -/* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ -#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */ -#define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */ -#define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */ -#define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO. - */ -struct ALT_QSPI_FLSHCMDWRDATALO_s -{ - uint32_t data : 32; /* Command Write Data Lower Byte */ -}; - -/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */ -typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */ -#define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8 - -/* - * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [31:0] | RW | 0x0 | ALT_QSPI_FLSHCMDWRDATAUP_DATA - * - */ -/* - * Field : data - * - * This is the command write data upper byte. This should be setup before - * triggering the command with execute field (bit 0) of the Flash Command Control - * register. It is the data that is to be written to the flash for any status or - * configuration write operation carried out by triggering the event in the Flash - * Command Control register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31 -/* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32 -/* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff -/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000 -/* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0 -/* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP. - */ -struct ALT_QSPI_FLSHCMDWRDATAUP_s -{ - uint32_t data : 32; /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */ -}; - -/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */ -typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac - -/* - * Register : Module ID Register - moduleid - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:-------|:----------------- - * [24:0] | R | 0x1001 | Module ID number - * [31:25] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Module ID number - value - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ -#define ALT_QSPI_MODULEID_VALUE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */ -#define ALT_QSPI_MODULEID_VALUE_MSB 24 -/* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */ -#define ALT_QSPI_MODULEID_VALUE_WIDTH 25 -/* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */ -#define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff -/* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */ -#define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000 -/* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */ -#define ALT_QSPI_MODULEID_VALUE_RESET 0x1001 -/* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */ -#define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0) -/* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */ -#define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_QSPI_MODULEID. - */ -struct ALT_QSPI_MODULEID_s -{ - const uint32_t value : 25; /* Module ID number */ - uint32_t : 7; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_QSPI_MODULEID. */ -typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */ -#define ALT_QSPI_MODULEID_OFST 0xfc - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_QSPI. - */ -struct ALT_QSPI_s -{ - volatile ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */ - volatile ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */ - volatile ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */ - volatile ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */ - volatile ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */ - volatile ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */ - volatile ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */ - volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ - volatile ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */ - volatile ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */ - volatile ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */ - volatile ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */ - volatile ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */ - volatile ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */ - volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ - volatile ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */ - volatile ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */ - volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ - volatile ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ - volatile ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ - volatile ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */ - volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ - volatile ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */ - volatile ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */ - volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ - volatile ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */ - volatile ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */ - volatile ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */ - volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ - volatile ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */ - volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ - volatile ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */ - volatile ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ - volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ - volatile ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ - volatile ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ - volatile ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ - volatile ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ - volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ - volatile ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */ -}; - -/* The typedef declaration for register group ALT_QSPI. */ -typedef volatile struct ALT_QSPI_s ALT_QSPI_t; -/* The struct declaration for the raw register contents of register group ALT_QSPI. */ -struct ALT_QSPI_raw_s -{ - volatile uint32_t cfg; /* ALT_QSPI_CFG */ - volatile uint32_t devrd; /* ALT_QSPI_DEVRD */ - volatile uint32_t devwr; /* ALT_QSPI_DEVWR */ - volatile uint32_t delay; /* ALT_QSPI_DELAY */ - volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */ - volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */ - volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */ - volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */ - volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */ - volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */ - volatile uint32_t modebit; /* ALT_QSPI_MODBIT */ - volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */ - volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */ - volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */ - volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */ - volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */ - volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */ - volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */ - volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */ - volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */ - volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */ - volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */ - volatile uint32_t indrd; /* ALT_QSPI_INDRD */ - volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */ - volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */ - volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */ - volatile uint32_t indwr; /* ALT_QSPI_INDWR */ - volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */ - volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */ - volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */ - volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */ - volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */ - volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */ - volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */ - volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */ - volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */ - volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */ - volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */ - volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */ - volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_QSPI. */ -typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_QSPI_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h deleted file mode 100644 index 19383eefe5..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_qspidata.h +++ /dev/null @@ -1,52 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_QSPIDATA */ - -#ifndef __ALTERA_ALT_QSPIDATA_H__ -#define __ALTERA_ALT_QSPIDATA_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : QSPI Flash Module Data (AHB Slave) - ALT_QSPIDATA - * QSPI Flash Module Data (AHB Slave) - * - * - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_QSPIDATA_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_rstmgr.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_rstmgr.h deleted file mode 100644 index ab4ac65dcb..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_rstmgr.h +++ /dev/null @@ -1,3382 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_RSTMGR */ - -#ifndef __ALTERA_ALT_RSTMGR_H__ -#define __ALTERA_ALT_RSTMGR_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : Reset Manager Module - ALT_RSTMGR - * Reset Manager Module - * - * Registers in the Reset Manager module - * - */ -/* - * Register : Status Register - stat - * - * The STAT register contains bits that indicate the reset source or a timeout - * event. For reset sources, a field is 1 if its associated reset requester caused - * the reset. For timeout events, a field is 1 if its associated timeout occured as - * part of a hardware sequenced warm/debug reset. - * - * Software clears bits by writing them with a value of 1. Writes to bits with a - * value of 0 are ignored. - * - * After a cold reset is complete, all bits are reset to their reset value except - * for the bit(s) that indicate the source of the cold reset. If multiple cold - * reset requests overlap with each other, the source de-asserts the request last - * will be logged. The other reset request source(s) de-assert the request in the - * same cycle will also be logged, the rest of the fields are reset to default - * value of 0. - * - * After a warm reset is complete, the bit(s) that indicate the source of the warm - * reset are set to 1. A warm reset doesn't clear any of the bits in the STAT - * register; these bits must be cleared by software writing the STAT register. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------------- - * [0] | RW | 0x0 | Power-On Voltage Detector Cold Reset - * [1] | RW | 0x0 | nPOR Pin Cold Reset - * [2] | RW | 0x0 | FPGA Core Cold Reset - * [3] | RW | 0x0 | CONFIG_IO Cold Reset - * [4] | RW | 0x0 | Software Cold Reset - * [7:5] | ??? | 0x0 | *UNDEFINED* - * [8] | RW | 0x0 | nRST Pin Warm Reset - * [9] | RW | 0x0 | FPGA Core Warm Reset - * [10] | RW | 0x0 | Software Warm Reset - * [11] | ??? | 0x0 | *UNDEFINED* - * [12] | RW | 0x0 | MPU Watchdog 0 Warm Reset - * [13] | RW | 0x0 | MPU Watchdog 1 Warm Reset - * [14] | RW | 0x0 | L4 Watchdog 0 Warm Reset - * [15] | RW | 0x0 | L4 Watchdog 1 Warm Reset - * [17:16] | ??? | 0x0 | *UNDEFINED* - * [18] | RW | 0x0 | FPGA Core Debug Reset - * [19] | RW | 0x0 | DAP Debug Reset - * [23:20] | ??? | 0x0 | *UNDEFINED* - * [24] | RW | 0x0 | SDRAM Self-Refresh Timeout - * [25] | RW | 0x0 | FPGA manager handshake Timeout - * [26] | RW | 0x0 | SCAN manager handshake Timeout - * [27] | RW | 0x0 | FPGA handshake Timeout - * [28] | RW | 0x0 | ETR Stall Timeout - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Power-On Voltage Detector Cold Reset - porvoltrst - * - * Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ -#define ALT_RSTMGR_STAT_PORVOLTRST_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ -#define ALT_RSTMGR_STAT_PORVOLTRST_MSB 0 -/* The width in bits of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ -#define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_PORVOLTRST register field value. */ -#define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001 -/* The mask used to clear the ALT_RSTMGR_STAT_PORVOLTRST register field value. */ -#define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe -/* The reset value of the ALT_RSTMGR_STAT_PORVOLTRST register field. */ -#define ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_PORVOLTRST field value from a register. */ -#define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_RSTMGR_STAT_PORVOLTRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : nPOR Pin Cold Reset - nporpinrst - * - * nPOR pin triggered a cold reset (por_pin_req = 1) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */ -#define ALT_RSTMGR_STAT_NPORPINRST_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */ -#define ALT_RSTMGR_STAT_NPORPINRST_MSB 1 -/* The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field. */ -#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value. */ -#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002 -/* The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value. */ -#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd -/* The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field. */ -#define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register. */ -#define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : FPGA Core Cold Reset - fpgacoldrst - * - * FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ -#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ -#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2 -/* The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ -#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */ -#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004 -/* The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */ -#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb -/* The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */ -#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register. */ -#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : CONFIG_IO Cold Reset - configiocoldrst - * - * FPGA entered CONFIG_IO mode and a triggered a cold reset - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ -#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ -#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3 -/* The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ -#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */ -#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008 -/* The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */ -#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */ -#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register. */ -#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Software Cold Reset - swcoldrst - * - * Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ -#define ALT_RSTMGR_STAT_SWCOLDRST_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ -#define ALT_RSTMGR_STAT_SWCOLDRST_MSB 4 -/* The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ -#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value. */ -#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010 -/* The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value. */ -#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef -/* The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field. */ -#define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register. */ -#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : nRST Pin Warm Reset - nrstpinrst - * - * nRST pin triggered a hardware sequenced warm reset - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ -#define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ -#define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8 -/* The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ -#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value. */ -#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100 -/* The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value. */ -#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff -/* The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field. */ -#define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register. */ -#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : FPGA Core Warm Reset - fpgawarmrst - * - * FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ -#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ -#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9 -/* The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ -#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */ -#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200 -/* The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */ -#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff -/* The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */ -#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register. */ -#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Software Warm Reset - swwarmrst - * - * Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm - * reset - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */ -#define ALT_RSTMGR_STAT_SWWARMRST_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */ -#define ALT_RSTMGR_STAT_SWWARMRST_MSB 10 -/* The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field. */ -#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value. */ -#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400 -/* The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value. */ -#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff -/* The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field. */ -#define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register. */ -#define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : MPU Watchdog 0 Warm Reset - mpuwd0rst - * - * MPU Watchdog 0 triggered a hardware sequenced warm reset - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ -#define ALT_RSTMGR_STAT_MPUWD0RST_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ -#define ALT_RSTMGR_STAT_MPUWD0RST_MSB 12 -/* The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ -#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value. */ -#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000 -/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value. */ -#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff -/* The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field. */ -#define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register. */ -#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000) - -/* - * Field : MPU Watchdog 1 Warm Reset - mpuwd1rst - * - * MPU Watchdog 1 triggered a hardware sequenced warm reset - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ -#define ALT_RSTMGR_STAT_MPUWD1RST_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ -#define ALT_RSTMGR_STAT_MPUWD1RST_MSB 13 -/* The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ -#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value. */ -#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000 -/* The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value. */ -#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff -/* The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field. */ -#define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register. */ -#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : L4 Watchdog 0 Warm Reset - l4wd0rst - * - * L4 Watchdog 0 triggered a hardware sequenced warm reset - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */ -#define ALT_RSTMGR_STAT_L4WD0RST_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */ -#define ALT_RSTMGR_STAT_L4WD0RST_MSB 14 -/* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */ -#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */ -#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000 -/* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */ -#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff -/* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */ -#define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */ -#define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000) - -/* - * Field : L4 Watchdog 1 Warm Reset - l4wd1rst - * - * L4 Watchdog 1 triggered a hardware sequenced warm reset - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */ -#define ALT_RSTMGR_STAT_L4WD1RST_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */ -#define ALT_RSTMGR_STAT_L4WD1RST_MSB 15 -/* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */ -#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */ -#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000 -/* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */ -#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff -/* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */ -#define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */ -#define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15) -/* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000) - -/* - * Field : FPGA Core Debug Reset - fpgadbgrst - * - * FPGA triggered debug reset (f2h_dbg_rst_req_n = 1) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ -#define ALT_RSTMGR_STAT_FPGADBGRST_LSB 18 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ -#define ALT_RSTMGR_STAT_FPGADBGRST_MSB 18 -/* The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ -#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value. */ -#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000 -/* The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value. */ -#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff -/* The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field. */ -#define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register. */ -#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18) -/* Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000) - -/* - * Field : DAP Debug Reset - cdbgreqrst - * - * DAP triggered debug reset - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ -#define ALT_RSTMGR_STAT_CDBGREQRST_LSB 19 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ -#define ALT_RSTMGR_STAT_CDBGREQRST_MSB 19 -/* The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ -#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value. */ -#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000 -/* The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value. */ -#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff -/* The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field. */ -#define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register. */ -#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19) -/* Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000) - -/* - * Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout - * - * A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to - * put the SDRAM devices into self-refresh mode before starting a hardware - * sequenced warm reset timed-out and the Reset Manager had to proceed with the - * warm reset anyway. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ -#define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ -#define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24 -/* The width in bits of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ -#define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */ -#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000 -/* The mask used to clear the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */ -#define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff -/* The reset value of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */ -#define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_SDRSELFREFTMO field value from a register. */ -#define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24) -/* Produces a ALT_RSTMGR_STAT_SDRSELFREFTMO register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000) - -/* - * Field : FPGA manager handshake Timeout - fpgamgrhstimeout - * - * A 1 indicates that Reset Manager's request to the FPGA manager to stop driving - * configuration clock to FPGA CB before starting a hardware sequenced warm reset - * timed-out and the Reset Manager had to proceed with the warm reset anyway. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ -#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ -#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25 -/* The width in bits of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ -#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */ -#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000 -/* The mask used to clear the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */ -#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff -/* The reset value of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */ -#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_FPGAMGRHSTMO field value from a register. */ -#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25) -/* Produces a ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000) - -/* - * Field : SCAN manager handshake Timeout - scanhstimeout - * - * A 1 indicates that Reset Manager's request to the SCAN manager to stop driving - * JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out - * and the Reset Manager had to proceed with the warm reset anyway. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ -#define ALT_RSTMGR_STAT_SCANHSTMO_LSB 26 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ -#define ALT_RSTMGR_STAT_SCANHSTMO_MSB 26 -/* The width in bits of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ -#define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_SCANHSTMO register field value. */ -#define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000 -/* The mask used to clear the ALT_RSTMGR_STAT_SCANHSTMO register field value. */ -#define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff -/* The reset value of the ALT_RSTMGR_STAT_SCANHSTMO register field. */ -#define ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_SCANHSTMO field value from a register. */ -#define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26) -/* Produces a ALT_RSTMGR_STAT_SCANHSTMO register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000) - -/* - * Field : FPGA handshake Timeout - fpgahstimeout - * - * A 1 indicates that Reset Manager's handshake request to FPGA before starting a - * hardware sequenced warm reset timed-out and the Reset Manager had to proceed - * with the warm reset anyway. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ -#define ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ -#define ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27 -/* The width in bits of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ -#define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */ -#define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000 -/* The mask used to clear the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */ -#define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff -/* The reset value of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */ -#define ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_FPGAHSTMO field value from a register. */ -#define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27) -/* Produces a ALT_RSTMGR_STAT_FPGAHSTMO register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000) - -/* - * Field : ETR Stall Timeout - etrstalltimeout - * - * A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to - * stall its AXI master port before starting a hardware sequenced warm reset timed- - * out and the Reset Manager had to proceed with the warm reset anyway. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ -#define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ -#define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28 -/* The width in bits of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ -#define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */ -#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000 -/* The mask used to clear the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */ -#define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff -/* The reset value of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */ -#define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0 -/* Extracts the ALT_RSTMGR_STAT_ETRSTALLTMO field value from a register. */ -#define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28) -/* Produces a ALT_RSTMGR_STAT_ETRSTALLTMO register field value suitable for setting the register. */ -#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_RSTMGR_STAT. - */ -struct ALT_RSTMGR_STAT_s -{ - uint32_t porvoltrst : 1; /* Power-On Voltage Detector Cold Reset */ - uint32_t nporpinrst : 1; /* nPOR Pin Cold Reset */ - uint32_t fpgacoldrst : 1; /* FPGA Core Cold Reset */ - uint32_t configiocoldrst : 1; /* CONFIG_IO Cold Reset */ - uint32_t swcoldrst : 1; /* Software Cold Reset */ - uint32_t : 3; /* *UNDEFINED* */ - uint32_t nrstpinrst : 1; /* nRST Pin Warm Reset */ - uint32_t fpgawarmrst : 1; /* FPGA Core Warm Reset */ - uint32_t swwarmrst : 1; /* Software Warm Reset */ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t mpuwd0rst : 1; /* MPU Watchdog 0 Warm Reset */ - uint32_t mpuwd1rst : 1; /* MPU Watchdog 1 Warm Reset */ - uint32_t l4wd0rst : 1; /* L4 Watchdog 0 Warm Reset */ - uint32_t l4wd1rst : 1; /* L4 Watchdog 1 Warm Reset */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t fpgadbgrst : 1; /* FPGA Core Debug Reset */ - uint32_t cdbgreqrst : 1; /* DAP Debug Reset */ - uint32_t : 4; /* *UNDEFINED* */ - uint32_t sdrselfreftimeout : 1; /* SDRAM Self-Refresh Timeout */ - uint32_t fpgamgrhstimeout : 1; /* FPGA manager handshake Timeout */ - uint32_t scanhstimeout : 1; /* SCAN manager handshake Timeout */ - uint32_t fpgahstimeout : 1; /* FPGA handshake Timeout */ - uint32_t etrstalltimeout : 1; /* ETR Stall Timeout */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_RSTMGR_STAT. */ -typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */ -#define ALT_RSTMGR_STAT_OFST 0x0 - -/* - * Register : Control Register - ctrl - * - * The CTRL register is used by software to control reset behavior.It includes - * fields for software to initiate the cold and warm reset, enable hardware - * handshake with other modules before warm reset, and perform software handshake. - * The software handshake sequence must match the hardware sequence. Software - * mustde-assert the handshake request after asserting warm reset and before de- - * assert the warm reset. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------------------------------- - * [0] | RW | 0x0 | Software Cold Reset Request - * [1] | RW | 0x0 | Software Warm Reset Request - * [3:2] | ??? | 0x0 | *UNDEFINED* - * [4] | RW | 0x0 | SDRAM Self-Refresh Enable - * [5] | RW | 0x0 | SDRAM Self-Refresh Request - * [6] | R | 0x0 | SDRAM Self-Refresh Acknowledge - * [7] | ??? | 0x0 | *UNDEFINED* - * [8] | RW | 0x0 | FPGA Manager Handshake Enable - * [9] | RW | 0x0 | FPGA Manager Handshake Request - * [10] | R | Unknown | FPGA Manager Handshake Acknowledge - * [11] | ??? | 0x0 | *UNDEFINED* - * [12] | RW | 0x0 | SCAN Manager Handshake Enable - * [13] | RW | 0x0 | SCAN Manager Handshake Request - * [14] | R | Unknown | SCAN Manager Handshake Acknowledge - * [15] | ??? | 0x0 | *UNDEFINED* - * [16] | RW | 0x0 | FPGA Handshake Enable - * [17] | RW | 0x0 | FPGA Handshake Request - * [18] | R | Unknown | FPGA Handshake Acknowledge - * [19] | ??? | 0x0 | *UNDEFINED* - * [20] | RW | 0x1 | ETR (Embedded Trace Router) Stall Enable - * [21] | RW | 0x0 | ETR (Embedded Trace Router) Stall Request - * [22] | R | 0x0 | ETR (Embedded Trace Router) Stall Acknowledge - * [23] | RW | 0x0 | ETR (Embedded Trace Router) Stall After Warm Reset - * [31:24] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Software Cold Reset Request - swcoldrstreq - * - * This is a one-shot bit written by software to 1 to trigger a cold reset. It - * always reads the value 0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ -#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ -#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0 -/* The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ -#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */ -#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001 -/* The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */ -#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe -/* The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */ -#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register. */ -#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Software Warm Reset Request - swwarmrstreq - * - * This is a one-shot bit written by software to 1 to trigger a hardware sequenced - * warm reset. It always reads the value 0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ -#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ -#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1 -/* The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ -#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */ -#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002 -/* The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */ -#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd -/* The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */ -#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register. */ -#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : SDRAM Self-Refresh Enable - sdrselfrefen - * - * This field controls whether the contents of SDRAM devices survive a hardware - * sequenced warm reset. If set to 1, the Reset Manager makes a request to the - * SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode - * before asserting warm reset signals. However, if SDRAM is already in warm reset, - * Handshake with SDRAM is not performed. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4 -/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */ -#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010 -/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */ -#define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef -/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFEN field value from a register. */ -#define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_RSTMGR_CTL_SDRSELFREFEN register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : SDRAM Self-Refresh Request - sdrselfrefreq - * - * Software writes this field 1 to request to the SDRAM Controller Subsystem that - * it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM - * contents across a software warm reset. - * - * Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0. - * Note that it is possible for the SDRAM Controller Subsystem to never assert - * SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5 -/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */ -#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020 -/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */ -#define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf -/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_SDRSELFREFREQ field value from a register. */ -#define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_RSTMGR_CTL_SDRSELFREFREQ register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack - * - * This is the acknowlege for a SDRAM self-refresh mode request initiated by the - * SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put - * the SDRAM devices into self-refresh mode. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6 -/* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */ -#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040 -/* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */ -#define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf -/* The reset value of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */ -#define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_SDRSELFREQACK field value from a register. */ -#define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_RSTMGR_CTL_SDRSELFREQACK register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : FPGA Manager Handshake Enable - fpgamgrhsen - * - * Enables a handshake between the Reset Manager and FPGA Manager before a warm - * reset. The handshake is used to warn the FPGA Manager that a warm reset it - * coming so it can prepare for it. When the FPGA Manager receives a warm reset - * handshake, the FPGA Manager drives its output clock to a quiescent state to - * avoid glitches. - * - * If set to 1, the Manager makes a request to the FPGA Managerbefore asserting - * warm reset signals. However if the FPGA Manager is already in warm reset, the - * handshake is skipped. - * - * If set to 0, the handshake is skipped. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8 -/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100 -/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff -/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSEN field value from a register. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSEN register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : FPGA Manager Handshake Request - fpgamgrhsreq - * - * Software writes this field 1 to request to the FPGA Manager to idle its output - * clock. - * - * Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0. - * Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so - * software should timeout in this case. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9 -/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200 -/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff -/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSREQ field value from a register. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack - * - * This is the acknowlege (high active) that the FPGA manager has successfully - * idled its output clock. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10 -/* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400 -/* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff -/* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field is UNKNOWN. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSACK field value from a register. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_RSTMGR_CTL_FPGAMGRHSACK register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : SCAN Manager Handshake Enable - scanmgrhsen - * - * Enables a handshake between the Reset Manager and Scan Manager before a warm - * reset. The handshake is used to warn the Scan Manager that a warm reset it - * coming so it can prepare for it. When the Scan Manager receives a warm reset - * handshake, the Scan Manager drives its output clocks to a quiescent state to - * avoid glitches. - * - * If set to 1, the Reset Manager makes a request to the Scan Managerbefore - * asserting warm reset signals. However if the Scan Manager is already in warm - * reset, the handshake is skipped. - * - * If set to 0, the handshake is skipped. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12 -/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */ -#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000 -/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */ -#define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff -/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSEN field value from a register. */ -#define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_RSTMGR_CTL_SCANMGRHSEN register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000) - -/* - * Field : SCAN Manager Handshake Request - scanmgrhsreq - * - * Software writes this field 1 to request to the SCAN manager to idle its output - * clocks. - * - * Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0. - * Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g. - * its input clock is disabled) so software should timeout in this case. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13 -/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */ -#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000 -/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */ -#define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff -/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSREQ field value from a register. */ -#define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_RSTMGR_CTL_SCANMGRHSREQ register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : SCAN Manager Handshake Acknowledge - scanmgrhsack - * - * This is the acknowlege (high active) that the SCAN manager has successfully - * idled its output clocks. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14 -/* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */ -#define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */ -#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000 -/* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */ -#define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff -/* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSACK register field is UNKNOWN. */ -#define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_SCANMGRHSACK field value from a register. */ -#define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_RSTMGR_CTL_SCANMGRHSACK register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000) - -/* - * Field : FPGA Handshake Enable - fpgahsen - * - * This field controls whether to perform handshake with FPGA before asserting warm - * reset. - * - * If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm - * reset signals. However if FPGA is already in warm reset state, the handshake is - * not performed. - * - * If set to 0, the handshake is not performed - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ -#define ALT_RSTMGR_CTL_FPGAHSEN_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ -#define ALT_RSTMGR_CTL_FPGAHSEN_MSB 16 -/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ -#define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSEN register field value. */ -#define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000 -/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSEN register field value. */ -#define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff -/* The reset value of the ALT_RSTMGR_CTL_FPGAHSEN register field. */ -#define ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_FPGAHSEN field value from a register. */ -#define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16) -/* Produces a ALT_RSTMGR_CTL_FPGAHSEN register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000) - -/* - * Field : FPGA Handshake Request - fpgahsreq - * - * Software writes this field 1 to initiate handshake request to FPGA . - * - * Software waits for the FPGAHSACK to be active and then writes this field to 0. - * Note that it is possible for the FPGA to never assert FPGAHSACK so software - * should timeout in this case. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ -#define ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ -#define ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17 -/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ -#define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */ -#define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000 -/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */ -#define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff -/* The reset value of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */ -#define ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_FPGAHSREQ field value from a register. */ -#define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17) -/* Produces a ALT_RSTMGR_CTL_FPGAHSREQ register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000) - -/* - * Field : FPGA Handshake Acknowledge - fpgahsack - * - * This is the acknowlege (high active) that the FPGA handshake acknowledge has - * been received by Reset Manager. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ -#define ALT_RSTMGR_CTL_FPGAHSACK_LSB 18 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ -#define ALT_RSTMGR_CTL_FPGAHSACK_MSB 18 -/* The width in bits of the ALT_RSTMGR_CTL_FPGAHSACK register field. */ -#define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_FPGAHSACK register field value. */ -#define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000 -/* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSACK register field value. */ -#define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff -/* The reset value of the ALT_RSTMGR_CTL_FPGAHSACK register field is UNKNOWN. */ -#define ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_FPGAHSACK field value from a register. */ -#define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18) -/* Produces a ALT_RSTMGR_CTL_FPGAHSACK register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000) - -/* - * Field : ETR (Embedded Trace Router) Stall Enable - etrstallen - * - * This field controls whether the ETR is requested to idle its AXI master - * interface (i.e. finish outstanding transactions and not initiate any more) to - * the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager - * makes a request to the ETR to stall its AXI master and waits for it to finish - * any outstanding AXI transactions before a warm reset of the L3 Interconnect or a - * debug reset of the ETR. This stalling is required because the debug logic - * (including the ETR) is reset on a debug reset and the ETR AXI master is - * connected to the L3 Interconnect which is reset on a warm reset and these resets - * can happen independently. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20 -/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */ -#define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000 -/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */ -#define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff -/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1 -/* Extracts the ALT_RSTMGR_CTL_ETRSTALLEN field value from a register. */ -#define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20) -/* Produces a ALT_RSTMGR_CTL_ETRSTALLEN register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000) - -/* - * Field : ETR (Embedded Trace Router) Stall Request - etrstallreq - * - * Software writes this field 1 to request to the ETR that it stalls its AXI master - * to the L3 Interconnect. - * - * Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. - * Note that it is possible for the ETR to never assert ETRSTALLACK so software - * should timeout if ETRSTALLACK is never asserted. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21 -/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */ -#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000 -/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */ -#define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff -/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_ETRSTALLREQ field value from a register. */ -#define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21) -/* Produces a ALT_RSTMGR_CTL_ETRSTALLREQ register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000) - -/* - * Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack - * - * This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ - * field. A 1 indicates that the ETR has stalled its AXI master - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22 -/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */ -#define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000 -/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */ -#define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff -/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_ETRSTALLACK field value from a register. */ -#define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22) -/* Produces a ALT_RSTMGR_CTL_ETRSTALLACK register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000) - -/* - * Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst - * - * If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to - * indicate that the stall of the ETR AXI master is pending. Hardware leaves the - * ETR stalled until software clears this field by writing it with 1. Software must - * only clear this field when it is ready to have the ETR AXI master start making - * AXI requests to write trace data. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23 -/* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */ -#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000 -/* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */ -#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff -/* The reset value of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */ -#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0 -/* Extracts the ALT_RSTMGR_CTL_ETRSTALLWARMRST field value from a register. */ -#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23) -/* Produces a ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value suitable for setting the register. */ -#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_RSTMGR_CTL. - */ -struct ALT_RSTMGR_CTL_s -{ - uint32_t swcoldrstreq : 1; /* Software Cold Reset Request */ - uint32_t swwarmrstreq : 1; /* Software Warm Reset Request */ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t sdrselfrefen : 1; /* SDRAM Self-Refresh Enable */ - uint32_t sdrselfrefreq : 1; /* SDRAM Self-Refresh Request */ - const uint32_t sdrselfreqack : 1; /* SDRAM Self-Refresh Acknowledge */ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t fpgamgrhsen : 1; /* FPGA Manager Handshake Enable */ - uint32_t fpgamgrhsreq : 1; /* FPGA Manager Handshake Request */ - const uint32_t fpgamgrhsack : 1; /* FPGA Manager Handshake Acknowledge */ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t scanmgrhsen : 1; /* SCAN Manager Handshake Enable */ - uint32_t scanmgrhsreq : 1; /* SCAN Manager Handshake Request */ - const uint32_t scanmgrhsack : 1; /* SCAN Manager Handshake Acknowledge */ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t fpgahsen : 1; /* FPGA Handshake Enable */ - uint32_t fpgahsreq : 1; /* FPGA Handshake Request */ - const uint32_t fpgahsack : 1; /* FPGA Handshake Acknowledge */ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t etrstallen : 1; /* ETR (Embedded Trace Router) Stall Enable */ - uint32_t etrstallreq : 1; /* ETR (Embedded Trace Router) Stall Request */ - const uint32_t etrstallack : 1; /* ETR (Embedded Trace Router) Stall Acknowledge */ - uint32_t etrstallwarmrst : 1; /* ETR (Embedded Trace Router) Stall After Warm Reset */ - uint32_t : 8; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_RSTMGR_CTL. */ -typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component. */ -#define ALT_RSTMGR_CTL_OFST 0x4 - -/* - * Register : Reset Cycles Count Register - counts - * - * The COUNTS register is used by software to control reset behavior.It includes - * fields for software to control the behavior of the warm reset and nRST pin. - * - * Fields are only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------------- - * [7:0] | RW | 0x80 | Warm reset release delay count - * [27:8] | RW | 0x800 | nRST Pin Count - * [31:28] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Warm reset release delay count - warmrstcycles - * - * On a warm reset, the Reset Manager releases the reset to the Clock Manager, and - * then waits for the number of cycles specified in this register before releasing - * the rest of the hardware controlled resets. Value must be greater than 16. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ -#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ -#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7 -/* The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ -#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8 -/* The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */ -#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff -/* The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */ -#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00 -/* The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */ -#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80 -/* Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register. */ -#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register. */ -#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff) - -/* - * Field : nRST Pin Count - nrstcnt - * - * The Reset Manager pulls down the nRST pin on a warm reset for the number of - * cycles specified in this register. A value of 0x0 prevents the Reset Manager - * from pulling down the nRST pin. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ -#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ -#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27 -/* The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ -#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20 -/* The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */ -#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00 -/* The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */ -#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff -/* The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */ -#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800 -/* Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register. */ -#define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8) -/* Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register. */ -#define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_RSTMGR_COUNTS. - */ -struct ALT_RSTMGR_COUNTS_s -{ - uint32_t warmrstcycles : 8; /* Warm reset release delay count */ - uint32_t nrstcnt : 20; /* nRST Pin Count */ - uint32_t : 4; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_RSTMGR_COUNTS. */ -typedef volatile struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component. */ -#define ALT_RSTMGR_COUNTS_OFST 0x8 - -/* - * Register : MPU Module Reset Register - mpumodrst - * - * The MPUMODRST register is used by software to trigger module resets (individual - * module reset signals). Software explicitly asserts and de-asserts module reset - * signals by writing bits in the appropriate *MODRST register. It is up to - * software to ensure module reset signals are asserted for the appropriate length - * of time and are de-asserted in the correct order. It is also up to software to - * not assert a module reset signal that would prevent software from de-asserting - * the module reset signal. For example, software should not assert the module - * reset to the CPU executing the software. - * - * Software writes a bit to 1 to assert the module reset signal and to 0 to de- - * assert the module reset signal. - * - * All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset - * by a cold reset. The CPU1 field is also reset by a warm reset if not masked by - * the corresponding MPUWARMMASK field. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------- - * [0] | RW | 0x0 | CPU0 - * [1] | RW | 0x1 | CPU1 - * [2] | RW | 0x0 | Watchdogs - * [3] | RW | 0x0 | SCU/Peripherals - * [4] | RW | 0x0 | L2 - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : CPU0 - cpu0 - * - * Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1, - * ittriggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is - * de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted. - * - * When software changes this field from 1 to 0, it triggers the following - * sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de- - * asserted. - * - * Software needs to wait for at least 64 osc1_clk cycles between each change of - * this field to keep the proper reset/clkoff sequence. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ -#define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ -#define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0 -/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ -#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */ -#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */ -#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */ -#define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0 -/* Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register. */ -#define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : CPU1 - cpu1 - * - * Resets Cortex-A9 CPU1 in MPU. - * - * It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until - * software is ready to release CPU1 from reset by writing 0 to this field. - * - * On single-core devices, writes to this field are ignored.On dual-core devices, - * writes to this field trigger the same sequence as writes to the CPU0 field - * (except the sequence is performed on CPU1). - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ -#define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ -#define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1 -/* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ -#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */ -#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002 -/* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */ -#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd -/* The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */ -#define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1 -/* Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register. */ -#define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Watchdogs - wds - * - * Resets both per-CPU Watchdog Reset Status registers in MPU. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */ -#define ALT_RSTMGR_MPUMODRST_WDS_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */ -#define ALT_RSTMGR_MPUMODRST_WDS_MSB 2 -/* The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field. */ -#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value. */ -#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004 -/* The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value. */ -#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb -/* The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field. */ -#define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0 -/* Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register. */ -#define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register. */ -#define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : SCU/Peripherals - scuper - * - * Resets SCU and peripherals. Peripherals consist of the interrupt controller, - * global timer, both per-CPU private timers, and both per-CPU watchdogs (except - * for the Watchdog Reset Status registers). - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ -#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ -#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3 -/* The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ -#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */ -#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008 -/* The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */ -#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */ -#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0 -/* Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register. */ -#define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register. */ -#define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : L2 - l2 - * - * Resets L2 cache controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */ -#define ALT_RSTMGR_MPUMODRST_L2_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */ -#define ALT_RSTMGR_MPUMODRST_L2_MSB 4 -/* The width in bits of the ALT_RSTMGR_MPUMODRST_L2 register field. */ -#define ALT_RSTMGR_MPUMODRST_L2_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MPUMODRST_L2 register field value. */ -#define ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010 -/* The mask used to clear the ALT_RSTMGR_MPUMODRST_L2 register field value. */ -#define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef -/* The reset value of the ALT_RSTMGR_MPUMODRST_L2 register field. */ -#define ALT_RSTMGR_MPUMODRST_L2_RESET 0x0 -/* Extracts the ALT_RSTMGR_MPUMODRST_L2 field value from a register. */ -#define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_RSTMGR_MPUMODRST_L2 register field value suitable for setting the register. */ -#define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_RSTMGR_MPUMODRST. - */ -struct ALT_RSTMGR_MPUMODRST_s -{ - uint32_t cpu0 : 1; /* CPU0 */ - uint32_t cpu1 : 1; /* CPU1 */ - uint32_t wds : 1; /* Watchdogs */ - uint32_t scuper : 1; /* SCU/Peripherals */ - uint32_t l2 : 1; /* L2 */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */ -typedef volatile struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */ -#define ALT_RSTMGR_MPUMODRST_OFST 0x10 - -/* - * Register : Peripheral Module Reset Register - permodrst - * - * The PERMODRST register is used by software to trigger module resets (individual - * module reset signals). Software explicitly asserts and de-asserts module reset - * signals by writing bits in the appropriate *MODRST register. It is up to - * software to ensure module reset signals are asserted for the appropriate length - * of time and are de-asserted in the correct order. It is also up to software to - * not assert a module reset signal that would prevent software from de-asserting - * the module reset signal. For example, software should not assert the module - * reset to the CPU executing the software. - * - * Software writes a bit to 1 to assert the module reset signal and to 0 to de- - * assert the module reset signal. - * - * All fields are reset by a cold reset.All fields are also reset by a warm reset - * if not masked by the corresponding PERWARMMASK field. - * - * The reset value of all fields is 1. This holds the corresponding module in reset - * until software is ready to release the module from reset by writing 0 to its - * field. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:--------------------------- - * [0] | RW | 0x1 | EMAC0 - * [1] | RW | 0x1 | EMAC1 - * [2] | RW | 0x1 | USB0 - * [3] | RW | 0x1 | USB1 - * [4] | RW | 0x1 | NAND Flash - * [5] | RW | 0x1 | QSPI Flash - * [6] | RW | 0x1 | L4 Watchdog 0 - * [7] | RW | 0x1 | L4 Watchdog 1 - * [8] | RW | 0x1 | OSC1 Timer 0 - * [9] | RW | 0x1 | OSC1 Timer 1 - * [10] | RW | 0x1 | SP Timer 0 - * [11] | RW | 0x1 | SP Timer 1 - * [12] | RW | 0x1 | I2C0 - * [13] | RW | 0x1 | I2C1 - * [14] | RW | 0x1 | I2C2 - * [15] | RW | 0x1 | I2C3 - * [16] | RW | 0x1 | UART0 - * [17] | RW | 0x1 | UART1 - * [18] | RW | 0x1 | SPIM0 - * [19] | RW | 0x1 | SPIM1 - * [20] | RW | 0x1 | SPIS0 - * [21] | RW | 0x1 | SPIS1 - * [22] | RW | 0x1 | SD/MMC - * [23] | RW | 0x1 | CAN0 - * [24] | RW | 0x1 | CAN1 - * [25] | RW | 0x1 | GPIO0 - * [26] | RW | 0x1 | GPIO1 - * [27] | RW | 0x1 | GPIO2 - * [28] | RW | 0x1 | DMA Controller - * [29] | RW | 0x1 | SDRAM Controller Subsystem - * [31:30] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : EMAC0 - emac0 - * - * Resets EMAC0 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ -#define ALT_RSTMGR_PERMODRST_EMAC0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ -#define ALT_RSTMGR_PERMODRST_EMAC0_MSB 0 -/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ -#define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */ -#define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */ -#define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */ -#define ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_EMAC0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_RSTMGR_PERMODRST_EMAC0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : EMAC1 - emac1 - * - * Resets EMAC1 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ -#define ALT_RSTMGR_PERMODRST_EMAC1_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ -#define ALT_RSTMGR_PERMODRST_EMAC1_MSB 1 -/* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ -#define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */ -#define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */ -#define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd -/* The reset value of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */ -#define ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_EMAC1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_RSTMGR_PERMODRST_EMAC1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : USB0 - usb0 - * - * Resets USB0 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */ -#define ALT_RSTMGR_PERMODRST_USB0_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */ -#define ALT_RSTMGR_PERMODRST_USB0_MSB 2 -/* The width in bits of the ALT_RSTMGR_PERMODRST_USB0 register field. */ -#define ALT_RSTMGR_PERMODRST_USB0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_USB0 register field value. */ -#define ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB0 register field value. */ -#define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb -/* The reset value of the ALT_RSTMGR_PERMODRST_USB0 register field. */ -#define ALT_RSTMGR_PERMODRST_USB0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_USB0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_RSTMGR_PERMODRST_USB0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : USB1 - usb1 - * - * Resets USB1 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */ -#define ALT_RSTMGR_PERMODRST_USB1_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */ -#define ALT_RSTMGR_PERMODRST_USB1_MSB 3 -/* The width in bits of the ALT_RSTMGR_PERMODRST_USB1 register field. */ -#define ALT_RSTMGR_PERMODRST_USB1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_USB1 register field value. */ -#define ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_USB1 register field value. */ -#define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_RSTMGR_PERMODRST_USB1 register field. */ -#define ALT_RSTMGR_PERMODRST_USB1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_USB1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_RSTMGR_PERMODRST_USB1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : NAND Flash - nand - * - * Resets NAND flash controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */ -#define ALT_RSTMGR_PERMODRST_NAND_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */ -#define ALT_RSTMGR_PERMODRST_NAND_MSB 4 -/* The width in bits of the ALT_RSTMGR_PERMODRST_NAND register field. */ -#define ALT_RSTMGR_PERMODRST_NAND_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_NAND register field value. */ -#define ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_NAND register field value. */ -#define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef -/* The reset value of the ALT_RSTMGR_PERMODRST_NAND register field. */ -#define ALT_RSTMGR_PERMODRST_NAND_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_NAND field value from a register. */ -#define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_RSTMGR_PERMODRST_NAND register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : QSPI Flash - qspi - * - * Resets QSPI flash controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */ -#define ALT_RSTMGR_PERMODRST_QSPI_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */ -#define ALT_RSTMGR_PERMODRST_QSPI_MSB 5 -/* The width in bits of the ALT_RSTMGR_PERMODRST_QSPI register field. */ -#define ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_QSPI register field value. */ -#define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_QSPI register field value. */ -#define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf -/* The reset value of the ALT_RSTMGR_PERMODRST_QSPI register field. */ -#define ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_QSPI field value from a register. */ -#define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_RSTMGR_PERMODRST_QSPI register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : L4 Watchdog 0 - l4wd0 - * - * Resets watchdog 0 connected to L4 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ -#define ALT_RSTMGR_PERMODRST_L4WD0_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ -#define ALT_RSTMGR_PERMODRST_L4WD0_MSB 6 -/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ -#define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */ -#define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */ -#define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf -/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */ -#define ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_L4WD0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_RSTMGR_PERMODRST_L4WD0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : L4 Watchdog 1 - l4wd1 - * - * Resets watchdog 1 connected to L4 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ -#define ALT_RSTMGR_PERMODRST_L4WD1_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ -#define ALT_RSTMGR_PERMODRST_L4WD1_MSB 7 -/* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ -#define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */ -#define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */ -#define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f -/* The reset value of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */ -#define ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_L4WD1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_RSTMGR_PERMODRST_L4WD1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : OSC1 Timer 0 - osc1timer0 - * - * Resets OSC1 timer 0 connected to L4 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8 -/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff -/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : OSC1 Timer 1 - osc1timer1 - * - * Resets OSC1 timer 1 connected to L4 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9 -/* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff -/* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : SP Timer 0 - sptimer0 - * - * Resets SP timer 0 connected to L4 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10 -/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff -/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_RSTMGR_PERMODRST_SPTMR0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : SP Timer 1 - sptimer1 - * - * Resets SP timer 1 connected to L4 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11 -/* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_SPTMR1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_RSTMGR_PERMODRST_SPTMR1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : I2C0 - i2c0 - * - * Resets I2C0 controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C0_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C0_MSB 12 -/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C0 register field value. */ -#define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C0 register field value. */ -#define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff -/* The reset value of the ALT_RSTMGR_PERMODRST_I2C0 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_I2C0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_RSTMGR_PERMODRST_I2C0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000) - -/* - * Field : I2C1 - i2c1 - * - * Resets I2C1 controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C1_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C1_MSB 13 -/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C1 register field value. */ -#define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C1 register field value. */ -#define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff -/* The reset value of the ALT_RSTMGR_PERMODRST_I2C1 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_I2C1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_RSTMGR_PERMODRST_I2C1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : I2C2 - i2c2 - * - * Resets I2C2 controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C2_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C2_MSB 14 -/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C2 register field value. */ -#define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C2 register field value. */ -#define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff -/* The reset value of the ALT_RSTMGR_PERMODRST_I2C2 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_I2C2 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_RSTMGR_PERMODRST_I2C2 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000) - -/* - * Field : I2C3 - i2c3 - * - * Resets I2C3 controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C3_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C3_MSB 15 -/* The width in bits of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_I2C3 register field value. */ -#define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C3 register field value. */ -#define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff -/* The reset value of the ALT_RSTMGR_PERMODRST_I2C3 register field. */ -#define ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_I2C3 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15) -/* Produces a ALT_RSTMGR_PERMODRST_I2C3 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000) - -/* - * Field : UART0 - uart0 - * - * Resets UART0 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */ -#define ALT_RSTMGR_PERMODRST_UART0_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */ -#define ALT_RSTMGR_PERMODRST_UART0_MSB 16 -/* The width in bits of the ALT_RSTMGR_PERMODRST_UART0 register field. */ -#define ALT_RSTMGR_PERMODRST_UART0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_UART0 register field value. */ -#define ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART0 register field value. */ -#define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff -/* The reset value of the ALT_RSTMGR_PERMODRST_UART0 register field. */ -#define ALT_RSTMGR_PERMODRST_UART0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_UART0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16) -/* Produces a ALT_RSTMGR_PERMODRST_UART0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000) - -/* - * Field : UART1 - uart1 - * - * Resets UART1 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */ -#define ALT_RSTMGR_PERMODRST_UART1_LSB 17 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */ -#define ALT_RSTMGR_PERMODRST_UART1_MSB 17 -/* The width in bits of the ALT_RSTMGR_PERMODRST_UART1 register field. */ -#define ALT_RSTMGR_PERMODRST_UART1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_UART1 register field value. */ -#define ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_UART1 register field value. */ -#define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff -/* The reset value of the ALT_RSTMGR_PERMODRST_UART1 register field. */ -#define ALT_RSTMGR_PERMODRST_UART1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_UART1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17) -/* Produces a ALT_RSTMGR_PERMODRST_UART1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000) - -/* - * Field : SPIM0 - spim0 - * - * Resets SPIM0 controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIM0_LSB 18 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIM0_MSB 18 -/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff -/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_SPIM0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18) -/* Produces a ALT_RSTMGR_PERMODRST_SPIM0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000) - -/* - * Field : SPIM1 - spim1 - * - * Resets SPIM1 controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIM1_LSB 19 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIM1_MSB 19 -/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff -/* The reset value of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_SPIM1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19) -/* Produces a ALT_RSTMGR_PERMODRST_SPIM1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000) - -/* - * Field : SPIS0 - spis0 - * - * Resets SPIS0 controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIS0_LSB 20 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIS0_MSB 20 -/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff -/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_SPIS0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20) -/* Produces a ALT_RSTMGR_PERMODRST_SPIS0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000) - -/* - * Field : SPIS1 - spis1 - * - * Resets SPIS1 controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIS1_LSB 21 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIS1_MSB 21 -/* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */ -#define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff -/* The reset value of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */ -#define ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_SPIS1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21) -/* Produces a ALT_RSTMGR_PERMODRST_SPIS1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000) - -/* - * Field : SD/MMC - sdmmc - * - * Resets SD/MMC controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ -#define ALT_RSTMGR_PERMODRST_SDMMC_LSB 22 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ -#define ALT_RSTMGR_PERMODRST_SDMMC_MSB 22 -/* The width in bits of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ -#define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_SDMMC register field value. */ -#define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDMMC register field value. */ -#define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff -/* The reset value of the ALT_RSTMGR_PERMODRST_SDMMC register field. */ -#define ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_SDMMC field value from a register. */ -#define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22) -/* Produces a ALT_RSTMGR_PERMODRST_SDMMC register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000) - -/* - * Field : CAN0 - can0 - * - * Resets CAN0 controller. - * - * Writes to this field on devices not containing CAN controllers will be ignored. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ -#define ALT_RSTMGR_PERMODRST_CAN0_LSB 23 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ -#define ALT_RSTMGR_PERMODRST_CAN0_MSB 23 -/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ -#define ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN0 register field value. */ -#define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN0 register field value. */ -#define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff -/* The reset value of the ALT_RSTMGR_PERMODRST_CAN0 register field. */ -#define ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_CAN0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23) -/* Produces a ALT_RSTMGR_PERMODRST_CAN0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000) - -/* - * Field : CAN1 - can1 - * - * Resets CAN1 controller. - * - * Writes to this field on devices not containing CAN controllers will be ignored. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ -#define ALT_RSTMGR_PERMODRST_CAN1_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ -#define ALT_RSTMGR_PERMODRST_CAN1_MSB 24 -/* The width in bits of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ -#define ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_CAN1 register field value. */ -#define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN1 register field value. */ -#define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff -/* The reset value of the ALT_RSTMGR_PERMODRST_CAN1 register field. */ -#define ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_CAN1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24) -/* Produces a ALT_RSTMGR_PERMODRST_CAN1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000) - -/* - * Field : GPIO0 - gpio0 - * - * Resets GPIO0 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO0_LSB 25 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO0_MSB 25 -/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */ -#define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */ -#define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff -/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_GPIO0 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25) -/* Produces a ALT_RSTMGR_PERMODRST_GPIO0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000) - -/* - * Field : GPIO1 - gpio1 - * - * Resets GPIO1 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO1_LSB 26 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO1_MSB 26 -/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */ -#define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */ -#define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff -/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_GPIO1 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26) -/* Produces a ALT_RSTMGR_PERMODRST_GPIO1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000) - -/* - * Field : GPIO2 - gpio2 - * - * Resets GPIO2 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO2_LSB 27 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO2_MSB 27 -/* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */ -#define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */ -#define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff -/* The reset value of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */ -#define ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_GPIO2 field value from a register. */ -#define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27) -/* Produces a ALT_RSTMGR_PERMODRST_GPIO2 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000) - -/* - * Field : DMA Controller - dma - * - * Resets DMA controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */ -#define ALT_RSTMGR_PERMODRST_DMA_LSB 28 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */ -#define ALT_RSTMGR_PERMODRST_DMA_MSB 28 -/* The width in bits of the ALT_RSTMGR_PERMODRST_DMA register field. */ -#define ALT_RSTMGR_PERMODRST_DMA_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_DMA register field value. */ -#define ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_DMA register field value. */ -#define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff -/* The reset value of the ALT_RSTMGR_PERMODRST_DMA register field. */ -#define ALT_RSTMGR_PERMODRST_DMA_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_DMA field value from a register. */ -#define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28) -/* Produces a ALT_RSTMGR_PERMODRST_DMA register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000) - -/* - * Field : SDRAM Controller Subsystem - sdr - * - * Resets SDRAM Controller Subsystem affected by a warm or cold reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */ -#define ALT_RSTMGR_PERMODRST_SDR_LSB 29 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */ -#define ALT_RSTMGR_PERMODRST_SDR_MSB 29 -/* The width in bits of the ALT_RSTMGR_PERMODRST_SDR register field. */ -#define ALT_RSTMGR_PERMODRST_SDR_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PERMODRST_SDR register field value. */ -#define ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000 -/* The mask used to clear the ALT_RSTMGR_PERMODRST_SDR register field value. */ -#define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff -/* The reset value of the ALT_RSTMGR_PERMODRST_SDR register field. */ -#define ALT_RSTMGR_PERMODRST_SDR_RESET 0x1 -/* Extracts the ALT_RSTMGR_PERMODRST_SDR field value from a register. */ -#define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29) -/* Produces a ALT_RSTMGR_PERMODRST_SDR register field value suitable for setting the register. */ -#define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_RSTMGR_PERMODRST. - */ -struct ALT_RSTMGR_PERMODRST_s -{ - uint32_t emac0 : 1; /* EMAC0 */ - uint32_t emac1 : 1; /* EMAC1 */ - uint32_t usb0 : 1; /* USB0 */ - uint32_t usb1 : 1; /* USB1 */ - uint32_t nand : 1; /* NAND Flash */ - uint32_t qspi : 1; /* QSPI Flash */ - uint32_t l4wd0 : 1; /* L4 Watchdog 0 */ - uint32_t l4wd1 : 1; /* L4 Watchdog 1 */ - uint32_t osc1timer0 : 1; /* OSC1 Timer 0 */ - uint32_t osc1timer1 : 1; /* OSC1 Timer 1 */ - uint32_t sptimer0 : 1; /* SP Timer 0 */ - uint32_t sptimer1 : 1; /* SP Timer 1 */ - uint32_t i2c0 : 1; /* I2C0 */ - uint32_t i2c1 : 1; /* I2C1 */ - uint32_t i2c2 : 1; /* I2C2 */ - uint32_t i2c3 : 1; /* I2C3 */ - uint32_t uart0 : 1; /* UART0 */ - uint32_t uart1 : 1; /* UART1 */ - uint32_t spim0 : 1; /* SPIM0 */ - uint32_t spim1 : 1; /* SPIM1 */ - uint32_t spis0 : 1; /* SPIS0 */ - uint32_t spis1 : 1; /* SPIS1 */ - uint32_t sdmmc : 1; /* SD/MMC */ - uint32_t can0 : 1; /* CAN0 */ - uint32_t can1 : 1; /* CAN1 */ - uint32_t gpio0 : 1; /* GPIO0 */ - uint32_t gpio1 : 1; /* GPIO1 */ - uint32_t gpio2 : 1; /* GPIO2 */ - uint32_t dma : 1; /* DMA Controller */ - uint32_t sdr : 1; /* SDRAM Controller Subsystem */ - uint32_t : 2; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_RSTMGR_PERMODRST. */ -typedef volatile struct ALT_RSTMGR_PERMODRST_s ALT_RSTMGR_PERMODRST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of the component. */ -#define ALT_RSTMGR_PERMODRST_OFST 0x14 - -/* - * Register : Peripheral 2 Module Reset Register - per2modrst - * - * The PER2MODRST register is used by software to trigger module resets (individual - * module reset signals). Software explicitly asserts and de-asserts module reset - * signals by writing bits in the appropriate *MODRST register. It is up to - * software to ensure module reset signals are asserted for the appropriate length - * of time and are de-asserted in the correct order. It is also up to software to - * not assert a module reset signal that would prevent software from de-asserting - * the module reset signal. For example, software should not assert the module - * reset to the CPU executing the software. - * - * Software writes a bit to 1 to assert the module reset signal and to 0 to de- - * assert the module reset signal. - * - * All fields are reset by a cold reset.All fields are also reset by a warm reset - * if not masked by the corresponding PERWARMMASK field. - * - * The reset value of all fields is 1. This holds the corresponding module in reset - * until software is ready to release the module from reset by writing 0 to its - * field. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [0] | RW | 0x1 | FPGA DMA0 - * [1] | RW | 0x1 | FPGA DMA1 - * [2] | RW | 0x1 | FPGA DMA2 - * [3] | RW | 0x1 | FPGA DMA3 - * [4] | RW | 0x1 | FPGA DMA4 - * [5] | RW | 0x1 | FPGA DMA5 - * [6] | RW | 0x1 | FPGA DMA6 - * [7] | RW | 0x1 | FPGA DMA7 - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : FPGA DMA0 - dmaif0 - * - * Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA - * Controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0 -/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1 -/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF0 field value from a register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF0 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : FPGA DMA1 - dmaif1 - * - * Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA - * Controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1 -/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002 -/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd -/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1 -/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF1 field value from a register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF1 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : FPGA DMA2 - dmaif2 - * - * Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA - * Controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2 -/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004 -/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb -/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1 -/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF2 field value from a register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF2 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : FPGA DMA3 - dmaif3 - * - * Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA - * Controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3 -/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008 -/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1 -/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF3 field value from a register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF3 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : FPGA DMA4 - dmaif4 - * - * Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA - * Controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4 -/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010 -/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef -/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1 -/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF4 field value from a register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF4 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : FPGA DMA5 - dmaif5 - * - * Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA - * Controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5 -/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020 -/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf -/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1 -/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF5 field value from a register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF5 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : FPGA DMA6 - dmaif6 - * - * Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA - * Controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6 -/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040 -/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf -/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1 -/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF6 field value from a register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF6 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : FPGA DMA7 - dmaif7 - * - * Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA - * Controller - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7 -/* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080 -/* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f -/* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1 -/* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF7 field value from a register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_RSTMGR_PER2MODRST_DMAIF7 register field value suitable for setting the register. */ -#define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_RSTMGR_PER2MODRST. - */ -struct ALT_RSTMGR_PER2MODRST_s -{ - uint32_t dmaif0 : 1; /* FPGA DMA0 */ - uint32_t dmaif1 : 1; /* FPGA DMA1 */ - uint32_t dmaif2 : 1; /* FPGA DMA2 */ - uint32_t dmaif3 : 1; /* FPGA DMA3 */ - uint32_t dmaif4 : 1; /* FPGA DMA4 */ - uint32_t dmaif5 : 1; /* FPGA DMA5 */ - uint32_t dmaif6 : 1; /* FPGA DMA6 */ - uint32_t dmaif7 : 1; /* FPGA DMA7 */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_RSTMGR_PER2MODRST. */ -typedef volatile struct ALT_RSTMGR_PER2MODRST_s ALT_RSTMGR_PER2MODRST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_RSTMGR_PER2MODRST register from the beginning of the component. */ -#define ALT_RSTMGR_PER2MODRST_OFST 0x18 - -/* - * Register : Bridge Module Reset Register - brgmodrst - * - * The BRGMODRST register is used by software to trigger module resets (individual - * module reset signals). Software explicitly asserts and de-asserts module reset - * signals by writing bits in the appropriate *MODRST register. It is up to - * software to ensure module reset signals are asserted for the appropriate length - * of time and are de-asserted in the correct order. It is also up to software to - * not assert a module reset signal that would prevent software from de-asserting - * the module reset signal. For example, software should not assert the module - * reset to the CPU executing the software. - * - * Software writes a bit to 1 to assert the module reset signal and to 0 to de- - * assert the module reset signal. - * - * All fields are reset by a cold reset.All fields are also reset by a warm reset - * if not masked by the corresponding BRGWARMMASK field. - * - * The reset value of all fields is 1. This holds the corresponding module in reset - * until software is ready to release the module from reset by writing 0 to its - * field. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------ - * [0] | RW | 0x1 | HPS2FPGA Bridge - * [1] | RW | 0x1 | LWHPS2FPGA Bridge - * [2] | RW | 0x1 | FPGA2HPS Bridge - * [31:3] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : HPS2FPGA Bridge - hps2fpga - * - * Resets HPS2FPGA Bridge - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */ -#define ALT_RSTMGR_BRGMODRST_H2F_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */ -#define ALT_RSTMGR_BRGMODRST_H2F_MSB 0 -/* The width in bits of the ALT_RSTMGR_BRGMODRST_H2F register field. */ -#define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_BRGMODRST_H2F register field value. */ -#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001 -/* The mask used to clear the ALT_RSTMGR_BRGMODRST_H2F register field value. */ -#define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe -/* The reset value of the ALT_RSTMGR_BRGMODRST_H2F register field. */ -#define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1 -/* Extracts the ALT_RSTMGR_BRGMODRST_H2F field value from a register. */ -#define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_RSTMGR_BRGMODRST_H2F register field value suitable for setting the register. */ -#define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : LWHPS2FPGA Bridge - lwhps2fpga - * - * Resets LWHPS2FPGA Bridge - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ -#define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ -#define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1 -/* The width in bits of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ -#define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */ -#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002 -/* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */ -#define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd -/* The reset value of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */ -#define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1 -/* Extracts the ALT_RSTMGR_BRGMODRST_LWH2F field value from a register. */ -#define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_RSTMGR_BRGMODRST_LWH2F register field value suitable for setting the register. */ -#define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : FPGA2HPS Bridge - fpga2hps - * - * Resets FPGA2HPS Bridge - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */ -#define ALT_RSTMGR_BRGMODRST_F2H_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */ -#define ALT_RSTMGR_BRGMODRST_F2H_MSB 2 -/* The width in bits of the ALT_RSTMGR_BRGMODRST_F2H register field. */ -#define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_BRGMODRST_F2H register field value. */ -#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004 -/* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2H register field value. */ -#define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb -/* The reset value of the ALT_RSTMGR_BRGMODRST_F2H register field. */ -#define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1 -/* Extracts the ALT_RSTMGR_BRGMODRST_F2H field value from a register. */ -#define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_RSTMGR_BRGMODRST_F2H register field value suitable for setting the register. */ -#define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_RSTMGR_BRGMODRST. - */ -struct ALT_RSTMGR_BRGMODRST_s -{ - uint32_t hps2fpga : 1; /* HPS2FPGA Bridge */ - uint32_t lwhps2fpga : 1; /* LWHPS2FPGA Bridge */ - uint32_t fpga2hps : 1; /* FPGA2HPS Bridge */ - uint32_t : 29; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */ -typedef volatile struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */ -#define ALT_RSTMGR_BRGMODRST_OFST 0x1c - -/* - * Register : Miscellaneous Module Reset Register - miscmodrst - * - * The MISCMODRST register is used by software to trigger module resets (individual - * module reset signals). Software explicitly asserts and de-asserts module reset - * signals by writing bits in the appropriate *MODRST register. It is up to - * software to ensure module reset signals are asserted for the appropriate length - * of time and are de-asserted in the correct order. It is also up to software to - * not assert a module reset signal that would prevent software from de-asserting - * the module reset signal. For example, software should not assert the module - * reset to the CPU executing the software. - * - * Software writes a bit to 1 to assert the module reset signal and to 0 to de- - * assert the module reset signal. - * - * All fields are only reset by a cold reset - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------------------------- - * [0] | RW | 0x0 | Boot ROM - * [1] | RW | 0x0 | On-chip RAM - * [2] | RW | 0x0 | System Manager (Cold or Warm) - * [3] | RW | 0x0 | System Manager (Cold-only) - * [4] | RW | 0x0 | FPGA Manager - * [5] | RW | 0x0 | ACP ID Mapper - * [6] | RW | 0x0 | HPS to FPGA Core (Cold or Warm) - * [7] | RW | 0x0 | HPS to FPGA Core (Cold-only) - * [8] | RW | 0x0 | nRST Pin - * [9] | RW | 0x0 | Timestamp - * [10] | RW | 0x0 | Clock Manager - * [11] | RW | 0x0 | Scan Manager - * [12] | RW | 0x0 | Freeze Controller - * [13] | RW | 0x0 | System/Debug - * [14] | RW | 0x0 | Debug - * [15] | RW | 0x0 | TAP Controller - * [16] | RW | 0x0 | SDRAM Controller Subsystem Cold Reset - * [31:17] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Boot ROM - rom - * - * Resets Boot ROM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */ -#define ALT_RSTMGR_MISCMODRST_ROM_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */ -#define ALT_RSTMGR_MISCMODRST_ROM_MSB 0 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_ROM register field. */ -#define ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_ROM register field value. */ -#define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ROM register field value. */ -#define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe -/* The reset value of the ALT_RSTMGR_MISCMODRST_ROM register field. */ -#define ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_ROM field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_RSTMGR_MISCMODRST_ROM register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : On-chip RAM - ocram - * - * Resets On-chip RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ -#define ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ -#define ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ -#define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */ -#define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */ -#define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd -/* The reset value of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */ -#define ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_OCRAM field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_RSTMGR_MISCMODRST_OCRAM register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : System Manager (Cold or Warm) - sysmgr - * - * Resets logic in System Manager that doesn't differentiate between cold and warm - * resets - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb -/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGR field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGR register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : System Manager (Cold-only) - sysmgrcold - * - * Resets logic in System Manager that is only reset by a cold reset (ignores warm - * reset) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : FPGA Manager - fpgamgr - * - * Resets FPGA Manager - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */ -#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */ -#define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef -/* The reset value of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_FPGAMGR field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_RSTMGR_MISCMODRST_FPGAMGR register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : ACP ID Mapper - acpidmap - * - * Resets ACP ID Mapper - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ -#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ -#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ -#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */ -#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */ -#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf -/* The reset value of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */ -#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_ACPIDMAP field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : HPS to FPGA Core (Cold or Warm) - s2f - * - * Resets logic in FPGA core that doesn't differentiate between HPS cold and warm - * resets (h2f_rst_n = 1) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */ -#define ALT_RSTMGR_MISCMODRST_S2F_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */ -#define ALT_RSTMGR_MISCMODRST_S2F_MSB 6 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2F register field. */ -#define ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2F register field value. */ -#define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2F register field value. */ -#define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf -/* The reset value of the ALT_RSTMGR_MISCMODRST_S2F register field. */ -#define ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_S2F field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_RSTMGR_MISCMODRST_S2F register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : HPS to FPGA Core (Cold-only) - s2fcold - * - * Resets logic in FPGA core that is only reset by a cold reset (ignores warm - * reset) (h2f_cold_rst_n = 1) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f -/* The reset value of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_S2FCOLD field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_RSTMGR_MISCMODRST_S2FCOLD register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : nRST Pin - nrstpin - * - * Pulls nRST pin low - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ -#define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ -#define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ -#define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */ -#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */ -#define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff -/* The reset value of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */ -#define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_NRSTPIN field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_RSTMGR_MISCMODRST_NRSTPIN register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Timestamp - timestampcold - * - * Resets debug timestamp to 0 (cold reset only) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff -/* The reset value of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_TSCOLD field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_RSTMGR_MISCMODRST_TSCOLD register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Clock Manager - clkmgrcold - * - * Resets Clock Manager (cold reset only) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff -/* The reset value of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : Scan Manager - scanmgr - * - * Resets Scan Manager - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */ -#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */ -#define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */ -#define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_SCANMGR field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_RSTMGR_MISCMODRST_SCANMGR register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : Freeze Controller - frzctrlcold - * - * Resets Freeze Controller in System Manager (cold reset only) - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff -/* The reset value of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000) - -/* - * Field : System/Debug - sysdbg - * - * Resets logic that spans the system and debug domains. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */ -#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */ -#define ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff -/* The reset value of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */ -#define ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_SYSDBG field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_RSTMGR_MISCMODRST_SYSDBG register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : Debug - dbg - * - * Resets logic located only in the debug domain. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */ -#define ALT_RSTMGR_MISCMODRST_DBG_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */ -#define ALT_RSTMGR_MISCMODRST_DBG_MSB 14 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_DBG register field. */ -#define ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_DBG register field value. */ -#define ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_DBG register field value. */ -#define ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff -/* The reset value of the ALT_RSTMGR_MISCMODRST_DBG register field. */ -#define ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_DBG field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_RSTMGR_MISCMODRST_DBG register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000) - -/* - * Field : TAP Controller - tapcold - * - * Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e. - * nTRST pin). Cold reset only. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff -/* The reset value of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_TAPCOLD field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15) -/* Produces a ALT_RSTMGR_MISCMODRST_TAPCOLD register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000) - -/* - * Field : SDRAM Controller Subsystem Cold Reset - sdrcold - * - * Resets logic in SDRAM Controller Subsystem affected only by a cold reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16 -/* The width in bits of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1 -/* The mask used to set the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000 -/* The mask used to clear the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */ -#define ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff -/* The reset value of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */ -#define ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0 -/* Extracts the ALT_RSTMGR_MISCMODRST_SDRCOLD field value from a register. */ -#define ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16) -/* Produces a ALT_RSTMGR_MISCMODRST_SDRCOLD register field value suitable for setting the register. */ -#define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_RSTMGR_MISCMODRST. - */ -struct ALT_RSTMGR_MISCMODRST_s -{ - uint32_t rom : 1; /* Boot ROM */ - uint32_t ocram : 1; /* On-chip RAM */ - uint32_t sysmgr : 1; /* System Manager (Cold or Warm) */ - uint32_t sysmgrcold : 1; /* System Manager (Cold-only) */ - uint32_t fpgamgr : 1; /* FPGA Manager */ - uint32_t acpidmap : 1; /* ACP ID Mapper */ - uint32_t s2f : 1; /* HPS to FPGA Core (Cold or Warm) */ - uint32_t s2fcold : 1; /* HPS to FPGA Core (Cold-only) */ - uint32_t nrstpin : 1; /* nRST Pin */ - uint32_t timestampcold : 1; /* Timestamp */ - uint32_t clkmgrcold : 1; /* Clock Manager */ - uint32_t scanmgr : 1; /* Scan Manager */ - uint32_t frzctrlcold : 1; /* Freeze Controller */ - uint32_t sysdbg : 1; /* System/Debug */ - uint32_t dbg : 1; /* Debug */ - uint32_t tapcold : 1; /* TAP Controller */ - uint32_t sdrcold : 1; /* SDRAM Controller Subsystem Cold Reset */ - uint32_t : 15; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_RSTMGR_MISCMODRST. */ -typedef volatile struct ALT_RSTMGR_MISCMODRST_s ALT_RSTMGR_MISCMODRST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_RSTMGR_MISCMODRST register from the beginning of the component. */ -#define ALT_RSTMGR_MISCMODRST_OFST 0x20 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_RSTMGR. - */ -struct ALT_RSTMGR_s -{ - volatile ALT_RSTMGR_STAT_t stat; /* ALT_RSTMGR_STAT */ - volatile ALT_RSTMGR_CTL_t ctrl; /* ALT_RSTMGR_CTL */ - volatile ALT_RSTMGR_COUNTS_t counts; /* ALT_RSTMGR_COUNTS */ - volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ - volatile ALT_RSTMGR_MPUMODRST_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */ - volatile ALT_RSTMGR_PERMODRST_t permodrst; /* ALT_RSTMGR_PERMODRST */ - volatile ALT_RSTMGR_PER2MODRST_t per2modrst; /* ALT_RSTMGR_PER2MODRST */ - volatile ALT_RSTMGR_BRGMODRST_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */ - volatile ALT_RSTMGR_MISCMODRST_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */ - volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_RSTMGR. */ -typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t; -/* The struct declaration for the raw register contents of register group ALT_RSTMGR. */ -struct ALT_RSTMGR_raw_s -{ - volatile uint32_t stat; /* ALT_RSTMGR_STAT */ - volatile uint32_t ctrl; /* ALT_RSTMGR_CTL */ - volatile uint32_t counts; /* ALT_RSTMGR_COUNTS */ - volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ - volatile uint32_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */ - volatile uint32_t permodrst; /* ALT_RSTMGR_PERMODRST */ - volatile uint32_t per2modrst; /* ALT_RSTMGR_PER2MODRST */ - volatile uint32_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */ - volatile uint32_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */ - volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_RSTMGR. */ -typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_RSTMGR_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_sdr.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_sdr.h deleted file mode 100644 index 785aa743cb..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_sdr.h +++ /dev/null @@ -1,4149 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_SDR */ - -#ifndef __ALTERA_ALT_SDR_H__ -#define __ALTERA_ALT_SDR_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : SDRAM Controller - ALT_SDR - * SDRAM Controller - * - * Address map for the SDRAM Interface registers - * - */ -/* - * Register Group : SDRAM Controller Module - ALT_SDR_CTL - * SDRAM Controller Module - * - * Address map for the SDRAM controller and multi-port front-end. - * - * All registers in this group reset to zero. - * - */ -/* - * Register : Controller Configuration Register - ctrlcfg - * - * The Controller Configuration Register determines the behavior of the controller. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------- - * [2:0] | RW | Unknown | DRAM Memory Type - * [7:3] | RW | Unknown | DRAM Memory Burst Length - * [9:8] | RW | Unknown | Address Interleaving Order - * [10] | RW | Unknown | ECC Enable - * [11] | RW | Unknown | ECC Auto-Correction Enable - * [12] | RW | Unknown | TBD - * [13] | RW | Unknown | Generate Single Bit Errors - * [14] | RW | Unknown | Generate Double Bit Errors - * [15] | RW | Unknown | Command Reorder Enable - * [21:16] | RW | Unknown | Starvation Limit - * [22] | RW | Unknown | DQS Tracking Enable - * [23] | RW | Unknown | No DM Pins Present - * [24] | RW | Unknown | Burst Interrupt Enable - * [25] | RW | Unknown | Burst Terminate Enable - * [31:26] | ??? | Unknown | *UNDEFINED* - * - */ -/* - * Field : DRAM Memory Type - memtype - * - * Selects memory type. Program this field with one of the following binary values, - * "001" for DDR2 SDRAM, "010" for DDR3 SDRAM, "011" - * for LPDDR1 SDRAM or "100" for LPDDR2 SDRAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ -#define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ -#define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */ -#define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */ -#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */ -#define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8 -/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_MEMTYPE field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0) -/* Produces a ALT_SDR_CTL_CTLCFG_MEMTYPE register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007) - -/* - * Field : DRAM Memory Burst Length - membl - * - * Configures burst length as a static decimal value. Legal values are valid for - * JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, this - * should be programmed with 8 (binary "01000"), for DDR2 it can be - * either 4 or 8 depending on the exact DRAM chip. LPDDR2 can be programmed with - * 4, 8, or 16 and LPDDR can be programmed with 2, 4, or 8. You must also program - * the membl field in the staticcfg register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ -#define ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ -#define ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */ -#define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */ -#define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */ -#define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07 -/* The reset value of the ALT_SDR_CTL_CTLCFG_MEMBL register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_MEMBL field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3) -/* Produces a ALT_SDR_CTL_CTLCFG_MEMBL register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8) - -/* - * Field : Address Interleaving Order - addrorder - * - * Selects the order for address interleaving. Programming this field with - * different values gives different mappings between the AXI or Avalon-MM address - * and the SDRAM address. Program this field with the following binary values to - * select the ordering. "00" - chip, row, bank, column, "01" - - * chip, bank, row, column, "10"-row, chip, bank, column - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ -#define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ -#define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */ -#define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */ -#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */ -#define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff -/* The reset value of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_ADDRORDER field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8) -/* Produces a ALT_SDR_CTL_CTLCFG_ADDRORDER register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300) - -/* - * Field : ECC Enable - eccen - * - * Enable the generation and checking of ECC. This bit must only be set if the - * memory connected to the SDRAM interface is 24 or 40 bits wide. If you set this, - * you must clear the useeccasdata field in the staticcfg register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ -#define ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ -#define ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */ -#define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */ -#define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */ -#define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff -/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCEN register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_ECCEN field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_SDR_CTL_CTLCFG_ECCEN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : ECC Auto-Correction Enable - ecccorren - * - * Enable auto correction of the read data returned when single bit error is - * detected. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ -#define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ -#define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */ -#define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */ -#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */ -#define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_ECCCORREN field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_SDR_CTL_CTLCFG_ECCCORREN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : TBD - cfg_enable_ecc_code_overwrites - * - * Set to a one to enable ECC overwrites. ECC overwrites occur when a correctable - * ECC error is seen and cause a new read/modify/write to be scheduled for that - * location to clear the ECC error. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ -#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ -#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */ -#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */ -#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */ -#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff -/* The reset value of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000) - -/* - * Field : Generate Single Bit Errors - gensbe - * - * Enable the deliberate insertion of single bit errors in data written to memory. - * This should only be used for testing purposes. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ -#define ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ -#define ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */ -#define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */ -#define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */ -#define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff -/* The reset value of the ALT_SDR_CTL_CTLCFG_GENSBE register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_GENSBE field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_SDR_CTL_CTLCFG_GENSBE register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : Generate Double Bit Errors - gendbe - * - * Enable the deliberate insertion of double bit errors in data written to memory. - * This should only be used for testing purposes. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ -#define ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ -#define ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */ -#define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */ -#define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */ -#define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff -/* The reset value of the ALT_SDR_CTL_CTLCFG_GENDBE register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_GENDBE field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_SDR_CTL_CTLCFG_GENDBE register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000) - -/* - * Field : Command Reorder Enable - reorderen - * - * This bit controls whether the controller can re-order operations to optimize - * SDRAM bandwidth. It should generally be set to a one. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ -#define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ -#define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */ -#define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */ -#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */ -#define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff -/* The reset value of the ALT_SDR_CTL_CTLCFG_REORDEREN register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_REORDEREN field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15) -/* Produces a ALT_SDR_CTL_CTLCFG_REORDEREN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000) - -/* - * Field : Starvation Limit - starvelimit - * - * Specifies the number of DRAM burst transactions an individual transaction will - * allow to reorder ahead of it before its priority is raised in the memory - * controller. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ -#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ -#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */ -#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */ -#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */ -#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff -/* The reset value of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_STARVELIMIT field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16) -/* Produces a ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000) - -/* - * Field : DQS Tracking Enable - dqstrken - * - * Enables DQS tracking in the PHY. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ -#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ -#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */ -#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */ -#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */ -#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff -/* The reset value of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_DQSTRKEN field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22) -/* Produces a ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000) - -/* - * Field : No DM Pins Present - nodmpins - * - * Set to a one to enable DRAM operation if no DM pins are connected. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ -#define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ -#define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */ -#define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */ -#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */ -#define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff -/* The reset value of the ALT_SDR_CTL_CTLCFG_NODMPINS register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_NODMPINS field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23) -/* Produces a ALT_SDR_CTL_CTLCFG_NODMPINS register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000) - -/* - * Field : Burst Interrupt Enable - burstintren - * - * Set to a one to enable the controller to issue burst interrupt commands. This - * must only be set when the DRAM memory type is LPDDR2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ -#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ -#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */ -#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */ -#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */ -#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff -/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTINTREN field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24) -/* Produces a ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000) - -/* - * Field : Burst Terminate Enable - bursttermen - * - * Set to a one to enable the controller to issue burst terminate commands. This - * must only be set when the DRAM memory type is LPDDR2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ -#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ -#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25 -/* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */ -#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */ -#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000 -/* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */ -#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff -/* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLCFG_BURSTTERMEN field value from a register. */ -#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25) -/* Produces a ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_CTLCFG. - */ -struct ALT_SDR_CTL_CTLCFG_s -{ - uint32_t memtype : 3; /* DRAM Memory Type */ - uint32_t membl : 5; /* DRAM Memory Burst Length */ - uint32_t addrorder : 2; /* Address Interleaving Order */ - uint32_t eccen : 1; /* ECC Enable */ - uint32_t ecccorren : 1; /* ECC Auto-Correction Enable */ - uint32_t cfg_enable_ecc_code_overwrites : 1; /* TBD */ - uint32_t gensbe : 1; /* Generate Single Bit Errors */ - uint32_t gendbe : 1; /* Generate Double Bit Errors */ - uint32_t reorderen : 1; /* Command Reorder Enable */ - uint32_t starvelimit : 6; /* Starvation Limit */ - uint32_t dqstrken : 1; /* DQS Tracking Enable */ - uint32_t nodmpins : 1; /* No DM Pins Present */ - uint32_t burstintren : 1; /* Burst Interrupt Enable */ - uint32_t bursttermen : 1; /* Burst Terminate Enable */ - uint32_t : 6; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_CTLCFG. */ -typedef volatile struct ALT_SDR_CTL_CTLCFG_s ALT_SDR_CTL_CTLCFG_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_CTLCFG register from the beginning of the component. */ -#define ALT_SDR_CTL_CTLCFG_OFST 0x0 - -/* - * Register : DRAM Timings 1 Register - dramtiming1 - * - * This register implements JEDEC standardized timing parameters. It should be - * programmed in clock cycles, for the value specified by the memory vendor. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------- - * [3:0] | RW | Unknown | CAS Write Latency - * [8:4] | RW | Unknown | Additive Latency - * [13:9] | RW | Unknown | CAS Read Latency - * [17:14] | RW | Unknown | Activate to Activate Delay - * [23:18] | RW | Unknown | Four Activate Window Time - * [31:24] | RW | Unknown | Refresh Cycle Time - * - */ -/* - * Field : CAS Write Latency - tcwl - * - * Memory write latency. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCWL field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCWL register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f) - -/* - * Field : Additive Latency - tal - * - * Memory additive latency. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TAL register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TAL field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_SDR_CTL_DRAMTIMING1_TAL register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : CAS Read Latency - tcl - * - * Memory read latency. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCL register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCL field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9) -/* Produces a ALT_SDR_CTL_DRAMTIMING1_TCL register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00) - -/* - * Field : Activate to Activate Delay - trrd - * - * The activate to activate, different banks timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRRD field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14) -/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRRD register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000) - -/* - * Field : Four Activate Window Time - tfaw - * - * The four-activate window timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TFAW field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18) -/* Produces a ALT_SDR_CTL_DRAMTIMING1_TFAW register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000) - -/* - * Field : Refresh Cycle Time - trfc - * - * The refresh cycle timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRFC field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24) -/* Produces a ALT_SDR_CTL_DRAMTIMING1_TRFC register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMTIMING1. - */ -struct ALT_SDR_CTL_DRAMTIMING1_s -{ - uint32_t tcwl : 4; /* CAS Write Latency */ - uint32_t tal : 5; /* Additive Latency */ - uint32_t tcl : 5; /* CAS Read Latency */ - uint32_t trrd : 4; /* Activate to Activate Delay */ - uint32_t tfaw : 6; /* Four Activate Window Time */ - uint32_t trfc : 8; /* Refresh Cycle Time */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING1. */ -typedef volatile struct ALT_SDR_CTL_DRAMTIMING1_s ALT_SDR_CTL_DRAMTIMING1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMTIMING1 register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMTIMING1_OFST 0x4 - -/* - * Register : DRAM Timings 2 Register - dramtiming2 - * - * This register implements JEDEC standardized timing parameters. It should be - * programmed in clock cycles, for the value specified by the memory vendor. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:-------------------------------- - * [12:0] | RW | Unknown | Refresh Interval - * [16:13] | RW | Unknown | Activate to Read or Write Delay - * [20:17] | RW | Unknown | Row Precharge Time - * [24:21] | RW | Unknown | Write Recovery Time - * [28:25] | RW | Unknown | Write to Read Time - * [31:29] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Refresh Interval - trefi - * - * The refresh interval timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000 -/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TREFI field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0) -/* Produces a ALT_SDR_CTL_DRAMTIMING2_TREFI register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff) - -/* - * Field : Activate to Read or Write Delay - trcd - * - * The activate to read/write timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRCD field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13) -/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRCD register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000) - -/* - * Field : Row Precharge Time - trp - * - * The precharge to activate timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRP register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRP field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17) -/* Produces a ALT_SDR_CTL_DRAMTIMING2_TRP register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000) - -/* - * Field : Write Recovery Time - twr - * - * The write recovery timing. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWR register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWR field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21) -/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWR register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000) - -/* - * Field : Write to Read Time - twtr - * - * The write to read timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWTR field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25) -/* Produces a ALT_SDR_CTL_DRAMTIMING2_TWTR register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMTIMING2. - */ -struct ALT_SDR_CTL_DRAMTIMING2_s -{ - uint32_t trefi : 13; /* Refresh Interval */ - uint32_t trcd : 4; /* Activate to Read or Write Delay */ - uint32_t trp : 4; /* Row Precharge Time */ - uint32_t twr : 4; /* Write Recovery Time */ - uint32_t twtr : 4; /* Write to Read Time */ - uint32_t : 3; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING2. */ -typedef volatile struct ALT_SDR_CTL_DRAMTIMING2_s ALT_SDR_CTL_DRAMTIMING2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMTIMING2 register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMTIMING2_OFST 0x8 - -/* - * Register : DRAM Timings 3 Register - dramtiming3 - * - * This register implements JEDEC standardized timing parameters. It should be - * programmed in clock cycles, for the value specified by the memory vendor. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:-------------------------------- - * [3:0] | RW | Unknown | Read to Precharge Time - * [8:4] | RW | Unknown | Activate to Precharge Time - * [14:9] | RW | Unknown | Row Cycle Time - * [18:15] | RW | Unknown | Mode Register Programming Delay - * [22:19] | RW | Unknown | CAS to CAS Delay - * [31:23] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Read to Precharge Time - trtp - * - * The read to precharge timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB 3 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK 0x0000000f -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRTP field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRTP register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value) (((value) << 0) & 0x0000000f) - -/* - * Field : Activate to Precharge Time - tras - * - * The activate to precharge timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB 8 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH 5 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK 0x000001f0 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK 0xfffffe0f -/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRAS field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value) (((value) & 0x000001f0) >> 4) -/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRAS register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value) (((value) << 4) & 0x000001f0) - -/* - * Field : Row Cycle Time - trc - * - * The activate to activate timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB 14 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH 6 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK 0x00007e00 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK 0xffff81ff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRC register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRC field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value) (((value) & 0x00007e00) >> 9) -/* Produces a ALT_SDR_CTL_DRAMTIMING3_TRC register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value) (((value) << 9) & 0x00007e00) - -/* - * Field : Mode Register Programming Delay - tmrd - * - * Mode register timing parameter. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB 18 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK 0x00078000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK 0xfff87fff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TMRD field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value) (((value) & 0x00078000) >> 15) -/* Produces a ALT_SDR_CTL_DRAMTIMING3_TMRD register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value) (((value) << 15) & 0x00078000) - -/* - * Field : CAS to CAS Delay - tccd - * - * The CAS to CAS delay time. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB 19 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB 22 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */ -#define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK 0x00780000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */ -#define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK 0xff87ffff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING3_TCCD field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value) (((value) & 0x00780000) >> 19) -/* Produces a ALT_SDR_CTL_DRAMTIMING3_TCCD register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value) (((value) << 19) & 0x00780000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMTIMING3. - */ -struct ALT_SDR_CTL_DRAMTIMING3_s -{ - uint32_t trtp : 4; /* Read to Precharge Time */ - uint32_t tras : 5; /* Activate to Precharge Time */ - uint32_t trc : 6; /* Row Cycle Time */ - uint32_t tmrd : 4; /* Mode Register Programming Delay */ - uint32_t tccd : 4; /* CAS to CAS Delay */ - uint32_t : 9; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING3. */ -typedef volatile struct ALT_SDR_CTL_DRAMTIMING3_s ALT_SDR_CTL_DRAMTIMING3_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMTIMING3 register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMTIMING3_OFST 0xc - -/* - * Register : DRAM Timings 4 Register - dramtiming4 - * - * This register implements JEDEC standardized timing parameters. It should be - * programmed in clock cycles, for the value specified by the memory vendor. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:------------------------------- - * [9:0] | RW | Unknown | Self-refresh Exit - * [19:10] | RW | Unknown | Power Down Exit - * [23:20] | RW | Unknown | Minimum Low Power State Cycles - * [31:24] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Self-refresh Exit - selfrfshexit - * - * The self refresh exit cycles, tXS. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ -#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ -#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB 9 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */ -#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH 10 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */ -#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK 0x000003ff -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */ -#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK 0xfffffc00 -/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value) (((value) & 0x000003ff) >> 0) -/* Produces a ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value) (((value) << 0) & 0x000003ff) - -/* - * Field : Power Down Exit - pwrdownexit - * - * The power down exit cycles, tXPDLL. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ -#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ -#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB 19 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */ -#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH 10 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */ -#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK 0x000ffc00 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */ -#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK 0xfff003ff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value) (((value) & 0x000ffc00) >> 10) -/* Produces a ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value) (((value) << 10) & 0x000ffc00) - -/* - * Field : Minimum Low Power State Cycles - minpwrsavecycles - * - * The minimum number of cycles to stay in a low power state. This applies to both - * power down and self-refresh and should be set to the greater of tPD and tCKESR. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ -#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ -#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB 23 -/* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */ -#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */ -#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK 0x00f00000 -/* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */ -#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK 0xff0fffff -/* The reset value of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES field value from a register. */ -#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value) (((value) & 0x00f00000) >> 20) -/* Produces a ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value) (((value) << 20) & 0x00f00000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMTIMING4. - */ -struct ALT_SDR_CTL_DRAMTIMING4_s -{ - uint32_t selfrfshexit : 10; /* Self-refresh Exit */ - uint32_t pwrdownexit : 10; /* Power Down Exit */ - uint32_t minpwrsavecycles : 4; /* Minimum Low Power State Cycles */ - uint32_t : 8; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING4. */ -typedef volatile struct ALT_SDR_CTL_DRAMTIMING4_s ALT_SDR_CTL_DRAMTIMING4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMTIMING4 register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMTIMING4_OFST 0x10 - -/* - * Register : Lower Power Timing Register - lowpwrtiming - * - * This register controls the behavior of the low power logic in the controller. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------- - * [15:0] | RW | Unknown | Auto-power Down Cycles - * [19:16] | RW | Unknown | Clock Disable Delay Cycles - * [31:20] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Auto-power Down Cycles - autopdcycles - * - * The number of idle clock cycles after which the controller should place the - * memory into power-down mode. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ -#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ -#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB 15 -/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */ -#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH 16 -/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */ -#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */ -#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK 0xffff0000 -/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field is UNKNOWN. */ -#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET 0x0 -/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES field value from a register. */ -#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value suitable for setting the register. */ -#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value) (((value) << 0) & 0x0000ffff) - -/* - * Field : Clock Disable Delay Cycles - clkdisablecycles - * - * Set to a the number of clocks after the execution of an self-refresh to stop the - * clock. This register is generally set based on PHY design latency and should - * generally not be changed. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ -#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ -#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB 19 -/* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */ -#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */ -#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK 0x000f0000 -/* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */ -#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK 0xfff0ffff -/* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field is UNKNOWN. */ -#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET 0x0 -/* Extracts the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES field value from a register. */ -#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value) (((value) & 0x000f0000) >> 16) -/* Produces a ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value suitable for setting the register. */ -#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value) (((value) << 16) & 0x000f0000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_LOWPWRTIMING. - */ -struct ALT_SDR_CTL_LOWPWRTIMING_s -{ - uint32_t autopdcycles : 16; /* Auto-power Down Cycles */ - uint32_t clkdisablecycles : 4; /* Clock Disable Delay Cycles */ - uint32_t : 12; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_LOWPWRTIMING. */ -typedef volatile struct ALT_SDR_CTL_LOWPWRTIMING_s ALT_SDR_CTL_LOWPWRTIMING_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_LOWPWRTIMING register from the beginning of the component. */ -#define ALT_SDR_CTL_LOWPWRTIMING_OFST 0x14 - -/* - * Register : ODT Control Register - dramodt - * - * This register controls which ODT pin is asserted during reads or writes. Bits - * [1:0] control which ODT pin is asserted during to accesses to chip select 0, - * bits [3:2] which ODT pin is asserted during accesses to chip select 1. For - * example, a value of "1001" will cause ODT[0] to be asserted for - * accesses to CS[0], and ODT[1] to be asserted for access to CS[1] pin. Set this - * to "0001" if there is only one chip select available. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:------------------ - * [3:0] | RW | Unknown | Write ODT Control - * [7:4] | RW | Unknown | Read ODT Control - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Write ODT Control - cfg_write_odt_chip - * - * This register controls which ODT pin is asserted during writes. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ -#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ -#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3 -/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */ -#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */ -#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f -/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */ -#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP field value from a register. */ -#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f) - -/* - * Field : Read ODT Control - cfg_read_odt_chip - * - * This register controls which ODT pin is asserted during reads. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ -#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ -#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7 -/* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */ -#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */ -#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0 -/* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */ -#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f -/* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP field value from a register. */ -#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4) -/* Produces a ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMODT. - */ -struct ALT_SDR_CTL_DRAMODT_s -{ - uint32_t cfg_write_odt_chip : 4; /* Write ODT Control */ - uint32_t cfg_read_odt_chip : 4; /* Read ODT Control */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMODT. */ -typedef volatile struct ALT_SDR_CTL_DRAMODT_s ALT_SDR_CTL_DRAMODT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMODT register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMODT_OFST 0x18 - -/* - * Register : DRAM Address Widths Register - dramaddrw - * - * This register configures the width of the various address fields of the DRAM. - * The values specified in this register must match the memory devices being used. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:------------------------- - * [4:0] | RW | Unknown | DRAM Column Address Bits - * [9:5] | RW | Unknown | DRAM Row Address Bits - * [12:10] | RW | Unknown | DRAM Bank Address Bits - * [15:13] | RW | Unknown | DRAM Chip Address Bits - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : DRAM Column Address Bits - colbits - * - * The number of column address bits for the memory devices in your memory - * interface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB 4 -/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH 5 -/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */ -#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK 0x0000001f -/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */ -#define ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK 0xffffffe0 -/* The reset value of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMADDRW_COLBITS field value from a register. */ -#define ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value) (((value) & 0x0000001f) >> 0) -/* Produces a ALT_SDR_CTL_DRAMADDRW_COLBITS register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value) (((value) << 0) & 0x0000001f) - -/* - * Field : DRAM Row Address Bits - rowbits - * - * The number of row address bits for the memory devices in your memory interface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB 9 -/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH 5 -/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */ -#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK 0x000003e0 -/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */ -#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK 0xfffffc1f -/* The reset value of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMADDRW_ROWBITS field value from a register. */ -#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value) (((value) & 0x000003e0) >> 5) -/* Produces a ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value) (((value) << 5) & 0x000003e0) - -/* - * Field : DRAM Bank Address Bits - bankbits - * - * The number of bank address bits for the memory devices in your memory interface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB 12 -/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH 3 -/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */ -#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK 0x00001c00 -/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */ -#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK 0xffffe3ff -/* The reset value of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMADDRW_BANKBITS field value from a register. */ -#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value) (((value) & 0x00001c00) >> 10) -/* Produces a ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value) (((value) << 10) & 0x00001c00) - -/* - * Field : DRAM Chip Address Bits - csbits - * - * The number of chip select address bits for the memory devices in your memory - * interface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB 15 -/* The width in bits of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */ -#define ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH 3 -/* The mask used to set the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */ -#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK 0x0000e000 -/* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */ -#define ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK 0xffff1fff -/* The reset value of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMADDRW_CSBITS field value from a register. */ -#define ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value) (((value) & 0x0000e000) >> 13) -/* Produces a ALT_SDR_CTL_DRAMADDRW_CSBITS register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value) (((value) << 13) & 0x0000e000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMADDRW. - */ -struct ALT_SDR_CTL_DRAMADDRW_s -{ - uint32_t colbits : 5; /* DRAM Column Address Bits */ - uint32_t rowbits : 5; /* DRAM Row Address Bits */ - uint32_t bankbits : 3; /* DRAM Bank Address Bits */ - uint32_t csbits : 3; /* DRAM Chip Address Bits */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMADDRW. */ -typedef volatile struct ALT_SDR_CTL_DRAMADDRW_s ALT_SDR_CTL_DRAMADDRW_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMADDRW register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMADDRW_OFST 0x2c - -/* - * Register : DRAM Interface Data Width Register - dramifwidth - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:-------------------------- - * [7:0] | RW | Unknown | DRAM Interface Data Width - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : DRAM Interface Data Width - ifwidth - * - * This register controls the interface width of the SDRAM interface, including any - * bits used for ECC. For example, for a 32-bit interface with ECC, program this - * register with 0x28. You must also program the ctrlwidth register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB 7 -/* The width in bits of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH 8 -/* The mask used to set the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK 0x000000ff -/* The mask used to clear the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK 0xffffff00 -/* The reset value of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH field value from a register. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMIFWIDTH. - */ -struct ALT_SDR_CTL_DRAMIFWIDTH_s -{ - uint32_t ifwidth : 8; /* DRAM Interface Data Width */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMIFWIDTH. */ -typedef volatile struct ALT_SDR_CTL_DRAMIFWIDTH_s ALT_SDR_CTL_DRAMIFWIDTH_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMIFWIDTH register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_OFST 0x30 - -/* - * Register : DRAM Devices Data Width Register - dramdevwidth - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:------------------------ - * [3:0] | RW | Unknown | DRAM Devices Data Width - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : DRAM Devices Data Width - devwidth - * - * This register specifies the width of the physical DRAM chips, for example 8 or - * 16. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB 3 -/* The width in bits of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH 4 -/* The mask used to set the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK 0x0000000f -/* The mask used to clear the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH field value from a register. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value) (((value) << 0) & 0x0000000f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. - */ -struct ALT_SDR_CTL_DRAMDEVWIDTH_s -{ - uint32_t devwidth : 4; /* DRAM Devices Data Width */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. */ -typedef volatile struct ALT_SDR_CTL_DRAMDEVWIDTH_s ALT_SDR_CTL_DRAMDEVWIDTH_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMDEVWIDTH register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_OFST 0x34 - -/* - * Register : DRAM Status Register - dramsts - * - * This register provides the status of the calibration and ECC logic. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:---------------------------- - * [0] | RW | Unknown | PHY Calibration Successful - * [1] | RW | Unknown | PHY Calibration Failed - * [2] | RW | Unknown | Single Bit Error Seen - * [3] | RW | Unknown | Double Bit Error Seen - * [4] | RW | Unknown | ECC Auto-Correction Dropped - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : PHY Calibration Successful - calsuccess - * - * This bit will be set to 1 if the PHY was able to successfully calibrate. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ -#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ -#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB 0 -/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */ -#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */ -#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */ -#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMSTS_CALSUCCESS field value from a register. */ -#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : PHY Calibration Failed - calfail - * - * This bit will be set to 1 if the PHY was unable to calibrate. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ -#define ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ -#define ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB 1 -/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */ -#define ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */ -#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */ -#define ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMSTS_CALFAIL field value from a register. */ -#define ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SDR_CTL_DRAMSTS_CALFAIL register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Single Bit Error Seen - sbeerr - * - * This bit will be set to 1 if there have been any ECC single bit errors detected. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ -#define ALT_SDR_CTL_DRAMSTS_SBEERR_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ -#define ALT_SDR_CTL_DRAMSTS_SBEERR_MSB 2 -/* The width in bits of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */ -#define ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */ -#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */ -#define ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SDR_CTL_DRAMSTS_SBEERR register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMSTS_SBEERR_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMSTS_SBEERR field value from a register. */ -#define ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SDR_CTL_DRAMSTS_SBEERR register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Double Bit Error Seen - dbeerr - * - * This bit will be set to 1 if there have been any ECC double bit errors detected. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ -#define ALT_SDR_CTL_DRAMSTS_DBEERR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ -#define ALT_SDR_CTL_DRAMSTS_DBEERR_MSB 3 -/* The width in bits of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */ -#define ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */ -#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */ -#define ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SDR_CTL_DRAMSTS_DBEERR register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMSTS_DBEERR_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMSTS_DBEERR field value from a register. */ -#define ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SDR_CTL_DRAMSTS_DBEERR register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : ECC Auto-Correction Dropped - corrdrop - * - * This bit will be set to 1 if there any auto-corrections have been dropped. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ -#define ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ -#define ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB 4 -/* The width in bits of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */ -#define ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */ -#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */ -#define ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK 0xffffffef -/* The reset value of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMSTS_CORRDROP field value from a register. */ -#define ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SDR_CTL_DRAMSTS_CORRDROP register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMSTS. - */ -struct ALT_SDR_CTL_DRAMSTS_s -{ - uint32_t calsuccess : 1; /* PHY Calibration Successful */ - uint32_t calfail : 1; /* PHY Calibration Failed */ - uint32_t sbeerr : 1; /* Single Bit Error Seen */ - uint32_t dbeerr : 1; /* Double Bit Error Seen */ - uint32_t corrdrop : 1; /* ECC Auto-Correction Dropped */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMSTS. */ -typedef volatile struct ALT_SDR_CTL_DRAMSTS_s ALT_SDR_CTL_DRAMSTS_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMSTS register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMSTS_OFST 0x38 - -/* - * Register : ECC Interrupt Register - dramintr - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:--------------------------------------- - * [0] | RW | Unknown | Interrupt Enable - * [1] | RW | Unknown | Mask Single Bit Error Interrupt - * [2] | RW | Unknown | Mask Double Bit Error Interrupt - * [3] | RW | Unknown | Mask Dropped Auto-correction Interrupt - * [4] | RW | Unknown | Clear Interrupt Signal - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Interrupt Enable - intren - * - * Enable the interrupt output. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ -#define ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ -#define ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0 -/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */ -#define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */ -#define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */ -#define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTREN register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMINTR_INTREN field value from a register. */ -#define ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SDR_CTL_DRAMINTR_INTREN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Mask Single Bit Error Interrupt - sbemask - * - * Mask the single bit error interrupt. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ -#define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ -#define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1 -/* The width in bits of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */ -#define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */ -#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */ -#define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMINTR_SBEMSK field value from a register. */ -#define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SDR_CTL_DRAMINTR_SBEMSK register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Mask Double Bit Error Interrupt - dbemask - * - * Mask the double bit error interrupt. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ -#define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ -#define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2 -/* The width in bits of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */ -#define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */ -#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */ -#define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMINTR_DBEMSK field value from a register. */ -#define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SDR_CTL_DRAMINTR_DBEMSK register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Mask Dropped Auto-correction Interrupt - corrdropmask - * - * Set this bit to a one to mask interrupts for an ECC correction write back - * needing to be dropped. This indicates a burst of memory errors in a short - * period of time. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ -#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ -#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3 -/* The width in bits of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */ -#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */ -#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */ -#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK field value from a register. */ -#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Clear Interrupt Signal - intrclr - * - * Writing to this self-clearing bit clears the interrupt signal. Writing to this - * bit also clears the error count and error address registers. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ -#define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ -#define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4 -/* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */ -#define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */ -#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */ -#define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef -/* The reset value of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field is UNKNOWN. */ -#define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DRAMINTR_INTRCLR field value from a register. */ -#define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SDR_CTL_DRAMINTR_INTRCLR register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DRAMINTR. - */ -struct ALT_SDR_CTL_DRAMINTR_s -{ - uint32_t intren : 1; /* Interrupt Enable */ - uint32_t sbemask : 1; /* Mask Single Bit Error Interrupt */ - uint32_t dbemask : 1; /* Mask Double Bit Error Interrupt */ - uint32_t corrdropmask : 1; /* Mask Dropped Auto-correction Interrupt */ - uint32_t intrclr : 1; /* Clear Interrupt Signal */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DRAMINTR. */ -typedef volatile struct ALT_SDR_CTL_DRAMINTR_s ALT_SDR_CTL_DRAMINTR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DRAMINTR register from the beginning of the component. */ -#define ALT_SDR_CTL_DRAMINTR_OFST 0x3c - -/* - * Register : ECC Single Bit Error Count Register - sbecount - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:----------------------- - * [7:0] | RW | Unknown | Single Bit Error Count - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Single Bit Error Count - count - * - * Reports the number of single bit errors that have occurred since the status - * register counters were last cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ -#define ALT_SDR_CTL_SBECOUNT_COUNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ -#define ALT_SDR_CTL_SBECOUNT_COUNT_MSB 7 -/* The width in bits of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */ -#define ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH 8 -/* The mask used to set the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */ -#define ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK 0x000000ff -/* The mask used to clear the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */ -#define ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK 0xffffff00 -/* The reset value of the ALT_SDR_CTL_SBECOUNT_COUNT register field is UNKNOWN. */ -#define ALT_SDR_CTL_SBECOUNT_COUNT_RESET 0x0 -/* Extracts the ALT_SDR_CTL_SBECOUNT_COUNT field value from a register. */ -#define ALT_SDR_CTL_SBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_SDR_CTL_SBECOUNT_COUNT register field value suitable for setting the register. */ -#define ALT_SDR_CTL_SBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_SBECOUNT. - */ -struct ALT_SDR_CTL_SBECOUNT_s -{ - uint32_t count : 8; /* Single Bit Error Count */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_SBECOUNT. */ -typedef volatile struct ALT_SDR_CTL_SBECOUNT_s ALT_SDR_CTL_SBECOUNT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_SBECOUNT register from the beginning of the component. */ -#define ALT_SDR_CTL_SBECOUNT_OFST 0x40 - -/* - * Register : ECC Double Bit Error Count Register - dbecount - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:----------------------- - * [7:0] | RW | Unknown | Double Bit Error Count - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Double Bit Error Count - count - * - * Reports the number of double bit errors that have occurred since the status - * register counters were last cleared. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ -#define ALT_SDR_CTL_DBECOUNT_COUNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ -#define ALT_SDR_CTL_DBECOUNT_COUNT_MSB 7 -/* The width in bits of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */ -#define ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH 8 -/* The mask used to set the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */ -#define ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK 0x000000ff -/* The mask used to clear the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */ -#define ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK 0xffffff00 -/* The reset value of the ALT_SDR_CTL_DBECOUNT_COUNT register field is UNKNOWN. */ -#define ALT_SDR_CTL_DBECOUNT_COUNT_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DBECOUNT_COUNT field value from a register. */ -#define ALT_SDR_CTL_DBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_SDR_CTL_DBECOUNT_COUNT register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DBECOUNT. - */ -struct ALT_SDR_CTL_DBECOUNT_s -{ - uint32_t count : 8; /* Double Bit Error Count */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DBECOUNT. */ -typedef volatile struct ALT_SDR_CTL_DBECOUNT_s ALT_SDR_CTL_DBECOUNT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DBECOUNT register from the beginning of the component. */ -#define ALT_SDR_CTL_DBECOUNT_OFST 0x44 - -/* - * Register : ECC Error Address Register - erraddr - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:------------------ - * [31:0] | RW | Unknown | ECC Error Address - * - */ -/* - * Field : ECC Error Address - addr - * - * The address of the most recent ECC error. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ -#define ALT_SDR_CTL_ERRADDR_ADDR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ -#define ALT_SDR_CTL_ERRADDR_ADDR_MSB 31 -/* The width in bits of the ALT_SDR_CTL_ERRADDR_ADDR register field. */ -#define ALT_SDR_CTL_ERRADDR_ADDR_WIDTH 32 -/* The mask used to set the ALT_SDR_CTL_ERRADDR_ADDR register field value. */ -#define ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SDR_CTL_ERRADDR_ADDR register field value. */ -#define ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK 0x00000000 -/* The reset value of the ALT_SDR_CTL_ERRADDR_ADDR register field is UNKNOWN. */ -#define ALT_SDR_CTL_ERRADDR_ADDR_RESET 0x0 -/* Extracts the ALT_SDR_CTL_ERRADDR_ADDR field value from a register. */ -#define ALT_SDR_CTL_ERRADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SDR_CTL_ERRADDR_ADDR register field value suitable for setting the register. */ -#define ALT_SDR_CTL_ERRADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_ERRADDR. - */ -struct ALT_SDR_CTL_ERRADDR_s -{ - uint32_t addr : 32; /* ECC Error Address */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_ERRADDR. */ -typedef volatile struct ALT_SDR_CTL_ERRADDR_s ALT_SDR_CTL_ERRADDR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_ERRADDR register from the beginning of the component. */ -#define ALT_SDR_CTL_ERRADDR_OFST 0x48 - -/* - * Register : ECC Auto-correction Dropped Count Register - dropcount - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:------------------------------ - * [7:0] | RW | Unknown | Dropped Auto-correction Count - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Dropped Auto-correction Count - corrdropcount - * - * This gives the count of the number of ECC write back transactions dropped due to - * the internal FIFO overflowing. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ -#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ -#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB 7 -/* The width in bits of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */ -#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH 8 -/* The mask used to set the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */ -#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK 0x000000ff -/* The mask used to clear the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */ -#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK 0xffffff00 -/* The reset value of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field is UNKNOWN. */ -#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT field value from a register. */ -#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DROPCOUNT. - */ -struct ALT_SDR_CTL_DROPCOUNT_s -{ - uint32_t corrdropcount : 8; /* Dropped Auto-correction Count */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DROPCOUNT. */ -typedef volatile struct ALT_SDR_CTL_DROPCOUNT_s ALT_SDR_CTL_DROPCOUNT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DROPCOUNT register from the beginning of the component. */ -#define ALT_SDR_CTL_DROPCOUNT_OFST 0x4c - -/* - * Register : ECC Auto-correction Dropped Address Register - dropaddr - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:-------------------------------- - * [31:0] | RW | Unknown | Dropped Auto-correction Address - * - */ -/* - * Field : Dropped Auto-correction Address - corrdropaddr - * - * This register gives the last address which was dropped. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ -#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ -#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB 31 -/* The width in bits of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */ -#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH 32 -/* The mask used to set the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */ -#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */ -#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK 0x00000000 -/* The reset value of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field is UNKNOWN. */ -#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET 0x0 -/* Extracts the ALT_SDR_CTL_DROPADDR_CORRDROPADDR field value from a register. */ -#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value suitable for setting the register. */ -#define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_DROPADDR. - */ -struct ALT_SDR_CTL_DROPADDR_s -{ - uint32_t corrdropaddr : 32; /* Dropped Auto-correction Address */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_DROPADDR. */ -typedef volatile struct ALT_SDR_CTL_DROPADDR_s ALT_SDR_CTL_DROPADDR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_DROPADDR register from the beginning of the component. */ -#define ALT_SDR_CTL_DROPADDR_OFST 0x50 - -/* - * Register : Low Power Control Register - lowpwreq - * - * This register instructs the controller to put the DRAM into a power down state. - * Note that some commands are only valid for certain memory types. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:--------------------------------- - * [0] | RW | Unknown | Deep Power Down Request - * [2:1] | RW | Unknown | Deep Power Down Chip Select Mask - * [3] | RW | Unknown | Self-refresh Request - * [5:4] | RW | Unknown | Self-refresh Chip Select Mask - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Deep Power Down Request - deeppwrdnreq - * - * Write a one to this bit to request a deep power down. This bit should only be - * written with LPDDR2 DRAMs, DDR3 DRAMs do not support deep power down. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0 -/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field is UNKNOWN. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0 -/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ field value from a register. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value suitable for setting the register. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Deep Power Down Chip Select Mask - deeppwrdnmask - * - * Write ones to this register to select which DRAM chip selects will be powered - * down. Typical usage is to set both of these bits when deeppwrdnreq is set but - * the controller does support putting a single chip into deep power down and - * keeping the other chip running. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2 -/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2 -/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006 -/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9 -/* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field is UNKNOWN. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0 -/* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK field value from a register. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1) -/* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value suitable for setting the register. */ -#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006) - -/* - * Field : Self-refresh Request - selfrshreq - * - * Write a one to this bit to request the RAM be put into a self refresh state. - * This bit is treated as a static value so the RAM will remain in self-refresh as - * long as this register bit is set to a one. This power down mode can be selected - * for all DRAMs supported by the controller. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3 -/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field is UNKNOWN. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0 -/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ field value from a register. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value suitable for setting the register. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Self-refresh Chip Select Mask - selfrfshmask - * - * Write a one to each bit of this field to have a self refresh request apply to - * both chips. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5 -/* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2 -/* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030 -/* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf -/* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field is UNKNOWN. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0 -/* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK field value from a register. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4) -/* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value suitable for setting the register. */ -#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_LOWPWREQ. - */ -struct ALT_SDR_CTL_LOWPWREQ_s -{ - uint32_t deeppwrdnreq : 1; /* Deep Power Down Request */ - uint32_t deeppwrdnmask : 2; /* Deep Power Down Chip Select Mask */ - uint32_t selfrshreq : 1; /* Self-refresh Request */ - uint32_t selfrfshmask : 2; /* Self-refresh Chip Select Mask */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_LOWPWREQ. */ -typedef volatile struct ALT_SDR_CTL_LOWPWREQ_s ALT_SDR_CTL_LOWPWREQ_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_LOWPWREQ register from the beginning of the component. */ -#define ALT_SDR_CTL_LOWPWREQ_OFST 0x54 - -/* - * Register : Low Power Acknowledge Register - lowpwrack - * - * This register gives the status of the power down commands requested by the Low - * Power Control register. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:---------------------------- - * [0] | RW | Unknown | Deep Power Down Acknowledge - * [1] | RW | Unknown | Self-refresh Acknowledge - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Deep Power Down Acknowledge - deeppwrdnack - * - * This bit is set to a one after a deep power down has been executed - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ -#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ -#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0 -/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */ -#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */ -#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */ -#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field is UNKNOWN. */ -#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0 -/* Extracts the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK field value from a register. */ -#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value suitable for setting the register. */ -#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Self-refresh Acknowledge - selfrfshack - * - * This bit is a one to indicate that the controller is in a self-refresh state. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ -#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ -#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1 -/* The width in bits of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */ -#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */ -#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */ -#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field is UNKNOWN. */ -#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0 -/* Extracts the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK field value from a register. */ -#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value suitable for setting the register. */ -#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_LOWPWRACK. - */ -struct ALT_SDR_CTL_LOWPWRACK_s -{ - uint32_t deeppwrdnack : 1; /* Deep Power Down Acknowledge */ - uint32_t selfrfshack : 1; /* Self-refresh Acknowledge */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_LOWPWRACK. */ -typedef volatile struct ALT_SDR_CTL_LOWPWRACK_s ALT_SDR_CTL_LOWPWRACK_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_LOWPWRACK register from the beginning of the component. */ -#define ALT_SDR_CTL_LOWPWRACK_OFST 0x58 - -/* - * Register : Static Configuration Register - staticcfg - * - * This register controls configuration values which cannot be updated while - * transactions are flowing. - * - * You should write once to this register with the membl and eccen fields set to - * your desired configuration, and then write to the register again with membl and - * eccen and the applycfg bit set. The applycfg bit is write only. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:---------------------------- - * [1:0] | RW | Unknown | Memory Burst Length - * [2] | RW | Unknown | Use ECC Bits As Data - * [3] | RW | Unknown | Apply Configuration Changes - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Memory Burst Length - membl - * - * This field specifies the DRAM burst length. Write the following values to set - * the a burst length appropriate for the specific DRAM being used. "00" - * for burst length 2, "01" for burst length 4, "10" for burst - * length 8. If you set this, you must also set the membl field in the ctrlcfg - * register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ -#define ALT_SDR_CTL_STATICCFG_MEMBL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ -#define ALT_SDR_CTL_STATICCFG_MEMBL_MSB 1 -/* The width in bits of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */ -#define ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH 2 -/* The mask used to set the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */ -#define ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */ -#define ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SDR_CTL_STATICCFG_MEMBL register field is UNKNOWN. */ -#define ALT_SDR_CTL_STATICCFG_MEMBL_RESET 0x0 -/* Extracts the ALT_SDR_CTL_STATICCFG_MEMBL field value from a register. */ -#define ALT_SDR_CTL_STATICCFG_MEMBL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SDR_CTL_STATICCFG_MEMBL register field value suitable for setting the register. */ -#define ALT_SDR_CTL_STATICCFG_MEMBL_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : Use ECC Bits As Data - useeccasdata - * - * This field allows the FPGA ports to directly access the extra data bits that are - * normally used to hold the ECC code. The interface width must be set to 24 or 40 - * in the dramifwidth register. If you set this, you must clear the eccen field in - * the ctrlcfg register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ -#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ -#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB 2 -/* The width in bits of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */ -#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */ -#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */ -#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field is UNKNOWN. */ -#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET 0x0 -/* Extracts the ALT_SDR_CTL_STATICCFG_USEECCASDATA field value from a register. */ -#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value suitable for setting the register. */ -#define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Apply Configuration Changes - applycfg - * - * Write with this bit set to apply all the settings loaded in SDR registers to the - * memory interface. This bit is write-only and always returns 0 if read. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ -#define ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ -#define ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB 3 -/* The width in bits of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */ -#define ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */ -#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */ -#define ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field is UNKNOWN. */ -#define ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET 0x0 -/* Extracts the ALT_SDR_CTL_STATICCFG_APPLYCFG field value from a register. */ -#define ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SDR_CTL_STATICCFG_APPLYCFG register field value suitable for setting the register. */ -#define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value) (((value) << 3) & 0x00000008) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_STATICCFG. - */ -struct ALT_SDR_CTL_STATICCFG_s -{ - uint32_t membl : 2; /* Memory Burst Length */ - uint32_t useeccasdata : 1; /* Use ECC Bits As Data */ - uint32_t applycfg : 1; /* Apply Configuration Changes */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_STATICCFG. */ -typedef volatile struct ALT_SDR_CTL_STATICCFG_s ALT_SDR_CTL_STATICCFG_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_STATICCFG register from the beginning of the component. */ -#define ALT_SDR_CTL_STATICCFG_OFST 0x5c - -/* - * Register : Memory Controller Width Register - ctrlwidth - * - * This register controls the width of the physical DRAM interface. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:--------------------------- - * [1:0] | RW | Unknown | Controller Interface Width - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Controller Interface Width - ctrlwidth - * - * Specifies controller DRAM interface width, with the following encoding. - * "00" for 8-bit, "01" for 16-bit (no ECC) or 24-bit (ECC - * enabled), "10" for 32-bit (no ECC) or 40-bit (ECC enabled). You must - * also program the dramifwidth register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ -#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ -#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB 1 -/* The width in bits of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */ -#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH 2 -/* The mask used to set the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */ -#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */ -#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field is UNKNOWN. */ -#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET 0x0 -/* Extracts the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH field value from a register. */ -#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value suitable for setting the register. */ -#define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_CTLWIDTH. - */ -struct ALT_SDR_CTL_CTLWIDTH_s -{ - uint32_t ctrlwidth : 2; /* Controller Interface Width */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_CTLWIDTH. */ -typedef volatile struct ALT_SDR_CTL_CTLWIDTH_s ALT_SDR_CTL_CTLWIDTH_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_CTLWIDTH register from the beginning of the component. */ -#define ALT_SDR_CTL_CTLWIDTH_OFST 0x60 - -/* - * Register : Port Configuration Register - portcfg - * - * This register should be set to a zero in any bit which corresponds to a port - * which does mostly sequential memory accesses. For ports with highly random - * accesses, the bit should be set to a one. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:---------------------- - * [9:0] | ??? | Unknown | *UNDEFINED* - * [19:10] | RW | Unknown | Auto-precharge Enable - * [31:20] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Auto-precharge Enable - autopchen - * - * One bit per control port. Set bit N to a 1 to have the controller request an - * automatic precharge following bus command completion (close the row - * automatically). Set to a zero to request that the controller attempt to keep a - * row open. For random dominated operations this register should be set to a 1 - * for all active ports. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ -#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ -#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB 19 -/* The width in bits of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */ -#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH 10 -/* The mask used to set the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */ -#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK 0x000ffc00 -/* The mask used to clear the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */ -#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK 0xfff003ff -/* The reset value of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field is UNKNOWN. */ -#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PORTCFG_AUTOPCHEN field value from a register. */ -#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value) (((value) & 0x000ffc00) >> 10) -/* Produces a ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value) (((value) << 10) & 0x000ffc00) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_PORTCFG. - */ -struct ALT_SDR_CTL_PORTCFG_s -{ - uint32_t : 10; /* *UNDEFINED* */ - uint32_t autopchen : 10; /* Auto-precharge Enable */ - uint32_t : 12; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_PORTCFG. */ -typedef volatile struct ALT_SDR_CTL_PORTCFG_s ALT_SDR_CTL_PORTCFG_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_PORTCFG register from the beginning of the component. */ -#define ALT_SDR_CTL_PORTCFG_OFST 0x7c - -/* - * Register : FPGA Ports Reset Control Register - fpgaportrst - * - * This register implements functionality to allow the CPU to control when the MPFE - * will enable the ports to the FPGA fabric. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:------------------- - * [13:0] | RW | Unknown | Port Reset Control - * [31:14] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Port Reset Control - portrstn - * - * This register should be written to with a 1 to enable the selected FPGA port to - * exit reset. Writing a bit to a zero will stretch the port reset until the - * register is written. Read data ports are connected to bits 3:0, with read data - * port 0 at bit 0 to read data port 3 at bit 3. Write data ports 0 to 3 are mapped - * to 4 to 7, with write data port 0 connected to bit 4 to write data port 3 at bit - * 7. Command ports are connected to bits 8 to 13, with command port 0 at bit 8 to - * command port 5 at bit 13. Expected usage would be to set all the bits at the - * same time but setting some bits to a zero and others to a one is supported. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ -#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ -#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB 13 -/* The width in bits of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */ -#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH 14 -/* The mask used to set the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */ -#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK 0x00003fff -/* The mask used to clear the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */ -#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK 0xffffc000 -/* The reset value of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field is UNKNOWN. */ -#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN field value from a register. */ -#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value) (((value) & 0x00003fff) >> 0) -/* Produces a ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value) (((value) << 0) & 0x00003fff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_FPGAPORTRST. - */ -struct ALT_SDR_CTL_FPGAPORTRST_s -{ - uint32_t portrstn : 14; /* Port Reset Control */ - uint32_t : 18; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_FPGAPORTRST. */ -typedef volatile struct ALT_SDR_CTL_FPGAPORTRST_s ALT_SDR_CTL_FPGAPORTRST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_FPGAPORTRST register from the beginning of the component. */ -#define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80 - -/* - * Register : Memory Protection Port Default Register - protportdefault - * - * This register controls the default protection assignment for a port. Ports - * which have explicit rules which define regions which are illegal to access - * should set the bits to pass by default. Ports which have explicit rules which - * define legal areas should set the bit to force all transactions to fail. - * Leaving this register to all zeros should be used for systems which do not - * desire any protection from the memory controller. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:-------------------- - * [9:0] | RW | Unknown | Port Default Action - * [31:10] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Port Default Action - portdefault - * - * Determines the default action for a transactions from a port. Set a bit to a - * zero to indicate that all accesses from the port should pass by default, set a - * bit to a one if the default protection is to fail the access. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB 9 -/* The width in bits of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH 10 -/* The mask used to set the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK 0x000003ff -/* The mask used to clear the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK 0xfffffc00 -/* The reset value of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT field value from a register. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value) (((value) & 0x000003ff) >> 0) -/* Produces a ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value) (((value) << 0) & 0x000003ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. - */ -struct ALT_SDR_CTL_PROTPORTDEFAULT_s -{ - uint32_t portdefault : 10; /* Port Default Action */ - uint32_t : 22; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. */ -typedef volatile struct ALT_SDR_CTL_PROTPORTDEFAULT_s ALT_SDR_CTL_PROTPORTDEFAULT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_PROTPORTDEFAULT register from the beginning of the component. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_OFST 0x8c - -/* - * Register : Memory Protection Address Register - protruleaddr - * - * This register is used to control the memory protection for port 0 transactions. - * Address ranges can either be used to allow access to memory regions or disallow - * access to memory regions. If trustzone is being used, access can be enabled for - * protected transactions or disabled for unprotected transactions. The default - * state of this register is to allow all access. Address values used for - * protection are only physical addresses. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:------------- - * [11:0] | RW | Unknown | Low Address - * [23:12] | RW | Unknown | High Address - * [31:24] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Low Address - lowaddr - * - * Lower 12 bits of the address for a check. Address is compared to be less than - * or equal to the address of a transaction. Note that since AXI transactions - * cannot cross a 4K byte boundary, the transaction start and transaction end - * address must also fall within the same 1MByte block pointed to by this address - * pointer. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ -#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ -#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB 11 -/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */ -#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH 12 -/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */ -#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK 0x00000fff -/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */ -#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK 0xfffff000 -/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULEADDR_LOWADDR field value from a register. */ -#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value) (((value) & 0x00000fff) >> 0) -/* Produces a ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value) (((value) << 0) & 0x00000fff) - -/* - * Field : High Address - highaddr - * - * Upper 12 bits of the address for a check. Address is compared to be greater - * than or equal to the address of a transaction. Note that since AXI transactions - * cannot cross a 4K byte boundary, the transaction start and transaction end - * address must also fall within the same 1MByte block pointed to by this address - * pointer. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ -#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ -#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB 23 -/* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */ -#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH 12 -/* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */ -#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK 0x00fff000 -/* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */ -#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK 0xff000fff -/* The reset value of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR field value from a register. */ -#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value) (((value) & 0x00fff000) >> 12) -/* Produces a ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value) (((value) << 12) & 0x00fff000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_PROTRULEADDR. - */ -struct ALT_SDR_CTL_PROTRULEADDR_s -{ - uint32_t lowaddr : 12; /* Low Address */ - uint32_t highaddr : 12; /* High Address */ - uint32_t : 8; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_PROTRULEADDR. */ -typedef volatile struct ALT_SDR_CTL_PROTRULEADDR_s ALT_SDR_CTL_PROTRULEADDR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_PROTRULEADDR register from the beginning of the component. */ -#define ALT_SDR_CTL_PROTRULEADDR_OFST 0x90 - -/* - * Register : Memory Protection ID Register - protruleid - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:------------ - * [11:0] | RW | Unknown | Low ID - * [23:12] | RW | Unknown | High ID - * [31:24] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Low ID - lowid - * - * AxID for the protection rule. Incoming AxID needs to be greater than or equal - * to this value. For all AxIDs from a port, AxID high should be programmed to all - * ones. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ -#define ALT_SDR_CTL_PROTRULEID_LOWID_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ -#define ALT_SDR_CTL_PROTRULEID_LOWID_MSB 11 -/* The width in bits of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */ -#define ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH 12 -/* The mask used to set the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */ -#define ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK 0x00000fff -/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */ -#define ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK 0xfffff000 -/* The reset value of the ALT_SDR_CTL_PROTRULEID_LOWID register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULEID_LOWID_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULEID_LOWID field value from a register. */ -#define ALT_SDR_CTL_PROTRULEID_LOWID_GET(value) (((value) & 0x00000fff) >> 0) -/* Produces a ALT_SDR_CTL_PROTRULEID_LOWID register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULEID_LOWID_SET(value) (((value) << 0) & 0x00000fff) - -/* - * Field : High ID - highid - * - * AxID for the protection rule. Incoming AxID needs to be less than or equal to - * this value. For all AxIDs from a port, AxID high should be programmed to all - * ones. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ -#define ALT_SDR_CTL_PROTRULEID_HIGHID_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ -#define ALT_SDR_CTL_PROTRULEID_HIGHID_MSB 23 -/* The width in bits of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */ -#define ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH 12 -/* The mask used to set the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */ -#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK 0x00fff000 -/* The mask used to clear the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */ -#define ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK 0xff000fff -/* The reset value of the ALT_SDR_CTL_PROTRULEID_HIGHID register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULEID_HIGHID_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULEID_HIGHID field value from a register. */ -#define ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value) (((value) & 0x00fff000) >> 12) -/* Produces a ALT_SDR_CTL_PROTRULEID_HIGHID register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value) (((value) << 12) & 0x00fff000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_PROTRULEID. - */ -struct ALT_SDR_CTL_PROTRULEID_s -{ - uint32_t lowid : 12; /* Low ID */ - uint32_t highid : 12; /* High ID */ - uint32_t : 8; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_PROTRULEID. */ -typedef volatile struct ALT_SDR_CTL_PROTRULEID_s ALT_SDR_CTL_PROTRULEID_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_PROTRULEID register from the beginning of the component. */ -#define ALT_SDR_CTL_PROTRULEID_OFST 0x94 - -/* - * Register : Memory Protection Rule Data Register - protruledata - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:---------------------- - * [1:0] | RW | Unknown | Security Bit Behavior - * [2] | RW | Unknown | Valid Rule - * [12:3] | RW | Unknown | Port Mask - * [13] | RW | Unknown | Rule Results - * [31:14] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Security Bit Behavior - security - * - * A value of 2'b00 will make the rule apply to secure transactions. - * - * A value of 2'b01 will make the rule apply to non-secure transactions. - * - * A value of 2'b10 or 2'b11 will make the rule apply to secure and non-secure - * transactions. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB 1 -/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH 2 -/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */ -#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */ -#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULEDATA_SECURITY field value from a register. */ -#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : Valid Rule - validrule - * - * Set to bit to a one to make a rule valid, set to a zero to invalidate a rule. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB 2 -/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */ -#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */ -#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE field value from a register. */ -#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Port Mask - portmask - * - * Set bit x to a one to have this rule apply to port x, set bit x to a zero to - * have the rule not apply to a port. Note that port 0-port 5 are the FPGA - * fabric ports, port 6 is L3 read, port 7 is CPU read, port 8 is L3 write, port 9 - * is CPU write. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB 12 -/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH 10 -/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */ -#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK 0x00001ff8 -/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */ -#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK 0xffffe007 -/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULEDATA_PORTMSK field value from a register. */ -#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value) (((value) & 0x00001ff8) >> 3) -/* Produces a ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value) (((value) << 3) & 0x00001ff8) - -/* - * Field : Rule Results - ruleresult - * - * Set this bit to a one to force a protection failure, zero to allow the access - * the succeed - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB 13 -/* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */ -#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */ -#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK 0x00002000 -/* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */ -#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK 0xffffdfff -/* The reset value of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULEDATA_RULERESULT field value from a register. */ -#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value) (((value) << 13) & 0x00002000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_PROTRULEDATA. - */ -struct ALT_SDR_CTL_PROTRULEDATA_s -{ - uint32_t security : 2; /* Security Bit Behavior */ - uint32_t validrule : 1; /* Valid Rule */ - uint32_t portmask : 10; /* Port Mask */ - uint32_t ruleresult : 1; /* Rule Results */ - uint32_t : 18; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_PROTRULEDATA. */ -typedef volatile struct ALT_SDR_CTL_PROTRULEDATA_s ALT_SDR_CTL_PROTRULEDATA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_PROTRULEDATA register from the beginning of the component. */ -#define ALT_SDR_CTL_PROTRULEDATA_OFST 0x98 - -/* - * Register : Memory Protection Rule Read-Write Register - protrulerdwr - * - * This register is used to perform read and write operations to the internal - * protection table. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:------------ - * [4:0] | RW | Unknown | Rule Offset - * [5] | RW | Unknown | Rule Write - * [6] | RW | Unknown | Rule Read - * [31:7] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Rule Offset - ruleoffset - * - * This field defines which of the 20 rules in the protection table you want to - * read or write. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ -#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ -#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB 4 -/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */ -#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH 5 -/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */ -#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK 0x0000001f -/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */ -#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK 0xffffffe0 -/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET field value from a register. */ -#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value) (((value) & 0x0000001f) >> 0) -/* Produces a ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value) (((value) << 0) & 0x0000001f) - -/* - * Field : Rule Write - writerule - * - * Write to this bit to have the memory_prot_data register to the table at the - * offset specified by port_offset. Bit automatically clears after a single cycle - * and the write operation is complete. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ -#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ -#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB 5 -/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */ -#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */ -#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK 0x00000020 -/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */ -#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK 0xffffffdf -/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULERDWR_WRRULE field value from a register. */ -#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Rule Read - readrule - * - * Write to this bit to have the memory_prot_data register loaded with the value - * from the internal protection table at offset. Table value will be loaded before - * a rdy is returned so read data from the register will be correct for any follow- - * on reads to the memory_prot_data register. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ -#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ -#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB 6 -/* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */ -#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH 1 -/* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */ -#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */ -#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field is UNKNOWN. */ -#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET 0x0 -/* Extracts the ALT_SDR_CTL_PROTRULERDWR_RDRULE field value from a register. */ -#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value suitable for setting the register. */ -#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value) (((value) << 6) & 0x00000040) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_PROTRULERDWR. - */ -struct ALT_SDR_CTL_PROTRULERDWR_s -{ - uint32_t ruleoffset : 5; /* Rule Offset */ - uint32_t writerule : 1; /* Rule Write */ - uint32_t readrule : 1; /* Rule Read */ - uint32_t : 25; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_PROTRULERDWR. */ -typedef volatile struct ALT_SDR_CTL_PROTRULERDWR_s ALT_SDR_CTL_PROTRULERDWR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_PROTRULERDWR register from the beginning of the component. */ -#define ALT_SDR_CTL_PROTRULERDWR_OFST 0x9c - -/* - * Register : QOS Control Register - qoslowpri - * - * This register controls the mapping of AXI4 QOS received from the FPGA fabric to - * the internal priority used for traffic prioritization. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:----------------------- - * [19:0] | RW | Unknown | Low Priority QoS Value - * [31:20] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Low Priority QoS Value - lowpriorityval - * - * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for - * each port in this register controls the priority used for a port - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ -#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ -#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB 19 -/* The width in bits of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */ -#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH 20 -/* The mask used to set the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */ -#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK 0x000fffff -/* The mask used to clear the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */ -#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK 0xfff00000 -/* The reset value of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field is UNKNOWN. */ -#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET 0x0 -/* Extracts the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL field value from a register. */ -#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0) -/* Produces a ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value suitable for setting the register. */ -#define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_QOSLOWPRI. - */ -struct ALT_SDR_CTL_QOSLOWPRI_s -{ - uint32_t lowpriorityval : 20; /* Low Priority QoS Value */ - uint32_t : 12; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_QOSLOWPRI. */ -typedef volatile struct ALT_SDR_CTL_QOSLOWPRI_s ALT_SDR_CTL_QOSLOWPRI_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_QOSLOWPRI register from the beginning of the component. */ -#define ALT_SDR_CTL_QOSLOWPRI_OFST 0xa0 - -/* - * Register : qoshighpri Register - qoshighpri - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:------------------------ - * [19:0] | RW | Unknown | High Priority QoS Value - * [31:20] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : High Priority QoS Value - highpriorityval - * - * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for - * each port in this register controls the priority used for a port - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ -#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ -#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB 19 -/* The width in bits of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */ -#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH 20 -/* The mask used to set the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */ -#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK 0x000fffff -/* The mask used to clear the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */ -#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK 0xfff00000 -/* The reset value of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field is UNKNOWN. */ -#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET 0x0 -/* Extracts the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL field value from a register. */ -#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0) -/* Produces a ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value suitable for setting the register. */ -#define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_QOSHIGHPRI. - */ -struct ALT_SDR_CTL_QOSHIGHPRI_s -{ - uint32_t highpriorityval : 20; /* High Priority QoS Value */ - uint32_t : 12; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_QOSHIGHPRI. */ -typedef volatile struct ALT_SDR_CTL_QOSHIGHPRI_s ALT_SDR_CTL_QOSHIGHPRI_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_QOSHIGHPRI register from the beginning of the component. */ -#define ALT_SDR_CTL_QOSHIGHPRI_OFST 0xa4 - -/* - * Register : qospriorityen Register - qospriorityen - * - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:-------------------- - * [9:0] | RW | Unknown | Per-Port QoS Enable - * [31:10] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Per-Port QoS Enable - priorityen - * - * This 10 bit field is set to a one to enable QOS usage for a port. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB 9 -/* The width in bits of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH 10 -/* The mask used to set the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK 0x000003ff -/* The mask used to clear the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK 0xfffffc00 -/* The reset value of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field is UNKNOWN. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET 0x0 -/* Extracts the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN field value from a register. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value) (((value) & 0x000003ff) >> 0) -/* Produces a ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value suitable for setting the register. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value) (((value) << 0) & 0x000003ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_QOSPRIORITYEN. - */ -struct ALT_SDR_CTL_QOSPRIORITYEN_s -{ - uint32_t priorityen : 10; /* Per-Port QoS Enable */ - uint32_t : 22; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_QOSPRIORITYEN. */ -typedef volatile struct ALT_SDR_CTL_QOSPRIORITYEN_s ALT_SDR_CTL_QOSPRIORITYEN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_QOSPRIORITYEN register from the beginning of the component. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_OFST 0xa8 - -/* - * Register : Scheduler priority Register - mppriority - * - * This register is used to configure the DRAM burst operation scheduling. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------- - * [29:0] | RW | Unknown | Port User Priorities - * [31:30] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Port User Priorities - userpriority - * - * Set absolute user priority of the port. Each port is represented by a 3 bit - * value, 000=lowest priority, 111=highest priority. Port 0 is bits 2:0. Port - * number offset corresponds to the control port assignment. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ -#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ -#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB 29 -/* The width in bits of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */ -#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH 30 -/* The mask used to set the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */ -#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK 0x3fffffff -/* The mask used to clear the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */ -#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK 0xc0000000 -/* The reset value of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field is UNKNOWN. */ -#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET 0x0 -/* Extracts the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY field value from a register. */ -#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value) (((value) & 0x3fffffff) >> 0) -/* Produces a ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value suitable for setting the register. */ -#define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value) (((value) << 0) & 0x3fffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_MPPRIORITY. - */ -struct ALT_SDR_CTL_MPPRIORITY_s -{ - uint32_t userpriority : 30; /* Port User Priorities */ - uint32_t : 2; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_MPPRIORITY. */ -typedef volatile struct ALT_SDR_CTL_MPPRIORITY_s ALT_SDR_CTL_MPPRIORITY_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_MPPRIORITY register from the beginning of the component. */ -#define ALT_SDR_CTL_MPPRIORITY_OFST 0xac - -/* - * Register : Controller Command Pool Priority Remap Register - remappriority - * - * This register controls the priority for transactions in the controller command - * pool. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:--------------- - * [7:0] | RW | Unknown | Priority Remap - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Priority Remap - priorityremap - * - * Set bit N of this register to the value to a one to enable the controller - * command pool priority bit of a transaction from MPFE priority N - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ -#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ -#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB 7 -/* The width in bits of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */ -#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH 8 -/* The mask used to set the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */ -#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK 0x000000ff -/* The mask used to clear the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */ -#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK 0xffffff00 -/* The reset value of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field is UNKNOWN. */ -#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET 0x0 -/* Extracts the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP field value from a register. */ -#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value suitable for setting the register. */ -#define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_REMAPPRIORITY. - */ -struct ALT_SDR_CTL_REMAPPRIORITY_s -{ - uint32_t priorityremap : 8; /* Priority Remap */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_REMAPPRIORITY. */ -typedef volatile struct ALT_SDR_CTL_REMAPPRIORITY_s ALT_SDR_CTL_REMAPPRIORITY_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_REMAPPRIORITY register from the beginning of the component. */ -#define ALT_SDR_CTL_REMAPPRIORITY_OFST 0xe0 - -/* - * Register Group : Port Sum of Weight Register - ALT_SDR_CTL_MPWT - * Port Sum of Weight Register - * - * This register is used to configure the DRAM burst operation scheduling. - * - */ -/* - * Register : Port Sum of Weight Register[1/4] - mpweight_0_4 - * - * This register is used to configure the DRAM burst operation scheduling. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:-------------------------- - * [31:0] | RW | Unknown | Port Static Weights[31:0] - * - */ -/* - * Field : Port Static Weights[31:0] - staticweight_31_0 - * - * Set static weight of the port. Each port is programmed with a 5 bit value. - * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB 31 -/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH 32 -/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK 0x00000000 -/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field is UNKNOWN. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET 0x0 -/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 field value from a register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value suitable for setting the register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. - */ -struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s -{ - uint32_t staticweight_31_0 : 32; /* Port Static Weights[31:0] */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. */ -typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register from the beginning of the component. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST 0x0 -/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST)) - -/* - * Register : Port Sum of Weight Register[2/4] - mpweight_1_4 - * - * This register is used to configure the DRAM burst operation scheduling. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------- - * [17:0] | RW | Unknown | Port Static Weights[49:32] - * [31:18] | RW | Unknown | Port Sum of Weights[13:0] - * - */ -/* - * Field : Port Static Weights[49:32] - staticweight_49_32 - * - * Set static weight of the port. Each port is programmed with a 5 bit value. - * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45 - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB 17 -/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH 18 -/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK 0x0003ffff -/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK 0xfffc0000 -/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field is UNKNOWN. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET 0x0 -/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 field value from a register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value) (((value) & 0x0003ffff) >> 0) -/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value suitable for setting the register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value) (((value) << 0) & 0x0003ffff) - -/* - * Field : Port Sum of Weights[13:0] - sumofweights_13_0 - * - * Set the sum of static weights for particular user priority. This register is - * used as part of the deficit round robin implementation. It should be set to the - * sum of the weights for the ports - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB 18 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB 31 -/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH 14 -/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK 0xfffc0000 -/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK 0x0003ffff -/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field is UNKNOWN. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET 0x0 -/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 field value from a register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value) (((value) & 0xfffc0000) >> 18) -/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value suitable for setting the register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value) (((value) << 18) & 0xfffc0000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. - */ -struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s -{ - uint32_t staticweight_49_32 : 18; /* Port Static Weights[49:32] */ - uint32_t sumofweights_13_0 : 14; /* Port Sum of Weights[13:0] */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. */ -typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register from the beginning of the component. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST 0x4 -/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST)) - -/* - * Register : Port Sum of Weight Register[3/4] - mpweight_2_4 - * - * This register is used to configure the DRAM burst operation scheduling. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:--------------------------- - * [31:0] | RW | Unknown | Port Sum of Weights[45:14] - * - */ -/* - * Field : Port Sum of Weights[45:14] - sumofweights_45_14 - * - * Set the sum of static weights for particular user priority. This register is - * used as part of the deficit round robin implementation. It should be set to the - * sum of the weights for the ports - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB 31 -/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH 32 -/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK 0x00000000 -/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field is UNKNOWN. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET 0x0 -/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 field value from a register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value suitable for setting the register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. - */ -struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s -{ - uint32_t sumofweights_45_14 : 32; /* Port Sum of Weights[45:14] */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. */ -typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register from the beginning of the component. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST 0x8 -/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST)) - -/* - * Register : Port Sum of Weight Register[4/4] - mpweight_3_4 - * - * This register is used to configure the DRAM burst operation scheduling. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------------- - * [17:0] | RW | Unknown | Port Sum of Weights[63:46] - * [31:18] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Port Sum of Weights[63:46] - sumofweights_63_46 - * - * Set the sum of static weights for particular user priority. This register is - * used as part of the deficit round robin implementation. It should be set to the - * sum of the weights for the ports - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB 17 -/* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH 18 -/* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK 0x0003ffff -/* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK 0xfffc0000 -/* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field is UNKNOWN. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET 0x0 -/* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 field value from a register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value) (((value) & 0x0003ffff) >> 0) -/* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value suitable for setting the register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value) (((value) << 0) & 0x0003ffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. - */ -struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s -{ - uint32_t sumofweights_63_46 : 18; /* Port Sum of Weights[63:46] */ - uint32_t : 14; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. */ -typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register from the beginning of the component. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST 0xc -/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register. */ -#define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SDR_CTL_MPWT. - */ -struct ALT_SDR_CTL_MPWT_s -{ - volatile ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */ - volatile ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */ - volatile ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */ - volatile ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */ -}; - -/* The typedef declaration for register group ALT_SDR_CTL_MPWT. */ -typedef volatile struct ALT_SDR_CTL_MPWT_s ALT_SDR_CTL_MPWT_t; -/* The struct declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */ -struct ALT_SDR_CTL_MPWT_raw_s -{ - volatile uint32_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */ - volatile uint32_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */ - volatile uint32_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */ - volatile uint32_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */ -typedef volatile struct ALT_SDR_CTL_MPWT_raw_s ALT_SDR_CTL_MPWT_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SDR_CTL. - */ -struct ALT_SDR_CTL_s -{ - volatile ALT_SDR_CTL_CTLCFG_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */ - volatile ALT_SDR_CTL_DRAMTIMING1_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */ - volatile ALT_SDR_CTL_DRAMTIMING2_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */ - volatile ALT_SDR_CTL_DRAMTIMING3_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */ - volatile ALT_SDR_CTL_DRAMTIMING4_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */ - volatile ALT_SDR_CTL_LOWPWRTIMING_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */ - volatile ALT_SDR_CTL_DRAMODT_t dramodt; /* ALT_SDR_CTL_DRAMODT */ - volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */ - volatile ALT_SDR_CTL_DRAMADDRW_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */ - volatile ALT_SDR_CTL_DRAMIFWIDTH_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */ - volatile ALT_SDR_CTL_DRAMDEVWIDTH_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */ - volatile ALT_SDR_CTL_DRAMSTS_t dramsts; /* ALT_SDR_CTL_DRAMSTS */ - volatile ALT_SDR_CTL_DRAMINTR_t dramintr; /* ALT_SDR_CTL_DRAMINTR */ - volatile ALT_SDR_CTL_SBECOUNT_t sbecount; /* ALT_SDR_CTL_SBECOUNT */ - volatile ALT_SDR_CTL_DBECOUNT_t dbecount; /* ALT_SDR_CTL_DBECOUNT */ - volatile ALT_SDR_CTL_ERRADDR_t erraddr; /* ALT_SDR_CTL_ERRADDR */ - volatile ALT_SDR_CTL_DROPCOUNT_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */ - volatile ALT_SDR_CTL_DROPADDR_t dropaddr; /* ALT_SDR_CTL_DROPADDR */ - volatile ALT_SDR_CTL_LOWPWREQ_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */ - volatile ALT_SDR_CTL_LOWPWRACK_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */ - volatile ALT_SDR_CTL_STATICCFG_t staticcfg; /* ALT_SDR_CTL_STATICCFG */ - volatile ALT_SDR_CTL_CTLWIDTH_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */ - volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */ - volatile ALT_SDR_CTL_PORTCFG_t portcfg; /* ALT_SDR_CTL_PORTCFG */ - volatile ALT_SDR_CTL_FPGAPORTRST_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */ - volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */ - volatile ALT_SDR_CTL_PROTPORTDEFAULT_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */ - volatile ALT_SDR_CTL_PROTRULEADDR_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */ - volatile ALT_SDR_CTL_PROTRULEID_t protruleid; /* ALT_SDR_CTL_PROTRULEID */ - volatile ALT_SDR_CTL_PROTRULEDATA_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */ - volatile ALT_SDR_CTL_PROTRULERDWR_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */ - volatile ALT_SDR_CTL_QOSLOWPRI_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */ - volatile ALT_SDR_CTL_QOSHIGHPRI_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */ - volatile ALT_SDR_CTL_QOSPRIORITYEN_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */ - volatile ALT_SDR_CTL_MPPRIORITY_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */ - volatile ALT_SDR_CTL_MPWT_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */ - volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */ - volatile ALT_SDR_CTL_REMAPPRIORITY_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */ - volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_SDR_CTL. */ -typedef volatile struct ALT_SDR_CTL_s ALT_SDR_CTL_t; -/* The struct declaration for the raw register contents of register group ALT_SDR_CTL. */ -struct ALT_SDR_CTL_raw_s -{ - volatile uint32_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */ - volatile uint32_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */ - volatile uint32_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */ - volatile uint32_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */ - volatile uint32_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */ - volatile uint32_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */ - volatile uint32_t dramodt; /* ALT_SDR_CTL_DRAMODT */ - volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */ - volatile uint32_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */ - volatile uint32_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */ - volatile uint32_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */ - volatile uint32_t dramsts; /* ALT_SDR_CTL_DRAMSTS */ - volatile uint32_t dramintr; /* ALT_SDR_CTL_DRAMINTR */ - volatile uint32_t sbecount; /* ALT_SDR_CTL_SBECOUNT */ - volatile uint32_t dbecount; /* ALT_SDR_CTL_DBECOUNT */ - volatile uint32_t erraddr; /* ALT_SDR_CTL_ERRADDR */ - volatile uint32_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */ - volatile uint32_t dropaddr; /* ALT_SDR_CTL_DROPADDR */ - volatile uint32_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */ - volatile uint32_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */ - volatile uint32_t staticcfg; /* ALT_SDR_CTL_STATICCFG */ - volatile uint32_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */ - volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */ - volatile uint32_t portcfg; /* ALT_SDR_CTL_PORTCFG */ - volatile uint32_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */ - volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */ - volatile uint32_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */ - volatile uint32_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */ - volatile uint32_t protruleid; /* ALT_SDR_CTL_PROTRULEID */ - volatile uint32_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */ - volatile uint32_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */ - volatile uint32_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */ - volatile uint32_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */ - volatile uint32_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */ - volatile uint32_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */ - volatile ALT_SDR_CTL_MPWT_raw_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */ - volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */ - volatile uint32_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */ - volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SDR_CTL. */ -typedef volatile struct ALT_SDR_CTL_raw_s ALT_SDR_CTL_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SDR. - */ -struct ALT_SDR_s -{ - volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */ - volatile ALT_SDR_CTL_t ctrlgrp; /* ALT_SDR_CTL */ - volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_SDR. */ -typedef volatile struct ALT_SDR_s ALT_SDR_t; -/* The struct declaration for the raw register contents of register group ALT_SDR. */ -struct ALT_SDR_raw_s -{ - volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */ - volatile ALT_SDR_CTL_raw_t ctrlgrp; /* ALT_SDR_CTL */ - volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SDR. */ -typedef volatile struct ALT_SDR_raw_s ALT_SDR_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_SDR_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_sysmgr.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_sysmgr.h deleted file mode 100644 index fce6d6e11e..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_sysmgr.h +++ /dev/null @@ -1,24810 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_SYSMGR */ - -#ifndef __ALTERA_ALT_SYSMGR_H__ -#define __ALTERA_ALT_SYSMGR_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : System Manager Module - ALT_SYSMGR - * System Manager Module - * - * Registers in the System Manager module - * - */ -/* - * Register : Silicon ID1 Register - siliconid1 - * - * Specifies Silicon ID and revision number. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------- - * [15:0] | R | 0x1 | Silicon Revision - * [31:16] | R | 0x0 | Silicon ID - * - */ -/* - * Field : Silicon Revision - rev - * - * Silicon revision number. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:------------ - * ALT_SYSMGR_SILICONID1_REV_E_REV1 | 0x1 | Revision 1 - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_SILICONID1_REV - * - * Revision 1 - */ -#define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */ -#define ALT_SYSMGR_SILICONID1_REV_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */ -#define ALT_SYSMGR_SILICONID1_REV_MSB 15 -/* The width in bits of the ALT_SYSMGR_SILICONID1_REV register field. */ -#define ALT_SYSMGR_SILICONID1_REV_WIDTH 16 -/* The mask used to set the ALT_SYSMGR_SILICONID1_REV register field value. */ -#define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_SYSMGR_SILICONID1_REV register field value. */ -#define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000 -/* The reset value of the ALT_SYSMGR_SILICONID1_REV register field. */ -#define ALT_SYSMGR_SILICONID1_REV_RESET 0x1 -/* Extracts the ALT_SYSMGR_SILICONID1_REV field value from a register. */ -#define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_SYSMGR_SILICONID1_REV register field value suitable for setting the register. */ -#define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff) - -/* - * Field : Silicon ID - id - * - * Silicon ID - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:---------------------------------------------- - * ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV | 0x0 | HPS in Cyclone V and Arria V SoC FPGA devices - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_SILICONID1_ID - * - * HPS in Cyclone V and Arria V SoC FPGA devices - */ -#define ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */ -#define ALT_SYSMGR_SILICONID1_ID_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */ -#define ALT_SYSMGR_SILICONID1_ID_MSB 31 -/* The width in bits of the ALT_SYSMGR_SILICONID1_ID register field. */ -#define ALT_SYSMGR_SILICONID1_ID_WIDTH 16 -/* The mask used to set the ALT_SYSMGR_SILICONID1_ID register field value. */ -#define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000 -/* The mask used to clear the ALT_SYSMGR_SILICONID1_ID register field value. */ -#define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff -/* The reset value of the ALT_SYSMGR_SILICONID1_ID register field. */ -#define ALT_SYSMGR_SILICONID1_ID_RESET 0x0 -/* Extracts the ALT_SYSMGR_SILICONID1_ID field value from a register. */ -#define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16) -/* Produces a ALT_SYSMGR_SILICONID1_ID register field value suitable for setting the register. */ -#define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_SILICONID1. - */ -struct ALT_SYSMGR_SILICONID1_s -{ - const uint32_t rev : 16; /* Silicon Revision */ - const uint32_t id : 16; /* Silicon ID */ -}; - -/* The typedef declaration for register ALT_SYSMGR_SILICONID1. */ -typedef volatile struct ALT_SYSMGR_SILICONID1_s ALT_SYSMGR_SILICONID1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_SILICONID1 register from the beginning of the component. */ -#define ALT_SYSMGR_SILICONID1_OFST 0x0 - -/* - * Register : Silicon ID2 Register - siliconid2 - * - * Reserved for future use. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [31:0] | R | 0x0 | Reserved - * - */ -/* - * Field : Reserved - rsv - * - * Reserved for future use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */ -#define ALT_SYSMGR_SILICONID2_RSV_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */ -#define ALT_SYSMGR_SILICONID2_RSV_MSB 31 -/* The width in bits of the ALT_SYSMGR_SILICONID2_RSV register field. */ -#define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32 -/* The mask used to set the ALT_SYSMGR_SILICONID2_RSV register field value. */ -#define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SYSMGR_SILICONID2_RSV register field value. */ -#define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000 -/* The reset value of the ALT_SYSMGR_SILICONID2_RSV register field. */ -#define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0 -/* Extracts the ALT_SYSMGR_SILICONID2_RSV field value from a register. */ -#define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SYSMGR_SILICONID2_RSV register field value suitable for setting the register. */ -#define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_SILICONID2. - */ -struct ALT_SYSMGR_SILICONID2_s -{ - const uint32_t rsv : 32; /* Reserved */ -}; - -/* The typedef declaration for register ALT_SYSMGR_SILICONID2. */ -typedef volatile struct ALT_SYSMGR_SILICONID2_s ALT_SYSMGR_SILICONID2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_SILICONID2 register from the beginning of the component. */ -#define ALT_SYSMGR_SILICONID2_OFST 0x4 - -/* - * Register : L4 Watchdog Debug Register - wddbg - * - * Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These - * control registers are used to drive the pause input signal of the L4 watchdogs. - * Note that the watchdogs built into the MPU automatically are paused when their - * associated CPU enters debug mode. Only reset by a cold reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [1:0] | RW | 0x3 | Debug Mode - * [3:2] | RW | 0x3 | Debug Mode - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Debug Mode - mode_0 - * - * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index - * matches L4 watchdog index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of - * : | | CPUs - * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug - * : | | mode - * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug - * : | | mode - * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in - * : | | debug mode - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 - * - * Continue normal operation ignoring debug mode of CPUs - */ -#define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 - * - * Pause normal operation only if CPU0 is in debug mode - */ -#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 - * - * Pause normal operation only if CPU1 is in debug mode - */ -#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0 - * - * Pause normal operation if CPU0 or CPU1 is in debug mode - */ -#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ -#define ALT_SYSMGR_WDDBG_MOD_0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ -#define ALT_SYSMGR_WDDBG_MOD_0_MSB 1 -/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ -#define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_0 register field value. */ -#define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_0 register field value. */ -#define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_WDDBG_MOD_0 register field. */ -#define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3 -/* Extracts the ALT_SYSMGR_WDDBG_MOD_0 field value from a register. */ -#define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_WDDBG_MOD_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : Debug Mode - mode_1 - * - * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index - * matches L4 watchdog index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of - * : | | CPUs - * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug - * : | | mode - * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug - * : | | mode - * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in - * : | | debug mode - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 - * - * Continue normal operation ignoring debug mode of CPUs - */ -#define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 - * - * Pause normal operation only if CPU0 is in debug mode - */ -#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 - * - * Pause normal operation only if CPU1 is in debug mode - */ -#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1 - * - * Pause normal operation if CPU0 or CPU1 is in debug mode - */ -#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ -#define ALT_SYSMGR_WDDBG_MOD_1_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ -#define ALT_SYSMGR_WDDBG_MOD_1_MSB 3 -/* The width in bits of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ -#define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_WDDBG_MOD_1 register field value. */ -#define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c -/* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_1 register field value. */ -#define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3 -/* The reset value of the ALT_SYSMGR_WDDBG_MOD_1 register field. */ -#define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3 -/* Extracts the ALT_SYSMGR_WDDBG_MOD_1 field value from a register. */ -#define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2) -/* Produces a ALT_SYSMGR_WDDBG_MOD_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_WDDBG. - */ -struct ALT_SYSMGR_WDDBG_s -{ - uint32_t mode_0 : 2; /* Debug Mode */ - uint32_t mode_1 : 2; /* Debug Mode */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_WDDBG. */ -typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_WDDBG register from the beginning of the component. */ -#define ALT_SYSMGR_WDDBG_OFST 0x10 - -/* - * Register : Boot Info Register - bootinfo - * - * Provides access to boot configuration information. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:--------|:--------------------- - * [2:0] | R | Unknown | Boot Select - * [4:3] | R | Unknown | Clock Select - * [7:5] | R | Unknown | HPS Pin Boot Select - * [9:8] | R | Unknown | HPS Pin Clock Select - * [31:10] | ??? | Unknown | *UNDEFINED* - * - */ -/* - * Field : Boot Select - bsel - * - * The boot select field specifies the boot source. It is read by the Boot ROM code - * on a cold or warm reset to determine the boot source. - * - * The HPS BSEL pins value are sampled upon deassertion of cold reset. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------------------|:------|:----------------------------------- - * ALT_SYSMGR_BOOT_BSEL_E_RSVD | 0x0 | Reserved - * ALT_SYSMGR_BOOT_BSEL_E_FPGA | 0x1 | FPGA (HPS2FPGA Bridge) - * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V | 0x2 | NAND Flash (1.8v) - * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V | 0x3 | NAND Flash (3.0v) - * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 | SD/MMC External Transceiver (1.8v) - * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 | SD/MMC Internal Transceiver (3.0v) - * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V | 0x6 | QSPI Flash (1.8v) - * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V | 0x7 | QSPI Flash (3.0v) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL - * - * Reserved - */ -#define ALT_SYSMGR_BOOT_BSEL_E_RSVD 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL - * - * FPGA (HPS2FPGA Bridge) - */ -#define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL - * - * NAND Flash (1.8v) - */ -#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL - * - * NAND Flash (3.0v) - */ -#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL - * - * SD/MMC External Transceiver (1.8v) - */ -#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL - * - * SD/MMC Internal Transceiver (3.0v) - */ -#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL - * - * QSPI Flash (1.8v) - */ -#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL - * - * QSPI Flash (3.0v) - */ -#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */ -#define ALT_SYSMGR_BOOT_BSEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */ -#define ALT_SYSMGR_BOOT_BSEL_MSB 2 -/* The width in bits of the ALT_SYSMGR_BOOT_BSEL register field. */ -#define ALT_SYSMGR_BOOT_BSEL_WIDTH 3 -/* The mask used to set the ALT_SYSMGR_BOOT_BSEL register field value. */ -#define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00000007 -/* The mask used to clear the ALT_SYSMGR_BOOT_BSEL register field value. */ -#define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xfffffff8 -/* The reset value of the ALT_SYSMGR_BOOT_BSEL register field is UNKNOWN. */ -#define ALT_SYSMGR_BOOT_BSEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_BOOT_BSEL field value from a register. */ -#define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00000007) >> 0) -/* Produces a ALT_SYSMGR_BOOT_BSEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 0) & 0x00000007) - -/* - * Field : Clock Select - csel - * - * The clock select field specifies clock information for booting. The clock select - * encoding is a function of the CSEL value. The clock select field is read by the - * Boot ROM code on a cold or warm reset when booting from a flash device to get - * information about how to setup the HPS clocking to boot from the specified clock - * device. - * - * The encoding of the clock select field is specified by the enum associated with - * this field. - * - * The HPS CSEL pins value are sampled upon deassertion of cold reset. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:------------------------------------------------ - * ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 | 0x0 | QSPI device clock is osc1_clk divided by 4, - * : | | SD/MMC device clock is osc1_clk divided by 4, - * : | | NAND device operation is osc1_clk divided by 25 - * ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 | 0x1 | QSPI device clock is osc1_clk divided by 2, - * : | | SD/MMC device clock is osc1_clk divided by 1, - * : | | NAND device operation is osc1_clk multiplied by - * : | | 20/25 - * ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 | 0x2 | QSPI device clock is osc1_clk divided by 1, - * : | | SD/MMC device clock is osc1_clk divided by 2, - * : | | NAND device operation is osc1_clk multiplied by - * : | | 10/25 - * ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 | 0x3 | QSPI device clock is osc1_clk multiplied by 2, - * : | | SD/MMC device clock is osc1_clk divided by 4, - * : | | NAND device operation is osc1_clk multiplied by - * : | | 5/25 - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL - * - * QSPI device clock is osc1_clk divided by 4, SD/MMC device clock is osc1_clk - * divided by 4, NAND device operation is osc1_clk divided by 25 - */ -#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL - * - * QSPI device clock is osc1_clk divided by 2, SD/MMC device clock is osc1_clk - * divided by 1, NAND device operation is osc1_clk multiplied by 20/25 - */ -#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL - * - * QSPI device clock is osc1_clk divided by 1, SD/MMC device clock is osc1_clk - * divided by 2, NAND device operation is osc1_clk multiplied by 10/25 - */ -#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL - * - * QSPI device clock is osc1_clk multiplied by 2, SD/MMC device clock is osc1_clk - * divided by 4, NAND device operation is osc1_clk multiplied by 5/25 - */ -#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */ -#define ALT_SYSMGR_BOOT_CSEL_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */ -#define ALT_SYSMGR_BOOT_CSEL_MSB 4 -/* The width in bits of the ALT_SYSMGR_BOOT_CSEL register field. */ -#define ALT_SYSMGR_BOOT_CSEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_BOOT_CSEL register field value. */ -#define ALT_SYSMGR_BOOT_CSEL_SET_MSK 0x00000018 -/* The mask used to clear the ALT_SYSMGR_BOOT_CSEL register field value. */ -#define ALT_SYSMGR_BOOT_CSEL_CLR_MSK 0xffffffe7 -/* The reset value of the ALT_SYSMGR_BOOT_CSEL register field is UNKNOWN. */ -#define ALT_SYSMGR_BOOT_CSEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_BOOT_CSEL field value from a register. */ -#define ALT_SYSMGR_BOOT_CSEL_GET(value) (((value) & 0x00000018) >> 3) -/* Produces a ALT_SYSMGR_BOOT_CSEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_BOOT_CSEL_SET(value) (((value) << 3) & 0x00000018) - -/* - * Field : HPS Pin Boot Select - pinbsel - * - * Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are - * sampled upon deassertion of cold reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */ -#define ALT_SYSMGR_BOOT_PINBSEL_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */ -#define ALT_SYSMGR_BOOT_PINBSEL_MSB 7 -/* The width in bits of the ALT_SYSMGR_BOOT_PINBSEL register field. */ -#define ALT_SYSMGR_BOOT_PINBSEL_WIDTH 3 -/* The mask used to set the ALT_SYSMGR_BOOT_PINBSEL register field value. */ -#define ALT_SYSMGR_BOOT_PINBSEL_SET_MSK 0x000000e0 -/* The mask used to clear the ALT_SYSMGR_BOOT_PINBSEL register field value. */ -#define ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK 0xffffff1f -/* The reset value of the ALT_SYSMGR_BOOT_PINBSEL register field is UNKNOWN. */ -#define ALT_SYSMGR_BOOT_PINBSEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_BOOT_PINBSEL field value from a register. */ -#define ALT_SYSMGR_BOOT_PINBSEL_GET(value) (((value) & 0x000000e0) >> 5) -/* Produces a ALT_SYSMGR_BOOT_PINBSEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_BOOT_PINBSEL_SET(value) (((value) << 5) & 0x000000e0) - -/* - * Field : HPS Pin Clock Select - pincsel - * - * Specifies the sampled value of the HPS CSEL pins. The value of HPS CSEL pins are - * sampled upon deassertion of cold reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */ -#define ALT_SYSMGR_BOOT_PINCSEL_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */ -#define ALT_SYSMGR_BOOT_PINCSEL_MSB 9 -/* The width in bits of the ALT_SYSMGR_BOOT_PINCSEL register field. */ -#define ALT_SYSMGR_BOOT_PINCSEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_BOOT_PINCSEL register field value. */ -#define ALT_SYSMGR_BOOT_PINCSEL_SET_MSK 0x00000300 -/* The mask used to clear the ALT_SYSMGR_BOOT_PINCSEL register field value. */ -#define ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK 0xfffffcff -/* The reset value of the ALT_SYSMGR_BOOT_PINCSEL register field is UNKNOWN. */ -#define ALT_SYSMGR_BOOT_PINCSEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_BOOT_PINCSEL field value from a register. */ -#define ALT_SYSMGR_BOOT_PINCSEL_GET(value) (((value) & 0x00000300) >> 8) -/* Produces a ALT_SYSMGR_BOOT_PINCSEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_BOOT_PINCSEL_SET(value) (((value) << 8) & 0x00000300) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_BOOT. - */ -struct ALT_SYSMGR_BOOT_s -{ - const uint32_t bsel : 3; /* Boot Select */ - const uint32_t csel : 2; /* Clock Select */ - const uint32_t pinbsel : 3; /* HPS Pin Boot Select */ - const uint32_t pincsel : 2; /* HPS Pin Clock Select */ - uint32_t : 22; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_BOOT. */ -typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_BOOT register from the beginning of the component. */ -#define ALT_SYSMGR_BOOT_OFST 0x14 - -/* - * Register : HPS Info Register - hpsinfo - * - * Provides information about the HPS capabilities. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:------------ - * [0] | R | Unknown | Dual Core - * [1] | R | Unknown | CAN - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Dual Core - dualcore - * - * Indicates if CPU1 is available in MPU or not. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------|:------|:--------------------------------------------- - * ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE | 0x0 | Not dual-core (only CPU0 available). - * ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE | 0x1 | Is dual-core (CPU0 and CPU1 both available). - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE - * - * Not dual-core (only CPU0 available). - */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE - * - * Is dual-core (CPU0 and CPU1 both available). - */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_MSB 0 -/* The width in bits of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_HPSINFO_DUALCORE register field is UNKNOWN. */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_RESET 0x0 -/* Extracts the ALT_SYSMGR_HPSINFO_DUALCORE field value from a register. */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_HPSINFO_DUALCORE register field value suitable for setting the register. */ -#define ALT_SYSMGR_HPSINFO_DUALCORE_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : CAN - can - * - * Indicates if CAN0 and CAN1 controllers are available or not. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------|:------|:--------------------------------- - * ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE | 0x0 | CAN0 and CAN1 are not available. - * ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE | 0x1 | CAN0 and CAN1 are available. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN - * - * CAN0 and CAN1 are not available. - */ -#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN - * - * CAN0 and CAN1 are available. - */ -#define ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */ -#define ALT_SYSMGR_HPSINFO_CAN_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */ -#define ALT_SYSMGR_HPSINFO_CAN_MSB 1 -/* The width in bits of the ALT_SYSMGR_HPSINFO_CAN register field. */ -#define ALT_SYSMGR_HPSINFO_CAN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_HPSINFO_CAN register field value. */ -#define ALT_SYSMGR_HPSINFO_CAN_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_HPSINFO_CAN register field value. */ -#define ALT_SYSMGR_HPSINFO_CAN_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_HPSINFO_CAN register field is UNKNOWN. */ -#define ALT_SYSMGR_HPSINFO_CAN_RESET 0x0 -/* Extracts the ALT_SYSMGR_HPSINFO_CAN field value from a register. */ -#define ALT_SYSMGR_HPSINFO_CAN_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_HPSINFO_CAN register field value suitable for setting the register. */ -#define ALT_SYSMGR_HPSINFO_CAN_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_HPSINFO. - */ -struct ALT_SYSMGR_HPSINFO_s -{ - const uint32_t dualcore : 1; /* Dual Core */ - const uint32_t can : 1; /* CAN */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_HPSINFO. */ -typedef volatile struct ALT_SYSMGR_HPSINFO_s ALT_SYSMGR_HPSINFO_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_HPSINFO register from the beginning of the component. */ -#define ALT_SYSMGR_HPSINFO_OFST 0x18 - -/* - * Register : Parity Fail Injection Register - parityinj - * - * Inject parity failures into the parity-protected RAMs in the MPU. Allows - * software to test the parity failure interrupt handler. The field array index - * corresponds to the CPU index. - * - * All fields are reset by a cold or warm reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------------------------------------------- - * [0] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM - * [1] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM - * [2] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM - * [3] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM - * [4] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM - * [5] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM - * [6] | RW | 0x0 | Parity Fail Injection for Main TLB RAM - * [7] | RW | 0x0 | Parity Fail Injection for Main TLB RAM - * [8] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM - * [9] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM - * [10] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM - * [11] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM - * [12] | RW | 0x0 | Parity Fail Injection for GHB RAM - * [13] | RW | 0x0 | Parity Fail Injection for GHB RAM - * [14] | RW | 0x0 | Parity Fail Injection for BTAC RAM - * [15] | RW | 0x0 | Parity Fail Injection for BTAC RAM - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_0 - * - * If 1, injecting parity error to Data Cache Data RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_0_MSB 0 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_0 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_1 - * - * If 1, injecting parity error to Data Cache Data RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_1_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_1_MSB 1 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_1_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_1 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_1_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_0 - * - * If 1, injecting parity error to Data Cache Tag RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_0_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_0_MSB 2 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_0_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_0 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_0_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_1 - * - * If 1, injecting parity error to Data Cache Tag RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_1_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_1_MSB 3 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_1_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_1 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_1_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_0 - * - * If 1, injecting parity error to Data Cache Outer RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_MSB 4 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_0 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_1 - * - * If 1, injecting parity error to Data Cache Outer RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_MSB 5 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET_MSK 0x00000020 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_CLR_MSK 0xffffffdf -/* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_1 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Parity Fail Injection for Main TLB RAM - maintlb_0 - * - * If 1, injecting parity error to Main TLB RAM.The field array index corresponds - * to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_MSB 6 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_0 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Parity Fail Injection for Main TLB RAM - maintlb_1 - * - * If 1, injecting parity error to Main TLB RAM.The field array index corresponds - * to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_MSB 7 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET_MSK 0x00000080 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_CLR_MSK 0xffffff7f -/* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_1 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_0 - * - * If 1, injecting parity error to Instruction Cache Data RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_0_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_0_MSB 8 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET_MSK 0x00000100 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_0_CLR_MSK 0xfffffeff -/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_0 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_0_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_1 - * - * If 1, injecting parity error to Instruction Cache Data RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_1_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_1_MSB 9 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET_MSK 0x00000200 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_1_CLR_MSK 0xfffffdff -/* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_1 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_1_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_0 - * - * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_0_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_0_MSB 10 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET_MSK 0x00000400 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_0_CLR_MSK 0xfffffbff -/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_0 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_0_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_1 - * - * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index - * corresponds to the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_1_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_1_MSB 11 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET_MSK 0x00000800 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_1_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_1 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_1_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : Parity Fail Injection for GHB RAM - ghb_0 - * - * If 1, injecting parity error to GHB RAM.The field array index corresponds to the - * CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_GHB_0_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_GHB_0_MSB 12 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_GHB_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_GHB_0_SET_MSK 0x00001000 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_GHB_0_CLR_MSK 0xffffefff -/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_GHB_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_0 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_GHB_0_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_SYSMGR_PARITYINJ_GHB_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_GHB_0_SET(value) (((value) << 12) & 0x00001000) - -/* - * Field : Parity Fail Injection for GHB RAM - ghb_1 - * - * If 1, injecting parity error to GHB RAM.The field array index corresponds to the - * CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_GHB_1_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_GHB_1_MSB 13 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_GHB_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_GHB_1_SET_MSK 0x00002000 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_GHB_1_CLR_MSK 0xffffdfff -/* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_GHB_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_GHB_1 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_GHB_1_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_SYSMGR_PARITYINJ_GHB_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_GHB_1_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : Parity Fail Injection for BTAC RAM - btac_0 - * - * If 1, injecting parity error to BTAC RAM.The field array index corresponds to - * the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_0_LSB 14 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_0_MSB 14 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET_MSK 0x00004000 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_0_CLR_MSK 0xffffbfff -/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_0 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_0_GET(value) (((value) & 0x00004000) >> 14) -/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_0_SET(value) (((value) << 14) & 0x00004000) - -/* - * Field : Parity Fail Injection for BTAC RAM - btac_1 - * - * If 1, injecting parity error to BTAC RAM.The field array index corresponds to - * the CPU index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_1_LSB 15 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_1_MSB 15 -/* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET_MSK 0x00008000 -/* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_1_CLR_MSK 0xffff7fff -/* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_1 field value from a register. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_1_GET(value) (((value) & 0x00008000) >> 15) -/* Produces a ALT_SYSMGR_PARITYINJ_BTAC_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_PARITYINJ_BTAC_1_SET(value) (((value) << 15) & 0x00008000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PARITYINJ. - */ -struct ALT_SYSMGR_PARITYINJ_s -{ - uint32_t dcdata_0 : 1; /* Parity Fail Injection for Data Cache Data RAM */ - uint32_t dcdata_1 : 1; /* Parity Fail Injection for Data Cache Data RAM */ - uint32_t dctag_0 : 1; /* Parity Fail Injection for Data Cache Tag RAM */ - uint32_t dctag_1 : 1; /* Parity Fail Injection for Data Cache Tag RAM */ - uint32_t dcouter_0 : 1; /* Parity Fail Injection for Data Cache Outer RAM */ - uint32_t dcouter_1 : 1; /* Parity Fail Injection for Data Cache Outer RAM */ - uint32_t maintlb_0 : 1; /* Parity Fail Injection for Main TLB RAM */ - uint32_t maintlb_1 : 1; /* Parity Fail Injection for Main TLB RAM */ - uint32_t icdata_0 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */ - uint32_t icdata_1 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */ - uint32_t ictag_0 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */ - uint32_t ictag_1 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */ - uint32_t ghb_0 : 1; /* Parity Fail Injection for GHB RAM */ - uint32_t ghb_1 : 1; /* Parity Fail Injection for GHB RAM */ - uint32_t btac_0 : 1; /* Parity Fail Injection for BTAC RAM */ - uint32_t btac_1 : 1; /* Parity Fail Injection for BTAC RAM */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PARITYINJ. */ -typedef volatile struct ALT_SYSMGR_PARITYINJ_s ALT_SYSMGR_PARITYINJ_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PARITYINJ register from the beginning of the component. */ -#define ALT_SYSMGR_PARITYINJ_OFST 0x1c - -/* - * Register Group : FPGA Interface Group - ALT_SYSMGR_FPGAINTF - * FPGA Interface Group - * - * Registers used to enable/disable interfaces between the FPGA and HPS. Required - * for either of the following situations:[list][*]Interfaces that cannot be - * disabled by putting an HPS module associated with the interface into - * reset.[*]HPS modules that accept signals from the FPGA fabric and those signals - * might interfere with the normal operation of the module.[/list]. - * - * All registers are only reset by a cold reset (ignore warm reset). - * - */ -/* - * Register : Global Disable Register - gbl - * - * Used to disable all interfaces between the FPGA and HPS. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------- - * [0] | RW | 0x1 | Global Interface - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Global Interface - intf - * - * Used to disable all interfaces between the FPGA and HPS. Software must ensure - * that all interfaces between the FPGA and HPS are inactive before disabling them. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS | 0x0 | All interfaces between FPGA and HPS are - * : | | disabled. - * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN | 0x1 | Interfaces between FPGA and HPS are not all - * : | | disabled. Interfaces can be indivdually disabled - * : | | by putting the HPS module associated with the - * : | | interface in reset using registers in the Reset - * : | | Manager or by using registers in this register - * : | | group of the System Manager for interfaces - * : | | without an associated module. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF - * - * All interfaces between FPGA and HPS are disabled. - */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF - * - * Interfaces between FPGA and HPS are not all disabled. Interfaces can be - * indivdually disabled by putting the HPS module associated with the interface in - * reset using registers in the Reset Manager or by using registers in this - * register group of the System Manager for interfaces without an associated - * module. - */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB 0 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET 0x1 -/* Extracts the ALT_SYSMGR_FPGAINTF_GBL_INTF field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_FPGAINTF_GBL_INTF register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_FPGAINTF_GBL. - */ -struct ALT_SYSMGR_FPGAINTF_GBL_s -{ - uint32_t intf : 1; /* Global Interface */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_GBL. */ -typedef volatile struct ALT_SYSMGR_FPGAINTF_GBL_s ALT_SYSMGR_FPGAINTF_GBL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_FPGAINTF_GBL register from the beginning of the component. */ -#define ALT_SYSMGR_FPGAINTF_GBL_OFST 0x0 - -/* - * Register : Individual Disable Register - indiv - * - * Used to disable individual interfaces between the FPGA and HPS. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [0] | RW | 0x1 | Reset Request Interface - * [1] | RW | 0x1 | JTAG Enable Interface - * [2] | RW | 0x1 | CONFIG_IO Interface - * [3] | RW | 0x1 | Boundary-Scan Interface - * [4] | RW | 0x1 | Trace Interface - * [5] | ??? | 0x1 | *UNDEFINED* - * [6] | RW | 0x1 | STM Event Interface - * [7] | RW | 0x1 | Cross Trigger Interface (CTI) - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Reset Request Interface - rstreqintf - * - * Used to disable the reset request interface. This interface allows logic in the - * FPGA fabric to request HPS resets. This field disables the following reset - * request signals from the FPGA fabric to HPS:[list][*]f2h_cold_rst_req_n - - * Triggers a cold reset of the HPS[*]f2h_warm_rst_req_n - Triggers a warm reset of - * the HPS[*]f2h_dbg_rst_req_n - Triggers a debug reset of the HPS[/list] - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS | 0x0 | Reset request interface is disabled. Logic in - * : | | the FPGA fabric cannot reset the HPS. - * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN | 0x1 | Reset request interface is enabled. Logic in the - * : | | FPGA fabric can reset the HPS. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF - * - * Reset request interface is disabled. Logic in the FPGA fabric cannot reset the - * HPS. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF - * - * Reset request interface is enabled. Logic in the FPGA fabric can reset the HPS. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB 0 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET 0x1 -/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : JTAG Enable Interface - jtagenintf - * - * Used to disable the JTAG enable interface. This interface allows logic in the - * FPGA fabric to disable the HPS JTAG operation. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:------------------------------------------------ - * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS | 0x0 | JTAG enable interface is disabled. Logic in the - * : | | FPGA fabric cannot disable the HPS JTAG. - * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN | 0x1 | JTAG enable interface is enabled. Logic in the - * : | | FPGA fabric can disable the HPS JTAG. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF - * - * JTAG enable interface is disabled. Logic in the FPGA fabric cannot disable the - * HPS JTAG. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF - * - * JTAG enable interface is enabled. Logic in the FPGA fabric can disable the HPS - * JTAG. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB 1 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET 0x1 -/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : CONFIG_IO Interface - configiointf - * - * Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP - * controller to execute the CONFIG_IO instruction and configure all device I/Os - * (FPGA and HPS). This is typically done before executing boundary-scan - * instructions. The CONFIG_IO interface must be enabled before attempting to send - * the CONFIG_IO instruction to the FPGA JTAG TAP controller. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS | 0x0 | CONFIG_IO interface is disabled. Execution of - * : | | the CONFIG_IO instruction in the FPGA JTAG TAP - * : | | controller is unsupported and produces undefined - * : | | results. - * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN | 0x1 | CONFIG_IO interface is enabled. Execution of the - * : | | CONFIG_IO instruction in the FPGA JTAG TAP - * : | | controller is supported. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF - * - * CONFIG_IO interface is disabled. Execution of the CONFIG_IO instruction in the - * FPGA JTAG TAP controller is unsupported and produces undefined results. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF - * - * CONFIG_IO interface is enabled. Execution of the CONFIG_IO instruction in the - * FPGA JTAG TAP controller is supported. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB 2 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET 0x1 -/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Boundary-Scan Interface - bscanintf - * - * Used to disable the boundary-scan interface. This interface allows the FPGA JTAG - * TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD, - * EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting - * to send the boundary-scan instructions to the FPGA JTAG TAP controller. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS | 0x0 | Boundary-scan interface is disabled. Execution - * : | | of boundary-scan instructions in the FPGA JTAG - * : | | TAP controller is unsupported and produces - * : | | undefined results. - * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN | 0x1 | Boundary-scan interface is enabled. Execution of - * : | | the boundary-scan instructions in the FPGA JTAG - * : | | TAP controller is supported. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF - * - * Boundary-scan interface is disabled. Execution of boundary-scan instructions in - * the FPGA JTAG TAP controller is unsupported and produces undefined results. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF - * - * Boundary-scan interface is enabled. Execution of the boundary-scan instructions - * in the FPGA JTAG TAP controller is supported. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB 3 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET 0x1 -/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Trace Interface - traceintf - * - * Used to disable the trace interface. This interface allows the HPS debug logic - * to send trace data to logic in the FPGA fabric. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:----------------------------------------------- - * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS | 0x0 | Trace interface is disabled. HPS debug logic - * : | | cannot send trace data to the FPGA fabric. - * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN | 0x1 | Trace interface is enabled. Other registers in - * : | | the HPS debug logic must be programmmed to - * : | | actually send trace data to the FPGA fabric. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF - * - * Trace interface is disabled. HPS debug logic cannot send trace data to the FPGA - * fabric. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF - * - * Trace interface is enabled. Other registers in the HPS debug logic must be - * programmmed to actually send trace data to the FPGA fabric. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB 4 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET 0x1 -/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : STM Event Interface - stmeventintf - * - * Used to disable the STM event interface. This interface allows logic in the FPGA - * fabric to trigger events to the STM debug module in the HPS. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------|:------|:----------------------------------------------- - * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS | 0x0 | STM event interface is disabled. Logic in the - * : | | FPGA fabric cannot trigger STM events. - * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN | 0x1 | STM event interface is enabled. Logic in the - * : | | FPGA fabric can trigger STM events. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF - * - * STM event interface is disabled. Logic in the FPGA fabric cannot trigger STM - * events. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF - * - * STM event interface is enabled. Logic in the FPGA fabric can trigger STM - * events. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB 6 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET 0x1 -/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Cross Trigger Interface (CTI) - crosstrigintf - * - * Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note - * that this doesn't prevent the HPS debug logic from sending triggers to the FPGA - * Fabric. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------------|:------|:---------------------------------- - * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS | 0x0 | FPGA Fabric cannot send triggers. - * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN | 0x1 | FPGA Fabric can send triggers. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF - * - * FPGA Fabric cannot send triggers. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF - * - * FPGA Fabric can send triggers. - */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB 7 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK 0x00000080 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK 0xffffff7f -/* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET 0x1 -/* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET(value) (((value) << 7) & 0x00000080) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_FPGAINTF_INDIV. - */ -struct ALT_SYSMGR_FPGAINTF_INDIV_s -{ - uint32_t rstreqintf : 1; /* Reset Request Interface */ - uint32_t jtagenintf : 1; /* JTAG Enable Interface */ - uint32_t configiointf : 1; /* CONFIG_IO Interface */ - uint32_t bscanintf : 1; /* Boundary-Scan Interface */ - uint32_t traceintf : 1; /* Trace Interface */ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t stmeventintf : 1; /* STM Event Interface */ - uint32_t crosstrigintf : 1; /* Cross Trigger Interface (CTI) */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_INDIV. */ -typedef volatile struct ALT_SYSMGR_FPGAINTF_INDIV_s ALT_SYSMGR_FPGAINTF_INDIV_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_FPGAINTF_INDIV register from the beginning of the component. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_OFST 0x4 - -/* - * Register : Module Disable Register - module - * - * Used to disable signals from the FPGA fabric to individual HPS modules. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [1:0] | ??? | 0x0 | *UNDEFINED* - * [2] | RW | 0x0 | EMAC Module - * [3] | RW | 0x0 | EMAC Module - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : EMAC Module - emac_0 - * - * Used to disable signals from the FPGA fabric to the EMAC modules that could - * potentially interfere with their normal operation. - * - * The array index corresponds to the EMAC module instance. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation - * : | | of the EMAC module. - * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN | 0x1 | Signals from FPGA fabric can potentially affect - * : | | operation of the EMAC module. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 - * - * Signals from FPGA fabric cannot affect operation of the EMAC module. - */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 - * - * Signals from FPGA fabric can potentially affect operation of the EMAC module. - */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_MSB 2 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : EMAC Module - emac_1 - * - * Used to disable signals from the FPGA fabric to the EMAC modules that could - * potentially interfere with their normal operation. - * - * The array index corresponds to the EMAC module instance. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation - * : | | of the EMAC module. - * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN | 0x1 | Signals from FPGA fabric can potentially affect - * : | | operation of the EMAC module. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 - * - * Signals from FPGA fabric cannot affect operation of the EMAC module. - */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 - * - * Signals from FPGA fabric can potentially affect operation of the EMAC module. - */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_MSB 3 -/* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 field value from a register. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET(value) (((value) << 3) & 0x00000008) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_FPGAINTF_MODULE. - */ -struct ALT_SYSMGR_FPGAINTF_MODULE_s -{ - uint32_t : 2; /* *UNDEFINED* */ - uint32_t emac_0 : 1; /* EMAC Module */ - uint32_t emac_1 : 1; /* EMAC Module */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_FPGAINTF_MODULE. */ -typedef volatile struct ALT_SYSMGR_FPGAINTF_MODULE_s ALT_SYSMGR_FPGAINTF_MODULE_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_FPGAINTF_MODULE register from the beginning of the component. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_OFST 0x8 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_FPGAINTF. - */ -struct ALT_SYSMGR_FPGAINTF_s -{ - volatile ALT_SYSMGR_FPGAINTF_GBL_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */ - volatile ALT_SYSMGR_FPGAINTF_INDIV_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */ - volatile ALT_SYSMGR_FPGAINTF_MODULE_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */ - volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_FPGAINTF. */ -typedef volatile struct ALT_SYSMGR_FPGAINTF_s ALT_SYSMGR_FPGAINTF_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */ -struct ALT_SYSMGR_FPGAINTF_raw_s -{ - volatile uint32_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */ - volatile uint32_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */ - volatile uint32_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */ - volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */ -typedef volatile struct ALT_SYSMGR_FPGAINTF_raw_s ALT_SYSMGR_FPGAINTF_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Scan Manager Group - ALT_SYSMGR_SCANMGR - * Scan Manager Group - * - * Registers related to the Scan Manager that aren't located inside the Scan - * Manager itself. - * - */ -/* - * Register : Scan Manager Control Register - ctrl - * - * Controls behaviors of Scan Manager not controlled by registers in the Scan - * Manager itself. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------- - * [0] | RW | 0x0 | FPGA JTAG Enable - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : FPGA JTAG Enable - fpgajtagen - * - * Controls whether FPGA JTAG pins or Scan Manager drives JTAG signals to the FPGA. - * - * Only reset by a cold reset (ignores warm reset). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------|:------|:------------------------------------------ - * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS | 0x0 | FPGA JTAG pins drive JTAG signals to FPGA - * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR | 0x1 | Scan Manager drives JTAG signals to FPGA - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN - * - * FPGA JTAG pins drive JTAG signals to FPGA - */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN - * - * Scan Manager drives JTAG signals to FPGA - */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB 0 -/* The width in bits of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET 0x0 -/* Extracts the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN field value from a register. */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value suitable for setting the register. */ -#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_SCANMGR_CTL. - */ -struct ALT_SYSMGR_SCANMGR_CTL_s -{ - uint32_t fpgajtagen : 1; /* FPGA JTAG Enable */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_SCANMGR_CTL. */ -typedef volatile struct ALT_SYSMGR_SCANMGR_CTL_s ALT_SYSMGR_SCANMGR_CTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_SCANMGR_CTL register from the beginning of the component. */ -#define ALT_SYSMGR_SCANMGR_CTL_OFST 0x0 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_SCANMGR. - */ -struct ALT_SYSMGR_SCANMGR_s -{ - volatile ALT_SYSMGR_SCANMGR_CTL_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_SCANMGR. */ -typedef volatile struct ALT_SYSMGR_SCANMGR_s ALT_SYSMGR_SCANMGR_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */ -struct ALT_SYSMGR_SCANMGR_raw_s -{ - volatile uint32_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */ -typedef volatile struct ALT_SYSMGR_SCANMGR_raw_s ALT_SYSMGR_SCANMGR_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Freeze Control Group - ALT_SYSMGR_FRZCTL - * Freeze Control Group - * - * Registers used to generate HPS IO freeze signals. - * - * All registers are only reset by a cold reset (ignore warm reset). - * - */ -/* - * Register : VIO Control Register - vioctrl - * - * Used to drive freeze signals to HPS VIO banks. - * - * The register array index corresponds to the freeze channel. - * - * Freeze channel 0 provides freeze signals to VIO bank 0 and 1. - * - * Freeze channel 1 provides freeze signals to VIO bank 2 and 3. Only drives freeze - * signals when SRC.VIO1 is set to SW. - * - * Freeze channel 2 provides freeze signals to VIO bank 4. - * - * All fields are only reset by a cold reset (ignore warm reset). - * - * The following equation determines when the weak pullup resistor is enabled: - * - * enabled = ~wkpullup | (CFF & cfg & tristate) - * - * where CFF is the value of weak pullup as set by IO configuration - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------- - * [0] | RW | 0x0 | IO Configuration - * [1] | RW | 0x0 | IO Bus Hold - * [2] | RW | 0x0 | IO Tri-State - * [3] | RW | 0x0 | IO Weak Pullup - * [4] | RW | 0x0 | IO Slew-rate - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : IO Configuration - cfg - * - * Controls IO configuration - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:----------------------------------------------- - * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe - * : | | value). - * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously - * : | | configured by software using the Scan Manager. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG - * - * Disable IO configuration (forced to a safe value). - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG - * - * Enables IO configuration as previously configured by software using the Scan - * Manager. - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0 -/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_CFG field value from a register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : IO Bus Hold - bushold - * - * Controls bus hold circuit - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit. - * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD - * - * Disable bus hold circuit. - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD - * - * Bus hold circuit controlled by IO configuration. - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1 -/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD field value from a register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : IO Tri-State - tristate - * - * Controls IO tri-state - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:--------------------------------------------- - * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled. - * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE - * - * IO tri-state enabled. - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE - * - * IO tri-state controlled by IO configuration. - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2 -/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE field value from a register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : IO Weak Pullup - wkpullup - * - * Controls weak pullup resistor - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:--------------------------------------------- - * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled. - * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO - * : | | configuration. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP - * - * Weak pullup resistor enabled. - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP - * - * Weak pullup resistor enable controlled by IO configuration. - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3 -/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP field value from a register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : IO Slew-rate - slew - * - * Controls IO slew-rate - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:------------------------------------------ - * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow. - * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW - * - * Slew-rate forced to slow. - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW - * - * Slew-rate controlled by IO configuration. - */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4 -/* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW field value from a register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. - */ -struct ALT_SYSMGR_FRZCTL_VIOCTL_s -{ - uint32_t cfg : 1; /* IO Configuration */ - uint32_t bushold : 1; /* IO Bus Hold */ - uint32_t tristate : 1; /* IO Tri-State */ - uint32_t wkpullup : 1; /* IO Weak Pullup */ - uint32_t slew : 1; /* IO Slew-rate */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. */ -typedef volatile struct ALT_SYSMGR_FRZCTL_VIOCTL_s ALT_SYSMGR_FRZCTL_VIOCTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_FRZCTL_VIOCTL register from the beginning of the component. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0 - -/* - * Register : HIO Control Register - hioctrl - * - * Used to drive freeze signals to HPS HIO bank (DDR SDRAM). - * - * All fields are only reset by a cold reset (ignore warm reset). - * - * The following equation determines when the weak pullup resistor is enabled: - * - * enabled = ~wkpullup | (CFF & cfg & tristate) - * - * where CFF is the value of weak pullup as set by IO configuration - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------------------- - * [0] | RW | 0x0 | IO Configuration - * [1] | RW | 0x0 | IO Bus Hold - * [2] | RW | 0x0 | IO Tri-State - * [3] | RW | 0x0 | IO Weak Pullup - * [4] | RW | 0x0 | IO Slew-rate - * [5] | RW | 0x1 | DLL Reset - * [6] | RW | 0x1 | OCT Reset - * [7] | RW | 0x1 | IO and DQS Reset - * [8] | RW | 0x0 | OCT Calibration and Configuration Enable - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : IO Configuration - cfg - * - * Controls IO configuration - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:----------------------------------------------- - * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe - * : | | value). - * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously - * : | | configured by software using the Scan Manager. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG - * - * Disable IO configuration (forced to a safe value). - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG - * - * Enables IO configuration as previously configured by software using the Scan - * Manager. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_CFG field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : IO Bus Hold - bushold - * - * Controls bus hold circuit - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit. - * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD - * - * Disable bus hold circuit. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD - * - * Bus hold circuit controlled by IO configuration. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : IO Tri-State - tristate - * - * Controls IO tri-state - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:--------------------------------------------- - * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled. - * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE - * - * IO tri-state enabled. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE - * - * IO tri-state controlled by IO configuration. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : IO Weak Pullup - wkpullup - * - * Controls weak pullup resistor - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:--------------------------------------------- - * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled. - * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO - * : | | configuration. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP - * - * Weak pullup resistor enabled. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP - * - * Weak pullup resistor enable controlled by IO configuration. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : IO Slew-rate - slew - * - * Controls IO slew-rate - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:------------------------------------------ - * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow. - * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW - * - * Slew-rate forced to slow. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW - * - * Slew-rate controlled by IO configuration. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : DLL Reset - dllrst - * - * Controls DLL (Delay-Locked Loop) reset. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------|:------|:---------------------------------------------- - * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS | 0x0 | No reset or clock gating. - * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN | 0x1 | Resets registers in the DLL and gates off DLL - * : | | clock. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST - * - * No reset or clock gating. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST - * - * Resets registers in the DLL and gates off DLL clock. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf -/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1 -/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : OCT Reset - octrst - * - * Controls OCT reset. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------|:------|:----------------------------- - * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS | 0x0 | No reset. - * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN | 0x1 | Resets registers in the OCT. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST - * - * No reset. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST - * - * Resets registers in the OCT. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1 -/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : IO and DQS Reset - regrst - * - * Controls IO and DQS reset. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------|:------|:------------------------------------------- - * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS | 0x0 | No reset. - * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN | 0x1 | Resets all IO registers and DQS registers. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST - * - * No reset. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST - * - * Resets all IO registers and DQS registers. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f -/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1 -/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : OCT Calibration and Configuration Enable - oct_cfgen_calstart - * - * Controls OCT calibration and OCT IO configuration enable. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS | 0x0 | Disables IO configuration (forced to a safe - * : | | value) in OCT calibration block. - * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN | 0x1 | Starts OCT calibration state machine and enables - * : | | IO configuration in OCT calibration block. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART - * - * Disables IO configuration (forced to a safe value) in OCT calibration block. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART - * - * Starts OCT calibration state machine and enables IO configuration in OCT - * calibration block. - */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff -/* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET(value) (((value) << 8) & 0x00000100) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. - */ -struct ALT_SYSMGR_FRZCTL_HIOCTL_s -{ - uint32_t cfg : 1; /* IO Configuration */ - uint32_t bushold : 1; /* IO Bus Hold */ - uint32_t tristate : 1; /* IO Tri-State */ - uint32_t wkpullup : 1; /* IO Weak Pullup */ - uint32_t slew : 1; /* IO Slew-rate */ - uint32_t dllrst : 1; /* DLL Reset */ - uint32_t octrst : 1; /* OCT Reset */ - uint32_t regrst : 1; /* IO and DQS Reset */ - uint32_t oct_cfgen_calstart : 1; /* OCT Calibration and Configuration Enable */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. */ -typedef volatile struct ALT_SYSMGR_FRZCTL_HIOCTL_s ALT_SYSMGR_FRZCTL_HIOCTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_FRZCTL_HIOCTL register from the beginning of the component. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10 - -/* - * Register : Source Register - src - * - * Contains register field to choose between software state machine (vioctrl array - * index [1] register) or hardware state machine in the Freeze Controller as the - * freeze signal source for VIO channel 1. - * - * All fields are only reset by a cold reset (ignore warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------- - * [0] | RW | 0x0 | VIO1 Freeze Signal Source - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : VIO1 Freeze Signal Source - vio1 - * - * The freeze signal source for VIO channel 1 (VIO bank 2 and bank 3). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW | 0x0 | VIO1 freeze signals are driven by software - * : | | writing to the VIOCTRL[1] register. The - * : | | VIO1-related fields in the hwctrl register are - * : | | active but don't effect the VIO1 freeze signals. - * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW | 0x1 | VIO1 freeze signals are driven by the hardware - * : | | state machine in the Freeze Controller. The - * : | | VIO1-related fields in the hwctrl register are - * : | | active and effect the VIO1 freeze signals. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1 - * - * VIO1 freeze signals are driven by software writing to the VIOCTRL[1] register. - * The VIO1-related fields in the hwctrl register are active but don't effect the - * VIO1 freeze signals. - */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1 - * - * VIO1 freeze signals are driven by the hardware state machine in the Freeze - * Controller. The VIO1-related fields in the hwctrl register are active and effect - * the VIO1 freeze signals. - */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB 0 -/* The width in bits of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET 0x0 -/* Extracts the ALT_SYSMGR_FRZCTL_SRC_VIO1 field value from a register. */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_FRZCTL_SRC. - */ -struct ALT_SYSMGR_FRZCTL_SRC_s -{ - uint32_t vio1 : 1; /* VIO1 Freeze Signal Source */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_FRZCTL_SRC. */ -typedef volatile struct ALT_SYSMGR_FRZCTL_SRC_s ALT_SYSMGR_FRZCTL_SRC_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_FRZCTL_SRC register from the beginning of the component. */ -#define ALT_SYSMGR_FRZCTL_SRC_OFST 0x14 - -/* - * Register : Hardware Control Register - hwctrl - * - * Activate freeze or thaw operations on VIO channel 1 (HPS IO bank 2 and bank 3) - * and monitor for completeness and the current state. - * - * These fields interact with the hardware state machine in the Freeze Controller. - * These fields can be accessed independent of the value of SRC1.VIO1 although they - * only have an effect on the VIO channel 1 freeze signals when SRC1.VIO1 is setup - * to have the hardware state machine be the freeze signal source. - * - * All fields are only reset by a cold reset (ignore warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------- - * [0] | RW | 0x1 | VIO channel 1 Freeze/Thaw request - * [2:1] | R | 0x2 | VIO channel 1 State - * [31:3] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : VIO channel 1 Freeze/Thaw request - vio1req - * - * Requests hardware state machine to generate freeze signal sequence to transition - * between frozen and thawed states. - * - * If this field is read by software, it contains the value previously written by - * software (i.e. this field is not written by hardware). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:-------------------------------------- - * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW | 0x0 | Requests a thaw (unfreeze) operation. - * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ | 0x1 | Requests a freeze operation. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ - * - * Requests a thaw (unfreeze) operation. - */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ - * - * Requests a freeze operation. - */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1 -/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : VIO channel 1 State - vio1state - * - * Software reads this field to determine the current frozen/thawed state of the - * VIO channel 1 or to determine when a freeze/thaw request is made by writing the - * corresponding *REQ field in this register has completed. - * - * Reset by a cold reset (ignores warm reset). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN | 0x0 | Transitioning from thawed state to frozen state. - * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED | 0x1 | Thawed state. I/Os behave as configured. I/Os - * : | | must be configured by the Scan Manager before - * : | | entering this state. - * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN | 0x2 | Frozen state. I/O configuration is ignored. - * : | | Instead, I/Os are in tri-state mode with a weak - * : | | pull-up. Scan Manager can be used to configure - * : | | the I/Os while they are frozen. - * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED | 0x3 | Transitioning from frozen state to thawed state. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE - * - * Transitioning from thawed state to frozen state. - */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE - * - * Thawed state. I/Os behave as configured. I/Os must be configured by the Scan - * Manager before entering this state. - */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE - * - * Frozen state. I/O configuration is ignored. Instead, I/Os are in tri-state mode - * with a weak pull-up. Scan Manager can be used to configure the I/Os while they - * are frozen. - */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE - * - * Transitioning from frozen state to thawed state. - */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2 -/* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006 -/* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9 -/* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2 -/* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE field value from a register. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET(value) (((value) & 0x00000006) >> 1) -/* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value suitable for setting the register. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET(value) (((value) << 1) & 0x00000006) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_FRZCTL_HWCTL. - */ -struct ALT_SYSMGR_FRZCTL_HWCTL_s -{ - uint32_t vio1req : 1; /* VIO channel 1 Freeze/Thaw request */ - const uint32_t vio1state : 2; /* VIO channel 1 State */ - uint32_t : 29; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_FRZCTL_HWCTL. */ -typedef volatile struct ALT_SYSMGR_FRZCTL_HWCTL_s ALT_SYSMGR_FRZCTL_HWCTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_FRZCTL_HWCTL register from the beginning of the component. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_FRZCTL. - */ -struct ALT_SYSMGR_FRZCTL_s -{ - volatile ALT_SYSMGR_FRZCTL_VIOCTL_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */ - volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ - volatile ALT_SYSMGR_FRZCTL_HIOCTL_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */ - volatile ALT_SYSMGR_FRZCTL_SRC_t src; /* ALT_SYSMGR_FRZCTL_SRC */ - volatile ALT_SYSMGR_FRZCTL_HWCTL_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */ - volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_FRZCTL. */ -typedef volatile struct ALT_SYSMGR_FRZCTL_s ALT_SYSMGR_FRZCTL_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */ -struct ALT_SYSMGR_FRZCTL_raw_s -{ - volatile uint32_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */ - volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */ - volatile uint32_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */ - volatile uint32_t src; /* ALT_SYSMGR_FRZCTL_SRC */ - volatile uint32_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */ - volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */ -typedef volatile struct ALT_SYSMGR_FRZCTL_raw_s ALT_SYSMGR_FRZCTL_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : EMAC Group - ALT_SYSMGR_EMAC - * EMAC Group - * - * External control registers for the EMACs - * - */ -/* - * Register : Control Register - ctrl - * - * Registers used by the EMACs. All fields are reset by a cold or warm reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------- - * [1:0] | RW | 0x2 | PHY Interface Select - * [3:2] | RW | 0x2 | PHY Interface Select - * [4] | RW | 0x0 | PTP Clock Select - * [5] | RW | 0x0 | PTP Clock Select - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : PHY Interface Select - physel_0 - * - * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC - * module when it exits from reset. The associated enum defines the allowed values. - * The field array index corresponds to the EMAC index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:------------------------------ - * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII | 0x0 | Select GMII/MII PHY interface - * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII | 0x1 | Select RGMII PHY interface - * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII | 0x2 | Select RMII PHY interface - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 - * - * Select GMII/MII PHY interface - */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 - * - * Select RGMII PHY interface - */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0 - * - * Select RMII PHY interface - */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1 -/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2 -/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 field value from a register. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : PHY Interface Select - physel_1 - * - * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC - * module when it exits from reset. The associated enum defines the allowed values. - * The field array index corresponds to the EMAC index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:------------------------------ - * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII | 0x0 | Select GMII/MII PHY interface - * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII | 0x1 | Select RGMII PHY interface - * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII | 0x2 | Select RMII PHY interface - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 - * - * Select GMII/MII PHY interface - */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 - * - * Select RGMII PHY interface - */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1 - * - * Select RMII PHY interface - */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3 -/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c -/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3 -/* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2 -/* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 field value from a register. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET(value) (((value) & 0x0000000c) >> 2) -/* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET(value) (((value) << 2) & 0x0000000c) - -/* - * Field : PTP Clock Select - ptpclksel_0 - * - * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC - * module when it exits from reset. The field array index corresponds to the EMAC - * index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------------|:------|:------------------------- - * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK | 0x0 | Selects osc1_clk - * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 - * - * Selects osc1_clk - */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 - * - * Selects fpga_ptp_ref_clk - */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4 -/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 field value from a register. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : PTP Clock Select - ptpclksel_1 - * - * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC - * module when it exits from reset. The field array index corresponds to the EMAC - * index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------------------------|:------|:------------------------- - * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK | 0x0 | Selects osc1_clk - * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 - * - * Selects osc1_clk - */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 - * - * Selects fpga_ptp_ref_clk - */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5 -/* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020 -/* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf -/* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 field value from a register. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET(value) (((value) << 5) & 0x00000020) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_EMAC_CTL. - */ -struct ALT_SYSMGR_EMAC_CTL_s -{ - uint32_t physel_0 : 2; /* PHY Interface Select */ - uint32_t physel_1 : 2; /* PHY Interface Select */ - uint32_t ptpclksel_0 : 1; /* PTP Clock Select */ - uint32_t ptpclksel_1 : 1; /* PTP Clock Select */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_EMAC_CTL. */ -typedef volatile struct ALT_SYSMGR_EMAC_CTL_s ALT_SYSMGR_EMAC_CTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_EMAC_CTL register from the beginning of the component. */ -#define ALT_SYSMGR_EMAC_CTL_OFST 0x0 - -/* - * Register : EMAC L3 Master AxCACHE Register - l3master - * - * Controls the L3 master ARCACHE and AWCACHE AXI signals. - * - * These register bits should be updated only during system initialization prior to - * removing the peripheral from reset. They may not be changed dynamically during - * peripheral operation - * - * All fields are reset by a cold or warm reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------- - * [3:0] | RW | 0x0 | EMAC ARCACHE - * [7:4] | RW | 0x0 | EMAC ARCACHE - * [11:8] | RW | 0x0 | EMAC AWCACHE - * [15:12] | RW | 0x0 | EMAC AWCACHE - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : EMAC ARCACHE - arcache_0 - * - * Specifies the values of the 2 EMAC ARCACHE signals. - * - * The field array index corresponds to the EMAC index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes - * : | | only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads - * : | | and writes. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and - * : | | writes. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Noncacheable and nonbufferable. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Bufferable only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Cacheable, but do not allocate. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Cacheable and bufferable, but do not allocate. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 0x4 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 0x5 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Cacheable write-through, allocate on reads only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Cacheable write-back, allocate on reads only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 0x8 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 0x9 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Cacheable write-through, allocate on writes only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Cacheable write-back, allocate on writes only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 0xc -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 0xd -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Cacheable write-through, allocate on both reads and writes. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 - * - * Cacheable write-back, allocate on both reads and writes. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB 3 -/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH 4 -/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK 0x0000000f -/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 field value from a register. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f) - -/* - * Field : EMAC ARCACHE - arcache_1 - * - * Specifies the values of the 2 EMAC ARCACHE signals. - * - * The field array index corresponds to the EMAC index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF | 0x1 | Bufferable only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 | 0x4 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 | 0x5 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 | 0x8 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 | 0x9 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes - * : | | only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 | 0xc | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 | 0xd | Reserved. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads - * : | | and writes. - * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and - * : | | writes. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Noncacheable and nonbufferable. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Bufferable only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Cacheable, but do not allocate. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Cacheable and bufferable, but do not allocate. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 0x4 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 0x5 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Cacheable write-through, allocate on reads only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Cacheable write-back, allocate on reads only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 0x8 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 0x9 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Cacheable write-through, allocate on writes only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Cacheable write-back, allocate on writes only. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 0xc -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 0xd -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Cacheable write-through, allocate on both reads and writes. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 - * - * Cacheable write-back, allocate on both reads and writes. - */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC 0xf - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB 7 -/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH 4 -/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK 0x000000f0 -/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK 0xffffff0f -/* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 field value from a register. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET(value) (((value) & 0x000000f0) >> 4) -/* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(value) (((value) << 4) & 0x000000f0) - -/* - * Field : EMAC AWCACHE - awcache_0 - * - * Specifies the values of the 2 EMAC AWCACHE signals. - * - * The field array index corresponds to the EMAC index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes - * : | | only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads - * : | | and writes. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and - * : | | writes. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Noncacheable and nonbufferable. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Bufferable only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Cacheable, but do not allocate. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Cacheable and bufferable, but do not allocate. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 0x4 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 0x5 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Cacheable write-through, allocate on reads only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Cacheable write-back, allocate on reads only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 0x8 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 0x9 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Cacheable write-through, allocate on writes only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Cacheable write-back, allocate on writes only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 0xc -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 0xd -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Cacheable write-through, allocate on both reads and writes. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 - * - * Cacheable write-back, allocate on both reads and writes. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB 11 -/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH 4 -/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK 0x00000f00 -/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK 0xfffff0ff -/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 field value from a register. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET(value) (((value) & 0x00000f00) >> 8) -/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET(value) (((value) << 8) & 0x00000f00) - -/* - * Field : EMAC AWCACHE - awcache_1 - * - * Specifies the values of the 2 EMAC AWCACHE signals. - * - * The field array index corresponds to the EMAC index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF | 0x1 | Bufferable only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 | 0x4 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 | 0x5 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 | 0x8 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 | 0x9 | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes - * : | | only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 | 0xc | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 | 0xd | Reserved. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads - * : | | and writes. - * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and - * : | | writes. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Noncacheable and nonbufferable. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Bufferable only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Cacheable, but do not allocate. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Cacheable and bufferable, but do not allocate. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 0x4 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 0x5 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Cacheable write-through, allocate on reads only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Cacheable write-back, allocate on reads only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 0x8 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 0x9 -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Cacheable write-through, allocate on writes only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Cacheable write-back, allocate on writes only. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 0xc -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Reserved. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 0xd -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Cacheable write-through, allocate on both reads and writes. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe -/* - * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 - * - * Cacheable write-back, allocate on both reads and writes. - */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC 0xf - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB 15 -/* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH 4 -/* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK 0x0000f000 -/* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK 0xffff0fff -/* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 field value from a register. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET(value) (((value) & 0x0000f000) >> 12) -/* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(value) (((value) << 12) & 0x0000f000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_EMAC_L3MST. - */ -struct ALT_SYSMGR_EMAC_L3MST_s -{ - uint32_t arcache_0 : 4; /* EMAC ARCACHE */ - uint32_t arcache_1 : 4; /* EMAC ARCACHE */ - uint32_t awcache_0 : 4; /* EMAC AWCACHE */ - uint32_t awcache_1 : 4; /* EMAC AWCACHE */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_EMAC_L3MST. */ -typedef volatile struct ALT_SYSMGR_EMAC_L3MST_s ALT_SYSMGR_EMAC_L3MST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_EMAC_L3MST register from the beginning of the component. */ -#define ALT_SYSMGR_EMAC_L3MST_OFST 0x4 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_EMAC. - */ -struct ALT_SYSMGR_EMAC_s -{ - volatile ALT_SYSMGR_EMAC_CTL_t ctrl; /* ALT_SYSMGR_EMAC_CTL */ - volatile ALT_SYSMGR_EMAC_L3MST_t l3master; /* ALT_SYSMGR_EMAC_L3MST */ - volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_EMAC. */ -typedef volatile struct ALT_SYSMGR_EMAC_s ALT_SYSMGR_EMAC_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */ -struct ALT_SYSMGR_EMAC_raw_s -{ - volatile uint32_t ctrl; /* ALT_SYSMGR_EMAC_CTL */ - volatile uint32_t l3master; /* ALT_SYSMGR_EMAC_L3MST */ - volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */ -typedef volatile struct ALT_SYSMGR_EMAC_raw_s ALT_SYSMGR_EMAC_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : DMA Controller Group - ALT_SYSMGR_DMA - * DMA Controller Group - * - * Registers used by the DMA Controller to enable secured system support and select - * DMA channels. - * - */ -/* - * Register : Control Register - ctrl - * - * Registers used by the DMA Controller. All fields are reset by a cold or warm - * reset. - * - * These register bits should be updated during system initialization prior to - * removing the DMA controller from reset. They may not be changed dynamically - * during DMA operation. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------------ - * [0] | RW | 0x0 | Channel Select - * [1] | RW | 0x0 | Channel Select - * [2] | RW | 0x0 | Channel Select - * [3] | RW | 0x0 | Channel Select - * [4] | RW | 0x0 | Manager Thread Security - * [12:5] | RW | 0x0 | IRQ Security - * [31:13] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Channel Select - chansel_0 - * - * Controls mux that selects whether FPGA or CAN connects to one of the DMA - * peripheral request interfaces.The peripheral request interface index equals the - * array index + 4. For example, array index 0 is for peripheral request index 4. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:----------------------------------------- - * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA | 0x0 | FPGA drives peripheral request interface - * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN | 0x1 | CAN drives peripheral request interface - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0 - * - * FPGA drives peripheral request interface - */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0 - * - * CAN drives peripheral request interface - */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0 -/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_0 field value from a register. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Channel Select - chansel_1 - * - * Controls mux that selects whether FPGA or CAN connects to one of the DMA - * peripheral request interfaces.The peripheral request interface index equals the - * array index + 4. For example, array index 0 is for peripheral request index 4. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:----------------------------------------- - * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA | 0x0 | FPGA drives peripheral request interface - * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN | 0x1 | CAN drives peripheral request interface - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1 - * - * FPGA drives peripheral request interface - */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1 - * - * CAN drives peripheral request interface - */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1 -/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_1 field value from a register. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Channel Select - chansel_2 - * - * Controls mux that selects whether FPGA or CAN connects to one of the DMA - * peripheral request interfaces.The peripheral request interface index equals the - * array index + 4. For example, array index 0 is for peripheral request index 4. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:----------------------------------------- - * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA | 0x0 | FPGA drives peripheral request interface - * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN | 0x1 | CAN drives peripheral request interface - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2 - * - * FPGA drives peripheral request interface - */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2 - * - * CAN drives peripheral request interface - */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2 -/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0 -/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_2 field value from a register. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value suitable for setting the register. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Channel Select - chansel_3 - * - * Controls mux that selects whether FPGA or CAN connects to one of the DMA - * peripheral request interfaces.The peripheral request interface index equals the - * array index + 4. For example, array index 0 is for peripheral request index 4. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------|:------|:----------------------------------------- - * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA | 0x0 | FPGA drives peripheral request interface - * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN | 0x1 | CAN drives peripheral request interface - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3 - * - * FPGA drives peripheral request interface - */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3 - * - * CAN drives peripheral request interface - */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3 -/* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0 -/* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_3 field value from a register. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value suitable for setting the register. */ -#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Manager Thread Security - mgrnonsecure - * - * Specifies the security state of the DMA manager thread. - * - * 0 = assigns DMA manager to the Secure state. - * - * 1 = assigns DMA manager to the Non-secure state. - * - * Sampled by the DMA controller when it exits from reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ -#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ -#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4 -/* The width in bits of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ -#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */ -#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */ -#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */ -#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0 -/* Extracts the ALT_SYSMGR_DMA_CTL_MGRNONSECURE field value from a register. */ -#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value suitable for setting the register. */ -#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : IRQ Security - irqnonsecure - * - * Specifies the security state of an event-interrupt resource. - * - * If bit index [x] is 0, the DMAC assigns event<x> or irq[x] to the Secure state. - * - * If bit index [x] is 1, the DMAC assigns event<x> or irq[x] to the Non-secure - * state. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ -#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ -#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12 -/* The width in bits of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ -#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8 -/* The mask used to set the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */ -#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0 -/* The mask used to clear the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */ -#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f -/* The reset value of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */ -#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0 -/* Extracts the ALT_SYSMGR_DMA_CTL_IRQNONSECURE field value from a register. */ -#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET(value) (((value) & 0x00001fe0) >> 5) -/* Produces a ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value suitable for setting the register. */ -#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET(value) (((value) << 5) & 0x00001fe0) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_DMA_CTL. - */ -struct ALT_SYSMGR_DMA_CTL_s -{ - uint32_t chansel_0 : 1; /* Channel Select */ - uint32_t chansel_1 : 1; /* Channel Select */ - uint32_t chansel_2 : 1; /* Channel Select */ - uint32_t chansel_3 : 1; /* Channel Select */ - uint32_t mgrnonsecure : 1; /* Manager Thread Security */ - uint32_t irqnonsecure : 8; /* IRQ Security */ - uint32_t : 19; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_DMA_CTL. */ -typedef volatile struct ALT_SYSMGR_DMA_CTL_s ALT_SYSMGR_DMA_CTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_DMA_CTL register from the beginning of the component. */ -#define ALT_SYSMGR_DMA_CTL_OFST 0x0 - -/* - * Register : Peripheral Security Register - persecurity - * - * Controls the security state of a peripheral request interface. Sampled by the - * DMA controller when it exits from reset. - * - * These register bits should be updated during system initialization prior to - * removing the DMA controller from reset. They may not be changed dynamically - * during DMA operation. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------- - * [31:0] | RW | 0x0 | Peripheral Non-Secure - * - */ -/* - * Field : Peripheral Non-Secure - nonsecure - * - * If bit index [x] is 0, the DMA controller assigns peripheral request interface x - * to the Secure state. - * - * If bit index [x] is 1, the DMA controller assigns peripheral request interface x - * to the Non-secure state. - * - * Reset by a cold or warm reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ -#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ -#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_MSB 31 -/* The width in bits of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ -#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_WIDTH 32 -/* The mask used to set the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */ -#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */ -#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_CLR_MSK 0x00000000 -/* The reset value of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */ -#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_RESET 0x0 -/* Extracts the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE field value from a register. */ -#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value suitable for setting the register. */ -#define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_DMA_PERSECURITY. - */ -struct ALT_SYSMGR_DMA_PERSECURITY_s -{ - uint32_t nonsecure : 32; /* Peripheral Non-Secure */ -}; - -/* The typedef declaration for register ALT_SYSMGR_DMA_PERSECURITY. */ -typedef volatile struct ALT_SYSMGR_DMA_PERSECURITY_s ALT_SYSMGR_DMA_PERSECURITY_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_DMA_PERSECURITY register from the beginning of the component. */ -#define ALT_SYSMGR_DMA_PERSECURITY_OFST 0x4 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_DMA. - */ -struct ALT_SYSMGR_DMA_s -{ - volatile ALT_SYSMGR_DMA_CTL_t ctrl; /* ALT_SYSMGR_DMA_CTL */ - volatile ALT_SYSMGR_DMA_PERSECURITY_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_DMA. */ -typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_DMA. */ -struct ALT_SYSMGR_DMA_raw_s -{ - volatile uint32_t ctrl; /* ALT_SYSMGR_DMA_CTL */ - volatile uint32_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_DMA. */ -typedef volatile struct ALT_SYSMGR_DMA_raw_s ALT_SYSMGR_DMA_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Preloader (initial software) Group - ALT_SYSMGR_ISW - * Preloader (initial software) Group - * - * Registers used by preloader code and the OS. - * - * All registers are only reset by a cold reset (ignore warm reset). - * - */ -/* - * Register : Preloader to OS Handoff Information - handoff - * - * These registers are used to store handoff infomation between the preloader and - * the OS. These 8 registers can be used to store any information. The contents of - * these registers have no impact on the state of the HPS hardware. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [31:0] | RW | 0x0 | Preloader Handoff Information - * - */ -/* - * Field : Preloader Handoff Information - value - * - * Preloader Handoff Information. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ -#define ALT_SYSMGR_ISW_HANDOFF_VALUE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ -#define ALT_SYSMGR_ISW_HANDOFF_VALUE_MSB 31 -/* The width in bits of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ -#define ALT_SYSMGR_ISW_HANDOFF_VALUE_WIDTH 32 -/* The mask used to set the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */ -#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */ -#define ALT_SYSMGR_ISW_HANDOFF_VALUE_CLR_MSK 0x00000000 -/* The reset value of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */ -#define ALT_SYSMGR_ISW_HANDOFF_VALUE_RESET 0x0 -/* Extracts the ALT_SYSMGR_ISW_HANDOFF_VALUE field value from a register. */ -#define ALT_SYSMGR_ISW_HANDOFF_VALUE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SYSMGR_ISW_HANDOFF_VALUE register field value suitable for setting the register. */ -#define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ISW_HANDOFF. - */ -struct ALT_SYSMGR_ISW_HANDOFF_s -{ - uint32_t value : 32; /* Preloader Handoff Information */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ISW_HANDOFF. */ -typedef volatile struct ALT_SYSMGR_ISW_HANDOFF_s ALT_SYSMGR_ISW_HANDOFF_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ISW_HANDOFF register from the beginning of the component. */ -#define ALT_SYSMGR_ISW_HANDOFF_OFST 0x0 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_ISW. - */ -struct ALT_SYSMGR_ISW_s -{ - volatile ALT_SYSMGR_ISW_HANDOFF_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_ISW. */ -typedef volatile struct ALT_SYSMGR_ISW_s ALT_SYSMGR_ISW_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ISW. */ -struct ALT_SYSMGR_ISW_raw_s -{ - volatile uint32_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ISW. */ -typedef volatile struct ALT_SYSMGR_ISW_raw_s ALT_SYSMGR_ISW_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Boot ROM Code Register Group - ALT_SYSMGR_ROMCODE - * Boot ROM Code Register Group - * - * Registers used by the Boot ROM code. All fields are only reset by a cold reset - * (ignore warm reset). - * - */ -/* - * Register : Control Register - ctrl - * - * Contains information used to control Boot ROM code. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------------- - * [0] | RW | 0x0 | Warm Reset Configure Pin Mux for Boot Pins - * [1] | RW | 0x0 | Warm Reset Configure IOs for Boot Pins - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Warm Reset Configure Pin Mux for Boot Pins - warmrstcfgpinmux - * - * Specifies whether the Boot ROM code configures the pin mux for boot pins after a - * warm reset. Note that the Boot ROM code always configures the pin mux for boot - * pins after a cold reset. After the Boot ROM code configures the pin mux for boot - * pins, it always disables this field. It is up to user software to enable this - * field if it wants a different behavior. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------------|:------|:---------------------------------------------- - * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD | 0x0 | Boot ROM code will not configure pin mux for - * : | | boot pins after a warm reset - * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END | 0x1 | Boot ROM code will configure pin mux for boot - * : | | pins after a warm reset - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX - * - * Boot ROM code will not configure pin mux for boot pins after a warm reset - */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX - * - * Boot ROM code will configure pin mux for boot pins after a warm reset - */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0 -/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX field value from a register. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Warm Reset Configure IOs for Boot Pins - warmrstcfgio - * - * Specifies whether the Boot ROM code configures the IOs used by boot after a warm - * reset. Note that the Boot ROM code always configures the IOs used by boot after - * a cold reset. After the Boot ROM code configures the IOs used by boot, it always - * disables this field. It is up to user software to enable this field if it wants - * a different behavior. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:------|:---------------------------------------------- - * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD | 0x0 | Boot ROM code will not configure IOs used by - * : | | boot after a warm reset - * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END | 0x1 | Boot ROM code will configure IOs used by boot - * : | | after a warm reset - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO - * - * Boot ROM code will not configure IOs used by boot after a warm reset - */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO - * - * Boot ROM code will configure IOs used by boot after a warm reset - */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_MSB 1 -/* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO field value from a register. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_CTL. - */ -struct ALT_SYSMGR_ROMCODE_CTL_s -{ - uint32_t warmrstcfgpinmux : 1; /* Warm Reset Configure Pin Mux for Boot Pins */ - uint32_t warmrstcfgio : 1; /* Warm Reset Configure IOs for Boot Pins */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CTL. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_CTL_s ALT_SYSMGR_ROMCODE_CTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_CTL register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_CTL_OFST 0x0 - -/* - * Register : CPU1 Start Address Register - cpu1startaddr - * - * When CPU1 is released from reset and the Boot ROM is located at the CPU1 reset - * exception address (the typical case), the Boot ROM reset handler code reads the - * address stored in this register and jumps it to hand off execution to user - * software. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [31:0] | RW | 0x0 | Address - * - */ -/* - * Field : Address - value - * - * Address for CPU1 to start executing at after coming out of reset. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB 31 -/* The width in bits of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH 32 -/* The mask used to set the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK 0x00000000 -/* The reset value of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE field value from a register. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. - */ -struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s -{ - uint32_t value : 32; /* Address */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST 0x4 - -/* - * Register : Preloader (initial software) State Register - initswstate - * - * The preloader software (loaded by the Boot ROM) writes the magic value - * 0x49535756 (ISWV in ASCII) to this register when it has reached a valid state. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [31:0] | RW | 0x0 | Value - * - */ -/* - * Field : Value - value - * - * Written with magic value. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------------|:-----------|:------------ - * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID | 0x0 | - * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID | 0x49535756 | - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE - * - */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE - * - */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_MSB 31 -/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_WIDTH 32 -/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000 -/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE field value from a register. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. - */ -struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s -{ - uint32_t value : 32; /* Value */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s ALT_SYSMGR_ROMCODE_INITSWSTATE_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWSTATE register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST 0x8 - -/* - * Register : Preloader (initial software) Last Image Loaded Register - initswlastld - * - * Contains the index of the last preloader software image loaded by the Boot ROM - * from the boot device. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [1:0] | RW | 0x0 | Index - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Index - index - * - * Index of last image loaded. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_MSB 1 -/* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX field value from a register. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. - */ -struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s -{ - uint32_t index : 2; /* Index */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s ALT_SYSMGR_ROMCODE_INITSWLASTLD_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST 0xc - -/* - * Register : Boot ROM Software State Register - bootromswstate - * - * 32-bits general purpose register used by the Boot ROM code. Actual usage is - * defined in the Boot ROM source code. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------ - * [31:0] | RW | 0x0 | Boot ROM Software State - * - */ -/* - * Field : Boot ROM Software State - value - * - * Reserved for Boot ROM use. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31 -/* The width in bits of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32 -/* The mask used to set the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000 -/* The reset value of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE field value from a register. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. - */ -struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s -{ - uint32_t value : 32; /* Boot ROM Software State */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST 0x10 - -/* - * Register Group : Warm Boot from On-Chip RAM Group - ALT_SYSMGR_ROMCODE_WARMRAM - * Warm Boot from On-Chip RAM Group - * - * Registers used by the Boot ROM code to support booting from the On-chip RAM on a - * warm reset. All these registers must be written by user software before a warm - * reset occurs to make use of this feature. - * - */ -/* - * Register : Enable Register - enable - * - * Enables or disables the warm reset from On-chip RAM feature. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [31:0] | RW | 0x0 | Warm Reset from On-chip RAM - * - */ -/* - * Field : Warm Reset from On-chip RAM - magic - * - * Controls whether Boot ROM will attempt to boot from the contents of the On-chip - * RAM on a warm reset. When this feature is enabled, the Boot ROM code will not - * configure boot IOs, the pin mux, or clocks. - * - * Note that the enable value is a 32-bit magic value (provided by the enum). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------|:-----------|:------------------------------------------------ - * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD | 0x0 | Boot ROM code will not attempt to boot from On- - * : | | chip RAM on a warm reset - * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END | 0xae9efebc | Boot ROM code will attempt to boot from On-chip - * : | | RAM on a warm reset - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC - * - * Boot ROM code will not attempt to boot from On-chip RAM on a warm reset - */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC - * - * Boot ROM code will attempt to boot from On-chip RAM on a warm reset - */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END 0xae9efebc - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_MSB 31 -/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_WIDTH 32 -/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000 -/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC field value from a register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. - */ -struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s -{ - uint32_t magic : 32; /* Warm Reset from On-chip RAM */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s ALT_SYSMGR_ROMCODE_WARMRAM_EN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST 0x0 -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST)) - -/* - * Register : Data Start Register - datastart - * - * Offset into On-chip RAM of the start of the region for CRC validation - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------------ - * [15:0] | RW | 0x0 | Data Start Offset - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Data Start Offset - offset - * - * Contains the byte offset into the On-chip RAM of the start of the On-chip RAM - * region for the warm boot CRC validation. The offset must be an integer multiple - * of 4 (i.e. aligned to a word). The Boot ROM code will set the top 16 bits to - * 0xFFFF and clear the bottom 2 bits. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_MSB 15 -/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_WIDTH 16 -/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_CLR_MSK 0xffff0000 -/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET field value from a register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0x0000ffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. - */ -struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s -{ - uint32_t offset : 16; /* Data Start Offset */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST 0x4 -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST)) - -/* - * Register : Length Register - length - * - * Length of region in On-chip RAM for CRC validation. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:------------ - * [15:0] | RW | 0x0 | Size - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Size - size - * - * Contains the length (in bytes) of the region in the On-chip RAM for the warm - * boot CRC validation. - * - * If the length is 0, the Boot ROM won't perform CRC calculation and CRC check to - * avoid overhead caused by CRC validation. - * - * If the START + LENGTH exceeds the maximum offset into the On-chip RAM, the Boot - * ROM won't boot from the On-chip RAM. - * - * The length must be an integer multiple of 4. - * - * The Boot ROM code will clear the top 16 bits and the bottom 2 bits. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_MSB 15 -/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_WIDTH 16 -/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_CLR_MSK 0xffff0000 -/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE field value from a register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0x0000ffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. - */ -struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s -{ - uint32_t size : 16; /* Size */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST 0x8 -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST)) - -/* - * Register : Execution Register - execution - * - * Offset into On-chip RAM to enter to on a warm boot. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:----------------- - * [15:0] | RW | 0x0 | Execution Offset - * [31:16] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Execution Offset - offset - * - * Contains the byte offset into the On-chip RAM that the Boot ROM will jump to if - * the CRC validation succeeds. - * - * The Boot ROM code will set the top 16 bits to 0xFFFF. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_MSB 15 -/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_WIDTH 16 -/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET_MSK 0x0000ffff -/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0xffff0000 -/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET field value from a register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0x0000ffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. - */ -struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s -{ - uint32_t offset : 16; /* Execution Offset */ - uint32_t : 16; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST 0xc -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST)) - -/* - * Register : Expected CRC Register - crc - * - * Length of region in On-chip RAM for CRC validation. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:-----------|:------------- - * [31:0] | RW | 0xe763552a | Expected CRC - * - */ -/* - * Field : Expected CRC - expected - * - * Contains the expected CRC of the region in the On-chip RAM.The Boot ROM code - * calculates the actual CRC for all bytes in the region specified by the DATA - * START an LENGTH registers. The contents of the EXECUTION register (after it has - * been read and modified by the Boot ROM code) is also included in the CRC - * calculation. The contents of the EXECUTION register is added to the CRC - * accumulator a byte at a time starting with the least significant byte. If the - * actual CRC doesn't match the expected CRC value in this register, the Boot ROM - * won't boot from the On-chip RAM. - * - * The CRC is a standard CRC32 with the polynomial: - * - * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + - * x^2 + x + 1 - * - * There is no reflection of the bits and the initial value of the remainder is - * 0xFFFFFFFF and the final value is exclusive ORed with 0xFFFFFFFF. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_MSB 31 -/* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_WIDTH 32 -/* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff -/* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000 -/* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_RESET 0xe763552a -/* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED field value from a register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. - */ -struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s -{ - uint32_t expected : 32; /* Expected CRC */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register from the beginning of the component. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST 0x10 -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register. */ -#define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. - */ -struct ALT_SYSMGR_ROMCODE_WARMRAM_s -{ - volatile ALT_SYSMGR_ROMCODE_WARMRAM_EN_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */ - volatile ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */ - volatile ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */ - volatile ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */ - volatile ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */ - volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_s ALT_SYSMGR_ROMCODE_WARMRAM_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */ -struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s -{ - volatile uint32_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */ - volatile uint32_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */ - volatile uint32_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */ - volatile uint32_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */ - volatile uint32_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */ - volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s ALT_SYSMGR_ROMCODE_WARMRAM_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_ROMCODE. - */ -struct ALT_SYSMGR_ROMCODE_s -{ - volatile ALT_SYSMGR_ROMCODE_CTL_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */ - volatile ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */ - volatile ALT_SYSMGR_ROMCODE_INITSWSTATE_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */ - volatile ALT_SYSMGR_ROMCODE_INITSWLASTLD_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */ - volatile ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */ - volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_ROMCODE_WARMRAM_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_ROMCODE. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_s ALT_SYSMGR_ROMCODE_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */ -struct ALT_SYSMGR_ROMCODE_raw_s -{ - volatile uint32_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */ - volatile uint32_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */ - volatile uint32_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */ - volatile uint32_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */ - volatile uint32_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */ - volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_ROMCODE_WARMRAM_raw_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */ -typedef volatile struct ALT_SYSMGR_ROMCODE_raw_s ALT_SYSMGR_ROMCODE_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Boot ROM Hardware Register Group - ALT_SYSMGR_ROMHW - * Boot ROM Hardware Register Group - * - * Registers used by the Boot ROM hardware, not the code within it. - * - */ -/* - * Register : Boot ROM Hardware Control Register - ctrl - * - * Controls behavior of Boot ROM hardware. - * - * All fields are only reset by a cold reset (ignore warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------------- - * [0] | RW | 0x0 | Wait State - * [1] | RW | 0x1 | Enable Safe Mode Warm Reset Update - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Wait State - waitstate - * - * Controls the number of wait states applied to the Boot ROM's read operation. - * - * This field is cleared on a cold reset and optionally updated by hardware upon - * deassertion of warm reset. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS | 0x0 | No wait states are applied to the Boom ROM's - * : | | read operation. - * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN | 0x1 | A single wait state is applied to the Boot ROM's - * : | | read operation. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE - * - * No wait states are applied to the Boom ROM's read operation. - */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE - * - * A single wait state is applied to the Boot ROM's read operation. - */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0 -/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0 -/* Extracts the ALT_SYSMGR_ROMHW_CTL_WAITSTATE field value from a register. */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Enable Safe Mode Warm Reset Update - ensfmdwru - * - * Controls whether the wait state bit is updated upon deassertion of warm reset. - * - * This field is set on a cold reset. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:----------------------------------------------- - * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS | 0x0 | Wait state bit is not updated upon deassertion - * : | | of warm reset. - * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN | 0x1 | Wait state bit is updated upon deassertion of - * : | | warm reset. It's value is updated based on the - * : | | control bit from clock manager which specifies - * : | | whether clock manager will be in safe mode or - * : | | not after warm reset. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU - * - * Wait state bit is not updated upon deassertion of warm reset. - */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU - * - * Wait state bit is updated upon deassertion of warm reset. - * - * It's value is updated based on the control bit from clock manager which - * specifies whether clock manager will be in safe mode or not after warm reset. - */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1 -/* The width in bits of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1 -/* Extracts the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU field value from a register. */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value suitable for setting the register. */ -#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET(value) (((value) << 1) & 0x00000002) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ROMHW_CTL. - */ -struct ALT_SYSMGR_ROMHW_CTL_s -{ - uint32_t waitstate : 1; /* Wait State */ - uint32_t ensfmdwru : 1; /* Enable Safe Mode Warm Reset Update */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ROMHW_CTL. */ -typedef volatile struct ALT_SYSMGR_ROMHW_CTL_s ALT_SYSMGR_ROMHW_CTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ROMHW_CTL register from the beginning of the component. */ -#define ALT_SYSMGR_ROMHW_CTL_OFST 0x0 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_ROMHW. - */ -struct ALT_SYSMGR_ROMHW_s -{ - volatile ALT_SYSMGR_ROMHW_CTL_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_ROMHW. */ -typedef volatile struct ALT_SYSMGR_ROMHW_s ALT_SYSMGR_ROMHW_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */ -struct ALT_SYSMGR_ROMHW_raw_s -{ - volatile uint32_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */ -typedef volatile struct ALT_SYSMGR_ROMHW_raw_s ALT_SYSMGR_ROMHW_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : SDMMC Controller Group - ALT_SYSMGR_SDMMC - * SDMMC Controller Group - * - * Registers related to SDMMC Controller which aren't located inside the SDMMC - * itself. - * - */ -/* - * Register : Control Register - ctrl - * - * Registers used by the SDMMC Controller. All fields are reset by a cold or warm - * reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [2:0] | RW | 0x0 | Drive Clock Phase Shift Select - * [5:3] | RW | 0x0 | Sample Clock Phase Shift Select - * [6] | RW | 0x0 | Feedback Clock Select - * [31:7] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Drive Clock Phase Shift Select - drvsel - * - * Select which phase shift of the clock for cclk_in_drv. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------------|:------|:-------------------------------------------- - * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL - * - * 0 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL - * - * 45 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL - * - * 90 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL - * - * 135 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 0x3 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL - * - * 180 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 0x4 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL - * - * 225 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 0x5 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL - * - * 270 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 0x6 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL - * - * 315 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB 2 -/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH 3 -/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK 0x00000007 -/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK 0xfffffff8 -/* The reset value of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_SDMMC_CTL_DRVSEL field value from a register. */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET(value) (((value) & 0x00000007) >> 0) -/* Produces a ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET(value) (((value) << 0) & 0x00000007) - -/* - * Field : Sample Clock Phase Shift Select - smplsel - * - * Select which phase shift of the clock for cclk_in_sample. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:-------------------------------------------- - * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected - * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL - * - * 0 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL - * - * 45 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL - * - * 90 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL - * - * 135 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 0x3 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL - * - * 180 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 0x4 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL - * - * 225 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 0x5 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL - * - * 270 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 0x6 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL - * - * 315 degrees phase shifted clock is selected - */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 0x7 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB 5 -/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH 3 -/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK 0x00000038 -/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK 0xffffffc7 -/* The reset value of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_SDMMC_CTL_SMPLSEL field value from a register. */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET(value) (((value) & 0x00000038) >> 3) -/* Produces a ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET(value) (((value) << 3) & 0x00000038) - -/* - * Field : Feedback Clock Select - fbclksel - * - * Select which fb_clk to be used as cclk_in_sample. - * - * If 0, cclk_in_sample is driven by internal phase shifted cclk_in. - * - * If 1, cclk_in_sample is driven by fb_clk_in. No phase shifting is provided - * internally on cclk_in_sample. - * - * Note: Using the feedback clock (setting this bit to 1) is not a supported use - * model. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB 6 -/* The width in bits of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */ -#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */ -#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */ -#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL field value from a register. */ -#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET(value) (((value) << 6) & 0x00000040) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_SDMMC_CTL. - */ -struct ALT_SYSMGR_SDMMC_CTL_s -{ - uint32_t drvsel : 3; /* Drive Clock Phase Shift Select */ - uint32_t smplsel : 3; /* Sample Clock Phase Shift Select */ - uint32_t fbclksel : 1; /* Feedback Clock Select */ - uint32_t : 25; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_SDMMC_CTL. */ -typedef volatile struct ALT_SYSMGR_SDMMC_CTL_s ALT_SYSMGR_SDMMC_CTL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_SDMMC_CTL register from the beginning of the component. */ -#define ALT_SYSMGR_SDMMC_CTL_OFST 0x0 - -/* - * Register : SD/MMC L3 Master HPROT Register - l3master - * - * Controls the L3 master HPROT AHB-Lite signal. - * - * These register bits should be updated only during system initialization prior to - * removing the peripheral from reset. They may not be changed dynamically during - * peripheral operation - * - * All fields are reset by a cold or warm reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------- - * [0] | RW | 0x1 | SD/MMC HPROT Data/Opcode - * [1] | RW | 0x1 | SD/MMC HPROT Privileged - * [2] | RW | 0x0 | SD/MMC HPROT Bufferable - * [3] | RW | 0x0 | SD/MMC HPROT Cacheable - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : SD/MMC HPROT Data/Opcode - hprotdata_0 - * - * Specifies if the L3 master access is for data or opcode for the SD/MMC module. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------------|:------|:------------- - * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch - * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 - * - * Opcode fetch - */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 - * - * Data access - */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_MSB 0 -/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_RESET 0x1 -/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 field value from a register. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : SD/MMC HPROT Privileged - hprotpriv_0 - * - * If 1, L3 master accesses for the SD/MMC module are privileged. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_MSB 1 -/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_RESET 0x1 -/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 field value from a register. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : SD/MMC HPROT Bufferable - hprotbuff_0 - * - * If 1, L3 master accesses for the SD/MMC module are bufferable. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_MSB 2 -/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 field value from a register. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : SD/MMC HPROT Cacheable - hprotcache_0 - * - * If 1, L3 master accesses for the SD/MMC module are cacheable. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_MSB 3 -/* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 field value from a register. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET(value) (((value) << 3) & 0x00000008) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_SDMMC_L3MST. - */ -struct ALT_SYSMGR_SDMMC_L3MST_s -{ - uint32_t hprotdata_0 : 1; /* SD/MMC HPROT Data/Opcode */ - uint32_t hprotpriv_0 : 1; /* SD/MMC HPROT Privileged */ - uint32_t hprotbuff_0 : 1; /* SD/MMC HPROT Bufferable */ - uint32_t hprotcache_0 : 1; /* SD/MMC HPROT Cacheable */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_SDMMC_L3MST. */ -typedef volatile struct ALT_SYSMGR_SDMMC_L3MST_s ALT_SYSMGR_SDMMC_L3MST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_SDMMC_L3MST register from the beginning of the component. */ -#define ALT_SYSMGR_SDMMC_L3MST_OFST 0x4 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_SDMMC. - */ -struct ALT_SYSMGR_SDMMC_s -{ - volatile ALT_SYSMGR_SDMMC_CTL_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */ - volatile ALT_SYSMGR_SDMMC_L3MST_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_SDMMC. */ -typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */ -struct ALT_SYSMGR_SDMMC_raw_s -{ - volatile uint32_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */ - volatile uint32_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */ -typedef volatile struct ALT_SYSMGR_SDMMC_raw_s ALT_SYSMGR_SDMMC_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : NAND Flash Controller Register Group - ALT_SYSMGR_NAND - * NAND Flash Controller Register Group - * - * Registers related to NAND Flash Controller which aren't located in the NAND - * Flash Controller itself. - * - */ -/* - * Register : Bootstrap Control Register - bootstrap - * - * Bootstrap fields sampled by NAND Flash Controller when released from reset. - * - * All fields are reset by a cold or warm reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------------- - * [0] | RW | 0x0 | Bootstrap Inhibit Initialization - * [1] | RW | 0x0 | Bootstrap 512 Byte Device - * [2] | RW | 0x0 | Bootstrap Inhibit Load Block 0 Page 0 - * [3] | RW | 0x0 | Bootstrap Two Row Address Cycles - * [31:4] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Bootstrap Inhibit Initialization - noinit - * - * If 1, inhibits NAND Flash Controller from performing initialization when coming - * out of reset. Instead, software must program all registers pertaining to device - * parameters like page size, width, etc. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0 -/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0 -/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT field value from a register. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value suitable for setting the register. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Bootstrap 512 Byte Device - page512 - * - * If 1, NAND device has a 512 byte page size. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 1 -/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0 -/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 field value from a register. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value suitable for setting the register. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Bootstrap Inhibit Load Block 0 Page 0 - noloadb0p0 - * - * If 1, inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND - * device as part of the initialization procedure. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 2 -/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0 -/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 field value from a register. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Bootstrap Two Row Address Cycles - tworowaddr - * - * If 1, NAND device requires only 2 row address cycles instead of the normal 3 row - * address cycles. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 3 -/* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0 -/* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR field value from a register. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value suitable for setting the register. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 3) & 0x00000008) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. - */ -struct ALT_SYSMGR_NAND_BOOTSTRAP_s -{ - uint32_t noinit : 1; /* Bootstrap Inhibit Initialization */ - uint32_t page512 : 1; /* Bootstrap 512 Byte Device */ - uint32_t noloadb0p0 : 1; /* Bootstrap Inhibit Load Block 0 Page 0 */ - uint32_t tworowaddr : 1; /* Bootstrap Two Row Address Cycles */ - uint32_t : 28; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. */ -typedef volatile struct ALT_SYSMGR_NAND_BOOTSTRAP_s ALT_SYSMGR_NAND_BOOTSTRAP_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_NAND_BOOTSTRAP register from the beginning of the component. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x0 - -/* - * Register : NAND L3 Master AxCACHE Register - l3master - * - * Controls the L3 master ARCACHE and AWCACHE AXI signals. - * - * These register bits should be updated only during system initialization prior to - * removing the peripheral from reset. They may not be changed dynamically during - * peripheral operation - * - * All fields are reset by a cold or warm reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------- - * [3:0] | RW | 0x0 | NAND ARCACHE - * [7:4] | RW | 0x0 | NAND AWCACHE - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : NAND ARCACHE - arcache_0 - * - * Specifies the value of the module ARCACHE signal. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes - * : | | only. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads - * : | | and writes. - * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and - * : | | writes. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Noncacheable and nonbufferable. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Bufferable only. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Cacheable, but do not allocate. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Cacheable and bufferable, but do not allocate. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Cacheable write-through, allocate on reads only. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Cacheable write-back, allocate on reads only. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Cacheable write-through, allocate on writes only. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Cacheable write-back, allocate on writes only. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Cacheable write-through, allocate on both reads and writes. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0 - * - * Cacheable write-back, allocate on both reads and writes. - */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3 -/* The width in bits of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4 -/* The mask used to set the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f -/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 field value from a register. */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f) - -/* - * Field : NAND AWCACHE - awcache_0 - * - * Specifies the value of the module AWCACHE signal. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------------------------|:------|:------------------------------------------------- - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes - * : | | only. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads - * : | | and writes. - * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and - * : | | writes. - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Noncacheable and nonbufferable. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Bufferable only. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Cacheable, but do not allocate. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Cacheable and bufferable, but do not allocate. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Cacheable write-through, allocate on reads only. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Cacheable write-back, allocate on reads only. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9 -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Cacheable write-through, allocate on writes only. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Cacheable write-back, allocate on writes only. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Reserved. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Cacheable write-through, allocate on both reads and writes. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe -/* - * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0 - * - * Cacheable write-back, allocate on both reads and writes. - */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7 -/* The width in bits of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4 -/* The mask used to set the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0 -/* The mask used to clear the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f -/* The reset value of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 field value from a register. */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4) -/* Produces a ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_NAND_L3MST. - */ -struct ALT_SYSMGR_NAND_L3MST_s -{ - uint32_t arcache_0 : 4; /* NAND ARCACHE */ - uint32_t awcache_0 : 4; /* NAND AWCACHE */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_NAND_L3MST. */ -typedef volatile struct ALT_SYSMGR_NAND_L3MST_s ALT_SYSMGR_NAND_L3MST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_NAND_L3MST register from the beginning of the component. */ -#define ALT_SYSMGR_NAND_L3MST_OFST 0x4 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_NAND. - */ -struct ALT_SYSMGR_NAND_s -{ - volatile ALT_SYSMGR_NAND_BOOTSTRAP_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */ - volatile ALT_SYSMGR_NAND_L3MST_t l3master; /* ALT_SYSMGR_NAND_L3MST */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_NAND. */ -typedef volatile struct ALT_SYSMGR_NAND_s ALT_SYSMGR_NAND_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_NAND. */ -struct ALT_SYSMGR_NAND_raw_s -{ - volatile uint32_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */ - volatile uint32_t l3master; /* ALT_SYSMGR_NAND_L3MST */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_NAND. */ -typedef volatile struct ALT_SYSMGR_NAND_raw_s ALT_SYSMGR_NAND_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : USB Controller Group - ALT_SYSMGR_USB - * USB Controller Group - * - * Registers related to USB Controllers which aren't located inside the USB - * controllers themselves. - * - */ -/* - * Register : USB L3 Master HPROT Register - l3master - * - * Controls the L3 master HPROT AHB-Lite signal. - * - * These register bits should be updated only during system initialization prior to - * removing the peripheral from reset. They may not be changed dynamically during - * peripheral operation - * - * All fields are reset by a cold or warm reset. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------- - * [0] | RW | 0x1 | USB HPROT Data/Opcode - * [1] | RW | 0x1 | USB HPROT Data/Opcode - * [2] | RW | 0x1 | USB HPROT Privileged - * [3] | RW | 0x1 | USB HPROT Privileged - * [4] | RW | 0x0 | USB HPROT Bufferable - * [5] | RW | 0x0 | USB HPROT Bufferable - * [6] | RW | 0x0 | USB HPROT Cacheable - * [7] | RW | 0x0 | USB HPROT Cacheable - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : USB HPROT Data/Opcode - hprotdata_0 - * - * Specifies if the L3 master access is for data or opcode for the USB modules. - * - * The field array index corresponds to the USB index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------- - * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch - * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0 - * - * Opcode fetch - */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0 - * - * Data access - */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_MSB 0 -/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_RESET 0x1 -/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 field value from a register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : USB HPROT Data/Opcode - hprotdata_1 - * - * Specifies if the L3 master access is for data or opcode for the USB modules. - * - * The field array index corresponds to the USB index. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------------------|:------|:------------- - * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE | 0x0 | Opcode fetch - * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA | 0x1 | Data access - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1 - * - * Opcode fetch - */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE 0x0 -/* - * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1 - * - * Data access - */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_MSB 1 -/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_RESET 0x1 -/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 field value from a register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : USB HPROT Privileged - hprotpriv_0 - * - * If 1, L3 master accesses for the USB modules are privileged. - * - * The field array index corresponds to the USB index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_MSB 2 -/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_RESET 0x1 -/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 field value from a register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : USB HPROT Privileged - hprotpriv_1 - * - * If 1, L3 master accesses for the USB modules are privileged. - * - * The field array index corresponds to the USB index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_MSB 3 -/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_RESET 0x1 -/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 field value from a register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : USB HPROT Bufferable - hprotbuff_0 - * - * If 1, L3 master accesses for the USB modules are bufferable. - * - * The field array index corresponds to the USB index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_MSB 4 -/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 field value from a register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : USB HPROT Bufferable - hprotbuff_1 - * - * If 1, L3 master accesses for the USB modules are bufferable. - * - * The field array index corresponds to the USB index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_MSB 5 -/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET_MSK 0x00000020 -/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_CLR_MSK 0xffffffdf -/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 field value from a register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : USB HPROT Cacheable - hprotcache_0 - * - * If 1, L3 master accesses for the USB modules are cacheable. - * - * The field array index corresponds to the USB index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_MSB 6 -/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_RESET 0x0 -/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 field value from a register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : USB HPROT Cacheable - hprotcache_1 - * - * If 1, L3 master accesses for the USB modules are cacheable. - * - * The field array index corresponds to the USB index. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_MSB 7 -/* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET_MSK 0x00000080 -/* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_CLR_MSK 0xffffff7f -/* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_RESET 0x0 -/* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 field value from a register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value suitable for setting the register. */ -#define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET(value) (((value) << 7) & 0x00000080) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_USB_L3MST. - */ -struct ALT_SYSMGR_USB_L3MST_s -{ - uint32_t hprotdata_0 : 1; /* USB HPROT Data/Opcode */ - uint32_t hprotdata_1 : 1; /* USB HPROT Data/Opcode */ - uint32_t hprotpriv_0 : 1; /* USB HPROT Privileged */ - uint32_t hprotpriv_1 : 1; /* USB HPROT Privileged */ - uint32_t hprotbuff_0 : 1; /* USB HPROT Bufferable */ - uint32_t hprotbuff_1 : 1; /* USB HPROT Bufferable */ - uint32_t hprotcache_0 : 1; /* USB HPROT Cacheable */ - uint32_t hprotcache_1 : 1; /* USB HPROT Cacheable */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_USB_L3MST. */ -typedef volatile struct ALT_SYSMGR_USB_L3MST_s ALT_SYSMGR_USB_L3MST_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_USB_L3MST register from the beginning of the component. */ -#define ALT_SYSMGR_USB_L3MST_OFST 0x0 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_USB. - */ -struct ALT_SYSMGR_USB_s -{ - volatile ALT_SYSMGR_USB_L3MST_t l3master; /* ALT_SYSMGR_USB_L3MST */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_USB. */ -typedef volatile struct ALT_SYSMGR_USB_s ALT_SYSMGR_USB_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_USB. */ -struct ALT_SYSMGR_USB_raw_s -{ - volatile uint32_t l3master; /* ALT_SYSMGR_USB_L3MST */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_USB. */ -typedef volatile struct ALT_SYSMGR_USB_raw_s ALT_SYSMGR_USB_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : ECC Management Register Group - ALT_SYSMGR_ECC - * ECC Management Register Group - * - * ECC error status and control for all ECC-protected HPS RAM blocks. - * - */ -/* - * Register : L2 Data RAM ECC Enable Register - l2 - * - * This register is used to enable ECC on the L2 Data RAM. ECC errors can be - * injected into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------------------------- - * [0] | RW | 0x0 | L2 Data RAM ECC Enable - * [1] | RW | 0x0 | L2 Data RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | L2 Data RAM ECC inject double bit, non-correctable error - * [31:3] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : L2 Data RAM ECC Enable - en - * - * Enable ECC for L2 Data RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */ -#define ALT_SYSMGR_ECC_L2_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */ -#define ALT_SYSMGR_ECC_L2_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_L2_EN register field. */ -#define ALT_SYSMGR_ECC_L2_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_L2_EN register field value. */ -#define ALT_SYSMGR_ECC_L2_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_L2_EN register field value. */ -#define ALT_SYSMGR_ECC_L2_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_L2_EN register field. */ -#define ALT_SYSMGR_ECC_L2_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_L2_EN field value from a register. */ -#define ALT_SYSMGR_ECC_L2_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_L2_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_L2_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : L2 Data RAM ECC inject single, correctable Error - injs - * - * Changing this bit from zero to one injects a single, correctable error into the - * L2 Data RAM. This only injects one error into the L2 Data RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */ -#define ALT_SYSMGR_ECC_L2_INJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */ -#define ALT_SYSMGR_ECC_L2_INJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_L2_INJS register field. */ -#define ALT_SYSMGR_ECC_L2_INJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_L2_INJS register field value. */ -#define ALT_SYSMGR_ECC_L2_INJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJS register field value. */ -#define ALT_SYSMGR_ECC_L2_INJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_L2_INJS register field. */ -#define ALT_SYSMGR_ECC_L2_INJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_L2_INJS field value from a register. */ -#define ALT_SYSMGR_ECC_L2_INJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_L2_INJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_L2_INJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : L2 Data RAM ECC inject double bit, non-correctable error - injd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the L2 Data RAM. This only injects one double bit error into the L2 Data RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */ -#define ALT_SYSMGR_ECC_L2_INJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */ -#define ALT_SYSMGR_ECC_L2_INJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_L2_INJD register field. */ -#define ALT_SYSMGR_ECC_L2_INJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_L2_INJD register field value. */ -#define ALT_SYSMGR_ECC_L2_INJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_L2_INJD register field value. */ -#define ALT_SYSMGR_ECC_L2_INJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_L2_INJD register field. */ -#define ALT_SYSMGR_ECC_L2_INJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_L2_INJD field value from a register. */ -#define ALT_SYSMGR_ECC_L2_INJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_L2_INJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_L2_INJD_SET(value) (((value) << 2) & 0x00000004) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_L2. - */ -struct ALT_SYSMGR_ECC_L2_s -{ - uint32_t en : 1; /* L2 Data RAM ECC Enable */ - uint32_t injs : 1; /* L2 Data RAM ECC inject single, correctable Error */ - uint32_t injd : 1; /* L2 Data RAM ECC inject double bit, non-correctable error */ - uint32_t : 29; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_L2. */ -typedef volatile struct ALT_SYSMGR_ECC_L2_s ALT_SYSMGR_ECC_L2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_L2 register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_L2_OFST 0x0 - -/* - * Register : On-chip RAM ECC Enable Register - ocram - * - * This register is used to enable ECC on the On-chip RAM. ECC errors can be - * injected into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------------------------------------- - * [0] | RW | 0x0 | On-chip RAM ECC Enable - * [1] | RW | 0x0 | On-chip RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | On-chip RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | On-chip RAM ECC single, correctable error interrupt status - * [4] | RW | 0x0 | On-chip RAM ECC double bit, non-correctable error interrupt status - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : On-chip RAM ECC Enable - en - * - * Enable ECC for On-chip RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ -#define ALT_SYSMGR_ECC_OCRAM_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ -#define ALT_SYSMGR_ECC_OCRAM_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ -#define ALT_SYSMGR_ECC_OCRAM_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_EN register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_EN register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_OCRAM_EN register field. */ -#define ALT_SYSMGR_ECC_OCRAM_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_OCRAM_EN field value from a register. */ -#define ALT_SYSMGR_ECC_OCRAM_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_OCRAM_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_OCRAM_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : On-chip RAM ECC inject single, correctable Error - injs - * - * Changing this bit from zero to one injects a single, correctable error into the - * On-chip RAM. This only injects one error into the On-chip RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ -#define ALT_SYSMGR_ECC_OCRAM_INJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ -#define ALT_SYSMGR_ECC_OCRAM_INJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ -#define ALT_SYSMGR_ECC_OCRAM_INJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_INJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */ -#define ALT_SYSMGR_ECC_OCRAM_INJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJS field value from a register. */ -#define ALT_SYSMGR_ECC_OCRAM_INJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_OCRAM_INJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_OCRAM_INJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : On-chip RAM ECC inject double bit, non-correctable error - injd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the On-chip RAM. This only injects one double bit error into the On-chip RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ -#define ALT_SYSMGR_ECC_OCRAM_INJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ -#define ALT_SYSMGR_ECC_OCRAM_INJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ -#define ALT_SYSMGR_ECC_OCRAM_INJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_INJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */ -#define ALT_SYSMGR_ECC_OCRAM_INJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_OCRAM_INJD field value from a register. */ -#define ALT_SYSMGR_ECC_OCRAM_INJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_OCRAM_INJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_OCRAM_INJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : On-chip RAM ECC single, correctable error interrupt status - serr - * - * This bit is an interrupt status bit for On-chip RAM ECC single, correctable - * error. It is set by hardware when single, correctable error occurs in On-chip - * RAM. Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ -#define ALT_SYSMGR_ECC_OCRAM_SERR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ -#define ALT_SYSMGR_ECC_OCRAM_SERR_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ -#define ALT_SYSMGR_ECC_OCRAM_SERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_SERR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */ -#define ALT_SYSMGR_ECC_OCRAM_SERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_OCRAM_SERR field value from a register. */ -#define ALT_SYSMGR_ECC_OCRAM_SERR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_OCRAM_SERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_OCRAM_SERR_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : On-chip RAM ECC double bit, non-correctable error interrupt status - derr - * - * This bit is an interrupt status bit for On-chip RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in On-chip RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ -#define ALT_SYSMGR_ECC_OCRAM_DERR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ -#define ALT_SYSMGR_ECC_OCRAM_DERR_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ -#define ALT_SYSMGR_ECC_OCRAM_DERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */ -#define ALT_SYSMGR_ECC_OCRAM_DERR_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */ -#define ALT_SYSMGR_ECC_OCRAM_DERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_OCRAM_DERR field value from a register. */ -#define ALT_SYSMGR_ECC_OCRAM_DERR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_OCRAM_DERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_OCRAM_DERR_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_OCRAM. - */ -struct ALT_SYSMGR_ECC_OCRAM_s -{ - uint32_t en : 1; /* On-chip RAM ECC Enable */ - uint32_t injs : 1; /* On-chip RAM ECC inject single, correctable Error */ - uint32_t injd : 1; /* On-chip RAM ECC inject double bit, non-correctable error */ - uint32_t serr : 1; /* On-chip RAM ECC single, correctable error interrupt status */ - uint32_t derr : 1; /* On-chip RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_OCRAM. */ -typedef volatile struct ALT_SYSMGR_ECC_OCRAM_s ALT_SYSMGR_ECC_OCRAM_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_OCRAM register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_OCRAM_OFST 0x4 - -/* - * Register : USB0 RAM ECC Enable Register - usb0 - * - * This register is used to enable ECC on the USB0 RAM. ECC errors can be injected - * into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------------------------------- - * [0] | RW | 0x0 | USB0 RAM ECC Enable - * [1] | RW | 0x0 | USB0 RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | USB0 RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | USB0 RAM ECC single, correctable error interrupt status - * [4] | RW | 0x0 | USB0 RAM ECC double bit, non-correctable error interrupt status - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : USB0 RAM ECC Enable - en - * - * Enable ECC for USB0 RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */ -#define ALT_SYSMGR_ECC_USB0_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */ -#define ALT_SYSMGR_ECC_USB0_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_USB0_EN register field. */ -#define ALT_SYSMGR_ECC_USB0_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB0_EN register field value. */ -#define ALT_SYSMGR_ECC_USB0_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_USB0_EN register field value. */ -#define ALT_SYSMGR_ECC_USB0_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_USB0_EN register field. */ -#define ALT_SYSMGR_ECC_USB0_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB0_EN field value from a register. */ -#define ALT_SYSMGR_ECC_USB0_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_USB0_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB0_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : USB0 RAM ECC inject single, correctable Error - injs - * - * Changing this bit from zero to one injects a single, correctable error into the - * USB0 RAM. This only injects one error into the USB0 RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */ -#define ALT_SYSMGR_ECC_USB0_INJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */ -#define ALT_SYSMGR_ECC_USB0_INJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJS register field. */ -#define ALT_SYSMGR_ECC_USB0_INJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJS register field value. */ -#define ALT_SYSMGR_ECC_USB0_INJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJS register field value. */ -#define ALT_SYSMGR_ECC_USB0_INJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_USB0_INJS register field. */ -#define ALT_SYSMGR_ECC_USB0_INJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB0_INJS field value from a register. */ -#define ALT_SYSMGR_ECC_USB0_INJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_USB0_INJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB0_INJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : USB0 RAM ECC inject double bit, non-correctable error - injd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the USB0 RAM. This only injects one double bit error into the USB0 RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */ -#define ALT_SYSMGR_ECC_USB0_INJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */ -#define ALT_SYSMGR_ECC_USB0_INJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_USB0_INJD register field. */ -#define ALT_SYSMGR_ECC_USB0_INJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB0_INJD register field value. */ -#define ALT_SYSMGR_ECC_USB0_INJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJD register field value. */ -#define ALT_SYSMGR_ECC_USB0_INJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_USB0_INJD register field. */ -#define ALT_SYSMGR_ECC_USB0_INJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB0_INJD field value from a register. */ -#define ALT_SYSMGR_ECC_USB0_INJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_USB0_INJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB0_INJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : USB0 RAM ECC single, correctable error interrupt status - serr - * - * This bit is an interrupt status bit for USB0 RAM ECC single, correctable error. - * It is set by hardware when single, correctable error occurs in USB0 RAM. - * Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */ -#define ALT_SYSMGR_ECC_USB0_SERR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */ -#define ALT_SYSMGR_ECC_USB0_SERR_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_USB0_SERR register field. */ -#define ALT_SYSMGR_ECC_USB0_SERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB0_SERR register field value. */ -#define ALT_SYSMGR_ECC_USB0_SERR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_USB0_SERR register field value. */ -#define ALT_SYSMGR_ECC_USB0_SERR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_USB0_SERR register field. */ -#define ALT_SYSMGR_ECC_USB0_SERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB0_SERR field value from a register. */ -#define ALT_SYSMGR_ECC_USB0_SERR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_USB0_SERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB0_SERR_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : USB0 RAM ECC double bit, non-correctable error interrupt status - derr - * - * This bit is an interrupt status bit for USB0 RAM ECC double bit, non-correctable - * error. It is set by hardware when double bit, non-correctable error occurs in - * USB0 RAM. Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */ -#define ALT_SYSMGR_ECC_USB0_DERR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */ -#define ALT_SYSMGR_ECC_USB0_DERR_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_USB0_DERR register field. */ -#define ALT_SYSMGR_ECC_USB0_DERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB0_DERR register field value. */ -#define ALT_SYSMGR_ECC_USB0_DERR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_USB0_DERR register field value. */ -#define ALT_SYSMGR_ECC_USB0_DERR_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_USB0_DERR register field. */ -#define ALT_SYSMGR_ECC_USB0_DERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB0_DERR field value from a register. */ -#define ALT_SYSMGR_ECC_USB0_DERR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_USB0_DERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB0_DERR_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_USB0. - */ -struct ALT_SYSMGR_ECC_USB0_s -{ - uint32_t en : 1; /* USB0 RAM ECC Enable */ - uint32_t injs : 1; /* USB0 RAM ECC inject single, correctable Error */ - uint32_t injd : 1; /* USB0 RAM ECC inject double bit, non-correctable error */ - uint32_t serr : 1; /* USB0 RAM ECC single, correctable error interrupt status */ - uint32_t derr : 1; /* USB0 RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_USB0. */ -typedef volatile struct ALT_SYSMGR_ECC_USB0_s ALT_SYSMGR_ECC_USB0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_USB0 register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_USB0_OFST 0x8 - -/* - * Register : USB1 RAM ECC Enable Register - usb1 - * - * This register is used to enable ECC on the USB1 RAM. ECC errors can be injected - * into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------------------------------- - * [0] | RW | 0x0 | USB1 RAM ECC Enable - * [1] | RW | 0x0 | USB1 RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | USB1 RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | USB1 RAM ECC single, correctable error interrupt status - * [4] | RW | 0x0 | USB1 RAM ECC double bit, non-correctable error interrupt status - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : USB1 RAM ECC Enable - en - * - * Enable ECC for USB1 RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */ -#define ALT_SYSMGR_ECC_USB1_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */ -#define ALT_SYSMGR_ECC_USB1_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_USB1_EN register field. */ -#define ALT_SYSMGR_ECC_USB1_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB1_EN register field value. */ -#define ALT_SYSMGR_ECC_USB1_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_USB1_EN register field value. */ -#define ALT_SYSMGR_ECC_USB1_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_USB1_EN register field. */ -#define ALT_SYSMGR_ECC_USB1_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB1_EN field value from a register. */ -#define ALT_SYSMGR_ECC_USB1_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_USB1_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB1_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : USB1 RAM ECC inject single, correctable Error - injs - * - * Changing this bit from zero to one injects a single, correctable error into the - * USB1 RAM. This only injects one error into the USB1 RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */ -#define ALT_SYSMGR_ECC_USB1_INJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */ -#define ALT_SYSMGR_ECC_USB1_INJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJS register field. */ -#define ALT_SYSMGR_ECC_USB1_INJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJS register field value. */ -#define ALT_SYSMGR_ECC_USB1_INJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJS register field value. */ -#define ALT_SYSMGR_ECC_USB1_INJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_USB1_INJS register field. */ -#define ALT_SYSMGR_ECC_USB1_INJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB1_INJS field value from a register. */ -#define ALT_SYSMGR_ECC_USB1_INJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_USB1_INJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB1_INJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : USB1 RAM ECC inject double bit, non-correctable error - injd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the USB1 RAM. This only injects one double bit error into the USB1 RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */ -#define ALT_SYSMGR_ECC_USB1_INJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */ -#define ALT_SYSMGR_ECC_USB1_INJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_USB1_INJD register field. */ -#define ALT_SYSMGR_ECC_USB1_INJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB1_INJD register field value. */ -#define ALT_SYSMGR_ECC_USB1_INJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJD register field value. */ -#define ALT_SYSMGR_ECC_USB1_INJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_USB1_INJD register field. */ -#define ALT_SYSMGR_ECC_USB1_INJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB1_INJD field value from a register. */ -#define ALT_SYSMGR_ECC_USB1_INJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_USB1_INJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB1_INJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : USB1 RAM ECC single, correctable error interrupt status - serr - * - * This bit is an interrupt status bit for USB1 RAM ECC single, correctable error. - * It is set by hardware when single, correctable error occurs in USB1 RAM. - * Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */ -#define ALT_SYSMGR_ECC_USB1_SERR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */ -#define ALT_SYSMGR_ECC_USB1_SERR_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_USB1_SERR register field. */ -#define ALT_SYSMGR_ECC_USB1_SERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB1_SERR register field value. */ -#define ALT_SYSMGR_ECC_USB1_SERR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_USB1_SERR register field value. */ -#define ALT_SYSMGR_ECC_USB1_SERR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_USB1_SERR register field. */ -#define ALT_SYSMGR_ECC_USB1_SERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB1_SERR field value from a register. */ -#define ALT_SYSMGR_ECC_USB1_SERR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_USB1_SERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB1_SERR_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : USB1 RAM ECC double bit, non-correctable error interrupt status - derr - * - * This bit is an interrupt status bit for USB1 RAM ECC double bit, non-correctable - * error. It is set by hardware when double bit, non-correctable error occurs in - * USB1 RAM. Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */ -#define ALT_SYSMGR_ECC_USB1_DERR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */ -#define ALT_SYSMGR_ECC_USB1_DERR_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_USB1_DERR register field. */ -#define ALT_SYSMGR_ECC_USB1_DERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_USB1_DERR register field value. */ -#define ALT_SYSMGR_ECC_USB1_DERR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_USB1_DERR register field value. */ -#define ALT_SYSMGR_ECC_USB1_DERR_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_USB1_DERR register field. */ -#define ALT_SYSMGR_ECC_USB1_DERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_USB1_DERR field value from a register. */ -#define ALT_SYSMGR_ECC_USB1_DERR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_USB1_DERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_USB1_DERR_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_USB1. - */ -struct ALT_SYSMGR_ECC_USB1_s -{ - uint32_t en : 1; /* USB1 RAM ECC Enable */ - uint32_t injs : 1; /* USB1 RAM ECC inject single, correctable Error */ - uint32_t injd : 1; /* USB1 RAM ECC inject double bit, non-correctable error */ - uint32_t serr : 1; /* USB1 RAM ECC single, correctable error interrupt status */ - uint32_t derr : 1; /* USB1 RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_USB1. */ -typedef volatile struct ALT_SYSMGR_ECC_USB1_s ALT_SYSMGR_ECC_USB1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_USB1 register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_USB1_OFST 0xc - -/* - * Register : EMAC0 RAM ECC Enable Register - emac0 - * - * This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected - * into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------------------------------------------ - * [0] | RW | 0x0 | EMAC0 RAM ECC Enable - * [1] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject single, correctable Error - * [4] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error - * [5] | RW | 0x0 | EMAC0 TXFIFO RAM ECC single, correctable error interrupt status - * [6] | RW | 0x0 | EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status - * [7] | RW | 0x0 | EMAC0 RXFIFO RAM ECC single, correctable error interrupt status - * [8] | RW | 0x0 | EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : EMAC0 RAM ECC Enable - en - * - * Enable ECC for EMAC0 RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ -#define ALT_SYSMGR_ECC_EMAC0_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ -#define ALT_SYSMGR_ECC_EMAC0_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ -#define ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_EN register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_EN register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_EMAC0_EN register field. */ -#define ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC0_EN field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC0_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_EMAC0_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC0_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : EMAC0 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs - * - * Changing this bit from zero to one injects a single, correctable error into the - * EMAC0 TXFIFO RAM. This only injects one error into the EMAC0 TXFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the EMAC0 TXFIFO RAM. This only injects one double bit error into the EMAC0 - * TXFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : EMAC0 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs - * - * Changing this bit from zero to one injects a single, correctable error into the - * EMAC0 RXFIFO RAM. This only injects one error into the EMAC0 RXFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the EMAC0 RXFIFO RAM. This only injects one double bit error into the EMAC0 - * RXFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : EMAC0 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr - * - * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC single, correctable - * error. It is set by hardware when single, correctable error occurs in EMAC0 - * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt - * status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf -/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr - * - * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : EMAC0 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr - * - * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC single, correctable - * error. It is set by hardware when single, correctable error occurs in EMAC0 - * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt - * status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f -/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr - * - * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff -/* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_EMAC0. - */ -struct ALT_SYSMGR_ECC_EMAC0_s -{ - uint32_t en : 1; /* EMAC0 RAM ECC Enable */ - uint32_t txfifoinjs : 1; /* EMAC0 TXFIFO RAM ECC inject single, correctable Error */ - uint32_t txfifoinjd : 1; /* EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error */ - uint32_t rxfifoinjs : 1; /* EMAC0 RXFIFO RAM ECC inject single, correctable Error */ - uint32_t rxfifoinjd : 1; /* EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error */ - uint32_t txfifoserr : 1; /* EMAC0 TXFIFO RAM ECC single, correctable error interrupt status */ - uint32_t txfifoderr : 1; /* EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status */ - uint32_t rxfifoserr : 1; /* EMAC0 RXFIFO RAM ECC single, correctable error interrupt status */ - uint32_t rxfifoderr : 1; /* EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC0. */ -typedef volatile struct ALT_SYSMGR_ECC_EMAC0_s ALT_SYSMGR_ECC_EMAC0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_EMAC0 register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_EMAC0_OFST 0x10 - -/* - * Register : EMAC1 RAM ECC Enable Register - emac1 - * - * This register is used to enable ECC on the EMAC1 RAM. ECC errors can be injected - * into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------------------------------------------ - * [0] | RW | 0x0 | EMAC1 RAM ECC Enable - * [1] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject single, correctable Error - * [4] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error - * [5] | RW | 0x0 | EMAC1 TXFIFO RAM ECC single, correctable error interrupt status - * [6] | RW | 0x0 | EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status - * [7] | RW | 0x0 | EMAC1 RXFIFO RAM ECC single, correctable error interrupt status - * [8] | RW | 0x0 | EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : EMAC1 RAM ECC Enable - en - * - * Enable ECC for EMAC1 RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ -#define ALT_SYSMGR_ECC_EMAC1_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ -#define ALT_SYSMGR_ECC_EMAC1_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ -#define ALT_SYSMGR_ECC_EMAC1_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_EN register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_EN register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_EMAC1_EN register field. */ -#define ALT_SYSMGR_ECC_EMAC1_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC1_EN field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC1_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_EMAC1_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC1_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : EMAC1 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs - * - * Changing this bit from zero to one injects a single, correctable error into the - * EMAC1 TXFIFO RAM. This only injects one error into the EMAC1 TXFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the EMAC1 TXFIFO RAM. This only injects one double bit error into the EMAC1 - * TXFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : EMAC1 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs - * - * Changing this bit from zero to one injects a single, correctable error into the - * EMAC1 RXFIFO RAM. This only injects one error into the EMAC1 RXFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the EMAC1 RXFIFO RAM. This only injects one double bit error into the EMAC1 - * RXFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : EMAC1 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr - * - * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC single, correctable - * error. It is set by hardware when single, correctable error occurs in EMAC1 - * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt - * status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_MSB 5 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK 0x00000020 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_CLR_MSK 0xffffffdf -/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr - * - * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in EMAC1 TXFIFO RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_MSB 6 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : EMAC1 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr - * - * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC single, correctable - * error. It is set by hardware when single, correctable error occurs in EMAC1 - * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt - * status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_MSB 7 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK 0x00000080 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_CLR_MSK 0xffffff7f -/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr - * - * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in EMAC1 RXFIFO RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_MSB 8 -/* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK 0x00000100 -/* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_CLR_MSK 0xfffffeff -/* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR field value from a register. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_EMAC1. - */ -struct ALT_SYSMGR_ECC_EMAC1_s -{ - uint32_t en : 1; /* EMAC1 RAM ECC Enable */ - uint32_t txfifoinjs : 1; /* EMAC1 TXFIFO RAM ECC inject single, correctable Error */ - uint32_t txfifoinjd : 1; /* EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error */ - uint32_t rxfifoinjs : 1; /* EMAC1 RXFIFO RAM ECC inject single, correctable Error */ - uint32_t rxfifoinjd : 1; /* EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error */ - uint32_t txfifoserr : 1; /* EMAC1 TXFIFO RAM ECC single, correctable error interrupt status */ - uint32_t txfifoderr : 1; /* EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status */ - uint32_t rxfifoserr : 1; /* EMAC1 RXFIFO RAM ECC single, correctable error interrupt status */ - uint32_t rxfifoderr : 1; /* EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_EMAC1. */ -typedef volatile struct ALT_SYSMGR_ECC_EMAC1_s ALT_SYSMGR_ECC_EMAC1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_EMAC1 register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_EMAC1_OFST 0x14 - -/* - * Register : DMA RAM ECC Enable Register - dma - * - * This register is used to enable ECC on the DMA RAM. ECC errors can be injected - * into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------------------------------- - * [0] | RW | 0x0 | DMA RAM ECC Enable - * [1] | RW | 0x0 | DMA RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | DMA RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | DMA RAM ECC single, correctable error interrupt status - * [4] | RW | 0x0 | DMA RAM ECC double bit, non-correctable error interrupt status - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : DMA RAM ECC Enable - en - * - * Enable ECC for DMA RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */ -#define ALT_SYSMGR_ECC_DMA_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */ -#define ALT_SYSMGR_ECC_DMA_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_DMA_EN register field. */ -#define ALT_SYSMGR_ECC_DMA_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_DMA_EN register field value. */ -#define ALT_SYSMGR_ECC_DMA_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_DMA_EN register field value. */ -#define ALT_SYSMGR_ECC_DMA_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_DMA_EN register field. */ -#define ALT_SYSMGR_ECC_DMA_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_DMA_EN field value from a register. */ -#define ALT_SYSMGR_ECC_DMA_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_DMA_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_DMA_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : DMA RAM ECC inject single, correctable Error - injs - * - * Changing this bit from zero to one injects a single, correctable error into the - * DMA RAM. This only injects one error into the DMA RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */ -#define ALT_SYSMGR_ECC_DMA_INJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */ -#define ALT_SYSMGR_ECC_DMA_INJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJS register field. */ -#define ALT_SYSMGR_ECC_DMA_INJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJS register field value. */ -#define ALT_SYSMGR_ECC_DMA_INJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJS register field value. */ -#define ALT_SYSMGR_ECC_DMA_INJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_DMA_INJS register field. */ -#define ALT_SYSMGR_ECC_DMA_INJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_DMA_INJS field value from a register. */ -#define ALT_SYSMGR_ECC_DMA_INJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_DMA_INJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_DMA_INJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : DMA RAM ECC inject double bit, non-correctable error - injd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the DMA RAM. This only injects one double bit error into the DMA RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */ -#define ALT_SYSMGR_ECC_DMA_INJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */ -#define ALT_SYSMGR_ECC_DMA_INJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_DMA_INJD register field. */ -#define ALT_SYSMGR_ECC_DMA_INJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_DMA_INJD register field value. */ -#define ALT_SYSMGR_ECC_DMA_INJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJD register field value. */ -#define ALT_SYSMGR_ECC_DMA_INJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_DMA_INJD register field. */ -#define ALT_SYSMGR_ECC_DMA_INJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_DMA_INJD field value from a register. */ -#define ALT_SYSMGR_ECC_DMA_INJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_DMA_INJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_DMA_INJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : DMA RAM ECC single, correctable error interrupt status - serr - * - * This bit is an interrupt status bit for DMA RAM ECC single, correctable error. - * It is set by hardware when single, correctable error occurs in DMA RAM. Software - * needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */ -#define ALT_SYSMGR_ECC_DMA_SERR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */ -#define ALT_SYSMGR_ECC_DMA_SERR_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_DMA_SERR register field. */ -#define ALT_SYSMGR_ECC_DMA_SERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_DMA_SERR register field value. */ -#define ALT_SYSMGR_ECC_DMA_SERR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_DMA_SERR register field value. */ -#define ALT_SYSMGR_ECC_DMA_SERR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_DMA_SERR register field. */ -#define ALT_SYSMGR_ECC_DMA_SERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_DMA_SERR field value from a register. */ -#define ALT_SYSMGR_ECC_DMA_SERR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_DMA_SERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_DMA_SERR_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : DMA RAM ECC double bit, non-correctable error interrupt status - derr - * - * This bit is an interrupt status bit for DMA RAM ECC double bit, non-correctable - * error. It is set by hardware when double bit, non-correctable error occurs in - * DMA RAM. Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */ -#define ALT_SYSMGR_ECC_DMA_DERR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */ -#define ALT_SYSMGR_ECC_DMA_DERR_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_DMA_DERR register field. */ -#define ALT_SYSMGR_ECC_DMA_DERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_DMA_DERR register field value. */ -#define ALT_SYSMGR_ECC_DMA_DERR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_DMA_DERR register field value. */ -#define ALT_SYSMGR_ECC_DMA_DERR_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_DMA_DERR register field. */ -#define ALT_SYSMGR_ECC_DMA_DERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_DMA_DERR field value from a register. */ -#define ALT_SYSMGR_ECC_DMA_DERR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_DMA_DERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_DMA_DERR_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_DMA. - */ -struct ALT_SYSMGR_ECC_DMA_s -{ - uint32_t en : 1; /* DMA RAM ECC Enable */ - uint32_t injs : 1; /* DMA RAM ECC inject single, correctable Error */ - uint32_t injd : 1; /* DMA RAM ECC inject double bit, non-correctable error */ - uint32_t serr : 1; /* DMA RAM ECC single, correctable error interrupt status */ - uint32_t derr : 1; /* DMA RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_DMA. */ -typedef volatile struct ALT_SYSMGR_ECC_DMA_s ALT_SYSMGR_ECC_DMA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_DMA register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_DMA_OFST 0x18 - -/* - * Register : CAN0 RAM ECC Enable Register - can0 - * - * This register is used to enable ECC on the CAN0 RAM. ECC errors can be injected - * into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------------------------------- - * [0] | RW | 0x0 | CAN0 RAM ECC Enable - * [1] | RW | 0x0 | CAN0 RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | CAN0 RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | CAN0 RAM ECC single, correctable error interrupt status - * [4] | RW | 0x0 | CAN0 RAM ECC double bit, non-correctable error interrupt status - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : CAN0 RAM ECC Enable - en - * - * Enable ECC for CAN0 RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */ -#define ALT_SYSMGR_ECC_CAN0_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */ -#define ALT_SYSMGR_ECC_CAN0_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_CAN0_EN register field. */ -#define ALT_SYSMGR_ECC_CAN0_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN0_EN register field value. */ -#define ALT_SYSMGR_ECC_CAN0_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_EN register field value. */ -#define ALT_SYSMGR_ECC_CAN0_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_CAN0_EN register field. */ -#define ALT_SYSMGR_ECC_CAN0_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN0_EN field value from a register. */ -#define ALT_SYSMGR_ECC_CAN0_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_CAN0_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN0_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : CAN0 RAM ECC inject single, correctable Error - injs - * - * Changing this bit from zero to one injects a single, correctable error into the - * CAN0 RAM. This only injects one error into the CAN0 RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ -#define ALT_SYSMGR_ECC_CAN0_INJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ -#define ALT_SYSMGR_ECC_CAN0_INJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ -#define ALT_SYSMGR_ECC_CAN0_INJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJS register field value. */ -#define ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJS register field value. */ -#define ALT_SYSMGR_ECC_CAN0_INJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJS register field. */ -#define ALT_SYSMGR_ECC_CAN0_INJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN0_INJS field value from a register. */ -#define ALT_SYSMGR_ECC_CAN0_INJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_CAN0_INJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN0_INJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : CAN0 RAM ECC inject double bit, non-correctable error - injd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the CAN0 RAM. This only injects one double bit error into the CAN0 RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ -#define ALT_SYSMGR_ECC_CAN0_INJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ -#define ALT_SYSMGR_ECC_CAN0_INJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ -#define ALT_SYSMGR_ECC_CAN0_INJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJD register field value. */ -#define ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJD register field value. */ -#define ALT_SYSMGR_ECC_CAN0_INJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_CAN0_INJD register field. */ -#define ALT_SYSMGR_ECC_CAN0_INJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN0_INJD field value from a register. */ -#define ALT_SYSMGR_ECC_CAN0_INJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_CAN0_INJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN0_INJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : CAN0 RAM ECC single, correctable error interrupt status - serr - * - * This bit is an interrupt status bit for CAN0 RAM ECC single, correctable error. - * It is set by hardware when single, correctable error occurs in CAN0 RAM. - * Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ -#define ALT_SYSMGR_ECC_CAN0_SERR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ -#define ALT_SYSMGR_ECC_CAN0_SERR_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ -#define ALT_SYSMGR_ECC_CAN0_SERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN0_SERR register field value. */ -#define ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_SERR register field value. */ -#define ALT_SYSMGR_ECC_CAN0_SERR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_CAN0_SERR register field. */ -#define ALT_SYSMGR_ECC_CAN0_SERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN0_SERR field value from a register. */ -#define ALT_SYSMGR_ECC_CAN0_SERR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_CAN0_SERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN0_SERR_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : CAN0 RAM ECC double bit, non-correctable error interrupt status - derr - * - * This bit is an interrupt status bit for CAN0 RAM ECC double bit, non-correctable - * error. It is set by hardware when double bit, non-correctable error occurs in - * CAN0 RAM. Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ -#define ALT_SYSMGR_ECC_CAN0_DERR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ -#define ALT_SYSMGR_ECC_CAN0_DERR_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ -#define ALT_SYSMGR_ECC_CAN0_DERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN0_DERR register field value. */ -#define ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN0_DERR register field value. */ -#define ALT_SYSMGR_ECC_CAN0_DERR_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_CAN0_DERR register field. */ -#define ALT_SYSMGR_ECC_CAN0_DERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN0_DERR field value from a register. */ -#define ALT_SYSMGR_ECC_CAN0_DERR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_CAN0_DERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN0_DERR_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_CAN0. - */ -struct ALT_SYSMGR_ECC_CAN0_s -{ - uint32_t en : 1; /* CAN0 RAM ECC Enable */ - uint32_t injs : 1; /* CAN0 RAM ECC inject single, correctable Error */ - uint32_t injd : 1; /* CAN0 RAM ECC inject double bit, non-correctable error */ - uint32_t serr : 1; /* CAN0 RAM ECC single, correctable error interrupt status */ - uint32_t derr : 1; /* CAN0 RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_CAN0. */ -typedef volatile struct ALT_SYSMGR_ECC_CAN0_s ALT_SYSMGR_ECC_CAN0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_CAN0 register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_CAN0_OFST 0x1c - -/* - * Register : CAN1 RAM ECC Enable Register - can1 - * - * This register is used to enable ECC on the CAN1 RAM. ECC errors can be injected - * into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------------------------------- - * [0] | RW | 0x0 | CAN1 RAM ECC Enable - * [1] | RW | 0x0 | CAN1 RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | CAN1 RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | CAN1 RAM ECC single, correctable error interrupt status - * [4] | RW | 0x0 | CAN1 RAM ECC double bit, non-correctable error interrupt status - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : CAN1 RAM ECC Enable - en - * - * Enable ECC for CAN1 RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */ -#define ALT_SYSMGR_ECC_CAN1_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */ -#define ALT_SYSMGR_ECC_CAN1_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_CAN1_EN register field. */ -#define ALT_SYSMGR_ECC_CAN1_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN1_EN register field value. */ -#define ALT_SYSMGR_ECC_CAN1_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_EN register field value. */ -#define ALT_SYSMGR_ECC_CAN1_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_CAN1_EN register field. */ -#define ALT_SYSMGR_ECC_CAN1_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN1_EN field value from a register. */ -#define ALT_SYSMGR_ECC_CAN1_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_CAN1_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN1_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : CAN1 RAM ECC inject single, correctable Error - injs - * - * Changing this bit from zero to one injects a single, correctable error into the - * CAN1 RAM. This only injects one error into the CAN1 RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ -#define ALT_SYSMGR_ECC_CAN1_INJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ -#define ALT_SYSMGR_ECC_CAN1_INJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ -#define ALT_SYSMGR_ECC_CAN1_INJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJS register field value. */ -#define ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJS register field value. */ -#define ALT_SYSMGR_ECC_CAN1_INJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJS register field. */ -#define ALT_SYSMGR_ECC_CAN1_INJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN1_INJS field value from a register. */ -#define ALT_SYSMGR_ECC_CAN1_INJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_CAN1_INJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN1_INJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : CAN1 RAM ECC inject double bit, non-correctable error - injd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the CAN1 RAM. This only injects one double bit error into the CAN1 RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ -#define ALT_SYSMGR_ECC_CAN1_INJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ -#define ALT_SYSMGR_ECC_CAN1_INJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ -#define ALT_SYSMGR_ECC_CAN1_INJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJD register field value. */ -#define ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJD register field value. */ -#define ALT_SYSMGR_ECC_CAN1_INJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_CAN1_INJD register field. */ -#define ALT_SYSMGR_ECC_CAN1_INJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN1_INJD field value from a register. */ -#define ALT_SYSMGR_ECC_CAN1_INJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_CAN1_INJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN1_INJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : CAN1 RAM ECC single, correctable error interrupt status - serr - * - * This bit is an interrupt status bit for CAN1 RAM ECC single, correctable error. - * It is set by hardware when single, correctable error occurs in CAN1 RAM. - * Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ -#define ALT_SYSMGR_ECC_CAN1_SERR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ -#define ALT_SYSMGR_ECC_CAN1_SERR_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ -#define ALT_SYSMGR_ECC_CAN1_SERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN1_SERR register field value. */ -#define ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_SERR register field value. */ -#define ALT_SYSMGR_ECC_CAN1_SERR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_CAN1_SERR register field. */ -#define ALT_SYSMGR_ECC_CAN1_SERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN1_SERR field value from a register. */ -#define ALT_SYSMGR_ECC_CAN1_SERR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_CAN1_SERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN1_SERR_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : CAN1 RAM ECC double bit, non-correctable error interrupt status - derr - * - * This bit is an interrupt status bit for CAN1 RAM ECC double bit, non-correctable - * error. It is set by hardware when double bit, non-correctable error occurs in - * CAN1 RAM. Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ -#define ALT_SYSMGR_ECC_CAN1_DERR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ -#define ALT_SYSMGR_ECC_CAN1_DERR_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ -#define ALT_SYSMGR_ECC_CAN1_DERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_CAN1_DERR register field value. */ -#define ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_CAN1_DERR register field value. */ -#define ALT_SYSMGR_ECC_CAN1_DERR_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_CAN1_DERR register field. */ -#define ALT_SYSMGR_ECC_CAN1_DERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_CAN1_DERR field value from a register. */ -#define ALT_SYSMGR_ECC_CAN1_DERR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_CAN1_DERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_CAN1_DERR_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_CAN1. - */ -struct ALT_SYSMGR_ECC_CAN1_s -{ - uint32_t en : 1; /* CAN1 RAM ECC Enable */ - uint32_t injs : 1; /* CAN1 RAM ECC inject single, correctable Error */ - uint32_t injd : 1; /* CAN1 RAM ECC inject double bit, non-correctable error */ - uint32_t serr : 1; /* CAN1 RAM ECC single, correctable error interrupt status */ - uint32_t derr : 1; /* CAN1 RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_CAN1. */ -typedef volatile struct ALT_SYSMGR_ECC_CAN1_s ALT_SYSMGR_ECC_CAN1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_CAN1 register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_CAN1_OFST 0x20 - -/* - * Register : NAND RAM ECC Enable Register - nand - * - * This register is used to enable ECC on the NAND RAM. ECC errors can be injected - * into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:-------------------------------------------------------------------------- - * [0] | RW | 0x0 | NAND RAM ECC Enable - * [1] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | NAND WRFIFO RAM ECC inject single, correctable Error - * [4] | RW | 0x0 | NAND WRFIFO RAM ECC inject double bit, non-correctable error - * [5] | RW | 0x0 | NAND RDFIFO RAM ECC inject single, correctable Error - * [6] | RW | 0x0 | NAND RDFIFO RAM ECC inject double bit, non-correctable error - * [7] | RW | 0x0 | NAND ECCBUFFER RAM ECC single, correctable error interrupt status - * [8] | RW | 0x0 | NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status - * [9] | RW | 0x0 | NAND WRFIFO RAM ECC single, correctable error interrupt status - * [10] | RW | 0x0 | NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status - * [11] | RW | 0x0 | NAND RDFIFO RAM ECC single, correctable error interrupt status - * [12] | RW | 0x0 | NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status - * [31:13] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : NAND RAM ECC Enable - en - * - * Enable ECC for NAND RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */ -#define ALT_SYSMGR_ECC_NAND_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */ -#define ALT_SYSMGR_ECC_NAND_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_EN register field. */ -#define ALT_SYSMGR_ECC_NAND_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_EN register field value. */ -#define ALT_SYSMGR_ECC_NAND_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_EN register field value. */ -#define ALT_SYSMGR_ECC_NAND_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_NAND_EN register field. */ -#define ALT_SYSMGR_ECC_NAND_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_EN field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_NAND_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : NAND ECCBUFFER RAM ECC inject single, correctable Error - eccbufinjs - * - * Changing this bit from zero to one injects a single, correctable error into the - * NAND ECCBUFFER RAM. This only injects one error into the NAND ECCBUFFER RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJS field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : NAND ECCBUFFER RAM ECC inject double bit, non-correctable error - eccbufinjd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the NAND ECCBUFFER RAM. This only injects one double bit error into the NAND - * ECCBUFFER RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJD field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : NAND WRFIFO RAM ECC inject single, correctable Error - wrfifoinjs - * - * Changing this bit from zero to one injects a single, correctable error into the - * NAND WRFIFO RAM. This only injects one error into the NAND WRFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJS field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : NAND WRFIFO RAM ECC inject double bit, non-correctable error - wrfifoinjd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the NAND WRFIFO RAM. This only injects one double bit error into the NAND WRFIFO - * RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJD field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : NAND RDFIFO RAM ECC inject single, correctable Error - rdfifoinjs - * - * Changing this bit from zero to one injects a single, correctable error into the - * NAND RDFIFO RAM. This only injects one error into the NAND RDFIFO RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB 5 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK 0x00000020 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK 0xffffffdf -/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJS field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : NAND RDFIFO RAM ECC inject double bit, non-correctable error - rdfifoinjd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the NAND RDFIFO RAM. This only injects one double bit error into the NAND RDFIFO - * RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB 6 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJD field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : NAND ECCBUFFER RAM ECC single, correctable error interrupt status - eccbufserr - * - * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC single, - * correctable error. It is set by hardware when single, correctable error occurs - * in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB 7 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK 0x00000080 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK 0xffffff7f -/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFSERR field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status - eccbufderr - * - * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear - * the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB 8 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK 0x00000100 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK 0xfffffeff -/* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFDERR field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : NAND WRFIFO RAM ECC single, correctable error interrupt status - wrfifoserr - * - * This bit is an interrupt status bit for NAND WRFIFO RAM ECC single, correctable - * error. It is set by hardware when single, correctable error occurs in NAND - * WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt - * status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB 9 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK 0x00000200 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK 0xfffffdff -/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOSERR field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status - wrfifoderr - * - * This bit is an interrupt status bit for NAND WRFIFO RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB 10 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK 0x00000400 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK 0xfffffbff -/* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFODERR field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : NAND RDFIFO RAM ECC single, correctable error interrupt status - rdfifoserr - * - * This bit is an interrupt status bit for NAND RDFIFO RAM ECC single, correctable - * error. It is set by hardware when single, correctable error occurs in NAND - * RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt - * status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB 11 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK 0x00000800 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOSERR field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status - rdfifoderr - * - * This bit is an interrupt status bit for NAND RDFIFO RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB 12 -/* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK 0x00001000 -/* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK 0xffffefff -/* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFODERR field value from a register. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET(value) (((value) << 12) & 0x00001000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_NAND. - */ -struct ALT_SYSMGR_ECC_NAND_s -{ - uint32_t en : 1; /* NAND RAM ECC Enable */ - uint32_t eccbufinjs : 1; /* NAND ECCBUFFER RAM ECC inject single, correctable Error */ - uint32_t eccbufinjd : 1; /* NAND ECCBUFFER RAM ECC inject double bit, non-correctable error */ - uint32_t wrfifoinjs : 1; /* NAND WRFIFO RAM ECC inject single, correctable Error */ - uint32_t wrfifoinjd : 1; /* NAND WRFIFO RAM ECC inject double bit, non-correctable error */ - uint32_t rdfifoinjs : 1; /* NAND RDFIFO RAM ECC inject single, correctable Error */ - uint32_t rdfifoinjd : 1; /* NAND RDFIFO RAM ECC inject double bit, non-correctable error */ - uint32_t eccbufserr : 1; /* NAND ECCBUFFER RAM ECC single, correctable error interrupt status */ - uint32_t eccbufderr : 1; /* NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status */ - uint32_t wrfifoserr : 1; /* NAND WRFIFO RAM ECC single, correctable error interrupt status */ - uint32_t wrfifoderr : 1; /* NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status */ - uint32_t rdfifoserr : 1; /* NAND RDFIFO RAM ECC single, correctable error interrupt status */ - uint32_t rdfifoderr : 1; /* NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 19; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_NAND. */ -typedef volatile struct ALT_SYSMGR_ECC_NAND_s ALT_SYSMGR_ECC_NAND_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_NAND register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_NAND_OFST 0x24 - -/* - * Register : QSPI RAM ECC Enable Register - qspi - * - * This register is used to enable ECC on the QSPI RAM. ECC errors can be injected - * into the write path using bits in this register. This register contains - * interrupt status of the ECC single/double bit error. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------------------------------- - * [0] | RW | 0x0 | QSPI RAM ECC Enable - * [1] | RW | 0x0 | QSPI RAM ECC inject single, correctable Error - * [2] | RW | 0x0 | QSPI RAM ECC inject double bit, non-correctable error - * [3] | RW | 0x0 | QSPI RAM ECC single, correctable error interrupt status - * [4] | RW | 0x0 | QSPI RAM ECC double bit, non-correctable error interrupt status - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : QSPI RAM ECC Enable - en - * - * Enable ECC for QSPI RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */ -#define ALT_SYSMGR_ECC_QSPI_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */ -#define ALT_SYSMGR_ECC_QSPI_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_QSPI_EN register field. */ -#define ALT_SYSMGR_ECC_QSPI_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_QSPI_EN register field value. */ -#define ALT_SYSMGR_ECC_QSPI_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_EN register field value. */ -#define ALT_SYSMGR_ECC_QSPI_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_QSPI_EN register field. */ -#define ALT_SYSMGR_ECC_QSPI_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_QSPI_EN field value from a register. */ -#define ALT_SYSMGR_ECC_QSPI_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_QSPI_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_QSPI_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : QSPI RAM ECC inject single, correctable Error - injs - * - * Changing this bit from zero to one injects a single, correctable error into the - * QSPI RAM. This only injects one error into the QSPI RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ -#define ALT_SYSMGR_ECC_QSPI_INJS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ -#define ALT_SYSMGR_ECC_QSPI_INJS_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ -#define ALT_SYSMGR_ECC_QSPI_INJS_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJS register field value. */ -#define ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJS register field value. */ -#define ALT_SYSMGR_ECC_QSPI_INJS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJS register field. */ -#define ALT_SYSMGR_ECC_QSPI_INJS_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_QSPI_INJS field value from a register. */ -#define ALT_SYSMGR_ECC_QSPI_INJS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_QSPI_INJS register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_QSPI_INJS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : QSPI RAM ECC inject double bit, non-correctable error - injd - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the QSPI RAM. This only injects one double bit error into the QSPI RAM. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ -#define ALT_SYSMGR_ECC_QSPI_INJD_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ -#define ALT_SYSMGR_ECC_QSPI_INJD_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ -#define ALT_SYSMGR_ECC_QSPI_INJD_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJD register field value. */ -#define ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJD register field value. */ -#define ALT_SYSMGR_ECC_QSPI_INJD_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_QSPI_INJD register field. */ -#define ALT_SYSMGR_ECC_QSPI_INJD_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_QSPI_INJD field value from a register. */ -#define ALT_SYSMGR_ECC_QSPI_INJD_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_QSPI_INJD register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_QSPI_INJD_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : QSPI RAM ECC single, correctable error interrupt status - serr - * - * This bit is an interrupt status bit for QSPI RAM ECC single, correctable error. - * It is set by hardware when single, correctable error occurs in QSPI RAM. - * Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ -#define ALT_SYSMGR_ECC_QSPI_SERR_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ -#define ALT_SYSMGR_ECC_QSPI_SERR_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ -#define ALT_SYSMGR_ECC_QSPI_SERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_QSPI_SERR register field value. */ -#define ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_SERR register field value. */ -#define ALT_SYSMGR_ECC_QSPI_SERR_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_QSPI_SERR register field. */ -#define ALT_SYSMGR_ECC_QSPI_SERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_QSPI_SERR field value from a register. */ -#define ALT_SYSMGR_ECC_QSPI_SERR_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_QSPI_SERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_QSPI_SERR_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : QSPI RAM ECC double bit, non-correctable error interrupt status - derr - * - * This bit is an interrupt status bit for QSPI RAM ECC double bit, non-correctable - * error. It is set by hardware when double bit, non-correctable error occurs in - * QSPI RAM. Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ -#define ALT_SYSMGR_ECC_QSPI_DERR_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ -#define ALT_SYSMGR_ECC_QSPI_DERR_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ -#define ALT_SYSMGR_ECC_QSPI_DERR_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_QSPI_DERR register field value. */ -#define ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_QSPI_DERR register field value. */ -#define ALT_SYSMGR_ECC_QSPI_DERR_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_QSPI_DERR register field. */ -#define ALT_SYSMGR_ECC_QSPI_DERR_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_QSPI_DERR field value from a register. */ -#define ALT_SYSMGR_ECC_QSPI_DERR_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_QSPI_DERR register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_QSPI_DERR_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_QSPI. - */ -struct ALT_SYSMGR_ECC_QSPI_s -{ - uint32_t en : 1; /* QSPI RAM ECC Enable */ - uint32_t injs : 1; /* QSPI RAM ECC inject single, correctable Error */ - uint32_t injd : 1; /* QSPI RAM ECC inject double bit, non-correctable error */ - uint32_t serr : 1; /* QSPI RAM ECC single, correctable error interrupt status */ - uint32_t derr : 1; /* QSPI RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_QSPI. */ -typedef volatile struct ALT_SYSMGR_ECC_QSPI_s ALT_SYSMGR_ECC_QSPI_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_QSPI register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_QSPI_OFST 0x28 - -/* - * Register : SDMMC RAM ECC Enable Register - sdmmc - * - * This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected - * into the write path using bits in this register. - * - * Only reset by a cold reset (ignores warm reset). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------------------------------------------ - * [0] | RW | 0x0 | SDMMC RAM ECC Enable - * [1] | RW | 0x0 | SDMMC Port A RAM ECC inject single, correctable Error at Port A - * [2] | RW | 0x0 | SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A - * [3] | RW | 0x0 | SDMMC Port B RAM ECC inject single, correctable Error at Port B - * [4] | RW | 0x0 | SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B - * [5] | RW | 0x0 | SDMMC Port A RAM ECC single, correctable error interrupt status - * [6] | RW | 0x0 | SDMMC Port A RAM ECC double bit, non-correctable error interrupt status - * [7] | RW | 0x0 | SDMMC Port B RAM ECC single, correctable error interrupt status - * [8] | RW | 0x0 | SDMMC Port B RAM ECC double bit, non-correctable error interrupt status - * [31:9] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : SDMMC RAM ECC Enable - en - * - * Enable ECC for SDMMC RAM - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ -#define ALT_SYSMGR_ECC_SDMMC_EN_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ -#define ALT_SYSMGR_ECC_SDMMC_EN_MSB 0 -/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ -#define ALT_SYSMGR_ECC_SDMMC_EN_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_EN register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_EN register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_EN_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_ECC_SDMMC_EN register field. */ -#define ALT_SYSMGR_ECC_SDMMC_EN_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_SDMMC_EN field value from a register. */ -#define ALT_SYSMGR_ECC_SDMMC_EN_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_ECC_SDMMC_EN register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_SDMMC_EN_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : SDMMC Port A RAM ECC inject single, correctable Error at Port A - injsporta - * - * Changing this bit from zero to one injects a single, correctable error into the - * SDMMC RAM at Port A. This only injects one error into the SDMMC RAM at Port A. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_MSB 1 -/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK 0x00000002 -/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_CLR_MSK 0xfffffffd -/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTA field value from a register. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A - injdporta - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the SDMMC RAM at Port A. This only injects one double bit error into the SDMMC - * RAM at Port A. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_MSB 2 -/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK 0x00000004 -/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_CLR_MSK 0xfffffffb -/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTA field value from a register. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : SDMMC Port B RAM ECC inject single, correctable Error at Port B - injsportb - * - * Changing this bit from zero to one injects a single, correctable error into the - * SDMMC RAM at Port B. This only injects one error into the SDMMC RAM at Port B. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_MSB 3 -/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK 0x00000008 -/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTB field value from a register. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B - injdportb - * - * Changing this bit from zero to one injects a double, non-correctable error into - * the SDMMC RAM at Port B. This only injects one double bit error into the SDMMC - * RAM at Port B. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_MSB 4 -/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK 0x00000010 -/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_CLR_MSK 0xffffffef -/* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTB field value from a register. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : SDMMC Port A RAM ECC single, correctable error interrupt status - serrporta - * - * This bit is an interrupt status bit for SDMMC Port A RAM ECC single, correctable - * error. It is set by hardware when single, correctable error occurs in SDMMC Port - * A RAM. Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_MSB 5 -/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK 0x00000020 -/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_CLR_MSK 0xffffffdf -/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTA field value from a register. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : SDMMC Port A RAM ECC double bit, non-correctable error interrupt status - derrporta - * - * This bit is an interrupt status bit for SDMMC Port A RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in SDMMC Port A RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_MSB 6 -/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK 0x00000040 -/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_CLR_MSK 0xffffffbf -/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTA field value from a register. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : SDMMC Port B RAM ECC single, correctable error interrupt status - serrportb - * - * This bit is an interrupt status bit for SDMMC Port B RAM ECC single, correctable - * error. It is set by hardware when single, correctable error occurs in SDMMC Port - * B RAM. Software needs to write 1 into this bit to clear the interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_MSB 7 -/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK 0x00000080 -/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_CLR_MSK 0xffffff7f -/* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTB field value from a register. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : SDMMC Port B RAM ECC double bit, non-correctable error interrupt status - derrportb - * - * This bit is an interrupt status bit for SDMMC Port B RAM ECC double bit, non- - * correctable error. It is set by hardware when double bit, non-correctable error - * occurs in SDMMC Port B RAM. Software needs to write 1 into this bit to clear the - * interrupt status. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_MSB 8 -/* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK 0x00000100 -/* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_CLR_MSK 0xfffffeff -/* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_RESET 0x0 -/* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTB field value from a register. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value suitable for setting the register. */ -#define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET(value) (((value) << 8) & 0x00000100) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_ECC_SDMMC. - */ -struct ALT_SYSMGR_ECC_SDMMC_s -{ - uint32_t en : 1; /* SDMMC RAM ECC Enable */ - uint32_t injsporta : 1; /* SDMMC Port A RAM ECC inject single, correctable Error at Port A */ - uint32_t injdporta : 1; /* SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A */ - uint32_t injsportb : 1; /* SDMMC Port B RAM ECC inject single, correctable Error at Port B */ - uint32_t injdportb : 1; /* SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B */ - uint32_t serrporta : 1; /* SDMMC Port A RAM ECC single, correctable error interrupt status */ - uint32_t derrporta : 1; /* SDMMC Port A RAM ECC double bit, non-correctable error interrupt status */ - uint32_t serrportb : 1; /* SDMMC Port B RAM ECC single, correctable error interrupt status */ - uint32_t derrportb : 1; /* SDMMC Port B RAM ECC double bit, non-correctable error interrupt status */ - uint32_t : 23; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_ECC_SDMMC. */ -typedef volatile struct ALT_SYSMGR_ECC_SDMMC_s ALT_SYSMGR_ECC_SDMMC_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_ECC_SDMMC register from the beginning of the component. */ -#define ALT_SYSMGR_ECC_SDMMC_OFST 0x2c - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_ECC. - */ -struct ALT_SYSMGR_ECC_s -{ - volatile ALT_SYSMGR_ECC_L2_t l2; /* ALT_SYSMGR_ECC_L2 */ - volatile ALT_SYSMGR_ECC_OCRAM_t ocram; /* ALT_SYSMGR_ECC_OCRAM */ - volatile ALT_SYSMGR_ECC_USB0_t usb0; /* ALT_SYSMGR_ECC_USB0 */ - volatile ALT_SYSMGR_ECC_USB1_t usb1; /* ALT_SYSMGR_ECC_USB1 */ - volatile ALT_SYSMGR_ECC_EMAC0_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */ - volatile ALT_SYSMGR_ECC_EMAC1_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */ - volatile ALT_SYSMGR_ECC_DMA_t dma; /* ALT_SYSMGR_ECC_DMA */ - volatile ALT_SYSMGR_ECC_CAN0_t can0; /* ALT_SYSMGR_ECC_CAN0 */ - volatile ALT_SYSMGR_ECC_CAN1_t can1; /* ALT_SYSMGR_ECC_CAN1 */ - volatile ALT_SYSMGR_ECC_NAND_t nand; /* ALT_SYSMGR_ECC_NAND */ - volatile ALT_SYSMGR_ECC_QSPI_t qspi; /* ALT_SYSMGR_ECC_QSPI */ - volatile ALT_SYSMGR_ECC_SDMMC_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */ - volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_ECC. */ -typedef volatile struct ALT_SYSMGR_ECC_s ALT_SYSMGR_ECC_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_ECC. */ -struct ALT_SYSMGR_ECC_raw_s -{ - volatile uint32_t l2; /* ALT_SYSMGR_ECC_L2 */ - volatile uint32_t ocram; /* ALT_SYSMGR_ECC_OCRAM */ - volatile uint32_t usb0; /* ALT_SYSMGR_ECC_USB0 */ - volatile uint32_t usb1; /* ALT_SYSMGR_ECC_USB1 */ - volatile uint32_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */ - volatile uint32_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */ - volatile uint32_t dma; /* ALT_SYSMGR_ECC_DMA */ - volatile uint32_t can0; /* ALT_SYSMGR_ECC_CAN0 */ - volatile uint32_t can1; /* ALT_SYSMGR_ECC_CAN1 */ - volatile uint32_t nand; /* ALT_SYSMGR_ECC_NAND */ - volatile uint32_t qspi; /* ALT_SYSMGR_ECC_QSPI */ - volatile uint32_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */ - volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ECC. */ -typedef volatile struct ALT_SYSMGR_ECC_raw_s ALT_SYSMGR_ECC_raw_t; -#endif /* __ASSEMBLY__ */ - - -/* - * Register Group : Pin Mux Control Group - ALT_SYSMGR_PINMUX - * Pin Mux Control Group - * - * Controls Pin Mux selections - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - */ -/* - * Register : emac0_tx_clk Mux Selection Register - EMACIO0 - * - * This register is used to control the peripherals connected to emac0_tx_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [1:0] | RW | 0x0 | emac0_tx_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_tx_clk Mux Selection Field - sel - * - * Select peripheral signals connected emac0_tx_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 0. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal RGMII0.TX_CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO0_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO0. - */ -struct ALT_SYSMGR_PINMUX_EMACIO0_s -{ - uint32_t sel : 2; /* emac0_tx_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO0. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO0_s ALT_SYSMGR_PINMUX_EMACIO0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO0 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_OFST 0x0 - -/* - * Register : emac0_tx_d0 Mux Selection Register - EMACIO1 - * - * This register is used to control the peripherals connected to emac0_tx_d0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac0_tx_d0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_tx_d0 Mux Selection Field - sel - * - * Select peripheral signals connected emac0_tx_d0. - * - * 0 : Pin is connected to GPIO/LoanIO number 1. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.D0. - * - * 3 : Pin is connected to Peripheral signal RGMII0.TXD0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO1_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO1. - */ -struct ALT_SYSMGR_PINMUX_EMACIO1_s -{ - uint32_t sel : 2; /* emac0_tx_d0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO1. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO1_s ALT_SYSMGR_PINMUX_EMACIO1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO1 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_OFST 0x4 - -/* - * Register : emac0_tx_d1 Mux Selection Register - EMACIO2 - * - * This register is used to control the peripherals connected to emac0_tx_d1 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac0_tx_d1 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_tx_d1 Mux Selection Field - sel - * - * Select peripheral signals connected emac0_tx_d1. - * - * 0 : Pin is connected to GPIO/LoanIO number 2. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.D1. - * - * 3 : Pin is connected to Peripheral signal RGMII0.TXD1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO2_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO2. - */ -struct ALT_SYSMGR_PINMUX_EMACIO2_s -{ - uint32_t sel : 2; /* emac0_tx_d1 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO2. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO2_s ALT_SYSMGR_PINMUX_EMACIO2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO2 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_OFST 0x8 - -/* - * Register : emac0_tx_d2 Mux Selection Register - EMACIO3 - * - * This register is used to control the peripherals connected to emac0_tx_d2 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac0_tx_d2 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_tx_d2 Mux Selection Field - sel - * - * Select peripheral signals connected emac0_tx_d2. - * - * 0 : Pin is connected to GPIO/LoanIO number 3. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.D2. - * - * 3 : Pin is connected to Peripheral signal RGMII0.TXD2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO3_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO3. - */ -struct ALT_SYSMGR_PINMUX_EMACIO3_s -{ - uint32_t sel : 2; /* emac0_tx_d2 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO3. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO3_s ALT_SYSMGR_PINMUX_EMACIO3_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO3 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_OFST 0xc - -/* - * Register : emac0_tx_d3 Mux Selection Register - EMACIO4 - * - * This register is used to control the peripherals connected to emac0_tx_d3 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac0_tx_d3 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_tx_d3 Mux Selection Field - sel - * - * Select peripheral signals connected emac0_tx_d3. - * - * 0 : Pin is connected to GPIO/LoanIO number 4. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.D3. - * - * 3 : Pin is connected to Peripheral signal RGMII0.TXD3. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO4_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO4. - */ -struct ALT_SYSMGR_PINMUX_EMACIO4_s -{ - uint32_t sel : 2; /* emac0_tx_d3 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO4. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO4_s ALT_SYSMGR_PINMUX_EMACIO4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO4 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_OFST 0x10 - -/* - * Register : emac0_rx_d0 Mux Selection Register - EMACIO5 - * - * This register is used to control the peripherals connected to emac0_rx_d0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac0_rx_d0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_rx_d0 Mux Selection Field - sel - * - * Select peripheral signals connected emac0_rx_d0. - * - * 0 : Pin is connected to GPIO/LoanIO number 5. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.D4. - * - * 3 : Pin is connected to Peripheral signal RGMII0.RXD0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO5_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO5. - */ -struct ALT_SYSMGR_PINMUX_EMACIO5_s -{ - uint32_t sel : 2; /* emac0_rx_d0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO5. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO5_s ALT_SYSMGR_PINMUX_EMACIO5_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO5 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_OFST 0x14 - -/* - * Register : emac0_mdio Mux Selection Register - EMACIO6 - * - * This register is used to control the peripherals connected to emac0_mdio - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [1:0] | RW | 0x0 | emac0_mdio Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_mdio Mux Selection Field - sel - * - * Select peripheral signals connected emac0_mdio. - * - * 0 : Pin is connected to GPIO/LoanIO number 6. - * - * 1 : Pin is connected to Peripheral signal I2C2.SDA. - * - * 2 : Pin is connected to Peripheral signal USB1.D5. - * - * 3 : Pin is connected to Peripheral signal RGMII0.MDIO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO6_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO6. - */ -struct ALT_SYSMGR_PINMUX_EMACIO6_s -{ - uint32_t sel : 2; /* emac0_mdio Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO6. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO6_s ALT_SYSMGR_PINMUX_EMACIO6_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO6 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_OFST 0x18 - -/* - * Register : emac0_mdc Mux Selection Register - EMACIO7 - * - * This register is used to control the peripherals connected to emac0_mdc - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | emac0_mdc Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_mdc Mux Selection Field - sel - * - * Select peripheral signals connected emac0_mdc. - * - * 0 : Pin is connected to GPIO/LoanIO number 7. - * - * 1 : Pin is connected to Peripheral signal I2C2.SCL. - * - * 2 : Pin is connected to Peripheral signal USB1.D6. - * - * 3 : Pin is connected to Peripheral signal RGMII0.MDC. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO7_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO7. - */ -struct ALT_SYSMGR_PINMUX_EMACIO7_s -{ - uint32_t sel : 2; /* emac0_mdc Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO7. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO7_s ALT_SYSMGR_PINMUX_EMACIO7_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO7 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_OFST 0x1c - -/* - * Register : emac0_rx_ctl Mux Selection Register - EMACIO8 - * - * This register is used to control the peripherals connected to emac0_rx_ctl - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [1:0] | RW | 0x0 | emac0_rx_ctl Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_rx_ctl Mux Selection Field - sel - * - * Select peripheral signals connected emac0_rx_ctl. - * - * 0 : Pin is connected to GPIO/LoanIO number 8. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.D7. - * - * 3 : Pin is connected to Peripheral signal RGMII0.RX_CTL. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO8_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO8. - */ -struct ALT_SYSMGR_PINMUX_EMACIO8_s -{ - uint32_t sel : 2; /* emac0_rx_ctl Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO8. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO8_s ALT_SYSMGR_PINMUX_EMACIO8_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO8 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_OFST 0x20 - -/* - * Register : emac0_tx_ctl Mux Selection Register - EMACIO9 - * - * This register is used to control the peripherals connected to emac0_tx_ctl - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [1:0] | RW | 0x0 | emac0_tx_ctl Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_tx_ctl Mux Selection Field - sel - * - * Select peripheral signals connected emac0_tx_ctl. - * - * 0 : Pin is connected to GPIO/LoanIO number 9. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal RGMII0.TX_CTL. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO9_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO9. - */ -struct ALT_SYSMGR_PINMUX_EMACIO9_s -{ - uint32_t sel : 2; /* emac0_tx_ctl Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO9. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO9_s ALT_SYSMGR_PINMUX_EMACIO9_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO9 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_OFST 0x24 - -/* - * Register : emac0_rx_clk Mux Selection Register - EMACIO10 - * - * This register is used to control the peripherals connected to emac0_rx_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [1:0] | RW | 0x0 | emac0_rx_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_rx_clk Mux Selection Field - sel - * - * Select peripheral signals connected emac0_rx_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 10. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.CLK. - * - * 3 : Pin is connected to Peripheral signal RGMII0.RX_CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO10_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO10. - */ -struct ALT_SYSMGR_PINMUX_EMACIO10_s -{ - uint32_t sel : 2; /* emac0_rx_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO10. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO10_s ALT_SYSMGR_PINMUX_EMACIO10_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO10 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_OFST 0x28 - -/* - * Register : emac0_rx_d1 Mux Selection Register - EMACIO11 - * - * This register is used to control the peripherals connected to emac0_rx_d1 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac0_rx_d1 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_rx_d1 Mux Selection Field - sel - * - * Select peripheral signals connected emac0_rx_d1. - * - * 0 : Pin is connected to GPIO/LoanIO number 11. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.STP. - * - * 3 : Pin is connected to Peripheral signal RGMII0.RXD1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO11_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO11. - */ -struct ALT_SYSMGR_PINMUX_EMACIO11_s -{ - uint32_t sel : 2; /* emac0_rx_d1 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO11. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO11_s ALT_SYSMGR_PINMUX_EMACIO11_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO11 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_OFST 0x2c - -/* - * Register : emac0_rx_d2 Mux Selection Register - EMACIO12 - * - * This register is used to control the peripherals connected to emac0_rx_d2 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac0_rx_d2 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_rx_d2 Mux Selection Field - sel - * - * Select peripheral signals connected emac0_rx_d2. - * - * 0 : Pin is connected to GPIO/LoanIO number 12. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.DIR. - * - * 3 : Pin is connected to Peripheral signal RGMII0.RXD2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO12_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO12. - */ -struct ALT_SYSMGR_PINMUX_EMACIO12_s -{ - uint32_t sel : 2; /* emac0_rx_d2 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO12. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO12_s ALT_SYSMGR_PINMUX_EMACIO12_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO12 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_OFST 0x30 - -/* - * Register : emac0_rx_d3 Mux Selection Register - EMACIO13 - * - * This register is used to control the peripherals connected to emac0_rx_d3 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac0_rx_d3 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac0_rx_d3 Mux Selection Field - sel - * - * Select peripheral signals connected emac0_rx_d3. - * - * 0 : Pin is connected to GPIO/LoanIO number 13. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB1.NXT. - * - * 3 : Pin is connected to Peripheral signal RGMII0.RXD3. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO13_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO13. - */ -struct ALT_SYSMGR_PINMUX_EMACIO13_s -{ - uint32_t sel : 2; /* emac0_rx_d3 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO13. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO13_s ALT_SYSMGR_PINMUX_EMACIO13_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO13 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_OFST 0x34 - -/* - * Register : emac1_tx_clk Mux Selection Register - EMACIO14 - * - * This register is used to control the peripherals connected to emac1_tx_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [1:0] | RW | 0x0 | emac1_tx_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_tx_clk Mux Selection Field - sel - * - * Select peripheral signals connected emac1_tx_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 48. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal RGMII1.TX_CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO14_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO14. - */ -struct ALT_SYSMGR_PINMUX_EMACIO14_s -{ - uint32_t sel : 2; /* emac1_tx_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO14. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO14_s ALT_SYSMGR_PINMUX_EMACIO14_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO14 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_OFST 0x38 - -/* - * Register : emac1_tx_d0 Mux Selection Register - EMACIO15 - * - * This register is used to control the peripherals connected to emac1_tx_d0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac1_tx_d0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_tx_d0 Mux Selection Field - sel - * - * Select peripheral signals connected emac1_tx_d0. - * - * 0 : Pin is connected to GPIO/LoanIO number 49. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal RGMII1.TXD0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO15_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO15. - */ -struct ALT_SYSMGR_PINMUX_EMACIO15_s -{ - uint32_t sel : 2; /* emac1_tx_d0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO15. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO15_s ALT_SYSMGR_PINMUX_EMACIO15_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO15 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_OFST 0x3c - -/* - * Register : emac1_tx_d1 Mux Selection Register - EMACIO16 - * - * This register is used to control the peripherals connected to emac1_tx_d1 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac1_tx_d1 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_tx_d1 Mux Selection Field - sel - * - * Select peripheral signals connected emac1_tx_d1. - * - * 0 : Pin is connected to GPIO/LoanIO number 50. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal RGMII1.TXD1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO16_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO16. - */ -struct ALT_SYSMGR_PINMUX_EMACIO16_s -{ - uint32_t sel : 2; /* emac1_tx_d1 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO16. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO16_s ALT_SYSMGR_PINMUX_EMACIO16_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO16 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_OFST 0x40 - -/* - * Register : emac1_tx_ctl Mux Selection Register - EMACIO17 - * - * This register is used to control the peripherals connected to emac1_tx_ctl - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [1:0] | RW | 0x0 | emac1_tx_ctl Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_tx_ctl Mux Selection Field - sel - * - * Select peripheral signals connected emac1_tx_ctl. - * - * 0 : Pin is connected to GPIO/LoanIO number 51. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal RGMII1.TX_CTL. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO17_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO17. - */ -struct ALT_SYSMGR_PINMUX_EMACIO17_s -{ - uint32_t sel : 2; /* emac1_tx_ctl Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO17. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO17_s ALT_SYSMGR_PINMUX_EMACIO17_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO17 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_OFST 0x44 - -/* - * Register : emac1_rx_d0 Mux Selection Register - EMACIO18 - * - * This register is used to control the peripherals connected to emac1_rx_d0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac1_rx_d0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_rx_d0 Mux Selection Field - sel - * - * Select peripheral signals connected emac1_rx_d0. - * - * 0 : Pin is connected to GPIO/LoanIO number 52. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal RGMII1.RXD0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO18_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO18. - */ -struct ALT_SYSMGR_PINMUX_EMACIO18_s -{ - uint32_t sel : 2; /* emac1_rx_d0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO18. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO18_s ALT_SYSMGR_PINMUX_EMACIO18_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO18 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_OFST 0x48 - -/* - * Register : emac1_rx_d1 Mux Selection Register - EMACIO19 - * - * This register is used to control the peripherals connected to emac1_rx_d1 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac1_rx_d1 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_rx_d1 Mux Selection Field - sel - * - * Select peripheral signals connected emac1_rx_d1. - * - * 0 : Pin is connected to GPIO/LoanIO number 53. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal RGMII1.RXD1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_EMACIO19_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO19. - */ -struct ALT_SYSMGR_PINMUX_EMACIO19_s -{ - uint32_t sel : 2; /* emac1_rx_d1 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO19. */ -typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO19_s ALT_SYSMGR_PINMUX_EMACIO19_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO19 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_OFST 0x4c - -/* - * Register : sdmmc_cmd Mux Selection Register - FLASHIO0 - * - * This register is used to control the peripherals connected to sdmmc_cmd - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | sdmmc_cmd Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_cmd Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_cmd. - * - * 0 : Pin is connected to GPIO/LoanIO number 36. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.D0. - * - * 3 : Pin is connected to Peripheral signal SDMMC.CMD. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO0_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO0_s -{ - uint32_t sel : 2; /* sdmmc_cmd Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO0_s ALT_SYSMGR_PINMUX_FLSHIO0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO0 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_OFST 0x50 - -/* - * Register : sdmmc_pwren Mux Selection Register - FLASHIO1 - * - * This register is used to control the peripherals connected to sdmmc_pwren - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | sdmmc_pwren Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_pwren Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_pwren. - * - * 0 : Pin is connected to GPIO/LoanIO number 37. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.D1. - * - * 3 : Pin is connected to Peripheral signal SDMMC.PWREN. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO1_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO1_s -{ - uint32_t sel : 2; /* sdmmc_pwren Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO1_s ALT_SYSMGR_PINMUX_FLSHIO1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO1 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_OFST 0x54 - -/* - * Register : sdmmc_d0 Mux Selection Register - FLASHIO2 - * - * This register is used to control the peripherals connected to sdmmc_d0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | sdmmc_d0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_d0 Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_d0. - * - * 0 : Pin is connected to GPIO/LoanIO number 38. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.D2. - * - * 3 : Pin is connected to Peripheral signal SDMMC.D0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO2_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO2_s -{ - uint32_t sel : 2; /* sdmmc_d0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO2_s ALT_SYSMGR_PINMUX_FLSHIO2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO2 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_OFST 0x58 - -/* - * Register : sdmmc_d1 Mux Selection Register - FLASHIO3 - * - * This register is used to control the peripherals connected to sdmmc_d1 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | sdmmc_d1 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_d1 Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_d1. - * - * 0 : Pin is connected to GPIO/LoanIO number 39. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.D3. - * - * 3 : Pin is connected to Peripheral signal SDMMC.D1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO3_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO3_s -{ - uint32_t sel : 2; /* sdmmc_d1 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO3_s ALT_SYSMGR_PINMUX_FLSHIO3_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO3 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_OFST 0x5c - -/* - * Register : sdmmc_d4 Mux Selection Register - FLASHIO4 - * - * This register is used to control the peripherals connected to sdmmc_d4 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | sdmmc_d4 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_d4 Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_d4. - * - * 0 : Pin is connected to GPIO/LoanIO number 40. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.D4. - * - * 3 : Pin is connected to Peripheral signal SDMMC.D4. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO4_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO4_s -{ - uint32_t sel : 2; /* sdmmc_d4 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO4_s ALT_SYSMGR_PINMUX_FLSHIO4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO4 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_OFST 0x60 - -/* - * Register : sdmmc_d5 Mux Selection Register - FLASHIO5 - * - * This register is used to control the peripherals connected to sdmmc_d5 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | sdmmc_d5 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_d5 Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_d5. - * - * 0 : Pin is connected to GPIO/LoanIO number 41. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.D5. - * - * 3 : Pin is connected to Peripheral signal SDMMC.D5. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO5_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO5_s -{ - uint32_t sel : 2; /* sdmmc_d5 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO5_s ALT_SYSMGR_PINMUX_FLSHIO5_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO5 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_OFST 0x64 - -/* - * Register : sdmmc_d6 Mux Selection Register - FLASHIO6 - * - * This register is used to control the peripherals connected to sdmmc_d6 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | sdmmc_d6 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_d6 Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_d6. - * - * 0 : Pin is connected to GPIO/LoanIO number 42. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.D6. - * - * 3 : Pin is connected to Peripheral signal SDMMC.D6. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO6_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO6_s -{ - uint32_t sel : 2; /* sdmmc_d6 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO6_s ALT_SYSMGR_PINMUX_FLSHIO6_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO6 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_OFST 0x68 - -/* - * Register : sdmmc_d7 Mux Selection Register - FLASHIO7 - * - * This register is used to control the peripherals connected to sdmmc_d7 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | sdmmc_d7 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_d7 Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_d7. - * - * 0 : Pin is connected to GPIO/LoanIO number 43. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.D7. - * - * 3 : Pin is connected to Peripheral signal SDMMC.D7. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO7_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO7_s -{ - uint32_t sel : 2; /* sdmmc_d7 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO7_s ALT_SYSMGR_PINMUX_FLSHIO7_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO7 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_OFST 0x6c - -/* - * Register : sdmmc_clk_in Mux Selection Register - FLASHIO8 - * - * This register is used to control the peripherals connected to sdmmc_clk_in - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [1:0] | RW | 0x0 | sdmmc_clk_in Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_clk_in Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_clk_in. - * - * 0 : Pin is connected to GPIO/LoanIO number 44. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.CLK. - * - * 3 : Pin is connected to Peripheral signal SDMMC.CLK_IN. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO8_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO8_s -{ - uint32_t sel : 2; /* sdmmc_clk_in Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO8_s ALT_SYSMGR_PINMUX_FLSHIO8_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO8 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_OFST 0x70 - -/* - * Register : sdmmc_clk Mux Selection Register - FLASHIO9 - * - * This register is used to control the peripherals connected to sdmmc_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | sdmmc_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_clk Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 45. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.STP. - * - * 3 : Pin is connected to Peripheral signal SDMMC.CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO9_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO9_s -{ - uint32_t sel : 2; /* sdmmc_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO9_s ALT_SYSMGR_PINMUX_FLSHIO9_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO9 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_OFST 0x74 - -/* - * Register : sdmmc_d2 Mux Selection Register - FLASHIO10 - * - * This register is used to control the peripherals connected to sdmmc_d2 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | sdmmc_d2 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_d2 Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_d2. - * - * 0 : Pin is connected to GPIO/LoanIO number 46. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.DIR. - * - * 3 : Pin is connected to Peripheral signal SDMMC.D2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO10_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO10_s -{ - uint32_t sel : 2; /* sdmmc_d2 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO10_s ALT_SYSMGR_PINMUX_FLSHIO10_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO10 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_OFST 0x78 - -/* - * Register : sdmmc_d3 Mux Selection Register - FLASHIO11 - * - * This register is used to control the peripherals connected to sdmmc_d3 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | sdmmc_d3 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : sdmmc_d3 Mux Selection Field - sel - * - * Select peripheral signals connected sdmmc_d3. - * - * 0 : Pin is connected to GPIO/LoanIO number 47. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal USB0.NXT. - * - * 3 : Pin is connected to Peripheral signal SDMMC.D3. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_FLSHIO11_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. - */ -struct ALT_SYSMGR_PINMUX_FLSHIO11_s -{ - uint32_t sel : 2; /* sdmmc_d3 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. */ -typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO11_s ALT_SYSMGR_PINMUX_FLSHIO11_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO11 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_OFST 0x7c - -/* - * Register : trace_clk Mux Selection Register - GENERALIO0 - * - * This register is used to control the peripherals connected to trace_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | trace_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : trace_clk Mux Selection Field - sel - * - * Select peripheral signals connected trace_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 48. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal TRACE.CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO0_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO0_s -{ - uint32_t sel : 2; /* trace_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO0_s ALT_SYSMGR_PINMUX_GENERALIO0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO0 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_OFST 0x80 - -/* - * Register : trace_d0 Mux Selection Register - GENERALIO1 - * - * This register is used to control the peripherals connected to trace_d0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | trace_d0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : trace_d0 Mux Selection Field - sel - * - * Select peripheral signals connected trace_d0. - * - * 0 : Pin is connected to GPIO/LoanIO number 49. - * - * 1 : Pin is connected to Peripheral signal UART0.RX. - * - * 2 : Pin is connected to Peripheral signal SPIS0.CLK. - * - * 3 : Pin is connected to Peripheral signal TRACE.D0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO1_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO1_s -{ - uint32_t sel : 2; /* trace_d0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO1_s ALT_SYSMGR_PINMUX_GENERALIO1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO1 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_OFST 0x84 - -/* - * Register : trace_d1 Mux Selection Register - GENERALIO2 - * - * This register is used to control the peripherals connected to trace_d1 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | trace_d1 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : trace_d1 Mux Selection Field - sel - * - * Select peripheral signals connected trace_d1. - * - * 0 : Pin is connected to GPIO/LoanIO number 50. - * - * 1 : Pin is connected to Peripheral signal UART0.TX. - * - * 2 : Pin is connected to Peripheral signal SPIS0.MOSI. - * - * 3 : Pin is connected to Peripheral signal TRACE.D1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO2_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO2_s -{ - uint32_t sel : 2; /* trace_d1 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO2_s ALT_SYSMGR_PINMUX_GENERALIO2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO2 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_OFST 0x88 - -/* - * Register : trace_d2 Mux Selection Register - GENERALIO3 - * - * This register is used to control the peripherals connected to trace_d2 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | trace_d2 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : trace_d2 Mux Selection Field - sel - * - * Select peripheral signals connected trace_d2. - * - * 0 : Pin is connected to GPIO/LoanIO number 51. - * - * 1 : Pin is connected to Peripheral signal I2C1.SDA. - * - * 2 : Pin is connected to Peripheral signal SPIS0.MISO. - * - * 3 : Pin is connected to Peripheral signal TRACE.D2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO3_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO3_s -{ - uint32_t sel : 2; /* trace_d2 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO3_s ALT_SYSMGR_PINMUX_GENERALIO3_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO3 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_OFST 0x8c - -/* - * Register : trace_d3 Mux Selection Register - GENERALIO4 - * - * This register is used to control the peripherals connected to trace_d3 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | trace_d3 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : trace_d3 Mux Selection Field - sel - * - * Select peripheral signals connected trace_d3. - * - * 0 : Pin is connected to GPIO/LoanIO number 52. - * - * 1 : Pin is connected to Peripheral signal I2C1.SCL. - * - * 2 : Pin is connected to Peripheral signal SPIS0.SS0. - * - * 3 : Pin is connected to Peripheral signal TRACE.D3. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO4_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO4_s -{ - uint32_t sel : 2; /* trace_d3 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO4_s ALT_SYSMGR_PINMUX_GENERALIO4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO4 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_OFST 0x90 - -/* - * Register : trace_d4 Mux Selection Register - GENERALIO5 - * - * This register is used to control the peripherals connected to trace_d4 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | trace_d4 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : trace_d4 Mux Selection Field - sel - * - * Select peripheral signals connected trace_d4. - * - * 0 : Pin is connected to GPIO/LoanIO number 53. - * - * 1 : Pin is connected to Peripheral signal CAN1.RX. - * - * 2 : Pin is connected to Peripheral signal SPIS1.CLK. - * - * 3 : Pin is connected to Peripheral signal TRACE.D4. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO5_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO5_s -{ - uint32_t sel : 2; /* trace_d4 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO5_s ALT_SYSMGR_PINMUX_GENERALIO5_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO5 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_OFST 0x94 - -/* - * Register : trace_d5 Mux Selection Register - GENERALIO6 - * - * This register is used to control the peripherals connected to trace_d5 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | trace_d5 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : trace_d5 Mux Selection Field - sel - * - * Select peripheral signals connected trace_d5. - * - * 0 : Pin is connected to GPIO/LoanIO number 54. - * - * 1 : Pin is connected to Peripheral signal CAN1.TX. - * - * 2 : Pin is connected to Peripheral signal SPIS1.MOSI. - * - * 3 : Pin is connected to Peripheral signal TRACE.D5. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO6_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO6_s -{ - uint32_t sel : 2; /* trace_d5 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO6_s ALT_SYSMGR_PINMUX_GENERALIO6_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO6 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_OFST 0x98 - -/* - * Register : trace_d6 Mux Selection Register - GENERALIO7 - * - * This register is used to control the peripherals connected to trace_d6 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | trace_d6 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : trace_d6 Mux Selection Field - sel - * - * Select peripheral signals connected trace_d6. - * - * 0 : Pin is connected to GPIO/LoanIO number 55. - * - * 1 : Pin is connected to Peripheral signal I2C0.SDA. - * - * 2 : Pin is connected to Peripheral signal SPIS1.SS0. - * - * 3 : Pin is connected to Peripheral signal TRACE.D6. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO7_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO7_s -{ - uint32_t sel : 2; /* trace_d6 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO7_s ALT_SYSMGR_PINMUX_GENERALIO7_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO7 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_OFST 0x9c - -/* - * Register : trace_d7 Mux Selection Register - GENERALIO8 - * - * This register is used to control the peripherals connected to trace_d7 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | trace_d7 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : trace_d7 Mux Selection Field - sel - * - * Select peripheral signals connected trace_d7. - * - * 0 : Pin is connected to GPIO/LoanIO number 56. - * - * 1 : Pin is connected to Peripheral signal I2C0.SCL. - * - * 2 : Pin is connected to Peripheral signal SPIS1.MISO. - * - * 3 : Pin is connected to Peripheral signal TRACE.D7. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO8_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO8_s -{ - uint32_t sel : 2; /* trace_d7 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO8_s ALT_SYSMGR_PINMUX_GENERALIO8_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO8 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_OFST 0xa0 - -/* - * Register : spim0_clk Mux Selection Register - GENERALIO9 - * - * This register is used to control the peripherals connected to spim0_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | spim0_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spim0_clk Mux Selection Field - sel - * - * Select peripheral signals connected spim0_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 57. - * - * 1 : Pin is connected to Peripheral signal UART0.CTS. - * - * 2 : Pin is connected to Peripheral signal I2C1.SDA. - * - * 3 : Pin is connected to Peripheral signal SPIM0.CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO9_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO9_s -{ - uint32_t sel : 2; /* spim0_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO9_s ALT_SYSMGR_PINMUX_GENERALIO9_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO9 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_OFST 0xa4 - -/* - * Register : spim0_mosi Mux Selection Register - GENERALIO10 - * - * This register is used to control the peripherals connected to spim0_mosi - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [1:0] | RW | 0x0 | spim0_mosi Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spim0_mosi Mux Selection Field - sel - * - * Select peripheral signals connected spim0_mosi. - * - * 0 : Pin is connected to GPIO/LoanIO number 58. - * - * 1 : Pin is connected to Peripheral signal UART0.RTS. - * - * 2 : Pin is connected to Peripheral signal I2C1.SCL. - * - * 3 : Pin is connected to Peripheral signal SPIM0.MOSI. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO10_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO10_s -{ - uint32_t sel : 2; /* spim0_mosi Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO10_s ALT_SYSMGR_PINMUX_GENERALIO10_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO10 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_OFST 0xa8 - -/* - * Register : spim0_miso Mux Selection Register - GENERALIO11 - * - * This register is used to control the peripherals connected to spim0_miso - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [1:0] | RW | 0x0 | spim0_miso Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spim0_miso Mux Selection Field - sel - * - * Select peripheral signals connected spim0_miso. - * - * 0 : Pin is connected to GPIO/LoanIO number 59. - * - * 1 : Pin is connected to Peripheral signal UART1.CTS. - * - * 2 : Pin is connected to Peripheral signal CAN1.RX. - * - * 3 : Pin is connected to Peripheral signal SPIM0.MISO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO11_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO11_s -{ - uint32_t sel : 2; /* spim0_miso Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO11_s ALT_SYSMGR_PINMUX_GENERALIO11_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO11 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_OFST 0xac - -/* - * Register : spim0_ss0 Mux Selection Register - GENERALIO12 - * - * This register is used to control the peripherals connected to spim0_ss0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | spim0_ss0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spim0_ss0 Mux Selection Field - sel - * - * Select peripheral signals connected spim0_ss0. - * - * 0 : Pin is connected to GPIO/LoanIO number 60. - * - * 1 : Pin is connected to Peripheral signal UART1.RTS. - * - * 2 : Pin is connected to Peripheral signal CAN1.TX. - * - * 3 : Pin is connected to Peripheral signal SPIM0.SS0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO12_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO12_s -{ - uint32_t sel : 2; /* spim0_ss0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO12_s ALT_SYSMGR_PINMUX_GENERALIO12_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO12 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_OFST 0xb0 - -/* - * Register : uart0_rx Mux Selection Register - GENERALIO13 - * - * This register is used to control the peripherals connected to uart0_rx - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | uart0_rx Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : uart0_rx Mux Selection Field - sel - * - * Select peripheral signals connected uart0_rx. - * - * 0 : Pin is connected to GPIO/LoanIO number 61. - * - * 1 : Pin is connected to Peripheral signal SPIM0.SS1. - * - * 2 : Pin is connected to Peripheral signal CAN0.RX. - * - * 3 : Pin is connected to Peripheral signal UART0.RX. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO13_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO13_s -{ - uint32_t sel : 2; /* uart0_rx Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO13_s ALT_SYSMGR_PINMUX_GENERALIO13_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO13 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_OFST 0xb4 - -/* - * Register : uart0_tx Mux Selection Register - GENERALIO14 - * - * This register is used to control the peripherals connected to uart0_tx - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | uart0_tx Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : uart0_tx Mux Selection Field - sel - * - * Select peripheral signals connected uart0_tx. - * - * 0 : Pin is connected to GPIO/LoanIO number 62. - * - * 1 : Pin is connected to Peripheral signal SPIM1.SS1. - * - * 2 : Pin is connected to Peripheral signal CAN0.TX. - * - * 3 : Pin is connected to Peripheral signal UART0.TX. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO14_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO14_s -{ - uint32_t sel : 2; /* uart0_tx Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO14_s ALT_SYSMGR_PINMUX_GENERALIO14_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO14 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_OFST 0xb8 - -/* - * Register : i2c0_sda Mux Selection Register - GENERALIO15 - * - * This register is used to control the peripherals connected to i2c0_sda - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | i2c0_sda Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : i2c0_sda Mux Selection Field - sel - * - * Select peripheral signals connected i2c0_sda. - * - * 0 : Pin is connected to GPIO/LoanIO number 63. - * - * 1 : Pin is connected to Peripheral signal SPIM1.CLK. - * - * 2 : Pin is connected to Peripheral signal UART1.RX. - * - * 3 : Pin is connected to Peripheral signal I2C0.SDA. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO15_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO15_s -{ - uint32_t sel : 2; /* i2c0_sda Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO15_s ALT_SYSMGR_PINMUX_GENERALIO15_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO15 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_OFST 0xbc - -/* - * Register : i2c0_scl Mux Selection Register - GENERALIO16 - * - * This register is used to control the peripherals connected to i2c0_scl - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | i2c0_scl Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : i2c0_scl Mux Selection Field - sel - * - * Select peripheral signals connected i2c0_scl. - * - * 0 : Pin is connected to GPIO/LoanIO number 64. - * - * 1 : Pin is connected to Peripheral signal SPIM1.MOSI. - * - * 2 : Pin is connected to Peripheral signal UART1.TX. - * - * 3 : Pin is connected to Peripheral signal I2C0.SCL. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO16_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO16_s -{ - uint32_t sel : 2; /* i2c0_scl Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO16_s ALT_SYSMGR_PINMUX_GENERALIO16_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO16 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_OFST 0xc0 - -/* - * Register : can0_rx Mux Selection Register - GENERALIO17 - * - * This register is used to control the peripherals connected to can0_rx - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [1:0] | RW | 0x0 | can0_rx Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : can0_rx Mux Selection Field - sel - * - * Select peripheral signals connected can0_rx. - * - * 0 : Pin is connected to GPIO/LoanIO number 65. - * - * 1 : Pin is connected to Peripheral signal SPIM1.MISO. - * - * 2 : Pin is connected to Peripheral signal UART0.RX. - * - * 3 : Pin is connected to Peripheral signal CAN0.RX. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO17_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO17_s -{ - uint32_t sel : 2; /* can0_rx Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO17_s ALT_SYSMGR_PINMUX_GENERALIO17_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO17 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_OFST 0xc4 - -/* - * Register : can0_tx Mux Selection Register - GENERALIO18 - * - * This register is used to control the peripherals connected to can0_tx - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [1:0] | RW | 0x0 | can0_tx Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : can0_tx Mux Selection Field - sel - * - * Select peripheral signals connected can0_tx. - * - * 0 : Pin is connected to GPIO/LoanIO number 66. - * - * 1 : Pin is connected to Peripheral signal SPIM1.SS0. - * - * 2 : Pin is connected to Peripheral signal UART0.TX. - * - * 3 : Pin is connected to Peripheral signal CAN0.TX. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO18_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO18_s -{ - uint32_t sel : 2; /* can0_tx Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO18_s ALT_SYSMGR_PINMUX_GENERALIO18_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO18 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_OFST 0xc8 - -/* - * Register : spis1_clk Mux Selection Register - GENERALIO19 - * - * This register is used to control the peripherals connected to spis1_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | spis1_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spis1_clk Mux Selection Field - sel - * - * Select peripheral signals connected spis1_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 67. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM1.CLK. - * - * 3 : Pin is connected to Peripheral signal SPIS1.CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO19_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO19_s -{ - uint32_t sel : 2; /* spis1_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO19_s ALT_SYSMGR_PINMUX_GENERALIO19_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO19 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_OFST 0xcc - -/* - * Register : spis1_mosi Mux Selection Register - GENERALIO20 - * - * This register is used to control the peripherals connected to spis1_mosi - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [1:0] | RW | 0x0 | spis1_mosi Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spis1_mosi Mux Selection Field - sel - * - * Select peripheral signals connected spis1_mosi. - * - * 0 : Pin is connected to GPIO/LoanIO number 68. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM1.MOSI. - * - * 3 : Pin is connected to Peripheral signal SPIS1.MOSI. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO20_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO20_s -{ - uint32_t sel : 2; /* spis1_mosi Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO20_s ALT_SYSMGR_PINMUX_GENERALIO20_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO20 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_OFST 0xd0 - -/* - * Register : spis1_miso Mux Selection Register - GENERALIO21 - * - * This register is used to control the peripherals connected to spis1_miso - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [1:0] | RW | 0x0 | spis1_miso Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spis1_miso Mux Selection Field - sel - * - * Select peripheral signals connected spis1_miso. - * - * 0 : Pin is connected to GPIO/LoanIO number 69. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM1.MISO. - * - * 3 : Pin is connected to Peripheral signal SPIS1.MISO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO21_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO21_s -{ - uint32_t sel : 2; /* spis1_miso Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO21_s ALT_SYSMGR_PINMUX_GENERALIO21_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO21 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_OFST 0xd4 - -/* - * Register : spis1_ss0 Mux Selection Register - GENERALIO22 - * - * This register is used to control the peripherals connected to spis1_ss0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | spis1_ss0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spis1_ss0 Mux Selection Field - sel - * - * Select peripheral signals connected spis1_ss0. - * - * 0 : Pin is connected to GPIO/LoanIO number 70. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM1.SS0. - * - * 3 : Pin is connected to Peripheral signal SPIS1.SS0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO22_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO22_s -{ - uint32_t sel : 2; /* spis1_ss0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO22_s ALT_SYSMGR_PINMUX_GENERALIO22_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO22 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_OFST 0xd8 - -/* - * Register : uart1_rx Mux Selection Register - GENERALIO23 - * - * This register is used to control the peripherals connected to uart1_rx - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | uart1_rx Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : uart1_rx Mux Selection Field - sel - * - * Select peripheral signals connected uart1_rx. - * - * 0 : Pin is connected to GPIO/LoanIO number 62. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM1.SS1. - * - * 3 : Pin is connected to Peripheral signal UART1.RX. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO23_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO23_s -{ - uint32_t sel : 2; /* uart1_rx Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO23_s ALT_SYSMGR_PINMUX_GENERALIO23_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO23 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_OFST 0xdc - -/* - * Register : uart1_tx Mux Selection Register - GENERALIO24 - * - * This register is used to control the peripherals connected to uart1_tx - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | uart1_tx Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : uart1_tx Mux Selection Field - sel - * - * Select peripheral signals connected uart1_tx. - * - * 0 : Pin is connected to GPIO/LoanIO number 63. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM0.CLK. - * - * 3 : Pin is connected to Peripheral signal UART1.TX. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO24_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO24_s -{ - uint32_t sel : 2; /* uart1_tx Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO24_s ALT_SYSMGR_PINMUX_GENERALIO24_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO24 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_OFST 0xe0 - -/* - * Register : i2c1_sda Mux Selection Register - GENERALIO25 - * - * This register is used to control the peripherals connected to i2c1_sda - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | i2c1_sda Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : i2c1_sda Mux Selection Field - sel - * - * Select peripheral signals connected i2c1_sda. - * - * 0 : Pin is connected to GPIO/LoanIO number 64. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM0.MOSI. - * - * 3 : Pin is connected to Peripheral signal I2C1.SDA. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO25_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO25_s -{ - uint32_t sel : 2; /* i2c1_sda Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO25_s ALT_SYSMGR_PINMUX_GENERALIO25_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO25 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_OFST 0xe4 - -/* - * Register : i2c1_scl Mux Selection Register - GENERALIO26 - * - * This register is used to control the peripherals connected to i2c1_scl - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | i2c1_scl Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : i2c1_scl Mux Selection Field - sel - * - * Select peripheral signals connected i2c1_scl. - * - * 0 : Pin is connected to GPIO/LoanIO number 65. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM0.MISO. - * - * 3 : Pin is connected to Peripheral signal I2C1.SCL. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO26_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO26_s -{ - uint32_t sel : 2; /* i2c1_scl Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO26_s ALT_SYSMGR_PINMUX_GENERALIO26_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO26 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_OFST 0xe8 - -/* - * Register : spim0_ss0_alt Mux Selection Register - GENERALIO27 - * - * This register is used to control the peripherals connected to spim0_ss0_alt - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------- - * [1:0] | RW | 0x0 | spim0_ss0_alt Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spim0_ss0_alt Mux Selection Field - sel - * - * Select peripheral signals connected spim0_ss0_alt. - * - * 0 : Pin is connected to GPIO/LoanIO number 66. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM0.SS0. - * - * 3 : Pin is connected to Peripheral signal not applicable. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO27_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO27_s -{ - uint32_t sel : 2; /* spim0_ss0_alt Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO27_s ALT_SYSMGR_PINMUX_GENERALIO27_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO27 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_OFST 0xec - -/* - * Register : spis0_clk Mux Selection Register - GENERALIO28 - * - * This register is used to control the peripherals connected to spis0_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | spis0_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spis0_clk Mux Selection Field - sel - * - * Select peripheral signals connected spis0_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 67. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal SPIM0.SS1. - * - * 3 : Pin is connected to Peripheral signal SPIS0.CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO28_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO28_s -{ - uint32_t sel : 2; /* spis0_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO28_s ALT_SYSMGR_PINMUX_GENERALIO28_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO28 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_OFST 0xf0 - -/* - * Register : spis0_mosi Mux Selection Register - GENERALIO29 - * - * This register is used to control the peripherals connected to spis0_mosi - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [1:0] | RW | 0x0 | spis0_mosi Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spis0_mosi Mux Selection Field - sel - * - * Select peripheral signals connected spis0_mosi. - * - * 0 : Pin is connected to GPIO/LoanIO number 68. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal SPIS0.MOSI. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO29_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO29_s -{ - uint32_t sel : 2; /* spis0_mosi Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO29_s ALT_SYSMGR_PINMUX_GENERALIO29_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO29 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_OFST 0xf4 - -/* - * Register : spis0_miso Mux Selection Register - GENERALIO30 - * - * This register is used to control the peripherals connected to spis0_miso - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [1:0] | RW | 0x0 | spis0_miso Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spis0_miso Mux Selection Field - sel - * - * Select peripheral signals connected spis0_miso. - * - * 0 : Pin is connected to GPIO/LoanIO number 69. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal SPIS0.MISO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO30_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO30_s -{ - uint32_t sel : 2; /* spis0_miso Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO30_s ALT_SYSMGR_PINMUX_GENERALIO30_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO30 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_OFST 0xf8 - -/* - * Register : spis0_ss0 Mux Selection Register - GENERALIO31 - * - * This register is used to control the peripherals connected to spis0_ss0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | spis0_ss0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : spis0_ss0 Mux Selection Field - sel - * - * Select peripheral signals connected spis0_ss0. - * - * 0 : Pin is connected to GPIO/LoanIO number 70. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal SPIS0.SS0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GENERALIO31_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. - */ -struct ALT_SYSMGR_PINMUX_GENERALIO31_s -{ - uint32_t sel : 2; /* spis0_ss0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO31_s ALT_SYSMGR_PINMUX_GENERALIO31_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO31 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_OFST 0xfc - -/* - * Register : nand_ale Mux Selection Register - MIXED1IO0 - * - * This register is used to control the peripherals connected to nand_ale - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_ale Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_ale Mux Selection Field - sel - * - * Select peripheral signals connected nand_ale. - * - * 0 : Pin is connected to GPIO/LoanIO number 14. - * - * 1 : Pin is connected to Peripheral signal QSPI.SS3. - * - * 2 : Pin is connected to Peripheral signal RGMII1.TX_CLK. - * - * 3 : Pin is connected to Peripheral signal NAND.ale. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO0_s -{ - uint32_t sel : 2; /* nand_ale Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO0_s ALT_SYSMGR_PINMUX_MIXED1IO0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO0 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_OFST 0x100 - -/* - * Register : nand_ce Mux Selection Register - MIXED1IO1 - * - * This register is used to control the peripherals connected to nand_ce - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [1:0] | RW | 0x0 | nand_ce Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_ce Mux Selection Field - sel - * - * Select peripheral signals connected nand_ce. - * - * 0 : Pin is connected to GPIO/LoanIO number 15. - * - * 1 : Pin is connected to Peripheral signal USB1.D0. - * - * 2 : Pin is connected to Peripheral signal RGMII1.TXD0. - * - * 3 : Pin is connected to Peripheral signal NAND.ce. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO1_s -{ - uint32_t sel : 2; /* nand_ce Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO1_s ALT_SYSMGR_PINMUX_MIXED1IO1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO1 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_OFST 0x104 - -/* - * Register : nand_cle Mux Selection Register - MIXED1IO2 - * - * This register is used to control the peripherals connected to nand_cle - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_cle Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_cle Mux Selection Field - sel - * - * Select peripheral signals connected nand_cle. - * - * 0 : Pin is connected to GPIO/LoanIO number 16. - * - * 1 : Pin is connected to Peripheral signal USB1.D1. - * - * 2 : Pin is connected to Peripheral signal RGMII1.TXD1. - * - * 3 : Pin is connected to Peripheral signal NAND.cle. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO2_s -{ - uint32_t sel : 2; /* nand_cle Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO2_s ALT_SYSMGR_PINMUX_MIXED1IO2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO2 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_OFST 0x108 - -/* - * Register : nand_re Mux Selection Register - MIXED1IO3 - * - * This register is used to control the peripherals connected to nand_re - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [1:0] | RW | 0x0 | nand_re Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_re Mux Selection Field - sel - * - * Select peripheral signals connected nand_re. - * - * 0 : Pin is connected to GPIO/LoanIO number 17. - * - * 1 : Pin is connected to Peripheral signal USB1.D2. - * - * 2 : Pin is connected to Peripheral signal RGMII1.TXD2. - * - * 3 : Pin is connected to Peripheral signal NAND.re. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO3_s -{ - uint32_t sel : 2; /* nand_re Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO3_s ALT_SYSMGR_PINMUX_MIXED1IO3_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO3 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_OFST 0x10c - -/* - * Register : nand_rb Mux Selection Register - MIXED1IO4 - * - * This register is used to control the peripherals connected to nand_rb - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [1:0] | RW | 0x0 | nand_rb Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_rb Mux Selection Field - sel - * - * Select peripheral signals connected nand_rb. - * - * 0 : Pin is connected to GPIO/LoanIO number 18. - * - * 1 : Pin is connected to Peripheral signal USB1.D3. - * - * 2 : Pin is connected to Peripheral signal RGMII1.TXD3. - * - * 3 : Pin is connected to Peripheral signal NAND.rb. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO4_s -{ - uint32_t sel : 2; /* nand_rb Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO4_s ALT_SYSMGR_PINMUX_MIXED1IO4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO4 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_OFST 0x110 - -/* - * Register : nand_dq0 Mux Selection Register - MIXED1IO5 - * - * This register is used to control the peripherals connected to nand_dq0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_dq0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_dq0 Mux Selection Field - sel - * - * Select peripheral signals connected nand_dq0. - * - * 0 : Pin is connected to GPIO/LoanIO number 19. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal RGMII1.RXD0. - * - * 3 : Pin is connected to Peripheral signal NAND.dq0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO5_s -{ - uint32_t sel : 2; /* nand_dq0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO5_s ALT_SYSMGR_PINMUX_MIXED1IO5_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO5 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_OFST 0x114 - -/* - * Register : nand_dq1 Mux Selection Register - MIXED1IO6 - * - * This register is used to control the peripherals connected to nand_dq1 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_dq1 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_dq1 Mux Selection Field - sel - * - * Select peripheral signals connected nand_dq1. - * - * 0 : Pin is connected to GPIO/LoanIO number 20. - * - * 1 : Pin is connected to Peripheral signal I2C3.SDA. - * - * 2 : Pin is connected to Peripheral signal RGMII1.MDIO. - * - * 3 : Pin is connected to Peripheral signal NAND.dq1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO6_s -{ - uint32_t sel : 2; /* nand_dq1 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO6_s ALT_SYSMGR_PINMUX_MIXED1IO6_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO6 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_OFST 0x118 - -/* - * Register : nand_dq2 Mux Selection Register - MIXED1IO7 - * - * This register is used to control the peripherals connected to nand_dq2 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_dq2 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_dq2 Mux Selection Field - sel - * - * Select peripheral signals connected nand_dq2. - * - * 0 : Pin is connected to GPIO/LoanIO number 21. - * - * 1 : Pin is connected to Peripheral signal I2C3.SCL. - * - * 2 : Pin is connected to Peripheral signal RGMII1.MDC. - * - * 3 : Pin is connected to Peripheral signal NAND.dq2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO7_s -{ - uint32_t sel : 2; /* nand_dq2 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO7_s ALT_SYSMGR_PINMUX_MIXED1IO7_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO7 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_OFST 0x11c - -/* - * Register : nand_dq3 Mux Selection Register - MIXED1IO8 - * - * This register is used to control the peripherals connected to nand_dq3 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_dq3 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_dq3 Mux Selection Field - sel - * - * Select peripheral signals connected nand_dq3. - * - * 0 : Pin is connected to GPIO/LoanIO number 22. - * - * 1 : Pin is connected to Peripheral signal USB1.D4. - * - * 2 : Pin is connected to Peripheral signal RGMII1.RX_CTL. - * - * 3 : Pin is connected to Peripheral signal NAND.dq3. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO8_s -{ - uint32_t sel : 2; /* nand_dq3 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO8_s ALT_SYSMGR_PINMUX_MIXED1IO8_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO8 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_OFST 0x120 - -/* - * Register : nand_dq4 Mux Selection Register - MIXED1IO9 - * - * This register is used to control the peripherals connected to nand_dq4 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_dq4 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_dq4 Mux Selection Field - sel - * - * Select peripheral signals connected nand_dq4. - * - * 0 : Pin is connected to GPIO/LoanIO number 23. - * - * 1 : Pin is connected to Peripheral signal USB1.D5. - * - * 2 : Pin is connected to Peripheral signal RGMII1.TX_CTL. - * - * 3 : Pin is connected to Peripheral signal NAND.dq4. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO9_s -{ - uint32_t sel : 2; /* nand_dq4 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO9_s ALT_SYSMGR_PINMUX_MIXED1IO9_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO9 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_OFST 0x124 - -/* - * Register : nand_dq5 Mux Selection Register - MIXED1IO10 - * - * This register is used to control the peripherals connected to nand_dq5 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_dq5 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_dq5 Mux Selection Field - sel - * - * Select peripheral signals connected nand_dq5. - * - * 0 : Pin is connected to GPIO/LoanIO number 24. - * - * 1 : Pin is connected to Peripheral signal USB1.D6. - * - * 2 : Pin is connected to Peripheral signal RGMII1.RX_CLK. - * - * 3 : Pin is connected to Peripheral signal NAND.dq5. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO10_s -{ - uint32_t sel : 2; /* nand_dq5 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO10_s ALT_SYSMGR_PINMUX_MIXED1IO10_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO10 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_OFST 0x128 - -/* - * Register : nand_dq6 Mux Selection Register - MIXED1IO11 - * - * This register is used to control the peripherals connected to nand_dq6 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_dq6 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_dq6 Mux Selection Field - sel - * - * Select peripheral signals connected nand_dq6. - * - * 0 : Pin is connected to GPIO/LoanIO number 25. - * - * 1 : Pin is connected to Peripheral signal USB1.D7. - * - * 2 : Pin is connected to Peripheral signal RGMII1.RXD1. - * - * 3 : Pin is connected to Peripheral signal NAND.dq6. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO11_s -{ - uint32_t sel : 2; /* nand_dq6 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO11_s ALT_SYSMGR_PINMUX_MIXED1IO11_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO11 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_OFST 0x12c - -/* - * Register : nand_dq7 Mux Selection Register - MIXED1IO12 - * - * This register is used to control the peripherals connected to nand_dq7 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | nand_dq7 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_dq7 Mux Selection Field - sel - * - * Select peripheral signals connected nand_dq7. - * - * 0 : Pin is connected to GPIO/LoanIO number 26. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal RGMII1.RXD2. - * - * 3 : Pin is connected to Peripheral signal NAND.dq7. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO12_s -{ - uint32_t sel : 2; /* nand_dq7 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO12_s ALT_SYSMGR_PINMUX_MIXED1IO12_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO12 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_OFST 0x130 - -/* - * Register : nand_wp Mux Selection Register - MIXED1IO13 - * - * This register is used to control the peripherals connected to nand_wp - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [1:0] | RW | 0x0 | nand_wp Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_wp Mux Selection Field - sel - * - * Select peripheral signals connected nand_wp. - * - * 0 : Pin is connected to GPIO/LoanIO number 27. - * - * 1 : Pin is connected to Peripheral signal QSPI.SS2. - * - * 2 : Pin is connected to Peripheral signal RGMII1.RXD3. - * - * 3 : Pin is connected to Peripheral signal NAND.wp. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO13_s -{ - uint32_t sel : 2; /* nand_wp Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO13_s ALT_SYSMGR_PINMUX_MIXED1IO13_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO13 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_OFST 0x134 - -/* - * Register : nand_we Mux Selection Register - MIXED1IO14 - * - * This register is used to control the peripherals connected to nand_we - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [1:0] | RW | 0x0 | nand_we Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : nand_we Mux Selection Field - sel - * - * Select peripheral signals connected nand_we. - * - * 0 : Pin is connected to GPIO/LoanIO number 28. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal QSPI.SS1. - * - * 3 : Pin is connected to Peripheral signal NAND.we. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO14_s -{ - uint32_t sel : 2; /* nand_we Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO14_s ALT_SYSMGR_PINMUX_MIXED1IO14_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO14 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_OFST 0x138 - -/* - * Register : qspi_io0 Mux Selection Register - MIXED1IO15 - * - * This register is used to control the peripherals connected to qspi_io0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | qspi_io0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : qspi_io0 Mux Selection Field - sel - * - * Select peripheral signals connected qspi_io0. - * - * 0 : Pin is connected to GPIO/LoanIO number 29. - * - * 1 : Pin is connected to Peripheral signal USB1.CLK. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal QSPI.IO0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO15_s -{ - uint32_t sel : 2; /* qspi_io0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO15_s ALT_SYSMGR_PINMUX_MIXED1IO15_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO15 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_OFST 0x13c - -/* - * Register : qspi_io1 Mux Selection Register - MIXED1IO16 - * - * This register is used to control the peripherals connected to qspi_io1 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | qspi_io1 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : qspi_io1 Mux Selection Field - sel - * - * Select peripheral signals connected qspi_io1. - * - * 0 : Pin is connected to GPIO/LoanIO number 30. - * - * 1 : Pin is connected to Peripheral signal USB1.STP. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal QSPI.IO1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO16_s -{ - uint32_t sel : 2; /* qspi_io1 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO16_s ALT_SYSMGR_PINMUX_MIXED1IO16_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO16 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_OFST 0x140 - -/* - * Register : qspi_io2 Mux Selection Register - MIXED1IO17 - * - * This register is used to control the peripherals connected to qspi_io2 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | qspi_io2 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : qspi_io2 Mux Selection Field - sel - * - * Select peripheral signals connected qspi_io2. - * - * 0 : Pin is connected to GPIO/LoanIO number 31. - * - * 1 : Pin is connected to Peripheral signal USB1.DIR. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal QSPI.IO2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO17_s -{ - uint32_t sel : 2; /* qspi_io2 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO17_s ALT_SYSMGR_PINMUX_MIXED1IO17_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO17 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_OFST 0x144 - -/* - * Register : qspi_io3 Mux Selection Register - MIXED1IO18 - * - * This register is used to control the peripherals connected to qspi_io3 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | qspi_io3 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : qspi_io3 Mux Selection Field - sel - * - * Select peripheral signals connected qspi_io3. - * - * 0 : Pin is connected to GPIO/LoanIO number 32. - * - * 1 : Pin is connected to Peripheral signal USB1.NXT. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal QSPI.IO3. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO18_s -{ - uint32_t sel : 2; /* qspi_io3 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO18_s ALT_SYSMGR_PINMUX_MIXED1IO18_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO18 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_OFST 0x148 - -/* - * Register : qspi_ss0 Mux Selection Register - MIXED1IO19 - * - * This register is used to control the peripherals connected to qspi_ss0 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | qspi_ss0 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : qspi_ss0 Mux Selection Field - sel - * - * Select peripheral signals connected qspi_ss0. - * - * 0 : Pin is connected to GPIO/LoanIO number 33. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal QSPI.SS0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO19_s -{ - uint32_t sel : 2; /* qspi_ss0 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO19_s ALT_SYSMGR_PINMUX_MIXED1IO19_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO19 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_OFST 0x14c - -/* - * Register : qpsi_clk Mux Selection Register - MIXED1IO20 - * - * This register is used to control the peripherals connected to qpsi_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | qpsi_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : qpsi_clk Mux Selection Field - sel - * - * Select peripheral signals connected qpsi_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 34. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal QSPI.CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO20_s -{ - uint32_t sel : 2; /* qpsi_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO20_s ALT_SYSMGR_PINMUX_MIXED1IO20_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO20 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_OFST 0x150 - -/* - * Register : qspi_ss1 Mux Selection Register - MIXED1IO21 - * - * This register is used to control the peripherals connected to qspi_ss1 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | qspi_ss1 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : qspi_ss1 Mux Selection Field - sel - * - * Select peripheral signals connected qspi_ss1. - * - * 0 : Pin is connected to GPIO/LoanIO number 35. - * - * 1 : Pin is connected to Peripheral signal not applicable. - * - * 2 : Pin is connected to Peripheral signal not applicable. - * - * 3 : Pin is connected to Peripheral signal QSPI.SS1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. - */ -struct ALT_SYSMGR_PINMUX_MIXED1IO21_s -{ - uint32_t sel : 2; /* qspi_ss1 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO21_s ALT_SYSMGR_PINMUX_MIXED1IO21_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO21 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_OFST 0x154 - -/* - * Register : emac1_mdio Mux Selection Register - MIXED2IO0 - * - * This register is used to control the peripherals connected to emac1_mdio - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------- - * [1:0] | RW | 0x0 | emac1_mdio Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_mdio Mux Selection Field - sel - * - * Select peripheral signals connected emac1_mdio. - * - * 0 : Pin is connected to GPIO/LoanIO number 54. - * - * 1 : Pin is connected to Peripheral signal SPIS0.CLK. - * - * 2 : Pin is connected to Peripheral signal SPIM0.CLK. - * - * 3 : Pin is connected to Peripheral signal RGMII1.MDIO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. - */ -struct ALT_SYSMGR_PINMUX_MIXED2IO0_s -{ - uint32_t sel : 2; /* emac1_mdio Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO0_s ALT_SYSMGR_PINMUX_MIXED2IO0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO0 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_OFST 0x158 - -/* - * Register : emac1_mdc Mux Selection Register - MIXED2IO1 - * - * This register is used to control the peripherals connected to emac1_mdc - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [1:0] | RW | 0x0 | emac1_mdc Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_mdc Mux Selection Field - sel - * - * Select peripheral signals connected emac1_mdc. - * - * 0 : Pin is connected to GPIO/LoanIO number 55. - * - * 1 : Pin is connected to Peripheral signal SPIS0.MOSI. - * - * 2 : Pin is connected to Peripheral signal SPIM0.MOSI. - * - * 3 : Pin is connected to Peripheral signal RGMII1.MDC. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. - */ -struct ALT_SYSMGR_PINMUX_MIXED2IO1_s -{ - uint32_t sel : 2; /* emac1_mdc Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO1_s ALT_SYSMGR_PINMUX_MIXED2IO1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO1 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_OFST 0x15c - -/* - * Register : emac1_tx_d2 Mux Selection Register - MIXED2IO2 - * - * This register is used to control the peripherals connected to emac1_tx_d2 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac1_tx_d2 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_tx_d2 Mux Selection Field - sel - * - * Select peripheral signals connected emac1_tx_d2. - * - * 0 : Pin is connected to GPIO/LoanIO number 56. - * - * 1 : Pin is connected to Peripheral signal SPIS0.MISO. - * - * 2 : Pin is connected to Peripheral signal SPIM0.MISO. - * - * 3 : Pin is connected to Peripheral signal RGMII1.TXD2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. - */ -struct ALT_SYSMGR_PINMUX_MIXED2IO2_s -{ - uint32_t sel : 2; /* emac1_tx_d2 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO2_s ALT_SYSMGR_PINMUX_MIXED2IO2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO2 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_OFST 0x160 - -/* - * Register : emac1_tx_d3 Mux Selection Register - MIXED2IO3 - * - * This register is used to control the peripherals connected to emac1_tx_d3 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac1_tx_d3 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_tx_d3 Mux Selection Field - sel - * - * Select peripheral signals connected emac1_tx_d3. - * - * 0 : Pin is connected to GPIO/LoanIO number 57. - * - * 1 : Pin is connected to Peripheral signal SPIS0.SS0. - * - * 2 : Pin is connected to Peripheral signal SPIM0.SS0. - * - * 3 : Pin is connected to Peripheral signal RGMII1.TXD3. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. - */ -struct ALT_SYSMGR_PINMUX_MIXED2IO3_s -{ - uint32_t sel : 2; /* emac1_tx_d3 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO3_s ALT_SYSMGR_PINMUX_MIXED2IO3_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO3 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_OFST 0x164 - -/* - * Register : emac1_rx_clk Mux Selection Register - MIXED2IO4 - * - * This register is used to control the peripherals connected to emac1_rx_clk - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [1:0] | RW | 0x0 | emac1_rx_clk Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_rx_clk Mux Selection Field - sel - * - * Select peripheral signals connected emac1_rx_clk. - * - * 0 : Pin is connected to GPIO/LoanIO number 58. - * - * 1 : Pin is connected to Peripheral signal SPIM1.CLK. - * - * 2 : Pin is connected to Peripheral signal SPIS1.CLK. - * - * 3 : Pin is connected to Peripheral signal RGMII1.RX_CLK. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. - */ -struct ALT_SYSMGR_PINMUX_MIXED2IO4_s -{ - uint32_t sel : 2; /* emac1_rx_clk Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO4_s ALT_SYSMGR_PINMUX_MIXED2IO4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO4 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_OFST 0x168 - -/* - * Register : emac1_rx_ctl Mux Selection Register - MIXED2IO5 - * - * This register is used to control the peripherals connected to emac1_rx_ctl - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------- - * [1:0] | RW | 0x0 | emac1_rx_ctl Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_rx_ctl Mux Selection Field - sel - * - * Select peripheral signals connected emac1_rx_ctl. - * - * 0 : Pin is connected to GPIO/LoanIO number 59. - * - * 1 : Pin is connected to Peripheral signal SPIM1.MOSI. - * - * 2 : Pin is connected to Peripheral signal SPIS1.MOSI. - * - * 3 : Pin is connected to Peripheral signal RGMII1.RX_CTL. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. - */ -struct ALT_SYSMGR_PINMUX_MIXED2IO5_s -{ - uint32_t sel : 2; /* emac1_rx_ctl Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO5_s ALT_SYSMGR_PINMUX_MIXED2IO5_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO5 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_OFST 0x16c - -/* - * Register : emac1_rx_d2 Mux Selection Register - MIXED2IO6 - * - * This register is used to control the peripherals connected to emac1_rx_d2 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac1_rx_d2 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_rx_d2 Mux Selection Field - sel - * - * Select peripheral signals connected emac1_rx_d2. - * - * 0 : Pin is connected to GPIO/LoanIO number 60. - * - * 1 : Pin is connected to Peripheral signal SPIM1.MISO. - * - * 2 : Pin is connected to Peripheral signal SPIS1.MISO. - * - * 3 : Pin is connected to Peripheral signal RGMII1.RXD2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. - */ -struct ALT_SYSMGR_PINMUX_MIXED2IO6_s -{ - uint32_t sel : 2; /* emac1_rx_d2 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO6_s ALT_SYSMGR_PINMUX_MIXED2IO6_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO6 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_OFST 0x170 - -/* - * Register : emac1_rx_d3 Mux Selection Register - MIXED2IO7 - * - * This register is used to control the peripherals connected to emac1_rx_d3 - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [1:0] | RW | 0x0 | emac1_rx_d3 Mux Selection Field - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : emac1_rx_d3 Mux Selection Field - sel - * - * Select peripheral signals connected emac1_rx_d3. - * - * 0 : Pin is connected to GPIO/LoanIO number 61. - * - * 1 : Pin is connected to Peripheral signal SPIM1.SS0. - * - * 2 : Pin is connected to Peripheral signal SPIS1.SS0. - * - * 3 : Pin is connected to Peripheral signal RGMII1.RXD3. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_MSB 1 -/* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_WIDTH 2 -/* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET_MSK 0x00000003 -/* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_CLR_MSK 0xfffffffc -/* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. - */ -struct ALT_SYSMGR_PINMUX_MIXED2IO7_s -{ - uint32_t sel : 2; /* emac1_rx_d3 Mux Selection Field */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. */ -typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO7_s ALT_SYSMGR_PINMUX_MIXED2IO7_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO7 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_OFST 0x174 - -/* - * Register : GPIO/LoanIO 48 Input Mux Selection Register - GPLINMUX48 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 48. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO48Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 48. - * - * 0 : Source for GPIO/LoanIO 48 is GENERALIO0. - * - * 1 : Source for GPIO/LoanIO 48 is EMACIO14. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX48_s -{ - uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX48_s ALT_SYSMGR_PINMUX_GPLINMUX48_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX48 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_OFST 0x178 - -/* - * Register : GPIO/LoanIO 49 Input Mux Selection Register - GPLINMUX49 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 49. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO49Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 49. - * - * 0 : Source for GPIO/LoanIO 49 is GENERALIO1. - * - * 1 : Source for GPIO/LoanIO 49 is EMACIO15. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX49_s -{ - uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX49_s ALT_SYSMGR_PINMUX_GPLINMUX49_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX49 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_OFST 0x17c - -/* - * Register : GPIO/LoanIO 50 Input Mux Selection Register - GPLINMUX50 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 50. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO50Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 50. - * - * 0 : Source for GPIO/LoanIO 50 is GENERALIO2. - * - * 1 : Source for GPIO/LoanIO 50 is EMACIO16. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX50_s -{ - uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX50_s ALT_SYSMGR_PINMUX_GPLINMUX50_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX50 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_OFST 0x180 - -/* - * Register : GPIO/LoanIO 51 Input Mux Selection Register - GPLINMUX51 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 51. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO51Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 51. - * - * 0 : Source for GPIO/LoanIO 51 is GENERALIO3. - * - * 1 : Source for GPIO/LoanIO 51 is EMACIO17. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX51_s -{ - uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX51_s ALT_SYSMGR_PINMUX_GPLINMUX51_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX51 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_OFST 0x184 - -/* - * Register : GPIO/LoanIO 52 Input Mux Selection Register - GPLINMUX52 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 52. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO52Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 52. - * - * 0 : Source for GPIO/LoanIO 52 is GENERALIO4. - * - * 1 : Source for GPIO/LoanIO 52 is EMACIO18. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX52_s -{ - uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX52_s ALT_SYSMGR_PINMUX_GPLINMUX52_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX52 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_OFST 0x188 - -/* - * Register : GPIO/LoanIO 53 Input Mux Selection Register - GPLINMUX53 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 53. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO53Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 53. - * - * 0 : Source for GPIO/LoanIO 53 is GENERALIO5. - * - * 1 : Source for GPIO/LoanIO 53 is EMACIO19. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX53_s -{ - uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX53_s ALT_SYSMGR_PINMUX_GPLINMUX53_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX53 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_OFST 0x18c - -/* - * Register : GPIO/LoanIO 54 Input Mux Selection Register - GPLINMUX54 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 54. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO54Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 54. - * - * 0 : Source for GPIO/LoanIO 54 is GENERALIO6. - * - * 1 : Source for GPIO/LoanIO 54 is MIXED2IO0. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX54_s -{ - uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX54_s ALT_SYSMGR_PINMUX_GPLINMUX54_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX54 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_OFST 0x190 - -/* - * Register : GPIO/LoanIO 55 Input Mux Selection Register - GPLINMUX55 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 55. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO55Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 55. - * - * 0 : Source for GPIO/LoanIO 55 is GENERALIO7. - * - * 1 : Source for GPIO/LoanIO 55 is MIXED2IO1. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX55_s -{ - uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX55_s ALT_SYSMGR_PINMUX_GPLINMUX55_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX55 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_OFST 0x194 - -/* - * Register : GPIO/LoanIO 56 Input Mux Selection Register - GPLINMUX56 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 56. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO56Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 56. - * - * 0 : Source for GPIO/LoanIO 56 is GENERALIO8. - * - * 1 : Source for GPIO/LoanIO 56 is MIXED2IO2. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX56_s -{ - uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX56_s ALT_SYSMGR_PINMUX_GPLINMUX56_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX56 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_OFST 0x198 - -/* - * Register : GPIO/LoanIO 57 Input Mux Selection Register - GPLINMUX57 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 57. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO57Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 57. - * - * 0 : Source for GPIO/LoanIO 57 is GENERALIO9. - * - * 1 : Source for GPIO/LoanIO 57 is MIXED2IO3. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX57_s -{ - uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX57_s ALT_SYSMGR_PINMUX_GPLINMUX57_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX57 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_OFST 0x19c - -/* - * Register : GPIO/LoanIO 58 Input Mux Selection Register - GPLINMUX58 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 58. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO58Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 58. - * - * 0 : Source for GPIO/LoanIO 58 is GENERALIO10. - * - * 1 : Source for GPIO/LoanIO 58 is MIXED2IO4. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX58_s -{ - uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX58_s ALT_SYSMGR_PINMUX_GPLINMUX58_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX58 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_OFST 0x1a0 - -/* - * Register : GPIO/LoanIO 59 Input Mux Selection Register - GPLINMUX59 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 59. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO59Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 59. - * - * 0 : Source for GPIO/LoanIO 59 is GENERALIO11. - * - * 1 : Source for GPIO/LoanIO 59 is MIXED2IO5. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX59_s -{ - uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX59_s ALT_SYSMGR_PINMUX_GPLINMUX59_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX59 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_OFST 0x1a4 - -/* - * Register : GPIO/LoanIO 60 Input Mux Selection Register - GPLINMUX60 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 60. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO60Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 60. - * - * 0 : Source for GPIO/LoanIO 60 is GENERALIO12. - * - * 1 : Source for GPIO/LoanIO 60 is MIXED2IO6. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX60_s -{ - uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX60_s ALT_SYSMGR_PINMUX_GPLINMUX60_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX60 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_OFST 0x1a8 - -/* - * Register : GPIO/LoanIO 61 Input Mux Selection Register - GPLINMUX61 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 61. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO61Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 61. - * - * 0 : Source for GPIO/LoanIO 61 is GENERALIO13. - * - * 1 : Source for GPIO/LoanIO 61 is MIXED2IO7. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX61_s -{ - uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX61_s ALT_SYSMGR_PINMUX_GPLINMUX61_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX61 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_OFST 0x1ac - -/* - * Register : GPIO/LoanIO 62 Input Mux Selection Register - GPLINMUX62 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 62. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO62Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 62. - * - * 0 : Source for GPIO/LoanIO 62 is GENERALIO14. - * - * 1 : Source for GPIO/LoanIO 62 is GENERALIO23. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX62_s -{ - uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX62_s ALT_SYSMGR_PINMUX_GPLINMUX62_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX62 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_OFST 0x1b0 - -/* - * Register : GPIO/LoanIO 63 Input Mux Selection Register - GPLINMUX63 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 63. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO63Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 63. - * - * 0 : Source for GPIO/LoanIO 63 is GENERALIO15. - * - * 1 : Source for GPIO/LoanIO 63 is GENERALIO24. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX63_s -{ - uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX63_s ALT_SYSMGR_PINMUX_GPLINMUX63_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX63 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_OFST 0x1b4 - -/* - * Register : GPIO/LoanIO 64 Input Mux Selection Register - GPLINMUX64 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 64. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO64Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 64. - * - * 0 : Source for GPIO/LoanIO 64 is GENERALIO16. - * - * 1 : Source for GPIO/LoanIO 64 is GENERALIO25. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX64_s -{ - uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX64_s ALT_SYSMGR_PINMUX_GPLINMUX64_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX64 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_OFST 0x1b8 - -/* - * Register : GPIO/LoanIO 65 Input Mux Selection Register - GPLINMUX65 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 65. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO65Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 65. - * - * 0 : Source for GPIO/LoanIO 65 is GENERALIO17. - * - * 1 : Source for GPIO/LoanIO 65 is GENERALIO26. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX65_s -{ - uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX65_s ALT_SYSMGR_PINMUX_GPLINMUX65_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX65 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_OFST 0x1bc - -/* - * Register : GPIO/LoanIO 66 Input Mux Selection Register - GPLINMUX66 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 66. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO66Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 66. - * - * 0 : Source for GPIO/LoanIO 66 is GENERALIO18. - * - * 1 : Source for GPIO/LoanIO 66 is GENERALIO27. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX66_s -{ - uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX66_s ALT_SYSMGR_PINMUX_GPLINMUX66_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX66 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_OFST 0x1c0 - -/* - * Register : GPIO/LoanIO 67 Input Mux Selection Register - GPLINMUX67 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 67. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO67Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 67. - * - * 0 : Source for GPIO/LoanIO 67 is GENERALIO19. - * - * 1 : Source for GPIO/LoanIO 67 is GENERALIO28. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX67_s -{ - uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX67_s ALT_SYSMGR_PINMUX_GPLINMUX67_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX67 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_OFST 0x1c4 - -/* - * Register : GPIO/LoanIO 68 Input Mux Selection Register - GPLINMUX68 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 68. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO68Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 68. - * - * 0 : Source for GPIO/LoanIO 68 is GENERALIO20. - * - * 1 : Source for GPIO/LoanIO 68 is GENERALIO29. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX68_s -{ - uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX68_s ALT_SYSMGR_PINMUX_GPLINMUX68_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX68 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_OFST 0x1c8 - -/* - * Register : GPIO/LoanIO 69 Input Mux Selection Register - GPLINMUX69 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 69. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO69Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 69. - * - * 0 : Source for GPIO/LoanIO 69 is GENERALIO21. - * - * 1 : Source for GPIO/LoanIO 69 is GENERALIO30. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX69_s -{ - uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX69_s ALT_SYSMGR_PINMUX_GPLINMUX69_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX69 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_OFST 0x1cc - -/* - * Register : GPIO/LoanIO 70 Input Mux Selection Register - GPLINMUX70 - * - * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects - * the input signal for GPIO/LoanIO 70. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO70Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 70. - * - * 0 : Source for GPIO/LoanIO 70 is GENERALIO22. - * - * 1 : Source for GPIO/LoanIO 70 is GENERALIO31. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. - */ -struct ALT_SYSMGR_PINMUX_GPLINMUX70_s -{ - uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX70_s ALT_SYSMGR_PINMUX_GPLINMUX70_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX70 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_OFST 0x1d0 - -/* - * Register : GPIO/LoanIO 0 Output/Output Enable Mux Selection Register - GPLMUX0 - * - * Selection between GPIO and LoanIO output and output enable for GPIO0 and - * LoanIO0. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO0Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO0Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 0. - * - * 0 : LoanIO 0 controls GPIO/LOANIO[0] output and output enable signals. - * - * 1 : GPIO 0 controls GPIO/LOANI[0] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX0_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX0_s -{ - uint32_t sel : 1; /* GPIO/Loan IO0Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX0_s ALT_SYSMGR_PINMUX_GPLMUX0_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX0 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_OFST 0x1d4 - -/* - * Register : GPIO/LoanIO 1 Output/Output Enable Mux Selection Register - GPLMUX1 - * - * Selection between GPIO and LoanIO output and output enable for GPIO1 and - * LoanIO1. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO1Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO1Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 1. - * - * 0 : LoanIO 1 controls GPIO/LOANIO[1] output and output enable signals. - * - * 1 : GPIO 1 controls GPIO/LOANI[1] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX1_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX1_s -{ - uint32_t sel : 1; /* GPIO/Loan IO1Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX1_s ALT_SYSMGR_PINMUX_GPLMUX1_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX1 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_OFST 0x1d8 - -/* - * Register : GPIO/LoanIO 2 Output/Output Enable Mux Selection Register - GPLMUX2 - * - * Selection between GPIO and LoanIO output and output enable for GPIO2 and - * LoanIO2. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO2Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO2Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 2. - * - * 0 : LoanIO 2 controls GPIO/LOANIO[2] output and output enable signals. - * - * 1 : GPIO 2 controls GPIO/LOANI[2] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX2_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX2_s -{ - uint32_t sel : 1; /* GPIO/Loan IO2Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX2_s ALT_SYSMGR_PINMUX_GPLMUX2_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX2 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_OFST 0x1dc - -/* - * Register : GPIO/LoanIO 3 Output/Output Enable Mux Selection Register - GPLMUX3 - * - * Selection between GPIO and LoanIO output and output enable for GPIO3 and - * LoanIO3. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO3Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO3Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 3. - * - * 0 : LoanIO 3 controls GPIO/LOANIO[3] output and output enable signals. - * - * 1 : GPIO 3 controls GPIO/LOANI[3] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX3_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX3_s -{ - uint32_t sel : 1; /* GPIO/Loan IO3Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX3_s ALT_SYSMGR_PINMUX_GPLMUX3_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX3 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_OFST 0x1e0 - -/* - * Register : GPIO/LoanIO 4 Output/Output Enable Mux Selection Register - GPLMUX4 - * - * Selection between GPIO and LoanIO output and output enable for GPIO4 and - * LoanIO4. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO4Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO4Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 4. - * - * 0 : LoanIO 4 controls GPIO/LOANIO[4] output and output enable signals. - * - * 1 : GPIO 4 controls GPIO/LOANI[4] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX4_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX4_s -{ - uint32_t sel : 1; /* GPIO/Loan IO4Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX4_s ALT_SYSMGR_PINMUX_GPLMUX4_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX4 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_OFST 0x1e4 - -/* - * Register : GPIO/LoanIO 5 Output/Output Enable Mux Selection Register - GPLMUX5 - * - * Selection between GPIO and LoanIO output and output enable for GPIO5 and - * LoanIO5. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO5Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO5Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 5. - * - * 0 : LoanIO 5 controls GPIO/LOANIO[5] output and output enable signals. - * - * 1 : GPIO 5 controls GPIO/LOANI[5] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX5_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX5_s -{ - uint32_t sel : 1; /* GPIO/Loan IO5Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX5_s ALT_SYSMGR_PINMUX_GPLMUX5_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX5 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_OFST 0x1e8 - -/* - * Register : GPIO/LoanIO 6 Output/Output Enable Mux Selection Register - GPLMUX6 - * - * Selection between GPIO and LoanIO output and output enable for GPIO6 and - * LoanIO6. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO6Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO6Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 6. - * - * 0 : LoanIO 6 controls GPIO/LOANIO[6] output and output enable signals. - * - * 1 : GPIO 6 controls GPIO/LOANI[6] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX6_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX6_s -{ - uint32_t sel : 1; /* GPIO/Loan IO6Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX6_s ALT_SYSMGR_PINMUX_GPLMUX6_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX6 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_OFST 0x1ec - -/* - * Register : GPIO/LoanIO 7 Output/Output Enable Mux Selection Register - GPLMUX7 - * - * Selection between GPIO and LoanIO output and output enable for GPIO7 and - * LoanIO7. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO7Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO7Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 7. - * - * 0 : LoanIO 7 controls GPIO/LOANIO[7] output and output enable signals. - * - * 1 : GPIO 7 controls GPIO/LOANI[7] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX7_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX7_s -{ - uint32_t sel : 1; /* GPIO/Loan IO7Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX7_s ALT_SYSMGR_PINMUX_GPLMUX7_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX7 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_OFST 0x1f0 - -/* - * Register : GPIO/LoanIO 8 Output/Output Enable Mux Selection Register - GPLMUX8 - * - * Selection between GPIO and LoanIO output and output enable for GPIO8 and - * LoanIO8. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO8Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO8Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 8. - * - * 0 : LoanIO 8 controls GPIO/LOANIO[8] output and output enable signals. - * - * 1 : GPIO 8 controls GPIO/LOANI[8] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX8_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX8_s -{ - uint32_t sel : 1; /* GPIO/Loan IO8Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX8_s ALT_SYSMGR_PINMUX_GPLMUX8_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX8 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_OFST 0x1f4 - -/* - * Register : GPIO/LoanIO 9 Output/Output Enable Mux Selection Register - GPLMUX9 - * - * Selection between GPIO and LoanIO output and output enable for GPIO9 and - * LoanIO9. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO9Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO9Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 9. - * - * 0 : LoanIO 9 controls GPIO/LOANIO[9] output and output enable signals. - * - * 1 : GPIO 9 controls GPIO/LOANI[9] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX9_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX9_s -{ - uint32_t sel : 1; /* GPIO/Loan IO9Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX9_s ALT_SYSMGR_PINMUX_GPLMUX9_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX9 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_OFST 0x1f8 - -/* - * Register : GPIO/LoanIO 10 Output/Output Enable Mux Selection Register - GPLMUX10 - * - * Selection between GPIO and LoanIO output and output enable for GPIO10 and - * LoanIO10. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO10Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO10Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 10. - * - * 0 : LoanIO 10 controls GPIO/LOANIO[10] output and output enable signals. - * - * 1 : GPIO 10 controls GPIO/LOANI[10] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX10_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX10_s -{ - uint32_t sel : 1; /* GPIO/Loan IO10Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX10_s ALT_SYSMGR_PINMUX_GPLMUX10_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX10 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_OFST 0x1fc - -/* - * Register : GPIO/LoanIO 11 Output/Output Enable Mux Selection Register - GPLMUX11 - * - * Selection between GPIO and LoanIO output and output enable for GPIO11 and - * LoanIO11. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO11Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO11Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 11. - * - * 0 : LoanIO 11 controls GPIO/LOANIO[11] output and output enable signals. - * - * 1 : GPIO 11 controls GPIO/LOANI[11] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX11_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX11_s -{ - uint32_t sel : 1; /* GPIO/Loan IO11Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX11_s ALT_SYSMGR_PINMUX_GPLMUX11_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX11 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_OFST 0x200 - -/* - * Register : GPIO/LoanIO 12 Output/Output Enable Mux Selection Register - GPLMUX12 - * - * Selection between GPIO and LoanIO output and output enable for GPIO12 and - * LoanIO12. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO12Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO12Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 12. - * - * 0 : LoanIO 12 controls GPIO/LOANIO[12] output and output enable signals. - * - * 1 : GPIO 12 controls GPIO/LOANI[12] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX12_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX12_s -{ - uint32_t sel : 1; /* GPIO/Loan IO12Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX12_s ALT_SYSMGR_PINMUX_GPLMUX12_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX12 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_OFST 0x204 - -/* - * Register : GPIO/LoanIO 13 Output/Output Enable Mux Selection Register - GPLMUX13 - * - * Selection between GPIO and LoanIO output and output enable for GPIO13 and - * LoanIO13. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO13Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO13Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 13. - * - * 0 : LoanIO 13 controls GPIO/LOANIO[13] output and output enable signals. - * - * 1 : GPIO 13 controls GPIO/LOANI[13] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX13_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX13_s -{ - uint32_t sel : 1; /* GPIO/Loan IO13Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX13_s ALT_SYSMGR_PINMUX_GPLMUX13_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX13 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_OFST 0x208 - -/* - * Register : GPIO/LoanIO 14 Output/Output Enable Mux Selection Register - GPLMUX14 - * - * Selection between GPIO and LoanIO output and output enable for GPIO14 and - * LoanIO14. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO14Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO14Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 14. - * - * 0 : LoanIO 14 controls GPIO/LOANIO[14] output and output enable signals. - * - * 1 : GPIO 14 controls GPIO/LOANI[14] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX14_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX14_s -{ - uint32_t sel : 1; /* GPIO/Loan IO14Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX14_s ALT_SYSMGR_PINMUX_GPLMUX14_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX14 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_OFST 0x20c - -/* - * Register : GPIO/LoanIO 15 Output/Output Enable Mux Selection Register - GPLMUX15 - * - * Selection between GPIO and LoanIO output and output enable for GPIO15 and - * LoanIO15. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO15Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO15Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 15. - * - * 0 : LoanIO 15 controls GPIO/LOANIO[15] output and output enable signals. - * - * 1 : GPIO 15 controls GPIO/LOANI[15] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX15_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX15_s -{ - uint32_t sel : 1; /* GPIO/Loan IO15Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX15_s ALT_SYSMGR_PINMUX_GPLMUX15_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX15 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_OFST 0x210 - -/* - * Register : GPIO/LoanIO 16 Output/Output Enable Mux Selection Register - GPLMUX16 - * - * Selection between GPIO and LoanIO output and output enable for GPIO16 and - * LoanIO16. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO16Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO16Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 16. - * - * 0 : LoanIO 16 controls GPIO/LOANIO[16] output and output enable signals. - * - * 1 : GPIO 16 controls GPIO/LOANI[16] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX16_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX16_s -{ - uint32_t sel : 1; /* GPIO/Loan IO16Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX16_s ALT_SYSMGR_PINMUX_GPLMUX16_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX16 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_OFST 0x214 - -/* - * Register : GPIO/LoanIO 17 Output/Output Enable Mux Selection Register - GPLMUX17 - * - * Selection between GPIO and LoanIO output and output enable for GPIO17 and - * LoanIO17. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO17Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO17Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 17. - * - * 0 : LoanIO 17 controls GPIO/LOANIO[17] output and output enable signals. - * - * 1 : GPIO 17 controls GPIO/LOANI[17] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX17_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX17_s -{ - uint32_t sel : 1; /* GPIO/Loan IO17Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX17_s ALT_SYSMGR_PINMUX_GPLMUX17_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX17 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_OFST 0x218 - -/* - * Register : GPIO/LoanIO 18 Output/Output Enable Mux Selection Register - GPLMUX18 - * - * Selection between GPIO and LoanIO output and output enable for GPIO18 and - * LoanIO18. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO18Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO18Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 18. - * - * 0 : LoanIO 18 controls GPIO/LOANIO[18] output and output enable signals. - * - * 1 : GPIO 18 controls GPIO/LOANI[18] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX18_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX18_s -{ - uint32_t sel : 1; /* GPIO/Loan IO18Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX18_s ALT_SYSMGR_PINMUX_GPLMUX18_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX18 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_OFST 0x21c - -/* - * Register : GPIO/LoanIO 19 Output/Output Enable Mux Selection Register - GPLMUX19 - * - * Selection between GPIO and LoanIO output and output enable for GPIO19 and - * LoanIO19. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO19Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO19Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 19. - * - * 0 : LoanIO 19 controls GPIO/LOANIO[19] output and output enable signals. - * - * 1 : GPIO 19 controls GPIO/LOANI[19] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX19_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX19_s -{ - uint32_t sel : 1; /* GPIO/Loan IO19Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX19_s ALT_SYSMGR_PINMUX_GPLMUX19_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX19 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_OFST 0x220 - -/* - * Register : GPIO/LoanIO 20 Output/Output Enable Mux Selection Register - GPLMUX20 - * - * Selection between GPIO and LoanIO output and output enable for GPIO20 and - * LoanIO20. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO20Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO20Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 20. - * - * 0 : LoanIO 20 controls GPIO/LOANIO[20] output and output enable signals. - * - * 1 : GPIO 20 controls GPIO/LOANI[20] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX20_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX20_s -{ - uint32_t sel : 1; /* GPIO/Loan IO20Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX20_s ALT_SYSMGR_PINMUX_GPLMUX20_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX20 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_OFST 0x224 - -/* - * Register : GPIO/LoanIO 21 Output/Output Enable Mux Selection Register - GPLMUX21 - * - * Selection between GPIO and LoanIO output and output enable for GPIO21 and - * LoanIO21. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO21Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO21Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 21. - * - * 0 : LoanIO 21 controls GPIO/LOANIO[21] output and output enable signals. - * - * 1 : GPIO 21 controls GPIO/LOANI[21] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX21_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX21_s -{ - uint32_t sel : 1; /* GPIO/Loan IO21Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX21_s ALT_SYSMGR_PINMUX_GPLMUX21_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX21 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_OFST 0x228 - -/* - * Register : GPIO/LoanIO 22 Output/Output Enable Mux Selection Register - GPLMUX22 - * - * Selection between GPIO and LoanIO output and output enable for GPIO22 and - * LoanIO22. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO22Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO22Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 22. - * - * 0 : LoanIO 22 controls GPIO/LOANIO[22] output and output enable signals. - * - * 1 : GPIO 22 controls GPIO/LOANI[22] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX22_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX22_s -{ - uint32_t sel : 1; /* GPIO/Loan IO22Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX22_s ALT_SYSMGR_PINMUX_GPLMUX22_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX22 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_OFST 0x22c - -/* - * Register : GPIO/LoanIO 23 Output/Output Enable Mux Selection Register - GPLMUX23 - * - * Selection between GPIO and LoanIO output and output enable for GPIO23 and - * LoanIO23. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO23Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO23Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 23. - * - * 0 : LoanIO 23 controls GPIO/LOANIO[23] output and output enable signals. - * - * 1 : GPIO 23 controls GPIO/LOANI[23] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX23_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX23_s -{ - uint32_t sel : 1; /* GPIO/Loan IO23Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX23_s ALT_SYSMGR_PINMUX_GPLMUX23_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX23 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_OFST 0x230 - -/* - * Register : GPIO/LoanIO 24 Output/Output Enable Mux Selection Register - GPLMUX24 - * - * Selection between GPIO and LoanIO output and output enable for GPIO24 and - * LoanIO24. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO24Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO24Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 24. - * - * 0 : LoanIO 24 controls GPIO/LOANIO[24] output and output enable signals. - * - * 1 : GPIO 24 controls GPIO/LOANI[24] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX24_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX24_s -{ - uint32_t sel : 1; /* GPIO/Loan IO24Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX24_s ALT_SYSMGR_PINMUX_GPLMUX24_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX24 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_OFST 0x234 - -/* - * Register : GPIO/LoanIO 25 Output/Output Enable Mux Selection Register - GPLMUX25 - * - * Selection between GPIO and LoanIO output and output enable for GPIO25 and - * LoanIO25. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO25Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO25Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 25. - * - * 0 : LoanIO 25 controls GPIO/LOANIO[25] output and output enable signals. - * - * 1 : GPIO 25 controls GPIO/LOANI[25] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX25_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX25_s -{ - uint32_t sel : 1; /* GPIO/Loan IO25Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX25_s ALT_SYSMGR_PINMUX_GPLMUX25_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX25 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_OFST 0x238 - -/* - * Register : GPIO/LoanIO 26 Output/Output Enable Mux Selection Register - GPLMUX26 - * - * Selection between GPIO and LoanIO output and output enable for GPIO26 and - * LoanIO26. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO26Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO26Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 26. - * - * 0 : LoanIO 26 controls GPIO/LOANIO[26] output and output enable signals. - * - * 1 : GPIO 26 controls GPIO/LOANI[26] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX26_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX26_s -{ - uint32_t sel : 1; /* GPIO/Loan IO26Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX26_s ALT_SYSMGR_PINMUX_GPLMUX26_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX26 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_OFST 0x23c - -/* - * Register : GPIO/LoanIO 27 Output/Output Enable Mux Selection Register - GPLMUX27 - * - * Selection between GPIO and LoanIO output and output enable for GPIO27 and - * LoanIO27. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO27Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO27Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 27. - * - * 0 : LoanIO 27 controls GPIO/LOANIO[27] output and output enable signals. - * - * 1 : GPIO 27 controls GPIO/LOANI[27] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX27_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX27_s -{ - uint32_t sel : 1; /* GPIO/Loan IO27Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX27_s ALT_SYSMGR_PINMUX_GPLMUX27_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX27 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_OFST 0x240 - -/* - * Register : GPIO/LoanIO 28 Output/Output Enable Mux Selection Register - GPLMUX28 - * - * Selection between GPIO and LoanIO output and output enable for GPIO28 and - * LoanIO28. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO28Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO28Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 28. - * - * 0 : LoanIO 28 controls GPIO/LOANIO[28] output and output enable signals. - * - * 1 : GPIO 28 controls GPIO/LOANI[28] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX28_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX28_s -{ - uint32_t sel : 1; /* GPIO/Loan IO28Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX28_s ALT_SYSMGR_PINMUX_GPLMUX28_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX28 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_OFST 0x244 - -/* - * Register : GPIO/LoanIO 29 Output/Output Enable Mux Selection Register - GPLMUX29 - * - * Selection between GPIO and LoanIO output and output enable for GPIO29 and - * LoanIO29. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO29Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO29Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 29. - * - * 0 : LoanIO 29 controls GPIO/LOANIO[29] output and output enable signals. - * - * 1 : GPIO 29 controls GPIO/LOANI[29] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX29_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX29_s -{ - uint32_t sel : 1; /* GPIO/Loan IO29Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX29_s ALT_SYSMGR_PINMUX_GPLMUX29_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX29 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_OFST 0x248 - -/* - * Register : GPIO/LoanIO 30 Output/Output Enable Mux Selection Register - GPLMUX30 - * - * Selection between GPIO and LoanIO output and output enable for GPIO30 and - * LoanIO30. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO30Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO30Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 30. - * - * 0 : LoanIO 30 controls GPIO/LOANIO[30] output and output enable signals. - * - * 1 : GPIO 30 controls GPIO/LOANI[30] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX30_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX30_s -{ - uint32_t sel : 1; /* GPIO/Loan IO30Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX30_s ALT_SYSMGR_PINMUX_GPLMUX30_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX30 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_OFST 0x24c - -/* - * Register : GPIO/LoanIO 31 Output/Output Enable Mux Selection Register - GPLMUX31 - * - * Selection between GPIO and LoanIO output and output enable for GPIO31 and - * LoanIO31. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO31Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO31Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 31. - * - * 0 : LoanIO 31 controls GPIO/LOANIO[31] output and output enable signals. - * - * 1 : GPIO 31 controls GPIO/LOANI[31] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX31_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX31_s -{ - uint32_t sel : 1; /* GPIO/Loan IO31Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX31_s ALT_SYSMGR_PINMUX_GPLMUX31_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX31 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_OFST 0x250 - -/* - * Register : GPIO/LoanIO 32 Output/Output Enable Mux Selection Register - GPLMUX32 - * - * Selection between GPIO and LoanIO output and output enable for GPIO32 and - * LoanIO32. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO32Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO32Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 32. - * - * 0 : LoanIO 32 controls GPIO/LOANIO[32] output and output enable signals. - * - * 1 : GPIO 32 controls GPIO/LOANI[32] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX32_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX32_s -{ - uint32_t sel : 1; /* GPIO/Loan IO32Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX32_s ALT_SYSMGR_PINMUX_GPLMUX32_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX32 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_OFST 0x254 - -/* - * Register : GPIO/LoanIO 33 Output/Output Enable Mux Selection Register - GPLMUX33 - * - * Selection between GPIO and LoanIO output and output enable for GPIO33 and - * LoanIO33. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO33Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO33Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 33. - * - * 0 : LoanIO 33 controls GPIO/LOANIO[33] output and output enable signals. - * - * 1 : GPIO 33 controls GPIO/LOANI[33] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX33_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX33_s -{ - uint32_t sel : 1; /* GPIO/Loan IO33Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX33_s ALT_SYSMGR_PINMUX_GPLMUX33_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX33 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_OFST 0x258 - -/* - * Register : GPIO/LoanIO 34 Output/Output Enable Mux Selection Register - GPLMUX34 - * - * Selection between GPIO and LoanIO output and output enable for GPIO34 and - * LoanIO34. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO34Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO34Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 34. - * - * 0 : LoanIO 34 controls GPIO/LOANIO[34] output and output enable signals. - * - * 1 : GPIO 34 controls GPIO/LOANI[34] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX34_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX34_s -{ - uint32_t sel : 1; /* GPIO/Loan IO34Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX34_s ALT_SYSMGR_PINMUX_GPLMUX34_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX34 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_OFST 0x25c - -/* - * Register : GPIO/LoanIO 35 Output/Output Enable Mux Selection Register - GPLMUX35 - * - * Selection between GPIO and LoanIO output and output enable for GPIO35 and - * LoanIO35. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO35Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO35Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 35. - * - * 0 : LoanIO 35 controls GPIO/LOANIO[35] output and output enable signals. - * - * 1 : GPIO 35 controls GPIO/LOANI[35] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX35_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX35_s -{ - uint32_t sel : 1; /* GPIO/Loan IO35Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX35_s ALT_SYSMGR_PINMUX_GPLMUX35_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX35 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_OFST 0x260 - -/* - * Register : GPIO/LoanIO 36 Output/Output Enable Mux Selection Register - GPLMUX36 - * - * Selection between GPIO and LoanIO output and output enable for GPIO36 and - * LoanIO36. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO36Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO36Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 36. - * - * 0 : LoanIO 36 controls GPIO/LOANIO[36] output and output enable signals. - * - * 1 : GPIO 36 controls GPIO/LOANI[36] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX36_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX36_s -{ - uint32_t sel : 1; /* GPIO/Loan IO36Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX36_s ALT_SYSMGR_PINMUX_GPLMUX36_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX36 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_OFST 0x264 - -/* - * Register : GPIO/LoanIO 37 Output/Output Enable Mux Selection Register - GPLMUX37 - * - * Selection between GPIO and LoanIO output and output enable for GPIO37 and - * LoanIO37. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO37Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO37Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 37. - * - * 0 : LoanIO 37 controls GPIO/LOANIO[37] output and output enable signals. - * - * 1 : GPIO 37 controls GPIO/LOANI[37] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX37_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX37_s -{ - uint32_t sel : 1; /* GPIO/Loan IO37Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX37_s ALT_SYSMGR_PINMUX_GPLMUX37_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX37 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_OFST 0x268 - -/* - * Register : GPIO/LoanIO 38 Output/Output Enable Mux Selection Register - GPLMUX38 - * - * Selection between GPIO and LoanIO output and output enable for GPIO38 and - * LoanIO38. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO38Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO38Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 38. - * - * 0 : LoanIO 38 controls GPIO/LOANIO[38] output and output enable signals. - * - * 1 : GPIO 38 controls GPIO/LOANI[38] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX38_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX38_s -{ - uint32_t sel : 1; /* GPIO/Loan IO38Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX38_s ALT_SYSMGR_PINMUX_GPLMUX38_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX38 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_OFST 0x26c - -/* - * Register : GPIO/LoanIO 39 Output/Output Enable Mux Selection Register - GPLMUX39 - * - * Selection between GPIO and LoanIO output and output enable for GPIO39 and - * LoanIO39. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO39Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO39Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 39. - * - * 0 : LoanIO 39 controls GPIO/LOANIO[39] output and output enable signals. - * - * 1 : GPIO 39 controls GPIO/LOANI[39] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX39_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX39_s -{ - uint32_t sel : 1; /* GPIO/Loan IO39Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX39_s ALT_SYSMGR_PINMUX_GPLMUX39_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX39 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_OFST 0x270 - -/* - * Register : GPIO/LoanIO 40 Output/Output Enable Mux Selection Register - GPLMUX40 - * - * Selection between GPIO and LoanIO output and output enable for GPIO40 and - * LoanIO40. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO40Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO40Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 40. - * - * 0 : LoanIO 40 controls GPIO/LOANIO[40] output and output enable signals. - * - * 1 : GPIO 40 controls GPIO/LOANI[40] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX40_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX40_s -{ - uint32_t sel : 1; /* GPIO/Loan IO40Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX40_s ALT_SYSMGR_PINMUX_GPLMUX40_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX40 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_OFST 0x274 - -/* - * Register : GPIO/LoanIO 41 Output/Output Enable Mux Selection Register - GPLMUX41 - * - * Selection between GPIO and LoanIO output and output enable for GPIO41 and - * LoanIO41. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO41Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO41Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 41. - * - * 0 : LoanIO 41 controls GPIO/LOANIO[41] output and output enable signals. - * - * 1 : GPIO 41 controls GPIO/LOANI[41] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX41_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX41_s -{ - uint32_t sel : 1; /* GPIO/Loan IO41Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX41_s ALT_SYSMGR_PINMUX_GPLMUX41_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX41 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_OFST 0x278 - -/* - * Register : GPIO/LoanIO 42 Output/Output Enable Mux Selection Register - GPLMUX42 - * - * Selection between GPIO and LoanIO output and output enable for GPIO42 and - * LoanIO42. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO42Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO42Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 42. - * - * 0 : LoanIO 42 controls GPIO/LOANIO[42] output and output enable signals. - * - * 1 : GPIO 42 controls GPIO/LOANI[42] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX42_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX42_s -{ - uint32_t sel : 1; /* GPIO/Loan IO42Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX42_s ALT_SYSMGR_PINMUX_GPLMUX42_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX42 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_OFST 0x27c - -/* - * Register : GPIO/LoanIO 43 Output/Output Enable Mux Selection Register - GPLMUX43 - * - * Selection between GPIO and LoanIO output and output enable for GPIO43 and - * LoanIO43. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO43Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO43Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 43. - * - * 0 : LoanIO 43 controls GPIO/LOANIO[43] output and output enable signals. - * - * 1 : GPIO 43 controls GPIO/LOANI[43] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX43_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX43_s -{ - uint32_t sel : 1; /* GPIO/Loan IO43Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX43_s ALT_SYSMGR_PINMUX_GPLMUX43_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX43 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_OFST 0x280 - -/* - * Register : GPIO/LoanIO 44 Output/Output Enable Mux Selection Register - GPLMUX44 - * - * Selection between GPIO and LoanIO output and output enable for GPIO44 and - * LoanIO44. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO44Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO44Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 44. - * - * 0 : LoanIO 44 controls GPIO/LOANIO[44] output and output enable signals. - * - * 1 : GPIO 44 controls GPIO/LOANI[44] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX44_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX44_s -{ - uint32_t sel : 1; /* GPIO/Loan IO44Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX44_s ALT_SYSMGR_PINMUX_GPLMUX44_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX44 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_OFST 0x284 - -/* - * Register : GPIO/LoanIO 45 Output/Output Enable Mux Selection Register - GPLMUX45 - * - * Selection between GPIO and LoanIO output and output enable for GPIO45 and - * LoanIO45. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO45Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO45Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 45. - * - * 0 : LoanIO 45 controls GPIO/LOANIO[45] output and output enable signals. - * - * 1 : GPIO 45 controls GPIO/LOANI[45] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX45_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX45_s -{ - uint32_t sel : 1; /* GPIO/Loan IO45Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX45_s ALT_SYSMGR_PINMUX_GPLMUX45_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX45 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_OFST 0x288 - -/* - * Register : GPIO/LoanIO 46 Output/Output Enable Mux Selection Register - GPLMUX46 - * - * Selection between GPIO and LoanIO output and output enable for GPIO46 and - * LoanIO46. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO46Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO46Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 46. - * - * 0 : LoanIO 46 controls GPIO/LOANIO[46] output and output enable signals. - * - * 1 : GPIO 46 controls GPIO/LOANI[46] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX46_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX46_s -{ - uint32_t sel : 1; /* GPIO/Loan IO46Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX46_s ALT_SYSMGR_PINMUX_GPLMUX46_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX46 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_OFST 0x28c - -/* - * Register : GPIO/LoanIO 47 Output/Output Enable Mux Selection Register - GPLMUX47 - * - * Selection between GPIO and LoanIO output and output enable for GPIO47 and - * LoanIO47. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO47Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO47Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 47. - * - * 0 : LoanIO 47 controls GPIO/LOANIO[47] output and output enable signals. - * - * 1 : GPIO 47 controls GPIO/LOANI[47] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX47_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX47_s -{ - uint32_t sel : 1; /* GPIO/Loan IO47Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX47_s ALT_SYSMGR_PINMUX_GPLMUX47_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX47 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_OFST 0x290 - -/* - * Register : GPIO/LoanIO 48 Output/Output Enable Mux Selection Register - GPLMUX48 - * - * Selection between GPIO and LoanIO output and output enable for GPIO48 and - * LoanIO48. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO48Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 48. - * - * 0 : LoanIO 48 controls GPIO/LOANIO[48] output and output enable signals. - * - * 1 : GPIO 48 controls GPIO/LOANI[48] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX48_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX48_s -{ - uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX48_s ALT_SYSMGR_PINMUX_GPLMUX48_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX48 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_OFST 0x294 - -/* - * Register : GPIO/LoanIO 49 Output/Output Enable Mux Selection Register - GPLMUX49 - * - * Selection between GPIO and LoanIO output and output enable for GPIO49 and - * LoanIO49. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO49Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 49. - * - * 0 : LoanIO 49 controls GPIO/LOANIO[49] output and output enable signals. - * - * 1 : GPIO 49 controls GPIO/LOANI[49] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX49_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX49_s -{ - uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX49_s ALT_SYSMGR_PINMUX_GPLMUX49_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX49 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_OFST 0x298 - -/* - * Register : GPIO/LoanIO 50 Output/Output Enable Mux Selection Register - GPLMUX50 - * - * Selection between GPIO and LoanIO output and output enable for GPIO50 and - * LoanIO50. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO50Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 50. - * - * 0 : LoanIO 50 controls GPIO/LOANIO[50] output and output enable signals. - * - * 1 : GPIO 50 controls GPIO/LOANI[50] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX50_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX50_s -{ - uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX50_s ALT_SYSMGR_PINMUX_GPLMUX50_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX50 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_OFST 0x29c - -/* - * Register : GPIO/LoanIO 51 Output/Output Enable Mux Selection Register - GPLMUX51 - * - * Selection between GPIO and LoanIO output and output enable for GPIO51 and - * LoanIO51. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO51Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 51. - * - * 0 : LoanIO 51 controls GPIO/LOANIO[51] output and output enable signals. - * - * 1 : GPIO 51 controls GPIO/LOANI[51] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX51_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX51_s -{ - uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX51_s ALT_SYSMGR_PINMUX_GPLMUX51_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX51 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_OFST 0x2a0 - -/* - * Register : GPIO/LoanIO 52 Output/Output Enable Mux Selection Register - GPLMUX52 - * - * Selection between GPIO and LoanIO output and output enable for GPIO52 and - * LoanIO52. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO52Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 52. - * - * 0 : LoanIO 52 controls GPIO/LOANIO[52] output and output enable signals. - * - * 1 : GPIO 52 controls GPIO/LOANI[52] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX52_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX52_s -{ - uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX52_s ALT_SYSMGR_PINMUX_GPLMUX52_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX52 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_OFST 0x2a4 - -/* - * Register : GPIO/LoanIO 53 Output/Output Enable Mux Selection Register - GPLMUX53 - * - * Selection between GPIO and LoanIO output and output enable for GPIO53 and - * LoanIO53. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO53Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 53. - * - * 0 : LoanIO 53 controls GPIO/LOANIO[53] output and output enable signals. - * - * 1 : GPIO 53 controls GPIO/LOANI[53] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX53_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX53_s -{ - uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX53_s ALT_SYSMGR_PINMUX_GPLMUX53_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX53 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_OFST 0x2a8 - -/* - * Register : GPIO/LoanIO 54 Output/Output Enable Mux Selection Register - GPLMUX54 - * - * Selection between GPIO and LoanIO output and output enable for GPIO54 and - * LoanIO54. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO54Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 54. - * - * 0 : LoanIO 54 controls GPIO/LOANIO[54] output and output enable signals. - * - * 1 : GPIO 54 controls GPIO/LOANI[54] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX54_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX54_s -{ - uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX54_s ALT_SYSMGR_PINMUX_GPLMUX54_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX54 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_OFST 0x2ac - -/* - * Register : GPIO/LoanIO 55 Output/Output Enable Mux Selection Register - GPLMUX55 - * - * Selection between GPIO and LoanIO output and output enable for GPIO55 and - * LoanIO55. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO55Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 55. - * - * 0 : LoanIO 55 controls GPIO/LOANIO[55] output and output enable signals. - * - * 1 : GPIO 55 controls GPIO/LOANI[55] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX55_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX55_s -{ - uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX55_s ALT_SYSMGR_PINMUX_GPLMUX55_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX55 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_OFST 0x2b0 - -/* - * Register : GPIO/LoanIO 56 Output/Output Enable Mux Selection Register - GPLMUX56 - * - * Selection between GPIO and LoanIO output and output enable for GPIO56 and - * LoanIO56. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO56Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 56. - * - * 0 : LoanIO 56 controls GPIO/LOANIO[56] output and output enable signals. - * - * 1 : GPIO 56 controls GPIO/LOANI[56] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX56_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX56_s -{ - uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX56_s ALT_SYSMGR_PINMUX_GPLMUX56_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX56 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_OFST 0x2b4 - -/* - * Register : GPIO/LoanIO 57 Output/Output Enable Mux Selection Register - GPLMUX57 - * - * Selection between GPIO and LoanIO output and output enable for GPIO57 and - * LoanIO57. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO57Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 57. - * - * 0 : LoanIO 57 controls GPIO/LOANIO[57] output and output enable signals. - * - * 1 : GPIO 57 controls GPIO/LOANI[57] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX57_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX57_s -{ - uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX57_s ALT_SYSMGR_PINMUX_GPLMUX57_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX57 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_OFST 0x2b8 - -/* - * Register : GPIO/LoanIO 58 Output/Output Enable Mux Selection Register - GPLMUX58 - * - * Selection between GPIO and LoanIO output and output enable for GPIO58 and - * LoanIO58. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO58Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 58. - * - * 0 : LoanIO 58 controls GPIO/LOANIO[58] output and output enable signals. - * - * 1 : GPIO 58 controls GPIO/LOANI[58] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX58_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX58_s -{ - uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX58_s ALT_SYSMGR_PINMUX_GPLMUX58_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX58 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_OFST 0x2bc - -/* - * Register : GPIO/LoanIO 59 Output/Output Enable Mux Selection Register - GPLMUX59 - * - * Selection between GPIO and LoanIO output and output enable for GPIO59 and - * LoanIO59. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO59Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 59. - * - * 0 : LoanIO 59 controls GPIO/LOANIO[59] output and output enable signals. - * - * 1 : GPIO 59 controls GPIO/LOANI[59] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX59_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX59_s -{ - uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX59_s ALT_SYSMGR_PINMUX_GPLMUX59_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX59 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_OFST 0x2c0 - -/* - * Register : GPIO/LoanIO 60 Output/Output Enable Mux Selection Register - GPLMUX60 - * - * Selection between GPIO and LoanIO output and output enable for GPIO60 and - * LoanIO60. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO60Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 60. - * - * 0 : LoanIO 60 controls GPIO/LOANIO[60] output and output enable signals. - * - * 1 : GPIO 60 controls GPIO/LOANI[60] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX60_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX60_s -{ - uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX60_s ALT_SYSMGR_PINMUX_GPLMUX60_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX60 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_OFST 0x2c4 - -/* - * Register : GPIO/LoanIO 61 Output/Output Enable Mux Selection Register - GPLMUX61 - * - * Selection between GPIO and LoanIO output and output enable for GPIO61 and - * LoanIO61. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO61Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 61. - * - * 0 : LoanIO 61 controls GPIO/LOANIO[61] output and output enable signals. - * - * 1 : GPIO 61 controls GPIO/LOANI[61] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX61_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX61_s -{ - uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX61_s ALT_SYSMGR_PINMUX_GPLMUX61_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX61 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_OFST 0x2c8 - -/* - * Register : GPIO/LoanIO 62 Output/Output Enable Mux Selection Register - GPLMUX62 - * - * Selection between GPIO and LoanIO output and output enable for GPIO62 and - * LoanIO62. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO62Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 62. - * - * 0 : LoanIO 62 controls GPIO/LOANIO[62] output and output enable signals. - * - * 1 : GPIO 62 controls GPIO/LOANI[62] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX62_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX62_s -{ - uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX62_s ALT_SYSMGR_PINMUX_GPLMUX62_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX62 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_OFST 0x2cc - -/* - * Register : GPIO/LoanIO 63 Output/Output Enable Mux Selection Register - GPLMUX63 - * - * Selection between GPIO and LoanIO output and output enable for GPIO63 and - * LoanIO63. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO63Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 63. - * - * 0 : LoanIO 63 controls GPIO/LOANIO[63] output and output enable signals. - * - * 1 : GPIO 63 controls GPIO/LOANI[63] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX63_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX63_s -{ - uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX63_s ALT_SYSMGR_PINMUX_GPLMUX63_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX63 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_OFST 0x2d0 - -/* - * Register : GPIO/LoanIO 64 Output/Output Enable Mux Selection Register - GPLMUX64 - * - * Selection between GPIO and LoanIO output and output enable for GPIO64 and - * LoanIO64. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO64Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 64. - * - * 0 : LoanIO 64 controls GPIO/LOANIO[64] output and output enable signals. - * - * 1 : GPIO 64 controls GPIO/LOANI[64] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX64_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX64_s -{ - uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX64_s ALT_SYSMGR_PINMUX_GPLMUX64_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX64 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_OFST 0x2d4 - -/* - * Register : GPIO/LoanIO 65 Output/Output Enable Mux Selection Register - GPLMUX65 - * - * Selection between GPIO and LoanIO output and output enable for GPIO65 and - * LoanIO65. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO65Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 65. - * - * 0 : LoanIO 65 controls GPIO/LOANIO[65] output and output enable signals. - * - * 1 : GPIO 65 controls GPIO/LOANI[65] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX65_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX65_s -{ - uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX65_s ALT_SYSMGR_PINMUX_GPLMUX65_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX65 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_OFST 0x2d8 - -/* - * Register : GPIO/LoanIO 66 Output/Output Enable Mux Selection Register - GPLMUX66 - * - * Selection between GPIO and LoanIO output and output enable for GPIO66 and - * LoanIO66. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO66Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 66. - * - * 0 : LoanIO 66 controls GPIO/LOANIO[66] output and output enable signals. - * - * 1 : GPIO 66 controls GPIO/LOANI[66] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX66_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX66_s -{ - uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX66_s ALT_SYSMGR_PINMUX_GPLMUX66_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX66 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_OFST 0x2dc - -/* - * Register : GPIO/LoanIO 67 Output/Output Enable Mux Selection Register - GPLMUX67 - * - * Selection between GPIO and LoanIO output and output enable for GPIO67 and - * LoanIO67. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO67Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 67. - * - * 0 : LoanIO 67 controls GPIO/LOANIO[67] output and output enable signals. - * - * 1 : GPIO 67 controls GPIO/LOANI[67] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX67_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX67_s -{ - uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX67_s ALT_SYSMGR_PINMUX_GPLMUX67_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX67 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_OFST 0x2e0 - -/* - * Register : GPIO/LoanIO 68 Output/Output Enable Mux Selection Register - GPLMUX68 - * - * Selection between GPIO and LoanIO output and output enable for GPIO68 and - * LoanIO68. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO68Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 68. - * - * 0 : LoanIO 68 controls GPIO/LOANIO[68] output and output enable signals. - * - * 1 : GPIO 68 controls GPIO/LOANI[68] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX68_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX68_s -{ - uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX68_s ALT_SYSMGR_PINMUX_GPLMUX68_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX68 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_OFST 0x2e4 - -/* - * Register : GPIO/LoanIO 69 Output/Output Enable Mux Selection Register - GPLMUX69 - * - * Selection between GPIO and LoanIO output and output enable for GPIO69 and - * LoanIO69. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO69Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 69. - * - * 0 : LoanIO 69 controls GPIO/LOANIO[69] output and output enable signals. - * - * 1 : GPIO 69 controls GPIO/LOANI[69] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX69_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX69_s -{ - uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX69_s ALT_SYSMGR_PINMUX_GPLMUX69_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX69 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_OFST 0x2e8 - -/* - * Register : GPIO/LoanIO 70 Output/Output Enable Mux Selection Register - GPLMUX70 - * - * Selection between GPIO and LoanIO output and output enable for GPIO70 and - * LoanIO70. These signals drive the Pin Mux. The Pin Mux must be configured to use - * GPIO/LoanIO in addition to these settings - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------------------- - * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : GPIO/Loan IO70Input Mux Selection Field - sel - * - * Select source for GPIO/LoanIO 70. - * - * 0 : LoanIO 70 controls GPIO/LOANIO[70] output and output enable signals. - * - * 1 : GPIO 70 controls GPIO/LOANI[70] output and output enable signals. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_GPLMUX70_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. - */ -struct ALT_SYSMGR_PINMUX_GPLMUX70_s -{ - uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. */ -typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX70_s ALT_SYSMGR_PINMUX_GPLMUX70_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX70 register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_OFST 0x2ec - -/* - * Register : Select source for NAND signals (HPS Pins or FPGA Interface) - NANDUSEFPGA - * - * Selection between HPS Pins and FPGA Interface for NAND signals. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------- - * [0] | RW | 0x0 | Selection for NAND signals - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Selection for NAND signals - sel - * - * Select connection for NAND. - * - * 0 : NAND uses HPS Pins. - * - * 1 : NAND uses the FPGA Inteface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. - */ -struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s -{ - uint32_t sel : 1; /* Selection for NAND signals */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. */ -typedef volatile struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s ALT_SYSMGR_PINMUX_NANDUSEFPGA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST 0x2f0 - -/* - * Register : Select source for RGMII1 signals (HPS Pins or FPGA Interface) - RGMII1USEFPGA - * - * Selection between HPS Pins and FPGA Interface for RGMII1 signals. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [0] | RW | 0x0 | Selection for RGMII1 signals - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Selection for RGMII1 signals - sel - * - * Select connection for RGMII1. - * - * 0 : RGMII1 uses HPS Pins. - * - * 1 : RGMII1 uses the FPGA Inteface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. - */ -struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s -{ - uint32_t sel : 1; /* Selection for RGMII1 signals */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. */ -typedef volatile struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST 0x2f8 - -/* - * Register : Select source for I2C0 signals (HPS Pins or FPGA Interface) - I2C0USEFPGA - * - * Selection between HPS Pins and FPGA Interface for I2C0 signals. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------- - * [0] | RW | 0x0 | Selection for I2C0 signals - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Selection for I2C0 signals - sel - * - * Select connection for I2C0. - * - * 0 : I2C0 uses HPS Pins. - * - * 1 : I2C0 uses the FPGA Inteface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. - */ -struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s -{ - uint32_t sel : 1; /* Selection for I2C0 signals */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. */ -typedef volatile struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s ALT_SYSMGR_PINMUX_I2C0USEFPGA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST 0x304 - -/* - * Register : Select source for RGMII0 signals (HPS Pins or FPGA Interface) - RGMII0USEFPGA - * - * Selection between HPS Pins and FPGA Interface for RGMII0 signals. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [0] | RW | 0x0 | Selection for RGMII0 signals - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Selection for RGMII0 signals - sel - * - * Select connection for RGMII0. - * - * 0 : RGMII0 uses HPS Pins. - * - * 1 : RGMII0 uses the FPGA Inteface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. - */ -struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s -{ - uint32_t sel : 1; /* Selection for RGMII0 signals */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. */ -typedef volatile struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST 0x314 - -/* - * Register : Select source for I2C3 signals (HPS Pins or FPGA Interface) - I2C3USEFPGA - * - * Selection between HPS Pins and FPGA Interface for I2C3 signals. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------- - * [0] | RW | 0x0 | Selection for I2C3 signals - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Selection for I2C3 signals - sel - * - * Select connection for I2C3. - * - * 0 : I2C3 uses HPS Pins. - * - * 1 : I2C3 uses the FPGA Inteface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. - */ -struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s -{ - uint32_t sel : 1; /* Selection for I2C3 signals */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. */ -typedef volatile struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s ALT_SYSMGR_PINMUX_I2C3USEFPGA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST 0x324 - -/* - * Register : Select source for I2C2 signals (HPS Pins or FPGA Interface) - I2C2USEFPGA - * - * Selection between HPS Pins and FPGA Interface for I2C2 signals. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------- - * [0] | RW | 0x0 | Selection for I2C2 signals - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Selection for I2C2 signals - sel - * - * Select connection for I2C2. - * - * 0 : I2C2 uses HPS Pins. - * - * 1 : I2C2 uses the FPGA Inteface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. - */ -struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s -{ - uint32_t sel : 1; /* Selection for I2C2 signals */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. */ -typedef volatile struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s ALT_SYSMGR_PINMUX_I2C2USEFPGA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST 0x328 - -/* - * Register : Select source for I2C1 signals (HPS Pins or FPGA Interface) - I2C1USEFPGA - * - * Selection between HPS Pins and FPGA Interface for I2C1 signals. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------------- - * [0] | RW | 0x0 | Selection for I2C1 signals - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Selection for I2C1 signals - sel - * - * Select connection for I2C1. - * - * 0 : I2C1 uses HPS Pins. - * - * 1 : I2C1 uses the FPGA Inteface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. - */ -struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s -{ - uint32_t sel : 1; /* Selection for I2C1 signals */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. */ -typedef volatile struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s ALT_SYSMGR_PINMUX_I2C1USEFPGA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST 0x32c - -/* - * Register : Select source for SPIM1 signals (HPS Pins or FPGA Interface) - SPIM1USEFPGA - * - * Selection between HPS Pins and FPGA Interface for SPIM1 signals. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [0] | RW | 0x0 | Selection for SPIM1 signals - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Selection for SPIM1 signals - sel - * - * Select connection for SPIM1. - * - * 0 : SPIM1 uses HPS Pins. - * - * 1 : SPIM1 uses the FPGA Inteface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. - */ -struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s -{ - uint32_t sel : 1; /* Selection for SPIM1 signals */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. */ -typedef volatile struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST 0x330 - -/* - * Register : Select source for SPIM0 signals (HPS Pins or FPGA Interface) - SPIM0USEFPGA - * - * Selection between HPS Pins and FPGA Interface for SPIM0 signals. - * - * Only reset by a cold reset (ignores warm reset). - * - * NOTE: These registers should not be modified after IO configuration.There is no - * support for dynamically changing the Pin Mux selections. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------------- - * [0] | RW | 0x0 | Selection for SPIM0 signals - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Selection for SPIM0 signals - sel - * - * Select connection for SPIM0. - * - * 0 : SPIM0 uses HPS Pins. - * - * 1 : SPIM0 uses the FPGA Inteface. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_MSB 0 -/* The width in bits of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_WIDTH 1 -/* The mask used to set the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET_MSK 0x00000001 -/* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_CLR_MSK 0xfffffffe -/* The reset value of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_RESET 0x0 -/* Extracts the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL field value from a register. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value suitable for setting the register. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. - */ -struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s -{ - uint32_t sel : 1; /* Selection for SPIM0 signals */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. */ -typedef volatile struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register from the beginning of the component. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST 0x338 - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR_PINMUX. - */ -struct ALT_SYSMGR_PINMUX_s -{ - volatile ALT_SYSMGR_PINMUX_EMACIO0_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */ - volatile ALT_SYSMGR_PINMUX_EMACIO1_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */ - volatile ALT_SYSMGR_PINMUX_EMACIO2_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */ - volatile ALT_SYSMGR_PINMUX_EMACIO3_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */ - volatile ALT_SYSMGR_PINMUX_EMACIO4_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */ - volatile ALT_SYSMGR_PINMUX_EMACIO5_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */ - volatile ALT_SYSMGR_PINMUX_EMACIO6_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */ - volatile ALT_SYSMGR_PINMUX_EMACIO7_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */ - volatile ALT_SYSMGR_PINMUX_EMACIO8_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */ - volatile ALT_SYSMGR_PINMUX_EMACIO9_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */ - volatile ALT_SYSMGR_PINMUX_EMACIO10_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */ - volatile ALT_SYSMGR_PINMUX_EMACIO11_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */ - volatile ALT_SYSMGR_PINMUX_EMACIO12_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */ - volatile ALT_SYSMGR_PINMUX_EMACIO13_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */ - volatile ALT_SYSMGR_PINMUX_EMACIO14_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */ - volatile ALT_SYSMGR_PINMUX_EMACIO15_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */ - volatile ALT_SYSMGR_PINMUX_EMACIO16_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */ - volatile ALT_SYSMGR_PINMUX_EMACIO17_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */ - volatile ALT_SYSMGR_PINMUX_EMACIO18_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */ - volatile ALT_SYSMGR_PINMUX_EMACIO19_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO0_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO1_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO2_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO3_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO4_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO5_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO6_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO7_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO8_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO9_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO10_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */ - volatile ALT_SYSMGR_PINMUX_FLSHIO11_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO0_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO1_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO2_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO3_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO4_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO5_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO6_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO7_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO8_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO9_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO10_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO11_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO12_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO13_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO14_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO15_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO16_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO17_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO18_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO19_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO20_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO21_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO22_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO23_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO24_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO25_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO26_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO27_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO28_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO29_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO30_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */ - volatile ALT_SYSMGR_PINMUX_GENERALIO31_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO0_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO1_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO2_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO3_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO4_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO5_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO6_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO7_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO8_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO9_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO10_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO11_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO12_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO13_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO14_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO15_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO16_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO17_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO18_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO19_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO20_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */ - volatile ALT_SYSMGR_PINMUX_MIXED1IO21_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */ - volatile ALT_SYSMGR_PINMUX_MIXED2IO0_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */ - volatile ALT_SYSMGR_PINMUX_MIXED2IO1_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */ - volatile ALT_SYSMGR_PINMUX_MIXED2IO2_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */ - volatile ALT_SYSMGR_PINMUX_MIXED2IO3_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */ - volatile ALT_SYSMGR_PINMUX_MIXED2IO4_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */ - volatile ALT_SYSMGR_PINMUX_MIXED2IO5_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */ - volatile ALT_SYSMGR_PINMUX_MIXED2IO6_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */ - volatile ALT_SYSMGR_PINMUX_MIXED2IO7_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX48_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX49_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX50_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX51_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX52_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX53_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX54_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX55_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX56_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX57_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX58_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX59_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX60_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX61_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX62_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX63_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX64_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX65_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX66_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX67_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX68_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX69_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */ - volatile ALT_SYSMGR_PINMUX_GPLINMUX70_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX0_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX1_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX2_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX3_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX4_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX5_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX6_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX7_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX8_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX9_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX10_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX11_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX12_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX13_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX14_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX15_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX16_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX17_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX18_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX19_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX20_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX21_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX22_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX23_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX24_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX25_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX26_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX27_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX28_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX29_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX30_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX31_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX33_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX34_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX35_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX36_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX37_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX38_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX39_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX40_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX41_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX42_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX43_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX44_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX45_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX46_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX47_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX48_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX49_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX50_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX51_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX52_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX53_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX54_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX55_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX56_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX57_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX58_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX59_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX60_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX61_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX62_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX63_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX64_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX65_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX66_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX67_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX68_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX69_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */ - volatile ALT_SYSMGR_PINMUX_GPLMUX70_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */ - volatile ALT_SYSMGR_PINMUX_NANDUSEFPGA_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */ - volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */ - volatile ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */ - volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_PINMUX_I2C0USEFPGA_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */ - volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */ - volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_PINMUX_I2C3USEFPGA_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */ - volatile ALT_SYSMGR_PINMUX_I2C2USEFPGA_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */ - volatile ALT_SYSMGR_PINMUX_I2C1USEFPGA_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */ - volatile ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */ - volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */ - volatile ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */ - volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_SYSMGR_PINMUX. */ -typedef volatile struct ALT_SYSMGR_PINMUX_s ALT_SYSMGR_PINMUX_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */ -struct ALT_SYSMGR_PINMUX_raw_s -{ - volatile uint32_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */ - volatile uint32_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */ - volatile uint32_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */ - volatile uint32_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */ - volatile uint32_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */ - volatile uint32_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */ - volatile uint32_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */ - volatile uint32_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */ - volatile uint32_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */ - volatile uint32_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */ - volatile uint32_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */ - volatile uint32_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */ - volatile uint32_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */ - volatile uint32_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */ - volatile uint32_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */ - volatile uint32_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */ - volatile uint32_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */ - volatile uint32_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */ - volatile uint32_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */ - volatile uint32_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */ - volatile uint32_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */ - volatile uint32_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */ - volatile uint32_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */ - volatile uint32_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */ - volatile uint32_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */ - volatile uint32_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */ - volatile uint32_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */ - volatile uint32_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */ - volatile uint32_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */ - volatile uint32_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */ - volatile uint32_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */ - volatile uint32_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */ - volatile uint32_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */ - volatile uint32_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */ - volatile uint32_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */ - volatile uint32_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */ - volatile uint32_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */ - volatile uint32_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */ - volatile uint32_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */ - volatile uint32_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */ - volatile uint32_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */ - volatile uint32_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */ - volatile uint32_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */ - volatile uint32_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */ - volatile uint32_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */ - volatile uint32_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */ - volatile uint32_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */ - volatile uint32_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */ - volatile uint32_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */ - volatile uint32_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */ - volatile uint32_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */ - volatile uint32_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */ - volatile uint32_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */ - volatile uint32_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */ - volatile uint32_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */ - volatile uint32_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */ - volatile uint32_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */ - volatile uint32_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */ - volatile uint32_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */ - volatile uint32_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */ - volatile uint32_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */ - volatile uint32_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */ - volatile uint32_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */ - volatile uint32_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */ - volatile uint32_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */ - volatile uint32_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */ - volatile uint32_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */ - volatile uint32_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */ - volatile uint32_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */ - volatile uint32_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */ - volatile uint32_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */ - volatile uint32_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */ - volatile uint32_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */ - volatile uint32_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */ - volatile uint32_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */ - volatile uint32_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */ - volatile uint32_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */ - volatile uint32_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */ - volatile uint32_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */ - volatile uint32_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */ - volatile uint32_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */ - volatile uint32_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */ - volatile uint32_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */ - volatile uint32_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */ - volatile uint32_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */ - volatile uint32_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */ - volatile uint32_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */ - volatile uint32_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */ - volatile uint32_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */ - volatile uint32_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */ - volatile uint32_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */ - volatile uint32_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */ - volatile uint32_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */ - volatile uint32_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */ - volatile uint32_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */ - volatile uint32_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */ - volatile uint32_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */ - volatile uint32_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */ - volatile uint32_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */ - volatile uint32_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */ - volatile uint32_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */ - volatile uint32_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */ - volatile uint32_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */ - volatile uint32_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */ - volatile uint32_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */ - volatile uint32_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */ - volatile uint32_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */ - volatile uint32_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */ - volatile uint32_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */ - volatile uint32_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */ - volatile uint32_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */ - volatile uint32_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */ - volatile uint32_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */ - volatile uint32_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */ - volatile uint32_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */ - volatile uint32_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */ - volatile uint32_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */ - volatile uint32_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */ - volatile uint32_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */ - volatile uint32_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */ - volatile uint32_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */ - volatile uint32_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */ - volatile uint32_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */ - volatile uint32_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */ - volatile uint32_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */ - volatile uint32_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */ - volatile uint32_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */ - volatile uint32_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */ - volatile uint32_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */ - volatile uint32_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */ - volatile uint32_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */ - volatile uint32_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */ - volatile uint32_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */ - volatile uint32_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */ - volatile uint32_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */ - volatile uint32_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */ - volatile uint32_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */ - volatile uint32_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */ - volatile uint32_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */ - volatile uint32_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */ - volatile uint32_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */ - volatile uint32_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */ - volatile uint32_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */ - volatile uint32_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */ - volatile uint32_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */ - volatile uint32_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */ - volatile uint32_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */ - volatile uint32_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */ - volatile uint32_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */ - volatile uint32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */ - volatile uint32_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */ - volatile uint32_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */ - volatile uint32_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */ - volatile uint32_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */ - volatile uint32_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */ - volatile uint32_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */ - volatile uint32_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */ - volatile uint32_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */ - volatile uint32_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */ - volatile uint32_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */ - volatile uint32_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */ - volatile uint32_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */ - volatile uint32_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */ - volatile uint32_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */ - volatile uint32_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */ - volatile uint32_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */ - volatile uint32_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */ - volatile uint32_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */ - volatile uint32_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */ - volatile uint32_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */ - volatile uint32_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */ - volatile uint32_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */ - volatile uint32_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */ - volatile uint32_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */ - volatile uint32_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */ - volatile uint32_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */ - volatile uint32_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */ - volatile uint32_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */ - volatile uint32_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */ - volatile uint32_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */ - volatile uint32_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */ - volatile uint32_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */ - volatile uint32_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */ - volatile uint32_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */ - volatile uint32_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */ - volatile uint32_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */ - volatile uint32_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */ - volatile uint32_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */ - volatile uint32_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */ - volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */ - volatile uint32_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */ - volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */ - volatile uint32_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */ - volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */ - volatile uint32_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */ - volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */ - volatile uint32_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */ - volatile uint32_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */ - volatile uint32_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */ - volatile uint32_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */ - volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */ - volatile uint32_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */ - volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */ -typedef volatile struct ALT_SYSMGR_PINMUX_raw_s ALT_SYSMGR_PINMUX_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_SYSMGR. - */ -struct ALT_SYSMGR_s -{ - volatile ALT_SYSMGR_SILICONID1_t siliconid1; /* ALT_SYSMGR_SILICONID1 */ - volatile ALT_SYSMGR_SILICONID2_t siliconid2; /* ALT_SYSMGR_SILICONID2 */ - volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_WDDBG_t wddbg; /* ALT_SYSMGR_WDDBG */ - volatile ALT_SYSMGR_BOOT_t bootinfo; /* ALT_SYSMGR_BOOT */ - volatile ALT_SYSMGR_HPSINFO_t hpsinfo; /* ALT_SYSMGR_HPSINFO */ - volatile ALT_SYSMGR_PARITYINJ_t parityinj; /* ALT_SYSMGR_PARITYINJ */ - volatile ALT_SYSMGR_FPGAINTF_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */ - volatile ALT_SYSMGR_SCANMGR_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */ - volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_FRZCTL_t frzctrl; /* ALT_SYSMGR_FRZCTL */ - volatile ALT_SYSMGR_EMAC_t emacgrp; /* ALT_SYSMGR_EMAC */ - volatile ALT_SYSMGR_DMA_t dmagrp; /* ALT_SYSMGR_DMA */ - volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_ISW_t iswgrp; /* ALT_SYSMGR_ISW */ - volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_ROMCODE_t romcodegrp; /* ALT_SYSMGR_ROMCODE */ - volatile ALT_SYSMGR_ROMHW_t romhwgrp; /* ALT_SYSMGR_ROMHW */ - volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ - volatile ALT_SYSMGR_SDMMC_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */ - volatile ALT_SYSMGR_NAND_t nandgrp; /* ALT_SYSMGR_NAND */ - volatile ALT_SYSMGR_USB_t usbgrp; /* ALT_SYSMGR_USB */ - volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_ECC_t eccgrp; /* ALT_SYSMGR_ECC */ - volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_PINMUX_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */ - volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register group ALT_SYSMGR. */ -typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t; -/* The struct declaration for the raw register contents of register group ALT_SYSMGR. */ -struct ALT_SYSMGR_raw_s -{ - volatile uint32_t siliconid1; /* ALT_SYSMGR_SILICONID1 */ - volatile uint32_t siliconid2; /* ALT_SYSMGR_SILICONID2 */ - volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */ - volatile uint32_t wddbg; /* ALT_SYSMGR_WDDBG */ - volatile uint32_t bootinfo; /* ALT_SYSMGR_BOOT */ - volatile uint32_t hpsinfo; /* ALT_SYSMGR_HPSINFO */ - volatile uint32_t parityinj; /* ALT_SYSMGR_PARITYINJ */ - volatile ALT_SYSMGR_FPGAINTF_raw_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */ - volatile ALT_SYSMGR_SCANMGR_raw_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */ - volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_FRZCTL_raw_t frzctrl; /* ALT_SYSMGR_FRZCTL */ - volatile ALT_SYSMGR_EMAC_raw_t emacgrp; /* ALT_SYSMGR_EMAC */ - volatile ALT_SYSMGR_DMA_raw_t dmagrp; /* ALT_SYSMGR_DMA */ - volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_ISW_raw_t iswgrp; /* ALT_SYSMGR_ISW */ - volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_ROMCODE_raw_t romcodegrp; /* ALT_SYSMGR_ROMCODE */ - volatile ALT_SYSMGR_ROMHW_raw_t romhwgrp; /* ALT_SYSMGR_ROMHW */ - volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */ - volatile ALT_SYSMGR_SDMMC_raw_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */ - volatile ALT_SYSMGR_NAND_raw_t nandgrp; /* ALT_SYSMGR_NAND */ - volatile ALT_SYSMGR_USB_raw_t usbgrp; /* ALT_SYSMGR_USB */ - volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_ECC_raw_t eccgrp; /* ALT_SYSMGR_ECC */ - volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */ - volatile ALT_SYSMGR_PINMUX_raw_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */ - volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_SYSMGR. */ -typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_SYSMGR_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_uart.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_uart.h deleted file mode 100644 index b64111960b..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/alt_uart.h +++ /dev/null @@ -1,5158 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - ALT_UART */ - -#ifndef __ALTERA_ALT_UART_H__ -#define __ALTERA_ALT_UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Component : UART Module - ALT_UART - * UART Module - * - * Registers in the UART module - * - */ -/* - * Register : Rx Buffer, Tx Holding, and Divisor Latch Low - rbr_thr_dll - * - * This is a multi-function register. This register holds receives and transmit - * data and controls the least-signficant 8 bits of the baud rate divisor. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------ - * [7:0] | RW | 0x0 | Value - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Value - value - * - * Receive Buffer Register: - * - * This register contains the data byte received on the serial input port - * (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0] - * in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of - * Register FCR is set to 0) the data in the RBR must be read before the next data - * arrives, otherwise it will be overwritten, resulting in an overrun error. If - * FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses - * the head of the receive FIFO. If the receive FIFO is full, and this register is - * not read before the next data character arrives, then the data already in the - * FIFO will be preserved but any incoming data will be lost. An overrun error will - * also occur. - * - * Transmit Holding Register: - * - * This register contains data to be transmitted on the serial output port. Data - * should only be written to the THR when the THR Empty bit [5] of the LSR Register - * is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and - * THRE is set to 1, writing a single character to the THR clears the THRE. Any - * additional writes to the THR before the THRE is set again causes the THR data to - * be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and - * THRE is set up to 128 characters of data may be written to the THR before the - * FIFO is full. Any attempt to write data when the FIFO is full results in the - * write data being lost. - * - * Divisor Latch Low: - * - * This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch - * register that contains the baud rate divisor for the UART. This register may - * only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The - * output baud rate is equal to the serial clock l4_sp_clk frequency divided by - * sixteen times the value of the baud rate divisor, as follows: - * - * baud rate = (serial clock freq) / (16 * divisor) - * - * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud - * clock is disabled and no serial communications will occur. Also, once the DLL is - * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before - * transmitting or receiving data. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */ -#define ALT_UART_RBR_THR_DLL_VALUE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */ -#define ALT_UART_RBR_THR_DLL_VALUE_MSB 7 -/* The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field. */ -#define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8 -/* The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value. */ -#define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff -/* The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value. */ -#define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00 -/* The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field. */ -#define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0 -/* Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register. */ -#define ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register. */ -#define ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_RBR_THR_DLL. - */ -struct ALT_UART_RBR_THR_DLL_s -{ - uint32_t value : 8; /* Value */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_RBR_THR_DLL. */ -typedef volatile struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component. */ -#define ALT_UART_RBR_THR_DLL_OFST 0x0 -/* The address of the ALT_UART_RBR_THR_DLL register. */ -#define ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST)) - -/* - * Register : Interrupt Enable and Divisor Latch High - ier_dlh - * - * This is a multi-function register. This register enables/disables receive and - * transmit interrupts and also controls the most-significant 8-bits of the baud - * rate divisor. - * - * Divisor Latch High Register: - * - * This register is accessed when the DLAB bit [7] of the LCR Register is set to - * 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output - * baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen - * times the value of the baud rate divisor, as follows: - * - * baud rate = (serial clock freq) / (16 * divisor): - * - * Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud - * clock is disabled and no serial communications will occur. Also, once the DLL is - * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before - * transmitting or receiving data. - * - * Interrupt Enable Register: - * - * This register may only be accessed when the DLAB bit [7] of the LCR Register is - * set to 0.Allows control of the Interrupt Enables for transmit and receive - * functions. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------------------- - * [0] | RW | 0x0 | DLH[0] and Receive Data Interrupt Enable - * [1] | RW | 0x0 | DLH[1] and Transmit Data Interrupt Control - * [2] | RW | 0x0 | DLH[2] and Enable Receiver Line Status - * [3] | RW | 0x0 | DLH[3] and Enable Modem Status Interrupt - * [4] | RW | 0x0 | DLH[4] - * [5] | RW | 0x0 | DLH[5] - * [6] | RW | 0x0 | DLH[6] - * [7] | RW | 0x0 | DLH[7] and PTIME THRE Interrupt Mode Enable - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0 - * - * Divisor Latch High Register: - * - * Bit 0 of DLH value. - * - * Interrupt Enable Register: - * - * Used to enable/disable the generation of the Receive Data Available Interrupt - * and the Character Timeout Interrupt(if FIFO's enabled). These are the second - * highest priority interrupts. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:------------------ - * ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD | 0x0 | Interrupt Disable - * ALT_UART_IER_DLH_ERBFI_DLH0_E_END | 0x1 | Interrupt Enable - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0 - * - * Interrupt Disable - */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0 - * - * Interrupt Enable - */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_MSB 0 -/* The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH 1 -/* The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_RESET 0x0 -/* Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register. */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register. */ -#define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl - * - * Divisor Latch High Register: - * - * Bit 1 of DLH value. - * - * Interrupt Enable Register: - * - * Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable - * the generation of Transmitter Holding Register Empty Interrupt. This is the - * third highest priority interrupt. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:------------ - * ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD | 0x0 | Tx disable - * ALT_UART_IER_DLH_ETBEI_DLHL_E_END | 0x1 | Tx enable - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL - * - * Tx disable - */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL - * - * Tx enable - */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_MSB 1 -/* The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH 1 -/* The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK 0x00000002 -/* The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK 0xfffffffd -/* The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_RESET 0x0 -/* Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register. */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register. */ -#define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2 - * - * Divisor Latch High Register: - * - * Bit 2 of DLH value. - * - * Interrupt Enable Register: - * - * This is used to enable/disable the generation of Receiver Line Status Interrupt. - * This is the highest priority interrupt. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:---------------------------- - * ALT_UART_IER_DLH_ELSI_DHL2_E_DISD | 0x0 | Disable interrupt line stat - * ALT_UART_IER_DLH_ELSI_DHL2_E_END | 0x1 | Enable interrupt line stat - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2 - * - * Disable interrupt line stat - */ -#define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2 - * - * Enable interrupt line stat - */ -#define ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ -#define ALT_UART_IER_DLH_ELSI_DHL2_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ -#define ALT_UART_IER_DLH_ELSI_DHL2_MSB 2 -/* The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ -#define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH 1 -/* The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */ -#define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK 0x00000004 -/* The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */ -#define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK 0xfffffffb -/* The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */ -#define ALT_UART_IER_DLH_ELSI_DHL2_RESET 0x0 -/* Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register. */ -#define ALT_UART_IER_DLH_ELSI_DHL2_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register. */ -#define ALT_UART_IER_DLH_ELSI_DHL2_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3 - * - * Divisor Latch High Register: - * - * Bit 3 of DLH value. - * - * Interrupt Enable Register: - * - * This is used to enable/disable the generation of Modem Status Interrupts. This - * is the fourth highest priority interrupt. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:------------------------------- - * ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD | 0x0 | disable modem status interrupt - * ALT_UART_IER_DLH_EDSSI_DHL3_E_END | 0x1 | enable modem status interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3 - * - * disable modem status interrupt - */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3 - * - * enable modem status interrupt - */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_MSB 3 -/* The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH 1 -/* The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK 0x00000008 -/* The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_RESET 0x0 -/* Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register. */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register. */ -#define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : DLH[4] - dlh4 - * - * Bit 4 of DLH value. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field. */ -#define ALT_UART_IER_DLH_DLH4_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field. */ -#define ALT_UART_IER_DLH_DLH4_MSB 4 -/* The width in bits of the ALT_UART_IER_DLH_DLH4 register field. */ -#define ALT_UART_IER_DLH_DLH4_WIDTH 1 -/* The mask used to set the ALT_UART_IER_DLH_DLH4 register field value. */ -#define ALT_UART_IER_DLH_DLH4_SET_MSK 0x00000010 -/* The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value. */ -#define ALT_UART_IER_DLH_DLH4_CLR_MSK 0xffffffef -/* The reset value of the ALT_UART_IER_DLH_DLH4 register field. */ -#define ALT_UART_IER_DLH_DLH4_RESET 0x0 -/* Extracts the ALT_UART_IER_DLH_DLH4 field value from a register. */ -#define ALT_UART_IER_DLH_DLH4_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register. */ -#define ALT_UART_IER_DLH_DLH4_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : DLH[5] - dlh5 - * - * Bit 5 of DLH value. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field. */ -#define ALT_UART_IER_DLH_DLH5_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field. */ -#define ALT_UART_IER_DLH_DLH5_MSB 5 -/* The width in bits of the ALT_UART_IER_DLH_DLH5 register field. */ -#define ALT_UART_IER_DLH_DLH5_WIDTH 1 -/* The mask used to set the ALT_UART_IER_DLH_DLH5 register field value. */ -#define ALT_UART_IER_DLH_DLH5_SET_MSK 0x00000020 -/* The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value. */ -#define ALT_UART_IER_DLH_DLH5_CLR_MSK 0xffffffdf -/* The reset value of the ALT_UART_IER_DLH_DLH5 register field. */ -#define ALT_UART_IER_DLH_DLH5_RESET 0x0 -/* Extracts the ALT_UART_IER_DLH_DLH5 field value from a register. */ -#define ALT_UART_IER_DLH_DLH5_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register. */ -#define ALT_UART_IER_DLH_DLH5_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : DLH[6] - dlh6 - * - * Bit 6 of DLH value. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field. */ -#define ALT_UART_IER_DLH_DLH6_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field. */ -#define ALT_UART_IER_DLH_DLH6_MSB 6 -/* The width in bits of the ALT_UART_IER_DLH_DLH6 register field. */ -#define ALT_UART_IER_DLH_DLH6_WIDTH 1 -/* The mask used to set the ALT_UART_IER_DLH_DLH6 register field value. */ -#define ALT_UART_IER_DLH_DLH6_SET_MSK 0x00000040 -/* The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value. */ -#define ALT_UART_IER_DLH_DLH6_CLR_MSK 0xffffffbf -/* The reset value of the ALT_UART_IER_DLH_DLH6 register field. */ -#define ALT_UART_IER_DLH_DLH6_RESET 0x0 -/* Extracts the ALT_UART_IER_DLH_DLH6 field value from a register. */ -#define ALT_UART_IER_DLH_DLH6_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register. */ -#define ALT_UART_IER_DLH_DLH6_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7 - * - * Divisor Latch High Register: - * - * Bit 7 of DLH value. - * - * Interrupt Enable Register: - * - * This is used to enable/disable the generation of THRE Interrupt. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:------------------------------------ - * ALT_UART_IER_DLH_PTIME_DLH7_E_DISD | 0x0 | disable tx-hold-reg-empty interrupt - * ALT_UART_IER_DLH_PTIME_DLH7_E_END | 0x1 | enable tx-hold-reg-empty interrupt - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7 - * - * disable tx-hold-reg-empty interrupt - */ -#define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7 - * - * enable tx-hold-reg-empty interrupt - */ -#define ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ -#define ALT_UART_IER_DLH_PTIME_DLH7_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ -#define ALT_UART_IER_DLH_PTIME_DLH7_MSB 7 -/* The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ -#define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH 1 -/* The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */ -#define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK 0x00000080 -/* The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */ -#define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK 0xffffff7f -/* The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */ -#define ALT_UART_IER_DLH_PTIME_DLH7_RESET 0x0 -/* Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register. */ -#define ALT_UART_IER_DLH_PTIME_DLH7_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register. */ -#define ALT_UART_IER_DLH_PTIME_DLH7_SET(value) (((value) << 7) & 0x00000080) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_IER_DLH. - */ -struct ALT_UART_IER_DLH_s -{ - uint32_t erbfi_dlh0 : 1; /* DLH[0] and Receive Data Interrupt Enable */ - uint32_t etbei_dlhl : 1; /* DLH[1] and Transmit Data Interrupt Control */ - uint32_t elsi_dhl2 : 1; /* DLH[2] and Enable Receiver Line Status */ - uint32_t edssi_dhl3 : 1; /* DLH[3] and Enable Modem Status Interrupt */ - uint32_t dlh4 : 1; /* DLH[4] */ - uint32_t dlh5 : 1; /* DLH[5] */ - uint32_t dlh6 : 1; /* DLH[6] */ - uint32_t ptime_dlh7 : 1; /* DLH[7] and PTIME THRE Interrupt Mode Enable */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_IER_DLH. */ -typedef volatile struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_IER_DLH register from the beginning of the component. */ -#define ALT_UART_IER_DLH_OFST 0x4 -/* The address of the ALT_UART_IER_DLH register. */ -#define ALT_UART_IER_DLH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST)) - -/* - * Register : Interrupt Identity Register (when read) - iir - * - * Returns interrupt identification and FIFO enable/disable when read. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------- - * [3:0] | R | 0x1 | Interrupt ID - * [5:4] | ??? | 0x0 | *UNDEFINED* - * [7:6] | R | 0x0 | FIFO Enabled - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Interrupt ID - id - * - * This indicates the highest priority pending interrupt. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:----------------------- - * ALT_UART_IIR_ID_E_MODMSTAT | 0x0 | Modem status - * ALT_UART_IIR_ID_E_NOINTRPENDING | 0x1 | No Interrupt pending - * ALT_UART_IIR_ID_E_THREMPTY | 0x2 | THR empty - * ALT_UART_IIR_ID_E_RXDATAVAILABLE | 0x4 | Receive data available - * ALT_UART_IIR_ID_E_RXLINESTAT | 0x6 | Receive line status - * ALT_UART_IIR_ID_E_CHARTMO | 0xc | Character timeout - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_IIR_ID - * - * Modem status - */ -#define ALT_UART_IIR_ID_E_MODMSTAT 0x0 -/* - * Enumerated value for register field ALT_UART_IIR_ID - * - * No Interrupt pending - */ -#define ALT_UART_IIR_ID_E_NOINTRPENDING 0x1 -/* - * Enumerated value for register field ALT_UART_IIR_ID - * - * THR empty - */ -#define ALT_UART_IIR_ID_E_THREMPTY 0x2 -/* - * Enumerated value for register field ALT_UART_IIR_ID - * - * Receive data available - */ -#define ALT_UART_IIR_ID_E_RXDATAVAILABLE 0x4 -/* - * Enumerated value for register field ALT_UART_IIR_ID - * - * Receive line status - */ -#define ALT_UART_IIR_ID_E_RXLINESTAT 0x6 -/* - * Enumerated value for register field ALT_UART_IIR_ID - * - * Character timeout - */ -#define ALT_UART_IIR_ID_E_CHARTMO 0xc - -/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_ID register field. */ -#define ALT_UART_IIR_ID_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_ID register field. */ -#define ALT_UART_IIR_ID_MSB 3 -/* The width in bits of the ALT_UART_IIR_ID register field. */ -#define ALT_UART_IIR_ID_WIDTH 4 -/* The mask used to set the ALT_UART_IIR_ID register field value. */ -#define ALT_UART_IIR_ID_SET_MSK 0x0000000f -/* The mask used to clear the ALT_UART_IIR_ID register field value. */ -#define ALT_UART_IIR_ID_CLR_MSK 0xfffffff0 -/* The reset value of the ALT_UART_IIR_ID register field. */ -#define ALT_UART_IIR_ID_RESET 0x1 -/* Extracts the ALT_UART_IIR_ID field value from a register. */ -#define ALT_UART_IIR_ID_GET(value) (((value) & 0x0000000f) >> 0) -/* Produces a ALT_UART_IIR_ID register field value suitable for setting the register. */ -#define ALT_UART_IIR_ID_SET(value) (((value) << 0) & 0x0000000f) - -/* - * Field : FIFO Enabled - fifoen - * - * This is used to indicate whether the FIFO's are enabled or disabled. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:-------------- - * ALT_UART_IIR_FIFOEN_E_DISD | 0x0 | FIFO disabled - * ALT_UART_IIR_FIFOEN_E_END | 0x3 | FIFO enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_IIR_FIFOEN - * - * FIFO disabled - */ -#define ALT_UART_IIR_FIFOEN_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_IIR_FIFOEN - * - * FIFO enabled - */ -#define ALT_UART_IIR_FIFOEN_E_END 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOEN register field. */ -#define ALT_UART_IIR_FIFOEN_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOEN register field. */ -#define ALT_UART_IIR_FIFOEN_MSB 7 -/* The width in bits of the ALT_UART_IIR_FIFOEN register field. */ -#define ALT_UART_IIR_FIFOEN_WIDTH 2 -/* The mask used to set the ALT_UART_IIR_FIFOEN register field value. */ -#define ALT_UART_IIR_FIFOEN_SET_MSK 0x000000c0 -/* The mask used to clear the ALT_UART_IIR_FIFOEN register field value. */ -#define ALT_UART_IIR_FIFOEN_CLR_MSK 0xffffff3f -/* The reset value of the ALT_UART_IIR_FIFOEN register field. */ -#define ALT_UART_IIR_FIFOEN_RESET 0x0 -/* Extracts the ALT_UART_IIR_FIFOEN field value from a register. */ -#define ALT_UART_IIR_FIFOEN_GET(value) (((value) & 0x000000c0) >> 6) -/* Produces a ALT_UART_IIR_FIFOEN register field value suitable for setting the register. */ -#define ALT_UART_IIR_FIFOEN_SET(value) (((value) << 6) & 0x000000c0) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_IIR. - */ -struct ALT_UART_IIR_s -{ - const uint32_t id : 4; /* Interrupt ID */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t fifoen : 2; /* FIFO Enabled */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_IIR. */ -typedef volatile struct ALT_UART_IIR_s ALT_UART_IIR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_IIR register from the beginning of the component. */ -#define ALT_UART_IIR_OFST 0x8 -/* The address of the ALT_UART_IIR register. */ -#define ALT_UART_IIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IIR_OFST)) - -/* - * Register : FIFO Control (when written) - fcr - * - * Controls FIFO Operations when written. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:--------|:----------------------- - * [0] | W | Unknown | FIFO Enable - * [1] | W | Unknown | Rx FIFO Reset - * [2] | W | Unknown | Tx FIFO Reset - * [3] | W | Unknown | DMA Mode - * [5:4] | W | Unknown | Tx Empty Trigger Level - * [7:6] | W | Unknown | Rx Trigger Level - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : FIFO Enable - fifoe - * - * Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value - * of this bit is changed both the Tx and Rx controller portion of FIFO's will be - * reset. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:--------------- - * ALT_UART_FCR_FIFOE_E_DISD | 0x0 | FIFOs disabled - * ALT_UART_FCR_FIFOE_E_END | 0x1 | FIFOs enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_FCR_FIFOE - * - * FIFOs disabled - */ -#define ALT_UART_FCR_FIFOE_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_FCR_FIFOE - * - * FIFOs enabled - */ -#define ALT_UART_FCR_FIFOE_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field. */ -#define ALT_UART_FCR_FIFOE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field. */ -#define ALT_UART_FCR_FIFOE_MSB 0 -/* The width in bits of the ALT_UART_FCR_FIFOE register field. */ -#define ALT_UART_FCR_FIFOE_WIDTH 1 -/* The mask used to set the ALT_UART_FCR_FIFOE register field value. */ -#define ALT_UART_FCR_FIFOE_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_FCR_FIFOE register field value. */ -#define ALT_UART_FCR_FIFOE_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_FCR_FIFOE register field is UNKNOWN. */ -#define ALT_UART_FCR_FIFOE_RESET 0x0 -/* Extracts the ALT_UART_FCR_FIFOE field value from a register. */ -#define ALT_UART_FCR_FIFOE_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register. */ -#define ALT_UART_FCR_FIFOE_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Rx FIFO Reset - rfifor - * - * Resets the control portion of the receive FIFO and treats the FIFO as empty. - * This will also de-assert the DMA Rxrequest and single signals. Note that this - * bit is self-clearing' and it is not necessary to clear this bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:---------------------------- - * ALT_UART_FCR_RFIFOR_E_NORST | 0x0 | No Reset of Rx FIFO Control - * ALT_UART_FCR_RFIFOR_E_RST | 0x1 | Resets of Rx FIFO Control - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_FCR_RFIFOR - * - * No Reset of Rx FIFO Control - */ -#define ALT_UART_FCR_RFIFOR_E_NORST 0x0 -/* - * Enumerated value for register field ALT_UART_FCR_RFIFOR - * - * Resets of Rx FIFO Control - */ -#define ALT_UART_FCR_RFIFOR_E_RST 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field. */ -#define ALT_UART_FCR_RFIFOR_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field. */ -#define ALT_UART_FCR_RFIFOR_MSB 1 -/* The width in bits of the ALT_UART_FCR_RFIFOR register field. */ -#define ALT_UART_FCR_RFIFOR_WIDTH 1 -/* The mask used to set the ALT_UART_FCR_RFIFOR register field value. */ -#define ALT_UART_FCR_RFIFOR_SET_MSK 0x00000002 -/* The mask used to clear the ALT_UART_FCR_RFIFOR register field value. */ -#define ALT_UART_FCR_RFIFOR_CLR_MSK 0xfffffffd -/* The reset value of the ALT_UART_FCR_RFIFOR register field is UNKNOWN. */ -#define ALT_UART_FCR_RFIFOR_RESET 0x0 -/* Extracts the ALT_UART_FCR_RFIFOR field value from a register. */ -#define ALT_UART_FCR_RFIFOR_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register. */ -#define ALT_UART_FCR_RFIFOR_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Tx FIFO Reset - xfifor - * - * Resets the control portion of the transmit FIFO and treats the FIFO as empty. - * This will also de-assert the DMA Tx request and single signals when additional - * DMA handshaking is used. - * - * Note that this bit is 'self-clearing' and it is not necessary to clear this bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:---------------------------- - * ALT_UART_FCR_XFIFOR_E_NORST | 0x0 | No Reset of Tx FIFO Control - * ALT_UART_FCR_XFIFOR_E_RST | 0x1 | Resets Tx FIFO Control - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_FCR_XFIFOR - * - * No Reset of Tx FIFO Control - */ -#define ALT_UART_FCR_XFIFOR_E_NORST 0x0 -/* - * Enumerated value for register field ALT_UART_FCR_XFIFOR - * - * Resets Tx FIFO Control - */ -#define ALT_UART_FCR_XFIFOR_E_RST 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field. */ -#define ALT_UART_FCR_XFIFOR_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field. */ -#define ALT_UART_FCR_XFIFOR_MSB 2 -/* The width in bits of the ALT_UART_FCR_XFIFOR register field. */ -#define ALT_UART_FCR_XFIFOR_WIDTH 1 -/* The mask used to set the ALT_UART_FCR_XFIFOR register field value. */ -#define ALT_UART_FCR_XFIFOR_SET_MSK 0x00000004 -/* The mask used to clear the ALT_UART_FCR_XFIFOR register field value. */ -#define ALT_UART_FCR_XFIFOR_CLR_MSK 0xfffffffb -/* The reset value of the ALT_UART_FCR_XFIFOR register field is UNKNOWN. */ -#define ALT_UART_FCR_XFIFOR_RESET 0x0 -/* Extracts the ALT_UART_FCR_XFIFOR field value from a register. */ -#define ALT_UART_FCR_XFIFOR_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register. */ -#define ALT_UART_FCR_XFIFOR_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : DMA Mode - dmam - * - * This determines the DMA signalling mode used for the uart_dma_tx_req_n and - * uart_dma_rx_req_n output signals when additional DMA handshaking signals are not - * selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0, - * the uart_dma_tx_req_n signal goes active low under the following conditions: - * - * * When the Transmitter Holding Register is empty in non-FIFO mode. - * - * * When the transmitter FIFO is empty in FIFO mode with Programmable THRE - * interrupt mode disabled. - * - * * When the transmitter FIFO is at or below the programmed threshold with - * Programmable THRE interrupt mode enabled. - * - * It goes inactive under the following conditions - * - * * When a single character has been written into the Transmitter Holding - * Register or transmitter FIFO with Programmable THRE interrupt mode disabled. - * - * * When the transmitter FIFO is above the threshold with Programmable THRE - * interrupt mode enabled. - * - * DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made - * continuously until the receiver FIFO has been emptied or the transmit FIFO has - * been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the - * following conditions: - * - * * When the transmitter FIFO is empty with Programmable THRE interrupt mode - * disabled. - * - * * When the transmitter FIFO is at or below the programmed threshold with - * Programmable THRE interrupt mode enabled. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:--------------------------- - * ALT_UART_FCR_DMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode - * ALT_UART_FCR_DMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_FCR_DMAM - * - * Single DMA Transfer Mode - */ -#define ALT_UART_FCR_DMAM_E_SINGLE 0x0 -/* - * Enumerated value for register field ALT_UART_FCR_DMAM - * - * Multiple DMA Transfer Mode - */ -#define ALT_UART_FCR_DMAM_E_MULT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field. */ -#define ALT_UART_FCR_DMAM_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field. */ -#define ALT_UART_FCR_DMAM_MSB 3 -/* The width in bits of the ALT_UART_FCR_DMAM register field. */ -#define ALT_UART_FCR_DMAM_WIDTH 1 -/* The mask used to set the ALT_UART_FCR_DMAM register field value. */ -#define ALT_UART_FCR_DMAM_SET_MSK 0x00000008 -/* The mask used to clear the ALT_UART_FCR_DMAM register field value. */ -#define ALT_UART_FCR_DMAM_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_UART_FCR_DMAM register field is UNKNOWN. */ -#define ALT_UART_FCR_DMAM_RESET 0x0 -/* Extracts the ALT_UART_FCR_DMAM field value from a register. */ -#define ALT_UART_FCR_DMAM_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register. */ -#define ALT_UART_FCR_DMAM_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Tx Empty Trigger Level - tet - * - * This is used to select the empty threshold level at which the THRE Interrupts - * will be generated when the mode is active. It also determines when the uart DMA - * transmit request signal uart_dma_tx_req_n will be asserted when in certain modes - * of operation. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------|:------|:----------------------- - * ALT_UART_FCR_TET_E_FIFOEMPTY | 0x0 | FIFO empty - * ALT_UART_FCR_TET_E_TWOCHARS | 0x1 | Two characters in FIFO - * ALT_UART_FCR_TET_E_QUARTERFULL | 0x2 | FIFO 1/4 full - * ALT_UART_FCR_TET_E_HALFFULL | 0x3 | FIFO 1/2 full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_FCR_TET - * - * FIFO empty - */ -#define ALT_UART_FCR_TET_E_FIFOEMPTY 0x0 -/* - * Enumerated value for register field ALT_UART_FCR_TET - * - * Two characters in FIFO - */ -#define ALT_UART_FCR_TET_E_TWOCHARS 0x1 -/* - * Enumerated value for register field ALT_UART_FCR_TET - * - * FIFO 1/4 full - */ -#define ALT_UART_FCR_TET_E_QUARTERFULL 0x2 -/* - * Enumerated value for register field ALT_UART_FCR_TET - * - * FIFO 1/2 full - */ -#define ALT_UART_FCR_TET_E_HALFFULL 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field. */ -#define ALT_UART_FCR_TET_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field. */ -#define ALT_UART_FCR_TET_MSB 5 -/* The width in bits of the ALT_UART_FCR_TET register field. */ -#define ALT_UART_FCR_TET_WIDTH 2 -/* The mask used to set the ALT_UART_FCR_TET register field value. */ -#define ALT_UART_FCR_TET_SET_MSK 0x00000030 -/* The mask used to clear the ALT_UART_FCR_TET register field value. */ -#define ALT_UART_FCR_TET_CLR_MSK 0xffffffcf -/* The reset value of the ALT_UART_FCR_TET register field is UNKNOWN. */ -#define ALT_UART_FCR_TET_RESET 0x0 -/* Extracts the ALT_UART_FCR_TET field value from a register. */ -#define ALT_UART_FCR_TET_GET(value) (((value) & 0x00000030) >> 4) -/* Produces a ALT_UART_FCR_TET register field value suitable for setting the register. */ -#define ALT_UART_FCR_TET_SET(value) (((value) << 4) & 0x00000030) - -/* - * Field : Rx Trigger Level - rt - * - * This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT): - * This is used to select the trigger level in the receiver FIFO at which the - * Received Data Available Interrupt will be generated. In auto flow control mode - * it is used to determine when the uart_rts_n signal will be de-asserted. It also - * determines when the uart_dma_rx_req_n signal will be asserted when in certain - * modes of operation. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:---------------------- - * ALT_UART_FCR_RT_E_ONECHAR | 0x0 | one character in fifo - * ALT_UART_FCR_RT_E_QUARTERFULL | 0x1 | FIFO 1/4 full - * ALT_UART_FCR_RT_E_HALFFULL | 0x2 | FIFO 1/2 full - * ALT_UART_FCR_RT_E_FULLLESS2 | 0x3 | FIFO 2 less than full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_FCR_RT - * - * one character in fifo - */ -#define ALT_UART_FCR_RT_E_ONECHAR 0x0 -/* - * Enumerated value for register field ALT_UART_FCR_RT - * - * FIFO 1/4 full - */ -#define ALT_UART_FCR_RT_E_QUARTERFULL 0x1 -/* - * Enumerated value for register field ALT_UART_FCR_RT - * - * FIFO 1/2 full - */ -#define ALT_UART_FCR_RT_E_HALFFULL 0x2 -/* - * Enumerated value for register field ALT_UART_FCR_RT - * - * FIFO 2 less than full - */ -#define ALT_UART_FCR_RT_E_FULLLESS2 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field. */ -#define ALT_UART_FCR_RT_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field. */ -#define ALT_UART_FCR_RT_MSB 7 -/* The width in bits of the ALT_UART_FCR_RT register field. */ -#define ALT_UART_FCR_RT_WIDTH 2 -/* The mask used to set the ALT_UART_FCR_RT register field value. */ -#define ALT_UART_FCR_RT_SET_MSK 0x000000c0 -/* The mask used to clear the ALT_UART_FCR_RT register field value. */ -#define ALT_UART_FCR_RT_CLR_MSK 0xffffff3f -/* The reset value of the ALT_UART_FCR_RT register field is UNKNOWN. */ -#define ALT_UART_FCR_RT_RESET 0x0 -/* Extracts the ALT_UART_FCR_RT field value from a register. */ -#define ALT_UART_FCR_RT_GET(value) (((value) & 0x000000c0) >> 6) -/* Produces a ALT_UART_FCR_RT register field value suitable for setting the register. */ -#define ALT_UART_FCR_RT_SET(value) (((value) << 6) & 0x000000c0) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_FCR. - */ -struct ALT_UART_FCR_s -{ - uint32_t fifoe : 1; /* FIFO Enable */ - uint32_t rfifor : 1; /* Rx FIFO Reset */ - uint32_t xfifor : 1; /* Tx FIFO Reset */ - uint32_t dmam : 1; /* DMA Mode */ - uint32_t tet : 2; /* Tx Empty Trigger Level */ - uint32_t rt : 2; /* Rx Trigger Level */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_FCR. */ -typedef volatile struct ALT_UART_FCR_s ALT_UART_FCR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_FCR register from the beginning of the component. */ -#define ALT_UART_FCR_OFST 0x8 -/* The address of the ALT_UART_FCR register. */ -#define ALT_UART_FCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST)) - -/* - * Register : Line Control Register (When Written) - lcr - * - * Formats serial data. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------- - * [1:0] | RW | 0x0 | Data Length Select - * [2] | RW | 0x0 | Stop Bits - * [3] | RW | 0x0 | Parity Enable - * [4] | RW | 0x0 | Even Parity Select - * [5] | ??? | 0x0 | *UNDEFINED* - * [6] | RW | 0x0 | Break Control Bit - * [7] | RW | 0x0 | Divisor Latch Access Bit - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Data Length Select - dls - * - * Data Length Select.Selects the number of data bits per character that the - * peripheral will transmit and receive. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------|:------|:------------ - * ALT_UART_LCR_DLS_E_LEN5 | 0x0 | 5 bits - * ALT_UART_LCR_DLS_E_LEN6 | 0x1 | 6 bits - * ALT_UART_LCR_DLS_E_LEN7 | 0x2 | 7 bits - * ALT_UART_LCR_DLS_E_LEN8 | 0x3 | 8 bits - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LCR_DLS - * - * 5 bits - */ -#define ALT_UART_LCR_DLS_E_LEN5 0x0 -/* - * Enumerated value for register field ALT_UART_LCR_DLS - * - * 6 bits - */ -#define ALT_UART_LCR_DLS_E_LEN6 0x1 -/* - * Enumerated value for register field ALT_UART_LCR_DLS - * - * 7 bits - */ -#define ALT_UART_LCR_DLS_E_LEN7 0x2 -/* - * Enumerated value for register field ALT_UART_LCR_DLS - * - * 8 bits - */ -#define ALT_UART_LCR_DLS_E_LEN8 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */ -#define ALT_UART_LCR_DLS_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */ -#define ALT_UART_LCR_DLS_MSB 1 -/* The width in bits of the ALT_UART_LCR_DLS register field. */ -#define ALT_UART_LCR_DLS_WIDTH 2 -/* The mask used to set the ALT_UART_LCR_DLS register field value. */ -#define ALT_UART_LCR_DLS_SET_MSK 0x00000003 -/* The mask used to clear the ALT_UART_LCR_DLS register field value. */ -#define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc -/* The reset value of the ALT_UART_LCR_DLS register field. */ -#define ALT_UART_LCR_DLS_RESET 0x0 -/* Extracts the ALT_UART_LCR_DLS field value from a register. */ -#define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */ -#define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : Stop Bits - stop - * - * Number of stop bits. Used to select the number of stop bits per character that - * the peripheral will transmit and receive.Note that regardless of the number of - * stop bits selected the receiver will only check the first stop bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------|:------|:------------------------------------------ - * ALT_UART_LCR_STOP_E_ONESTOP | 0x0 | one stop bit - * ALT_UART_LCR_STOP_E_ONEPOINT5STOP | 0x1 | 1.5 stop bits when DLS (LCR[1:0]) is zero - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LCR_STOP - * - * one stop bit - */ -#define ALT_UART_LCR_STOP_E_ONESTOP 0x0 -/* - * Enumerated value for register field ALT_UART_LCR_STOP - * - * 1.5 stop bits when DLS (LCR[1:0]) is zero - */ -#define ALT_UART_LCR_STOP_E_ONEPOINT5STOP 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */ -#define ALT_UART_LCR_STOP_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */ -#define ALT_UART_LCR_STOP_MSB 2 -/* The width in bits of the ALT_UART_LCR_STOP register field. */ -#define ALT_UART_LCR_STOP_WIDTH 1 -/* The mask used to set the ALT_UART_LCR_STOP register field value. */ -#define ALT_UART_LCR_STOP_SET_MSK 0x00000004 -/* The mask used to clear the ALT_UART_LCR_STOP register field value. */ -#define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb -/* The reset value of the ALT_UART_LCR_STOP register field. */ -#define ALT_UART_LCR_STOP_RESET 0x0 -/* Extracts the ALT_UART_LCR_STOP field value from a register. */ -#define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */ -#define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Parity Enable - pen - * - * This bit is used to enable and disable parity generation and detection in a - * transmitted and received data character. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------|:------|:---------------- - * ALT_UART_LCR_PEN_E_DISD | 0x0 | parity disabled - * ALT_UART_LCR_PEN_E_END | 0x1 | parity enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LCR_PEN - * - * parity disabled - */ -#define ALT_UART_LCR_PEN_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_LCR_PEN - * - * parity enabled - */ -#define ALT_UART_LCR_PEN_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */ -#define ALT_UART_LCR_PEN_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */ -#define ALT_UART_LCR_PEN_MSB 3 -/* The width in bits of the ALT_UART_LCR_PEN register field. */ -#define ALT_UART_LCR_PEN_WIDTH 1 -/* The mask used to set the ALT_UART_LCR_PEN register field value. */ -#define ALT_UART_LCR_PEN_SET_MSK 0x00000008 -/* The mask used to clear the ALT_UART_LCR_PEN register field value. */ -#define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_UART_LCR_PEN register field. */ -#define ALT_UART_LCR_PEN_RESET 0x0 -/* Extracts the ALT_UART_LCR_PEN field value from a register. */ -#define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */ -#define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Even Parity Select - eps - * - * This is used to select between even and odd parity, when parity is enabled (PEN - * set to one). If set to one, an even number of logic '1's is transmitted or - * checked. If set to zero, an odd number of logic '1's is transmitted or checked. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:------------ - * ALT_UART_LCR_EPS_E_ODDPAR | 0x0 | odd parity - * ALT_UART_LCR_EPS_E_EVENPAR | 0x1 | even parity - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LCR_EPS - * - * odd parity - */ -#define ALT_UART_LCR_EPS_E_ODDPAR 0x0 -/* - * Enumerated value for register field ALT_UART_LCR_EPS - * - * even parity - */ -#define ALT_UART_LCR_EPS_E_EVENPAR 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */ -#define ALT_UART_LCR_EPS_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */ -#define ALT_UART_LCR_EPS_MSB 4 -/* The width in bits of the ALT_UART_LCR_EPS register field. */ -#define ALT_UART_LCR_EPS_WIDTH 1 -/* The mask used to set the ALT_UART_LCR_EPS register field value. */ -#define ALT_UART_LCR_EPS_SET_MSK 0x00000010 -/* The mask used to clear the ALT_UART_LCR_EPS register field value. */ -#define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef -/* The reset value of the ALT_UART_LCR_EPS register field. */ -#define ALT_UART_LCR_EPS_RESET 0x0 -/* Extracts the ALT_UART_LCR_EPS field value from a register. */ -#define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */ -#define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Break Control Bit - break - * - * This is used to cause a break condition to be transmitted to the receiving - * device. If set to one the serial output is forced to the spacing (logic 0) - * state. When not in Loopback Mode, as determined by MCR[4], the sout line is - * forced low until the Break bit is cleared. When in Loopback Mode, the break - * condition is internally looped back to the receiver and the sir_out_n line is - * forced low. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */ -#define ALT_UART_LCR_BREAK_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */ -#define ALT_UART_LCR_BREAK_MSB 6 -/* The width in bits of the ALT_UART_LCR_BREAK register field. */ -#define ALT_UART_LCR_BREAK_WIDTH 1 -/* The mask used to set the ALT_UART_LCR_BREAK register field value. */ -#define ALT_UART_LCR_BREAK_SET_MSK 0x00000040 -/* The mask used to clear the ALT_UART_LCR_BREAK register field value. */ -#define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf -/* The reset value of the ALT_UART_LCR_BREAK register field. */ -#define ALT_UART_LCR_BREAK_RESET 0x0 -/* Extracts the ALT_UART_LCR_BREAK field value from a register. */ -#define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */ -#define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Divisor Latch Access Bit - dlab - * - * Used to enable reading and writing of the Divisor Latch register (DLL and DLH) - * to set the baud rate of the UART. This bit must be cleared after initial baud - * rate setup in order to access other registers. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */ -#define ALT_UART_LCR_DLAB_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */ -#define ALT_UART_LCR_DLAB_MSB 7 -/* The width in bits of the ALT_UART_LCR_DLAB register field. */ -#define ALT_UART_LCR_DLAB_WIDTH 1 -/* The mask used to set the ALT_UART_LCR_DLAB register field value. */ -#define ALT_UART_LCR_DLAB_SET_MSK 0x00000080 -/* The mask used to clear the ALT_UART_LCR_DLAB register field value. */ -#define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f -/* The reset value of the ALT_UART_LCR_DLAB register field. */ -#define ALT_UART_LCR_DLAB_RESET 0x0 -/* Extracts the ALT_UART_LCR_DLAB field value from a register. */ -#define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */ -#define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_LCR. - */ -struct ALT_UART_LCR_s -{ - uint32_t dls : 2; /* Data Length Select */ - uint32_t stop : 1; /* Stop Bits */ - uint32_t pen : 1; /* Parity Enable */ - uint32_t eps : 1; /* Even Parity Select */ - uint32_t : 1; /* *UNDEFINED* */ - uint32_t break_ : 1; /* Break Control Bit */ - uint32_t dlab : 1; /* Divisor Latch Access Bit */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_LCR. */ -typedef volatile struct ALT_UART_LCR_s ALT_UART_LCR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_LCR register from the beginning of the component. */ -#define ALT_UART_LCR_OFST 0xc -/* The address of the ALT_UART_LCR register. */ -#define ALT_UART_LCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LCR_OFST)) - -/* - * Register : Modem Control Register - mcr - * - * Reports various operations of the modem signals - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------- - * [0] | RW | 0x0 | Data Terminal Ready - * [1] | RW | 0x0 | Request to Send - * [2] | RW | 0x0 | Out1 - * [3] | RW | 0x0 | out2 - * [4] | RW | 0x0 | LoopBack Bit - * [5] | RW | 0x0 | Auto Flow Control Enable - * [31:6] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Data Terminal Ready - dtr - * - * This is used to directly control the Data Terminal Ready output. The value - * written to this location is inverted and driven out on uart_dtr_n, that is: The - * Data Terminal Ready output is used to inform the modem or data set that the UART - * is ready to establish communications. - * - * Note that Loopback mode bit [4] of MCR is set to one, the uart_dtr_n output is - * held inactive high while the value of this location is internally looped back - * to an input. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:--------------------------------- - * ALT_UART_MCR_DTR_E_LOGIC1 | 0x0 | uart_dtr_n de-asserted (logic 1) - * ALT_UART_MCR_DTR_E_LOGIC0 | 0x1 | uart_dtr_n asserted (logic 0) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MCR_DTR - * - * uart_dtr_n de-asserted (logic 1) - */ -#define ALT_UART_MCR_DTR_E_LOGIC1 0x0 -/* - * Enumerated value for register field ALT_UART_MCR_DTR - * - * uart_dtr_n asserted (logic 0) - */ -#define ALT_UART_MCR_DTR_E_LOGIC0 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */ -#define ALT_UART_MCR_DTR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */ -#define ALT_UART_MCR_DTR_MSB 0 -/* The width in bits of the ALT_UART_MCR_DTR register field. */ -#define ALT_UART_MCR_DTR_WIDTH 1 -/* The mask used to set the ALT_UART_MCR_DTR register field value. */ -#define ALT_UART_MCR_DTR_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_MCR_DTR register field value. */ -#define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_MCR_DTR register field. */ -#define ALT_UART_MCR_DTR_RESET 0x0 -/* Extracts the ALT_UART_MCR_DTR field value from a register. */ -#define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */ -#define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Request to Send - rts - * - * This is used to directly control the Request to Send (uart_rts_n) output. The - * Request to Send (uart_rts_n) output is used to inform the modem or data set that - * the UART is ready to exchange data. When Auto RTS Flow Control is not enabled - * (MCR[5] set to zero), the uart_rts_n signal is set low by programming MCR[1] - * (RTS) to a high. If Auto Flow Control is active (MCR[5] set to one) and FIFO's - * enable (FCR[0] set to one), the uart_rts_n output is controlled in the same way, - * but is also gated with the receiver FIFO threshold trigger (uart_rts_n is - * inactive high when above the threshold). The uart_rts_n signal will be de- - * asserted when MCR[1] is set low. - * - * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held - * inactive high while the value of this location is internally looped back to an - * input. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:--------------------------------- - * ALT_UART_MCR_RTS_E_LOGIC1 | 0x0 | uart_rts_n de-asserted (logic 1) - * ALT_UART_MCR_RTS_E_LOGIC0 | 0x1 | uart_rts_n asserted (logic 0) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MCR_RTS - * - * uart_rts_n de-asserted (logic 1) - */ -#define ALT_UART_MCR_RTS_E_LOGIC1 0x0 -/* - * Enumerated value for register field ALT_UART_MCR_RTS - * - * uart_rts_n asserted (logic 0) - */ -#define ALT_UART_MCR_RTS_E_LOGIC0 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */ -#define ALT_UART_MCR_RTS_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */ -#define ALT_UART_MCR_RTS_MSB 1 -/* The width in bits of the ALT_UART_MCR_RTS register field. */ -#define ALT_UART_MCR_RTS_WIDTH 1 -/* The mask used to set the ALT_UART_MCR_RTS register field value. */ -#define ALT_UART_MCR_RTS_SET_MSK 0x00000002 -/* The mask used to clear the ALT_UART_MCR_RTS register field value. */ -#define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd -/* The reset value of the ALT_UART_MCR_RTS register field. */ -#define ALT_UART_MCR_RTS_RESET 0x0 -/* Extracts the ALT_UART_MCR_RTS field value from a register. */ -#define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */ -#define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Out1 - out1 - * - * The value written to this location is inverted and driven out on uart_out1_n - * pin. - * - * Note that in Loopback mode (MCR[4] set to one), the uart_out1_n output is held - * inactive high while the value of this location is internally looped back to an - * input. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:---------------------------------- - * ALT_UART_MCR_OUT1_E_LOGIC1 | 0x0 | uart_out1_n de-asserted (logic 1) - * ALT_UART_MCR_OUT1_E_LOGIC0 | 0x1 | uart_out1_n asserted (logic 0) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MCR_OUT1 - * - * uart_out1_n de-asserted (logic 1) - */ -#define ALT_UART_MCR_OUT1_E_LOGIC1 0x0 -/* - * Enumerated value for register field ALT_UART_MCR_OUT1 - * - * uart_out1_n asserted (logic 0) - */ -#define ALT_UART_MCR_OUT1_E_LOGIC0 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */ -#define ALT_UART_MCR_OUT1_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */ -#define ALT_UART_MCR_OUT1_MSB 2 -/* The width in bits of the ALT_UART_MCR_OUT1 register field. */ -#define ALT_UART_MCR_OUT1_WIDTH 1 -/* The mask used to set the ALT_UART_MCR_OUT1 register field value. */ -#define ALT_UART_MCR_OUT1_SET_MSK 0x00000004 -/* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */ -#define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb -/* The reset value of the ALT_UART_MCR_OUT1 register field. */ -#define ALT_UART_MCR_OUT1_RESET 0x0 -/* Extracts the ALT_UART_MCR_OUT1 field value from a register. */ -#define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */ -#define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : out2 - out2 - * - * This is used to directly control the user-designated uart_out2_n output. The - * value written to this location is inverted and driven out on uart_out2_n - * - * Note: In Loopback mode bit 4 of the modem control register (MCR) is set to one, - * the uart_out2_n output is held inactive high while the value of this location is - * internally looped back to an input. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:---------------------------------- - * ALT_UART_MCR_OUT2_E_LOGIC1 | 0x0 | uart_out2_n de-asserted (logic 1) - * ALT_UART_MCR_OUT2_E_LOGIC0 | 0x1 | uart_out2_n asserted (logic 0) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MCR_OUT2 - * - * uart_out2_n de-asserted (logic 1) - */ -#define ALT_UART_MCR_OUT2_E_LOGIC1 0x0 -/* - * Enumerated value for register field ALT_UART_MCR_OUT2 - * - * uart_out2_n asserted (logic 0) - */ -#define ALT_UART_MCR_OUT2_E_LOGIC0 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */ -#define ALT_UART_MCR_OUT2_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */ -#define ALT_UART_MCR_OUT2_MSB 3 -/* The width in bits of the ALT_UART_MCR_OUT2 register field. */ -#define ALT_UART_MCR_OUT2_WIDTH 1 -/* The mask used to set the ALT_UART_MCR_OUT2 register field value. */ -#define ALT_UART_MCR_OUT2_SET_MSK 0x00000008 -/* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */ -#define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_UART_MCR_OUT2 register field. */ -#define ALT_UART_MCR_OUT2_RESET 0x0 -/* Extracts the ALT_UART_MCR_OUT2 field value from a register. */ -#define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */ -#define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : LoopBack Bit - loopback - * - * This is used to put the UART into a diagnostic mode for test purposes. If UART - * mode is NOT active, bit [6] of the modem control register MCR is set to zero, - * data on the sout line is held high, while serial data output is looped back to - * the sin line, internally. In this mode all the interrupts are fully functional. - * Also, in loopback mode, the modem control inputs (uart_dsr_n, uart_cts_n, - * uart_ri_n, uart_dcd_n) are disconnected and the modem control outputs - * (uart_dtr_n, uart_rts_n, uart_out1_n, uart_out2_n) are loopedback to the inputs, - * internally. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */ -#define ALT_UART_MCR_LOOPBACK_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */ -#define ALT_UART_MCR_LOOPBACK_MSB 4 -/* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */ -#define ALT_UART_MCR_LOOPBACK_WIDTH 1 -/* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */ -#define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010 -/* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */ -#define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef -/* The reset value of the ALT_UART_MCR_LOOPBACK register field. */ -#define ALT_UART_MCR_LOOPBACK_RESET 0x0 -/* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */ -#define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */ -#define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Auto Flow Control Enable - afce - * - * When FIFOs are enabled, the Auto Flow Control enable bits are active. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------|:------|:-------------------------------- - * ALT_UART_MCR_AFCE_E_DISD | 0x0 | Auto Flow Control Mode disabled - * ALT_UART_MCR_AFCE_E_END | 0x1 | Auto Flow Control Mode enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MCR_AFCE - * - * Auto Flow Control Mode disabled - */ -#define ALT_UART_MCR_AFCE_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_MCR_AFCE - * - * Auto Flow Control Mode enabled - */ -#define ALT_UART_MCR_AFCE_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */ -#define ALT_UART_MCR_AFCE_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */ -#define ALT_UART_MCR_AFCE_MSB 5 -/* The width in bits of the ALT_UART_MCR_AFCE register field. */ -#define ALT_UART_MCR_AFCE_WIDTH 1 -/* The mask used to set the ALT_UART_MCR_AFCE register field value. */ -#define ALT_UART_MCR_AFCE_SET_MSK 0x00000020 -/* The mask used to clear the ALT_UART_MCR_AFCE register field value. */ -#define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf -/* The reset value of the ALT_UART_MCR_AFCE register field. */ -#define ALT_UART_MCR_AFCE_RESET 0x0 -/* Extracts the ALT_UART_MCR_AFCE field value from a register. */ -#define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */ -#define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_MCR. - */ -struct ALT_UART_MCR_s -{ - uint32_t dtr : 1; /* Data Terminal Ready */ - uint32_t rts : 1; /* Request to Send */ - uint32_t out1 : 1; /* Out1 */ - uint32_t out2 : 1; /* out2 */ - uint32_t loopback : 1; /* LoopBack Bit */ - uint32_t afce : 1; /* Auto Flow Control Enable */ - uint32_t : 26; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_MCR. */ -typedef volatile struct ALT_UART_MCR_s ALT_UART_MCR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_MCR register from the beginning of the component. */ -#define ALT_UART_MCR_OFST 0x10 -/* The address of the ALT_UART_MCR register. */ -#define ALT_UART_MCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST)) - -/* - * Register : Line Status Register - lsr - * - * Reports status of transmit and receive. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------------ - * [0] | R | 0x0 | Data Ready bit - * [1] | R | 0x0 | Overrun error - * [2] | R | 0x0 | Parity Error - * [3] | R | 0x0 | Framing Error - * [4] | R | 0x0 | Break Interrupt - * [5] | R | 0x1 | Transmit Holding Register Empty bit - * [6] | R | 0x1 | Transmitter Empty bit - * [7] | R | 0x0 | Receiver FIFO Error bit - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Data Ready bit - dr - * - * This is used to indicate that the receiver contains at least one character in - * the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the - * non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:-------------- - * ALT_UART_LSR_DR_E_NODATARDY | 0x0 | no data ready - * ALT_UART_LSR_DR_E_DATARDY | 0x1 | data ready - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LSR_DR - * - * no data ready - */ -#define ALT_UART_LSR_DR_E_NODATARDY 0x0 -/* - * Enumerated value for register field ALT_UART_LSR_DR - * - * data ready - */ -#define ALT_UART_LSR_DR_E_DATARDY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */ -#define ALT_UART_LSR_DR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */ -#define ALT_UART_LSR_DR_MSB 0 -/* The width in bits of the ALT_UART_LSR_DR register field. */ -#define ALT_UART_LSR_DR_WIDTH 1 -/* The mask used to set the ALT_UART_LSR_DR register field value. */ -#define ALT_UART_LSR_DR_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_LSR_DR register field value. */ -#define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_LSR_DR register field. */ -#define ALT_UART_LSR_DR_RESET 0x0 -/* Extracts the ALT_UART_LSR_DR field value from a register. */ -#define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */ -#define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Overrun error - oe - * - * This is used to indicate the occurrence of an overrun error. This occurs if a - * new data character was received before the previous data was read. In the non- - * FIFO mode, the OE bit is set when a new character arrives in the receiver before - * the previous character was read from the RBR. When this happens, the data in the - * RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is - * full and new character arrives at the receiver. The data in the FIFO is retained - * and the data in the receive shift register is lost.Reading the LSR clears the OE - * bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:----------------- - * ALT_UART_LSR_OE_E_NOOVERRUN | 0x0 | no overrun error - * ALT_UART_LSR_OE_E_OVERRUN | 0x1 | overrun error - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LSR_OE - * - * no overrun error - */ -#define ALT_UART_LSR_OE_E_NOOVERRUN 0x0 -/* - * Enumerated value for register field ALT_UART_LSR_OE - * - * overrun error - */ -#define ALT_UART_LSR_OE_E_OVERRUN 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */ -#define ALT_UART_LSR_OE_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */ -#define ALT_UART_LSR_OE_MSB 1 -/* The width in bits of the ALT_UART_LSR_OE register field. */ -#define ALT_UART_LSR_OE_WIDTH 1 -/* The mask used to set the ALT_UART_LSR_OE register field value. */ -#define ALT_UART_LSR_OE_SET_MSK 0x00000002 -/* The mask used to clear the ALT_UART_LSR_OE register field value. */ -#define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd -/* The reset value of the ALT_UART_LSR_OE register field. */ -#define ALT_UART_LSR_OE_RESET 0x0 -/* Extracts the ALT_UART_LSR_OE field value from a register. */ -#define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */ -#define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Parity Error - pe - * - * This is used to indicate the occurrence of a parity error in the receiver if the - * Parity Enable (PEN) bit (LCR[3]) is set. Since the parity error is associated - * with a character received, it is revealed when the character with the parity - * error arrives at the top of the FIFO. It should be noted that the Parity Error - * (PE) bit (LSR[2]) will be set if a break interrupt has occurred, as indicated by - * Break Interrupt (BI) bit (LSR[4]). Reading the LSR clears the PE bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:---------------- - * ALT_UART_LSR_PE_E_NOPARITYERR | 0x0 | no parity error - * ALT_UART_LSR_PE_E_PARITYERR | 0x1 | no parity error - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LSR_PE - * - * no parity error - */ -#define ALT_UART_LSR_PE_E_NOPARITYERR 0x0 -/* - * Enumerated value for register field ALT_UART_LSR_PE - * - * no parity error - */ -#define ALT_UART_LSR_PE_E_PARITYERR 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */ -#define ALT_UART_LSR_PE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */ -#define ALT_UART_LSR_PE_MSB 2 -/* The width in bits of the ALT_UART_LSR_PE register field. */ -#define ALT_UART_LSR_PE_WIDTH 1 -/* The mask used to set the ALT_UART_LSR_PE register field value. */ -#define ALT_UART_LSR_PE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_UART_LSR_PE register field value. */ -#define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_UART_LSR_PE register field. */ -#define ALT_UART_LSR_PE_RESET 0x0 -/* Extracts the ALT_UART_LSR_PE field value from a register. */ -#define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */ -#define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Framing Error - fe - * - * This is used to indicate the occurrence of a framing error in the receiver. A - * framing error occurs when the receiver does not detect a valid STOP bit in the - * received data. In the FIFO mode, since the framing error is associated with a - * character received, it is revealed when the character with the framing error is - * at the top of the FIFO. When a framing error occurs the UART will try to - * resynchronize. It does this by assuming that the error was due to the start bit - * of the next character and then continues receiving the other bit i.e. data, - * and/or parity and stop. It should be noted that the Framing Error (FE) - * bit(LSR[3]) will be set if a break interrupt has occurred, as indicated by a - * Break Interrupt BIT bit (LSR[4]). Reading the LSR clears the FE bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:----------------- - * ALT_UART_LSR_FE_E_NOFRMERR | 0x0 | no framing error - * ALT_UART_LSR_FE_E_FRMERR | 0x1 | framing error - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LSR_FE - * - * no framing error - */ -#define ALT_UART_LSR_FE_E_NOFRMERR 0x0 -/* - * Enumerated value for register field ALT_UART_LSR_FE - * - * framing error - */ -#define ALT_UART_LSR_FE_E_FRMERR 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */ -#define ALT_UART_LSR_FE_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */ -#define ALT_UART_LSR_FE_MSB 3 -/* The width in bits of the ALT_UART_LSR_FE register field. */ -#define ALT_UART_LSR_FE_WIDTH 1 -/* The mask used to set the ALT_UART_LSR_FE register field value. */ -#define ALT_UART_LSR_FE_SET_MSK 0x00000008 -/* The mask used to clear the ALT_UART_LSR_FE register field value. */ -#define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_UART_LSR_FE register field. */ -#define ALT_UART_LSR_FE_RESET 0x0 -/* Extracts the ALT_UART_LSR_FE field value from a register. */ -#define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */ -#define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Break Interrupt - bi - * - * This is used to indicate the detection of a break sequence on the serial input - * data. Set whenever the serial input, sin, is held in a logic 0 state for longer - * than the sum of start time + data bits + parity + stop bits. A break condition - * on serial input causes one and only one character, consisting of all zeros, to - * be received by the UART. The character associated with the break condition is - * carried through the FIFO and is revealed when the character is at the top of the - * FIFO. Reading the LSR clears the BI bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */ -#define ALT_UART_LSR_BI_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */ -#define ALT_UART_LSR_BI_MSB 4 -/* The width in bits of the ALT_UART_LSR_BI register field. */ -#define ALT_UART_LSR_BI_WIDTH 1 -/* The mask used to set the ALT_UART_LSR_BI register field value. */ -#define ALT_UART_LSR_BI_SET_MSK 0x00000010 -/* The mask used to clear the ALT_UART_LSR_BI register field value. */ -#define ALT_UART_LSR_BI_CLR_MSK 0xffffffef -/* The reset value of the ALT_UART_LSR_BI register field. */ -#define ALT_UART_LSR_BI_RESET 0x0 -/* Extracts the ALT_UART_LSR_BI field value from a register. */ -#define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */ -#define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Transmit Holding Register Empty bit - thre - * - * If THRE mode is disabled (IER[7] set to zero) this bit indicates that the THR or - * Tx FIFO is empty. This bit is set whenever data is transferred from the THR or - * Tx FIFO to the transmitter shift register and no new data has been written to - * the THR or Tx FIFO. This also causes a THRE Interrupt to occur, if the THRE - * Interrupt is enabled. If both THRE and FIFOs are enabled, both (IER[7] set to - * one and FCR[0] set to one respectively), the functionality will indicate the - * transmitter FIFO is full, and no longer controls THRE interrupts, which are then - * controlled by the FCR[5:4] thresholdsetting. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */ -#define ALT_UART_LSR_THRE_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */ -#define ALT_UART_LSR_THRE_MSB 5 -/* The width in bits of the ALT_UART_LSR_THRE register field. */ -#define ALT_UART_LSR_THRE_WIDTH 1 -/* The mask used to set the ALT_UART_LSR_THRE register field value. */ -#define ALT_UART_LSR_THRE_SET_MSK 0x00000020 -/* The mask used to clear the ALT_UART_LSR_THRE register field value. */ -#define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf -/* The reset value of the ALT_UART_LSR_THRE register field. */ -#define ALT_UART_LSR_THRE_RESET 0x1 -/* Extracts the ALT_UART_LSR_THRE field value from a register. */ -#define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */ -#define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Transmitter Empty bit - temt - * - * If in FIFO mode and FIFO's enabled (FCR[0] set to one), this bit is set whenever - * the Transmitter Shift Register and the FIFO are both empty. If FIFO's are - * disabled, this bit is set whenever the Transmitter Holding Register and the - * Transmitter Shift Register are both empty. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:----------------------- - * ALT_UART_LSR_TEMT_E_NOTEMPTY | 0x0 | Transmit Empty not set - * ALT_UART_LSR_TEMT_E_EMPTY | 0x1 | Transmit Empty set - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LSR_TEMT - * - * Transmit Empty not set - */ -#define ALT_UART_LSR_TEMT_E_NOTEMPTY 0x0 -/* - * Enumerated value for register field ALT_UART_LSR_TEMT - * - * Transmit Empty set - */ -#define ALT_UART_LSR_TEMT_E_EMPTY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */ -#define ALT_UART_LSR_TEMT_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */ -#define ALT_UART_LSR_TEMT_MSB 6 -/* The width in bits of the ALT_UART_LSR_TEMT register field. */ -#define ALT_UART_LSR_TEMT_WIDTH 1 -/* The mask used to set the ALT_UART_LSR_TEMT register field value. */ -#define ALT_UART_LSR_TEMT_SET_MSK 0x00000040 -/* The mask used to clear the ALT_UART_LSR_TEMT register field value. */ -#define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf -/* The reset value of the ALT_UART_LSR_TEMT register field. */ -#define ALT_UART_LSR_TEMT_RESET 0x1 -/* Extracts the ALT_UART_LSR_TEMT field value from a register. */ -#define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */ -#define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Receiver FIFO Error bit - rfe - * - * This bit is only relevant when FIFO's are enabled (FCR[0] set to one). This is - * used to indicate if there is at least one parity error, framing error, or break - * indication in the FIFO. This bit is cleared when the LSR is read and the - * character with the error is at the top of the receiver FIFO and there are no - * subsequent errors in the FIFO. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------|:------|:-------------------- - * ALT_UART_LSR_RFE_E_NOERR | 0x0 | no error in Rx FIFO - * ALT_UART_LSR_RFE_E_ERR | 0x1 | error in Rx FIFO - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_LSR_RFE - * - * no error in Rx FIFO - */ -#define ALT_UART_LSR_RFE_E_NOERR 0x0 -/* - * Enumerated value for register field ALT_UART_LSR_RFE - * - * error in Rx FIFO - */ -#define ALT_UART_LSR_RFE_E_ERR 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */ -#define ALT_UART_LSR_RFE_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */ -#define ALT_UART_LSR_RFE_MSB 7 -/* The width in bits of the ALT_UART_LSR_RFE register field. */ -#define ALT_UART_LSR_RFE_WIDTH 1 -/* The mask used to set the ALT_UART_LSR_RFE register field value. */ -#define ALT_UART_LSR_RFE_SET_MSK 0x00000080 -/* The mask used to clear the ALT_UART_LSR_RFE register field value. */ -#define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f -/* The reset value of the ALT_UART_LSR_RFE register field. */ -#define ALT_UART_LSR_RFE_RESET 0x0 -/* Extracts the ALT_UART_LSR_RFE field value from a register. */ -#define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */ -#define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_LSR. - */ -struct ALT_UART_LSR_s -{ - const uint32_t dr : 1; /* Data Ready bit */ - const uint32_t oe : 1; /* Overrun error */ - const uint32_t pe : 1; /* Parity Error */ - const uint32_t fe : 1; /* Framing Error */ - const uint32_t bi : 1; /* Break Interrupt */ - const uint32_t thre : 1; /* Transmit Holding Register Empty bit */ - const uint32_t temt : 1; /* Transmitter Empty bit */ - const uint32_t rfe : 1; /* Receiver FIFO Error bit */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_LSR. */ -typedef volatile struct ALT_UART_LSR_s ALT_UART_LSR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_LSR register from the beginning of the component. */ -#define ALT_UART_LSR_OFST 0x14 -/* The address of the ALT_UART_LSR register. */ -#define ALT_UART_LSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LSR_OFST)) - -/* - * Register : Modem Status Register - msr - * - * It should be noted that whenever bits 0, 1, 2 or 3 are set to logic one, to - * indicate a change on the modem control inputs, a modem status interrupt will be - * generated if enabled via the IER regardless of when the change occurred. Since - * the delta bits (bits 0, 1, 3) can get set after a reset if their respective - * modem signals are active (see individual bits for details), a read of the MSR - * after reset can be performed to prevent unwanted interrupts. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------------- - * [0] | R | 0x0 | Delta Clear to Send - * [1] | R | 0x0 | Delta Data Set Ready - * [2] | R | 0x0 | Trailing Edge of Ring Indicator - * [3] | R | 0x0 | Delta Data Carrier Detect - * [4] | R | 0x0 | Clear to Send - * [5] | R | 0x0 | Data Set Ready - * [6] | R | 0x0 | Ring Indicator - * [7] | R | 0x0 | Data Carrier Detect - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Delta Clear to Send - dcts - * - * This is used to indicate that the modem control line uart_cts_n has changed - * since the last time the MSR was read. That is: Reading the MSR clears the DCTS - * bit. In Loopback Mode bit [4] of MCR set to one, DCTS reflects changes on bit - * [1] RTS of register MCR. - * - * Note: If the DCTS bit is not set and the uart_cts_n signal is asserted (low) and - * a reset occurs (software or otherwise), then the DCTS bit will get set when the - * reset is removed if the uart_cts_n signal remains asserted. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:----------------------------------------------- - * ALT_UART_MSR_DCTS_E_NOCHG | 0x0 | no change on uart_cts_n since last read of MSR - * ALT_UART_MSR_DCTS_E_CHG | 0x1 | change on uart_cts_n since last read of MSR - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MSR_DCTS - * - * no change on uart_cts_n since last read of MSR - */ -#define ALT_UART_MSR_DCTS_E_NOCHG 0x0 -/* - * Enumerated value for register field ALT_UART_MSR_DCTS - * - * change on uart_cts_n since last read of MSR - */ -#define ALT_UART_MSR_DCTS_E_CHG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */ -#define ALT_UART_MSR_DCTS_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */ -#define ALT_UART_MSR_DCTS_MSB 0 -/* The width in bits of the ALT_UART_MSR_DCTS register field. */ -#define ALT_UART_MSR_DCTS_WIDTH 1 -/* The mask used to set the ALT_UART_MSR_DCTS register field value. */ -#define ALT_UART_MSR_DCTS_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_MSR_DCTS register field value. */ -#define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_MSR_DCTS register field. */ -#define ALT_UART_MSR_DCTS_RESET 0x0 -/* Extracts the ALT_UART_MSR_DCTS field value from a register. */ -#define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */ -#define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Delta Data Set Ready - ddsr - * - * This is used to indicate that the modem control line uart_dsr_n has changed - * since the last time the MSR was read. Reading the MSR clears the DDSR bit.In - * Loopback Mode (MCR[4] set to one), DDSR reflects changes on bit [0] DTR of - * register MCR . - * - * Note, if the DDSR bit is not set and the uart_dsr_n signal is asserted (low) and - * a reset occurs (software or otherwise), then the DDSR bit will get set when the - * reset is removed if the uart_dsr_n signal remains asserted. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:----------------------------------------------- - * ALT_UART_MSR_DDSR_E_NOCHG | 0x0 | no change on uart_dsr_n since last read of MSR - * ALT_UART_MSR_DDSR_E_CHG | 0x1 | change on uart_dsr_n since last read of MSR - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MSR_DDSR - * - * no change on uart_dsr_n since last read of MSR - */ -#define ALT_UART_MSR_DDSR_E_NOCHG 0x0 -/* - * Enumerated value for register field ALT_UART_MSR_DDSR - * - * change on uart_dsr_n since last read of MSR - */ -#define ALT_UART_MSR_DDSR_E_CHG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */ -#define ALT_UART_MSR_DDSR_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */ -#define ALT_UART_MSR_DDSR_MSB 1 -/* The width in bits of the ALT_UART_MSR_DDSR register field. */ -#define ALT_UART_MSR_DDSR_WIDTH 1 -/* The mask used to set the ALT_UART_MSR_DDSR register field value. */ -#define ALT_UART_MSR_DDSR_SET_MSK 0x00000002 -/* The mask used to clear the ALT_UART_MSR_DDSR register field value. */ -#define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd -/* The reset value of the ALT_UART_MSR_DDSR register field. */ -#define ALT_UART_MSR_DDSR_RESET 0x0 -/* Extracts the ALT_UART_MSR_DDSR field value from a register. */ -#define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */ -#define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Trailing Edge of Ring Indicator - teri - * - * This is used to indicate that a change on the input uart_ri_n (from an active - * low, to an inactive high state) has occurred since the last time the MSR was - * read. Reading the MSR clears the TERI bit. In Loopback Mode bit [4] of register - * MCR is set to one, TERI reflects when bit [2] of register MCR has changed state - * from a high to a low. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:---------------------------------------------- - * ALT_UART_MSR_TERI_E_NOCHG | 0x0 | no change on uart_ri_n since last read of MSR - * ALT_UART_MSR_TERI_E_CHG | 0x1 | change on uart_ri_n since last read of MSR - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MSR_TERI - * - * no change on uart_ri_n since last read of MSR - */ -#define ALT_UART_MSR_TERI_E_NOCHG 0x0 -/* - * Enumerated value for register field ALT_UART_MSR_TERI - * - * change on uart_ri_n since last read of MSR - */ -#define ALT_UART_MSR_TERI_E_CHG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */ -#define ALT_UART_MSR_TERI_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */ -#define ALT_UART_MSR_TERI_MSB 2 -/* The width in bits of the ALT_UART_MSR_TERI register field. */ -#define ALT_UART_MSR_TERI_WIDTH 1 -/* The mask used to set the ALT_UART_MSR_TERI register field value. */ -#define ALT_UART_MSR_TERI_SET_MSK 0x00000004 -/* The mask used to clear the ALT_UART_MSR_TERI register field value. */ -#define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb -/* The reset value of the ALT_UART_MSR_TERI register field. */ -#define ALT_UART_MSR_TERI_RESET 0x0 -/* Extracts the ALT_UART_MSR_TERI field value from a register. */ -#define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */ -#define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Delta Data Carrier Detect - ddcd - * - * This is used to indicate that the modem control line dcd_n has changed since the - * last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback - * Mode bit [4] of register MCR is set to one, DDCD reflects changes bit [3] - * uart_out2 of register MCR. - * - * Note: If the DDCD bit is not set and the uart_dcd_n signal is asserted (low) and - * a reset occurs (software or otherwise), then the DDCD bit will get set when the - * reset is removed if the uart_dcd_n signal remains asserted. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:----------------------------------------------- - * ALT_UART_MSR_DDCD_E_NOCHG | 0x0 | no change on uart_dcd_n since last read of MSR - * ALT_UART_MSR_DDCD_E_CHG | 0x1 | change on uart_dcd_n since last read of MSR - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MSR_DDCD - * - * no change on uart_dcd_n since last read of MSR - */ -#define ALT_UART_MSR_DDCD_E_NOCHG 0x0 -/* - * Enumerated value for register field ALT_UART_MSR_DDCD - * - * change on uart_dcd_n since last read of MSR - */ -#define ALT_UART_MSR_DDCD_E_CHG 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */ -#define ALT_UART_MSR_DDCD_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */ -#define ALT_UART_MSR_DDCD_MSB 3 -/* The width in bits of the ALT_UART_MSR_DDCD register field. */ -#define ALT_UART_MSR_DDCD_WIDTH 1 -/* The mask used to set the ALT_UART_MSR_DDCD register field value. */ -#define ALT_UART_MSR_DDCD_SET_MSK 0x00000008 -/* The mask used to clear the ALT_UART_MSR_DDCD register field value. */ -#define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_UART_MSR_DDCD register field. */ -#define ALT_UART_MSR_DDCD_RESET 0x0 -/* Extracts the ALT_UART_MSR_DDCD field value from a register. */ -#define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */ -#define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Clear to Send - cts - * - * This is used to indicate the current state of the modem control line uart_cts_n. - * That is, this bit is the complement uart_cts_n. When the Clear to Send input - * (uart_cts_n) is asserted it is an indication that the modem or data set is ready - * to exchange data with the uart. In Loopback Mode bit [4] of register MCR is set - * to one, CTS is the same as bit [1] RTS of register MCR. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:------------------------------------------ - * ALT_UART_MSR_CTS_E_LOGIC1 | 0x0 | uart_cts_n input is de-asserted (logic 1) - * ALT_UART_MSR_CTS_E_LOGIC0 | 0x1 | uart_cts_n input is asserted (logic 0) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MSR_CTS - * - * uart_cts_n input is de-asserted (logic 1) - */ -#define ALT_UART_MSR_CTS_E_LOGIC1 0x0 -/* - * Enumerated value for register field ALT_UART_MSR_CTS - * - * uart_cts_n input is asserted (logic 0) - */ -#define ALT_UART_MSR_CTS_E_LOGIC0 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */ -#define ALT_UART_MSR_CTS_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */ -#define ALT_UART_MSR_CTS_MSB 4 -/* The width in bits of the ALT_UART_MSR_CTS register field. */ -#define ALT_UART_MSR_CTS_WIDTH 1 -/* The mask used to set the ALT_UART_MSR_CTS register field value. */ -#define ALT_UART_MSR_CTS_SET_MSK 0x00000010 -/* The mask used to clear the ALT_UART_MSR_CTS register field value. */ -#define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef -/* The reset value of the ALT_UART_MSR_CTS register field. */ -#define ALT_UART_MSR_CTS_RESET 0x0 -/* Extracts the ALT_UART_MSR_CTS field value from a register. */ -#define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */ -#define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : Data Set Ready - dsr - * - * This is used to indicate the current state of the modem control line uart_dsr_n. - * That is this bit is the complement f uart_dsr_n. When the Data Set Ready input - * (uart_dsr_n) is asserted it is an indication that the modem or data set is ready - * to establish communications with the uart. In Loopback Mode bit [4] of register - * MCR is set to one, DSR is the same as bit [0] (DTR) of register MCR. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:------------------------------------------ - * ALT_UART_MSR_DSR_E_LOGIC1 | 0x0 | uart_dsr_n input is de-asserted (logic 1) - * ALT_UART_MSR_DSR_E_LOGIC0 | 0x1 | uart_dsr_n input is asserted (logic 0) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MSR_DSR - * - * uart_dsr_n input is de-asserted (logic 1) - */ -#define ALT_UART_MSR_DSR_E_LOGIC1 0x0 -/* - * Enumerated value for register field ALT_UART_MSR_DSR - * - * uart_dsr_n input is asserted (logic 0) - */ -#define ALT_UART_MSR_DSR_E_LOGIC0 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */ -#define ALT_UART_MSR_DSR_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */ -#define ALT_UART_MSR_DSR_MSB 5 -/* The width in bits of the ALT_UART_MSR_DSR register field. */ -#define ALT_UART_MSR_DSR_WIDTH 1 -/* The mask used to set the ALT_UART_MSR_DSR register field value. */ -#define ALT_UART_MSR_DSR_SET_MSK 0x00000020 -/* The mask used to clear the ALT_UART_MSR_DSR register field value. */ -#define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf -/* The reset value of the ALT_UART_MSR_DSR register field. */ -#define ALT_UART_MSR_DSR_RESET 0x0 -/* Extracts the ALT_UART_MSR_DSR field value from a register. */ -#define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */ -#define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : Ring Indicator - ri - * - * This bit is used to indicate the current state of the modem control line - * uart_ri_n. That is this bit is the complement uart_ri_n. When the Ring Indicator - * input (uart_ri_n) is asserted it is an indication that a telephone ringing - * signal has been received by the modem or data set. In Loopback Mode bit [4] of - * register MCR set to one, RI is the same as bit [2] uart_out1_n of register MCR. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------|:------|:----------------------------------------- - * ALT_UART_MSR_RI_E_LOGIC1 | 0x0 | uart_ri_n input is de-asserted (logic 1) - * ALT_UART_MSR_RI_E_LOGIC0 | 0x1 | uart_ri_n input is asserted (logic 0) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MSR_RI - * - * uart_ri_n input is de-asserted (logic 1) - */ -#define ALT_UART_MSR_RI_E_LOGIC1 0x0 -/* - * Enumerated value for register field ALT_UART_MSR_RI - * - * uart_ri_n input is asserted (logic 0) - */ -#define ALT_UART_MSR_RI_E_LOGIC0 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */ -#define ALT_UART_MSR_RI_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */ -#define ALT_UART_MSR_RI_MSB 6 -/* The width in bits of the ALT_UART_MSR_RI register field. */ -#define ALT_UART_MSR_RI_WIDTH 1 -/* The mask used to set the ALT_UART_MSR_RI register field value. */ -#define ALT_UART_MSR_RI_SET_MSK 0x00000040 -/* The mask used to clear the ALT_UART_MSR_RI register field value. */ -#define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf -/* The reset value of the ALT_UART_MSR_RI register field. */ -#define ALT_UART_MSR_RI_RESET 0x0 -/* Extracts the ALT_UART_MSR_RI field value from a register. */ -#define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */ -#define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : Data Carrier Detect - dcd - * - * This is used to indicate the current state of the modem control line uart_dcd_n. - * That is this bit is the complement uart_dcd_n. When the Data Carrier Detect - * input (uart_dcd_n) is asserted it is an indication that the carrier has been - * detected by the modem or data set. In Loopback Mode (MCR[4] set to one), DCD is - * the same as MCR[3] (uart_out2). - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:------------------------------------------ - * ALT_UART_MSR_DCD_E_LOGIC1 | 0x0 | uart_dcd_n input is de-asserted (logic 1) - * ALT_UART_MSR_DCD_E_LOGIC0 | 0x1 | uart_dcd_n input is asserted (logic 0) - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_MSR_DCD - * - * uart_dcd_n input is de-asserted (logic 1) - */ -#define ALT_UART_MSR_DCD_E_LOGIC1 0x0 -/* - * Enumerated value for register field ALT_UART_MSR_DCD - * - * uart_dcd_n input is asserted (logic 0) - */ -#define ALT_UART_MSR_DCD_E_LOGIC0 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */ -#define ALT_UART_MSR_DCD_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */ -#define ALT_UART_MSR_DCD_MSB 7 -/* The width in bits of the ALT_UART_MSR_DCD register field. */ -#define ALT_UART_MSR_DCD_WIDTH 1 -/* The mask used to set the ALT_UART_MSR_DCD register field value. */ -#define ALT_UART_MSR_DCD_SET_MSK 0x00000080 -/* The mask used to clear the ALT_UART_MSR_DCD register field value. */ -#define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f -/* The reset value of the ALT_UART_MSR_DCD register field. */ -#define ALT_UART_MSR_DCD_RESET 0x0 -/* Extracts the ALT_UART_MSR_DCD field value from a register. */ -#define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */ -#define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_MSR. - */ -struct ALT_UART_MSR_s -{ - const uint32_t dcts : 1; /* Delta Clear to Send */ - const uint32_t ddsr : 1; /* Delta Data Set Ready */ - const uint32_t teri : 1; /* Trailing Edge of Ring Indicator */ - const uint32_t ddcd : 1; /* Delta Data Carrier Detect */ - const uint32_t cts : 1; /* Clear to Send */ - const uint32_t dsr : 1; /* Data Set Ready */ - const uint32_t ri : 1; /* Ring Indicator */ - const uint32_t dcd : 1; /* Data Carrier Detect */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_MSR. */ -typedef volatile struct ALT_UART_MSR_s ALT_UART_MSR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_MSR register from the beginning of the component. */ -#define ALT_UART_MSR_OFST 0x18 -/* The address of the ALT_UART_MSR register. */ -#define ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST)) - -/* - * Register : Scratchpad Register - scr - * - * Scratchpad Register - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------- - * [7:0] | RW | 0x0 | Scratchpad Register - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Scratchpad Register - scr - * - * This register is for programmers to use as a temporary storage space. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */ -#define ALT_UART_SCR_SCR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */ -#define ALT_UART_SCR_SCR_MSB 7 -/* The width in bits of the ALT_UART_SCR_SCR register field. */ -#define ALT_UART_SCR_SCR_WIDTH 8 -/* The mask used to set the ALT_UART_SCR_SCR register field value. */ -#define ALT_UART_SCR_SCR_SET_MSK 0x000000ff -/* The mask used to clear the ALT_UART_SCR_SCR register field value. */ -#define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00 -/* The reset value of the ALT_UART_SCR_SCR register field. */ -#define ALT_UART_SCR_SCR_RESET 0x0 -/* Extracts the ALT_UART_SCR_SCR field value from a register. */ -#define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */ -#define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_SCR. - */ -struct ALT_UART_SCR_s -{ - uint32_t scr : 8; /* Scratchpad Register */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_SCR. */ -typedef volatile struct ALT_UART_SCR_s ALT_UART_SCR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_SCR register from the beginning of the component. */ -#define ALT_UART_SCR_OFST 0x1c -/* The address of the ALT_UART_SCR register. */ -#define ALT_UART_SCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SCR_OFST)) - -/* - * Register : Shadow Receive Buffer Register - srbr - * - * Used to accomadate burst accesses from the master. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------------- - * [7:0] | RW | 0x0 | Shadow Receive Buffer - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Shadow Receive Buffer - srbr - * - * This is a shadow register for the RBR and has been allocated one 32-bit location - * so as to accommodate burst accesses from the master.This register contains the - * data byte received on the serial input port (sin). The data in this register is - * valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. - * If FIFOs are disabled, bit [0] of register FCR set to zero, the data in the RBR - * must be read before the next data arrives, otherwise it will be overwritten, - * resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this - * register accesses the head of the receive FIFO. If the receive FIFO is full and - * this register is not read before the next data character arrives, then the data - * already in the FIFO will be preserved but any incoming data will be lost. An - * overrun error will also occur. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR register field. */ -#define ALT_UART_SRBR_SRBR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR register field. */ -#define ALT_UART_SRBR_SRBR_MSB 7 -/* The width in bits of the ALT_UART_SRBR_SRBR register field. */ -#define ALT_UART_SRBR_SRBR_WIDTH 8 -/* The mask used to set the ALT_UART_SRBR_SRBR register field value. */ -#define ALT_UART_SRBR_SRBR_SET_MSK 0x000000ff -/* The mask used to clear the ALT_UART_SRBR_SRBR register field value. */ -#define ALT_UART_SRBR_SRBR_CLR_MSK 0xffffff00 -/* The reset value of the ALT_UART_SRBR_SRBR register field. */ -#define ALT_UART_SRBR_SRBR_RESET 0x0 -/* Extracts the ALT_UART_SRBR_SRBR field value from a register. */ -#define ALT_UART_SRBR_SRBR_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_UART_SRBR_SRBR register field value suitable for setting the register. */ -#define ALT_UART_SRBR_SRBR_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_SRBR. - */ -struct ALT_UART_SRBR_s -{ - uint32_t srbr : 8; /* Shadow Receive Buffer */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_SRBR. */ -typedef volatile struct ALT_UART_SRBR_s ALT_UART_SRBR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_SRBR register from the beginning of the component. */ -#define ALT_UART_SRBR_OFST 0x30 -/* The address of the ALT_UART_SRBR register. */ -#define ALT_UART_SRBR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST)) - -/* - * Register : Shadow Transmit Buffer Register - sthr - * - * Used to accomadate burst accesses from the master. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------- - * [7:0] | RW | 0x0 | Shadow Transmit Buffer - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Shadow Transmit Buffer - sthr - * - * This is a shadow register for the THR and has been allocated sixteen 32-bit - * locations so as to accommodate burst accesses from the master. This register - * contains data to be transmitted on the serial output port (sout). Data should - * only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If - * FIFO's are disabled bit [0] of register FCR set to zero and THRE is set, writing - * a single character to the THR clears the THRE. Any additional writes to the THR - * before the THRE is set again causes the THR data to be overwritten. If FIFO's - * are enabled bit [0] of register FCR set to one and THRE is set, 128 characters - * of data may be written to the THR before the FIFO is full. The UART FIFO depth - * is configured for 128 characters. Any attempt to write data when the FIFO is - * full results in the write data being lost. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_STHR_STHR register field. */ -#define ALT_UART_STHR_STHR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_STHR_STHR register field. */ -#define ALT_UART_STHR_STHR_MSB 7 -/* The width in bits of the ALT_UART_STHR_STHR register field. */ -#define ALT_UART_STHR_STHR_WIDTH 8 -/* The mask used to set the ALT_UART_STHR_STHR register field value. */ -#define ALT_UART_STHR_STHR_SET_MSK 0x000000ff -/* The mask used to clear the ALT_UART_STHR_STHR register field value. */ -#define ALT_UART_STHR_STHR_CLR_MSK 0xffffff00 -/* The reset value of the ALT_UART_STHR_STHR register field. */ -#define ALT_UART_STHR_STHR_RESET 0x0 -/* Extracts the ALT_UART_STHR_STHR field value from a register. */ -#define ALT_UART_STHR_STHR_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_UART_STHR_STHR register field value suitable for setting the register. */ -#define ALT_UART_STHR_STHR_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_STHR. - */ -struct ALT_UART_STHR_s -{ - uint32_t sthr : 8; /* Shadow Transmit Buffer */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_STHR. */ -typedef volatile struct ALT_UART_STHR_s ALT_UART_STHR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_STHR register from the beginning of the component. */ -#define ALT_UART_STHR_OFST 0x34 -/* The address of the ALT_UART_STHR register. */ -#define ALT_UART_STHR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STHR_OFST)) - -/* - * Register : FIFO Access Register - far - * - * This register is used in FIFO access testing. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------- - * [0] | RW | 0x0 | FIFO ACCESS Bit - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : FIFO ACCESS Bit - srbr_sthr - * - * This register is used to enable a FIFO access mode for testing, so that the - * receive FIFO can be written by the master and the transmit FIFO can be read by - * the master when FIFO's are enabled. When FIFO's are not enabled it allows the - * RBR to be written by the master and the THR to be read by the master - * - * Note: That when the FIFO access mode is enabled/disabled, the control portion of - * the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:-------------------------- - * ALT_UART_FAR_SRBR_STHR_E_DISD | 0x0 | FIFO access mode disabled - * ALT_UART_FAR_SRBR_STHR_E_END | 0x1 | FIFO access mode enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_FAR_SRBR_STHR - * - * FIFO access mode disabled - */ -#define ALT_UART_FAR_SRBR_STHR_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_FAR_SRBR_STHR - * - * FIFO access mode enabled - */ -#define ALT_UART_FAR_SRBR_STHR_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_FAR_SRBR_STHR register field. */ -#define ALT_UART_FAR_SRBR_STHR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_FAR_SRBR_STHR register field. */ -#define ALT_UART_FAR_SRBR_STHR_MSB 0 -/* The width in bits of the ALT_UART_FAR_SRBR_STHR register field. */ -#define ALT_UART_FAR_SRBR_STHR_WIDTH 1 -/* The mask used to set the ALT_UART_FAR_SRBR_STHR register field value. */ -#define ALT_UART_FAR_SRBR_STHR_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_FAR_SRBR_STHR register field value. */ -#define ALT_UART_FAR_SRBR_STHR_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_FAR_SRBR_STHR register field. */ -#define ALT_UART_FAR_SRBR_STHR_RESET 0x0 -/* Extracts the ALT_UART_FAR_SRBR_STHR field value from a register. */ -#define ALT_UART_FAR_SRBR_STHR_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_FAR_SRBR_STHR register field value suitable for setting the register. */ -#define ALT_UART_FAR_SRBR_STHR_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_FAR. - */ -struct ALT_UART_FAR_s -{ - uint32_t srbr_sthr : 1; /* FIFO ACCESS Bit */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_FAR. */ -typedef volatile struct ALT_UART_FAR_s ALT_UART_FAR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_FAR register from the beginning of the component. */ -#define ALT_UART_FAR_OFST 0x70 -/* The address of the ALT_UART_FAR register. */ -#define ALT_UART_FAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FAR_OFST)) - -/* - * Register : Transmit FIFO Read Register - tfr - * - * Used in FIFO Access test mode. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------- - * [7:0] | R | 0x0 | Transmit FIFO Read - * [31:8] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Transmit FIFO Read - tfr - * - * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to - * one). When FIFO's are enabled, reading this register gives the data at the top - * of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the - * next data value that is currently at the top of the FIFO. When FIFO's are not - * enabled, reading this register gives the data in the THR. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */ -#define ALT_UART_TFR_TFR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */ -#define ALT_UART_TFR_TFR_MSB 7 -/* The width in bits of the ALT_UART_TFR_TFR register field. */ -#define ALT_UART_TFR_TFR_WIDTH 8 -/* The mask used to set the ALT_UART_TFR_TFR register field value. */ -#define ALT_UART_TFR_TFR_SET_MSK 0x000000ff -/* The mask used to clear the ALT_UART_TFR_TFR register field value. */ -#define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00 -/* The reset value of the ALT_UART_TFR_TFR register field. */ -#define ALT_UART_TFR_TFR_RESET 0x0 -/* Extracts the ALT_UART_TFR_TFR field value from a register. */ -#define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */ -#define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_TFR. - */ -struct ALT_UART_TFR_s -{ - const uint32_t tfr : 8; /* Transmit FIFO Read */ - uint32_t : 24; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_TFR. */ -typedef volatile struct ALT_UART_TFR_s ALT_UART_TFR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_TFR register from the beginning of the component. */ -#define ALT_UART_TFR_OFST 0x74 -/* The address of the ALT_UART_TFR register. */ -#define ALT_UART_TFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFR_OFST)) - -/* - * Register : Receive FIFO Write - RFW - * - * Used only with FIFO access test mode. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:--------------------------- - * [7:0] | W | 0x0 | Receive FIFO Write Field - * [8] | W | 0x0 | Receive FIFO Parity Error - * [9] | W | 0x0 | Receive FIFO Framing Error - * [31:10] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Receive FIFO Write Field - rfwd - * - * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to - * one). When FIFO's are enabled, the data that is written to the RFWD is pushed - * into the receive FIFO. Each consecutive write pushes the new data to the next - * write location in the receive FIFO. When FIFO's are not enabled, the data that - * is written to the RFWD is pushed into the RBR. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */ -#define ALT_UART_RFW_RFWD_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */ -#define ALT_UART_RFW_RFWD_MSB 7 -/* The width in bits of the ALT_UART_RFW_RFWD register field. */ -#define ALT_UART_RFW_RFWD_WIDTH 8 -/* The mask used to set the ALT_UART_RFW_RFWD register field value. */ -#define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff -/* The mask used to clear the ALT_UART_RFW_RFWD register field value. */ -#define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00 -/* The reset value of the ALT_UART_RFW_RFWD register field. */ -#define ALT_UART_RFW_RFWD_RESET 0x0 -/* Extracts the ALT_UART_RFW_RFWD field value from a register. */ -#define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0) -/* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */ -#define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff) - -/* - * Field : Receive FIFO Parity Error - rfpe - * - * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to - * one). When FIFO's are enabled, this bit is used to write parity error detection - * information to the receive FIFO. When FIFO's are not enabled, this bit is used - * to write parity error detection information to the RBR. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */ -#define ALT_UART_RFW_RFPE_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */ -#define ALT_UART_RFW_RFPE_MSB 8 -/* The width in bits of the ALT_UART_RFW_RFPE register field. */ -#define ALT_UART_RFW_RFPE_WIDTH 1 -/* The mask used to set the ALT_UART_RFW_RFPE register field value. */ -#define ALT_UART_RFW_RFPE_SET_MSK 0x00000100 -/* The mask used to clear the ALT_UART_RFW_RFPE register field value. */ -#define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff -/* The reset value of the ALT_UART_RFW_RFPE register field. */ -#define ALT_UART_RFW_RFPE_RESET 0x0 -/* Extracts the ALT_UART_RFW_RFPE field value from a register. */ -#define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */ -#define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : Receive FIFO Framing Error - RFFE - * - * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to - * one). When FIFO's are enabled, this bit is used to write framing error detection - * information to the receive FIFO. When FIFO's are not enabled, this bit is used - * to write framing error detection information to the RBR. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */ -#define ALT_UART_RFW_RFFE_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */ -#define ALT_UART_RFW_RFFE_MSB 9 -/* The width in bits of the ALT_UART_RFW_RFFE register field. */ -#define ALT_UART_RFW_RFFE_WIDTH 1 -/* The mask used to set the ALT_UART_RFW_RFFE register field value. */ -#define ALT_UART_RFW_RFFE_SET_MSK 0x00000200 -/* The mask used to clear the ALT_UART_RFW_RFFE register field value. */ -#define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff -/* The reset value of the ALT_UART_RFW_RFFE register field. */ -#define ALT_UART_RFW_RFFE_RESET 0x0 -/* Extracts the ALT_UART_RFW_RFFE field value from a register. */ -#define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */ -#define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_RFW. - */ -struct ALT_UART_RFW_s -{ - uint32_t rfwd : 8; /* Receive FIFO Write Field */ - uint32_t rfpe : 1; /* Receive FIFO Parity Error */ - uint32_t RFFE : 1; /* Receive FIFO Framing Error */ - uint32_t : 22; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_RFW. */ -typedef volatile struct ALT_UART_RFW_s ALT_UART_RFW_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_RFW register from the beginning of the component. */ -#define ALT_UART_RFW_OFST 0x78 -/* The address of the ALT_UART_RFW register. */ -#define ALT_UART_RFW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFW_OFST)) - -/* - * Register : UART Status Register - usr - * - * Status of FIFO Operations. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------- - * [0] | ??? | 0x0 | *UNDEFINED* - * [1] | R | 0x1 | Transmit FIFO Not Full - * [2] | R | 0x1 | Transmit FIFO Empty - * [3] | R | 0x0 | Receive FIFO Not Empty - * [4] | R | 0x0 | Receive FIFO Full - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Transmit FIFO Not Full - tfnf - * - * This Bit is used to indicate that the transmit FIFO in not full. This bit is - * cleared when the Tx FIFO is full. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:-------------------------- - * ALT_UART_USR_TFNF_E_FULL | 0x0 | Transmit FIFO is full - * ALT_UART_USR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_USR_TFNF - * - * Transmit FIFO is full - */ -#define ALT_UART_USR_TFNF_E_FULL 0x0 -/* - * Enumerated value for register field ALT_UART_USR_TFNF - * - * Transmit FIFO is not full - */ -#define ALT_UART_USR_TFNF_E_NOTFULL 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */ -#define ALT_UART_USR_TFNF_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */ -#define ALT_UART_USR_TFNF_MSB 1 -/* The width in bits of the ALT_UART_USR_TFNF register field. */ -#define ALT_UART_USR_TFNF_WIDTH 1 -/* The mask used to set the ALT_UART_USR_TFNF register field value. */ -#define ALT_UART_USR_TFNF_SET_MSK 0x00000002 -/* The mask used to clear the ALT_UART_USR_TFNF register field value. */ -#define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd -/* The reset value of the ALT_UART_USR_TFNF register field. */ -#define ALT_UART_USR_TFNF_RESET 0x1 -/* Extracts the ALT_UART_USR_TFNF field value from a register. */ -#define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */ -#define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Transmit FIFO Empty - tfe - * - * This is used to indicate that the transmit FIFO is completely empty. This bit is - * cleared when the Tx FIFO is no longer empty. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:--------------------------- - * ALT_UART_USR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty - * ALT_UART_USR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_USR_TFE - * - * Transmit FIFO is not empty - */ -#define ALT_UART_USR_TFE_E_NOTEMPTY 0x0 -/* - * Enumerated value for register field ALT_UART_USR_TFE - * - * Transmit FIFO is empty - */ -#define ALT_UART_USR_TFE_E_EMPTY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */ -#define ALT_UART_USR_TFE_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */ -#define ALT_UART_USR_TFE_MSB 2 -/* The width in bits of the ALT_UART_USR_TFE register field. */ -#define ALT_UART_USR_TFE_WIDTH 1 -/* The mask used to set the ALT_UART_USR_TFE register field value. */ -#define ALT_UART_USR_TFE_SET_MSK 0x00000004 -/* The mask used to clear the ALT_UART_USR_TFE register field value. */ -#define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb -/* The reset value of the ALT_UART_USR_TFE register field. */ -#define ALT_UART_USR_TFE_RESET 0x1 -/* Extracts the ALT_UART_USR_TFE field value from a register. */ -#define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */ -#define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004) - -/* - * Field : Receive FIFO Not Empty - rfne - * - * This Bit is used to indicate that the receive FIFO contains one or more entries. - * This bit is cleared when the Rx FIFO is empty. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:-------------------------- - * ALT_UART_USR_RFNE_E_EMPTY | 0x0 | Receiive FIFO is empty - * ALT_UART_USR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_USR_RFNE - * - * Receiive FIFO is empty - */ -#define ALT_UART_USR_RFNE_E_EMPTY 0x0 -/* - * Enumerated value for register field ALT_UART_USR_RFNE - * - * Receive FIFO is not empty - */ -#define ALT_UART_USR_RFNE_E_NOTEMPTY 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */ -#define ALT_UART_USR_RFNE_LSB 3 -/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */ -#define ALT_UART_USR_RFNE_MSB 3 -/* The width in bits of the ALT_UART_USR_RFNE register field. */ -#define ALT_UART_USR_RFNE_WIDTH 1 -/* The mask used to set the ALT_UART_USR_RFNE register field value. */ -#define ALT_UART_USR_RFNE_SET_MSK 0x00000008 -/* The mask used to clear the ALT_UART_USR_RFNE register field value. */ -#define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7 -/* The reset value of the ALT_UART_USR_RFNE register field. */ -#define ALT_UART_USR_RFNE_RESET 0x0 -/* Extracts the ALT_UART_USR_RFNE field value from a register. */ -#define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3) -/* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */ -#define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008) - -/* - * Field : Receive FIFO Full - rff - * - * This Bit is used to indicate that the receive FIFO is completely full. This bit - * is cleared when the Rx FIFO is no longer full. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------|:------|:----------------------- - * ALT_UART_USR_RFF_E_NOTFULL | 0x0 | Receiive FIFO not full - * ALT_UART_USR_RFF_E_FULL | 0x1 | Transmit FIFO is full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_USR_RFF - * - * Receiive FIFO not full - */ -#define ALT_UART_USR_RFF_E_NOTFULL 0x0 -/* - * Enumerated value for register field ALT_UART_USR_RFF - * - * Transmit FIFO is full - */ -#define ALT_UART_USR_RFF_E_FULL 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */ -#define ALT_UART_USR_RFF_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */ -#define ALT_UART_USR_RFF_MSB 4 -/* The width in bits of the ALT_UART_USR_RFF register field. */ -#define ALT_UART_USR_RFF_WIDTH 1 -/* The mask used to set the ALT_UART_USR_RFF register field value. */ -#define ALT_UART_USR_RFF_SET_MSK 0x00000010 -/* The mask used to clear the ALT_UART_USR_RFF register field value. */ -#define ALT_UART_USR_RFF_CLR_MSK 0xffffffef -/* The reset value of the ALT_UART_USR_RFF register field. */ -#define ALT_UART_USR_RFF_RESET 0x0 -/* Extracts the ALT_UART_USR_RFF field value from a register. */ -#define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */ -#define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_USR. - */ -struct ALT_UART_USR_s -{ - uint32_t : 1; /* *UNDEFINED* */ - const uint32_t tfnf : 1; /* Transmit FIFO Not Full */ - const uint32_t tfe : 1; /* Transmit FIFO Empty */ - const uint32_t rfne : 1; /* Receive FIFO Not Empty */ - const uint32_t rff : 1; /* Receive FIFO Full */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_USR. */ -typedef volatile struct ALT_UART_USR_s ALT_UART_USR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_USR register from the beginning of the component. */ -#define ALT_UART_USR_OFST 0x7c -/* The address of the ALT_UART_USR register. */ -#define ALT_UART_USR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_USR_OFST)) - -/* - * Register : Transmit FIFO Level - tfl - * - * This register is used to specify the number of data entries in the Tx FIFO. - * Status Bits in USR register monitor the FIFO state. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------- - * [4:0] | R | 0x0 | Transmit FIFO Level - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Transmit FIFO Level - tfl - * - * This indicates the number of data entries in the transmit FIFO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */ -#define ALT_UART_TFL_TFL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */ -#define ALT_UART_TFL_TFL_MSB 4 -/* The width in bits of the ALT_UART_TFL_TFL register field. */ -#define ALT_UART_TFL_TFL_WIDTH 5 -/* The mask used to set the ALT_UART_TFL_TFL register field value. */ -#define ALT_UART_TFL_TFL_SET_MSK 0x0000001f -/* The mask used to clear the ALT_UART_TFL_TFL register field value. */ -#define ALT_UART_TFL_TFL_CLR_MSK 0xffffffe0 -/* The reset value of the ALT_UART_TFL_TFL register field. */ -#define ALT_UART_TFL_TFL_RESET 0x0 -/* Extracts the ALT_UART_TFL_TFL field value from a register. */ -#define ALT_UART_TFL_TFL_GET(value) (((value) & 0x0000001f) >> 0) -/* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */ -#define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x0000001f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_TFL. - */ -struct ALT_UART_TFL_s -{ - const uint32_t tfl : 5; /* Transmit FIFO Level */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_TFL. */ -typedef volatile struct ALT_UART_TFL_s ALT_UART_TFL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_TFL register from the beginning of the component. */ -#define ALT_UART_TFL_OFST 0x80 -/* The address of the ALT_UART_TFL register. */ -#define ALT_UART_TFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFL_OFST)) - -/* - * Register : Receive FIFO Level Write - rfl - * - * This register is used to specify the number of data entries in the Tx FIFO. - * Status Bits in USR register monitor the FIFO state. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------------------- - * [4:0] | R | 0x0 | Receive FIFO Level Status - * [31:5] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Receive FIFO Level Status - rfl - * - * This indicates the number of data entries in the receive FIFO. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */ -#define ALT_UART_RFL_RFL_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */ -#define ALT_UART_RFL_RFL_MSB 4 -/* The width in bits of the ALT_UART_RFL_RFL register field. */ -#define ALT_UART_RFL_RFL_WIDTH 5 -/* The mask used to set the ALT_UART_RFL_RFL register field value. */ -#define ALT_UART_RFL_RFL_SET_MSK 0x0000001f -/* The mask used to clear the ALT_UART_RFL_RFL register field value. */ -#define ALT_UART_RFL_RFL_CLR_MSK 0xffffffe0 -/* The reset value of the ALT_UART_RFL_RFL register field. */ -#define ALT_UART_RFL_RFL_RESET 0x0 -/* Extracts the ALT_UART_RFL_RFL field value from a register. */ -#define ALT_UART_RFL_RFL_GET(value) (((value) & 0x0000001f) >> 0) -/* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */ -#define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x0000001f) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_RFL. - */ -struct ALT_UART_RFL_s -{ - const uint32_t rfl : 5; /* Receive FIFO Level Status */ - uint32_t : 27; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_RFL. */ -typedef volatile struct ALT_UART_RFL_s ALT_UART_RFL_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_RFL register from the beginning of the component. */ -#define ALT_UART_RFL_OFST 0x84 -/* The address of the ALT_UART_RFL register. */ -#define ALT_UART_RFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFL_OFST)) - -/* - * Register : Software Reset Register - srr - * - * Provides Software Resets for Tx/Rx FIFO's and the uart. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:-------------- - * [0] | W | 0x0 | UART Reset - * [1] | W | 0x0 | Rx FIFO Reset - * [2] | W | 0x0 | Tx FIFO Reset - * [31:3] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : UART Reset - ur - * - * This asynchronously resets the UART and synchronously removes the reset - * assertion. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------|:------|:-------------- - * ALT_UART_SRR_UR_E_NORST | 0x0 | No reset Uart - * ALT_UART_SRR_UR_E_RST | 0x1 | Reset Uart - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_SRR_UR - * - * No reset Uart - */ -#define ALT_UART_SRR_UR_E_NORST 0x0 -/* - * Enumerated value for register field ALT_UART_SRR_UR - * - * Reset Uart - */ -#define ALT_UART_SRR_UR_E_RST 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */ -#define ALT_UART_SRR_UR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */ -#define ALT_UART_SRR_UR_MSB 0 -/* The width in bits of the ALT_UART_SRR_UR register field. */ -#define ALT_UART_SRR_UR_WIDTH 1 -/* The mask used to set the ALT_UART_SRR_UR register field value. */ -#define ALT_UART_SRR_UR_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_SRR_UR register field value. */ -#define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_SRR_UR register field. */ -#define ALT_UART_SRR_UR_RESET 0x0 -/* Extracts the ALT_UART_SRR_UR field value from a register. */ -#define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */ -#define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001) - -/* - * Field : Rx FIFO Reset - rfr - * - * This is a shadow register for the Rx FIFO Reset bit (FCR[1]). This can be used - * to remove the burden on software having to store previously written FCR values - * (which are pretty static) just to reset the receive FIFO. This resets the - * control portion of the receive FIFO and treats the FIFO as empty. This will also - * de-assert the DMA Rx request and single signals. Note that this bit is 'self- - * clearing' and it is not necessary to clear this bit. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------|:------|:----------------- - * ALT_UART_SRR_RFR_E_NORST | 0x0 | No reset Rx FIFO - * ALT_UART_SRR_RFR_E_RST | 0x1 | Reset Rx FIFO - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_SRR_RFR - * - * No reset Rx FIFO - */ -#define ALT_UART_SRR_RFR_E_NORST 0x0 -/* - * Enumerated value for register field ALT_UART_SRR_RFR - * - * Reset Rx FIFO - */ -#define ALT_UART_SRR_RFR_E_RST 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */ -#define ALT_UART_SRR_RFR_LSB 1 -/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */ -#define ALT_UART_SRR_RFR_MSB 1 -/* The width in bits of the ALT_UART_SRR_RFR register field. */ -#define ALT_UART_SRR_RFR_WIDTH 1 -/* The mask used to set the ALT_UART_SRR_RFR register field value. */ -#define ALT_UART_SRR_RFR_SET_MSK 0x00000002 -/* The mask used to clear the ALT_UART_SRR_RFR register field value. */ -#define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd -/* The reset value of the ALT_UART_SRR_RFR register field. */ -#define ALT_UART_SRR_RFR_RESET 0x0 -/* Extracts the ALT_UART_SRR_RFR field value from a register. */ -#define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1) -/* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */ -#define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002) - -/* - * Field : Tx FIFO Reset - xfr - * - * This is a shadow register forthe Tx FIFO Reset bit (FCR[2]). This can be used - * to remove the burden on software having to store previously written FCR values - * (which are pretty static) just to reset the transmit FIFO.This resets the - * control portion of the transmit FIFO and treats the FIFO as empty. This will - * also de-assert the DMA Tx request and single signals. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------|:------|:----------------- - * ALT_UART_SRR_XFR_E_NORST | 0x0 | No reset Tx FIFO - * ALT_UART_SRR_XFR_E_RST | 0x1 | Reset Tx FIFO - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_SRR_XFR - * - * No reset Tx FIFO - */ -#define ALT_UART_SRR_XFR_E_NORST 0x0 -/* - * Enumerated value for register field ALT_UART_SRR_XFR - * - * Reset Tx FIFO - */ -#define ALT_UART_SRR_XFR_E_RST 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */ -#define ALT_UART_SRR_XFR_LSB 2 -/* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */ -#define ALT_UART_SRR_XFR_MSB 2 -/* The width in bits of the ALT_UART_SRR_XFR register field. */ -#define ALT_UART_SRR_XFR_WIDTH 1 -/* The mask used to set the ALT_UART_SRR_XFR register field value. */ -#define ALT_UART_SRR_XFR_SET_MSK 0x00000004 -/* The mask used to clear the ALT_UART_SRR_XFR register field value. */ -#define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb -/* The reset value of the ALT_UART_SRR_XFR register field. */ -#define ALT_UART_SRR_XFR_RESET 0x0 -/* Extracts the ALT_UART_SRR_XFR field value from a register. */ -#define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2) -/* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */ -#define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_SRR. - */ -struct ALT_UART_SRR_s -{ - uint32_t ur : 1; /* UART Reset */ - uint32_t rfr : 1; /* Rx FIFO Reset */ - uint32_t xfr : 1; /* Tx FIFO Reset */ - uint32_t : 29; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_SRR. */ -typedef volatile struct ALT_UART_SRR_s ALT_UART_SRR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_SRR register from the beginning of the component. */ -#define ALT_UART_SRR_OFST 0x88 -/* The address of the ALT_UART_SRR register. */ -#define ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST)) - -/* - * Register : Shadow Request to Send - srts - * - * This is a shadow register for the RTS status (MCR[1]), this can be used to - * remove the burden of having to performing a read modify write on the MCR. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------- - * [0] | RW | 0x0 | Shadow Request to Send - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Shadow Request to Send - srts - * - * This is used to directly control the Request to Send (uart_rts_n) output. The - * Request to Send (uart_rts_n) output is used to inform the modem or data set that - * the UART is read to exchange data. The uart_rts_n signal is set low by - * programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set to one) - * and FIFO's are enabled (FCR[0] set to one), the uart_rts_n output is controlled - * in the same way, but is also gated with the receiver FIFO threshold trigger - * (uart_rts_n is inactive high when above the threshold). - * - * Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held - * inactive high while the value of this location is internally looped back to an - * input. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:------------------ - * ALT_UART_SRTS_SRTS_E_LOGIC0 | 0x1 | uart_rts_n logic0 - * ALT_UART_SRTS_SRTS_E_LOGIC1 | 0x0 | uart_rts_n logic1 - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_SRTS_SRTS - * - * uart_rts_n logic0 - */ -#define ALT_UART_SRTS_SRTS_E_LOGIC0 0x1 -/* - * Enumerated value for register field ALT_UART_SRTS_SRTS - * - * uart_rts_n logic1 - */ -#define ALT_UART_SRTS_SRTS_E_LOGIC1 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */ -#define ALT_UART_SRTS_SRTS_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */ -#define ALT_UART_SRTS_SRTS_MSB 0 -/* The width in bits of the ALT_UART_SRTS_SRTS register field. */ -#define ALT_UART_SRTS_SRTS_WIDTH 1 -/* The mask used to set the ALT_UART_SRTS_SRTS register field value. */ -#define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */ -#define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_SRTS_SRTS register field. */ -#define ALT_UART_SRTS_SRTS_RESET 0x0 -/* Extracts the ALT_UART_SRTS_SRTS field value from a register. */ -#define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */ -#define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_SRTS. - */ -struct ALT_UART_SRTS_s -{ - uint32_t srts : 1; /* Shadow Request to Send */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_SRTS. */ -typedef volatile struct ALT_UART_SRTS_s ALT_UART_SRTS_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */ -#define ALT_UART_SRTS_OFST 0x8c -/* The address of the ALT_UART_SRTS register. */ -#define ALT_UART_SRTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRTS_OFST)) - -/* - * Register : Shadow Break Control Register - sbcr - * - * This is a shadow register for the Break bit [6] of the register LCR. This can be - * used to remove the burden of having to performing a read modify write on the - * LCR. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:--------------------- - * [0] | RW | 0x0 | Shadow Break Control - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Shadow Break Control - sbcr - * - * This is used to cause a break condition to be transmitted to the receiving - * device. If set to one the serial output is forced to the spacing (logic 0) - * state. When not in Loopback Mode, as determined by MCR[4], the uart_txd line is - * forced low until the Break bit is cleared. When in Loopback Mode, the break - * condition is internally looped back to the receiver. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:---------------------------- - * ALT_UART_SBCR_SBCR_E_DISD | 0x0 | no break - * ALT_UART_SBCR_SBCR_E_END | 0x1 | break serial output spacing - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_SBCR_SBCR - * - * no break - */ -#define ALT_UART_SBCR_SBCR_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_SBCR_SBCR - * - * break serial output spacing - */ -#define ALT_UART_SBCR_SBCR_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCR register field. */ -#define ALT_UART_SBCR_SBCR_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCR register field. */ -#define ALT_UART_SBCR_SBCR_MSB 0 -/* The width in bits of the ALT_UART_SBCR_SBCR register field. */ -#define ALT_UART_SBCR_SBCR_WIDTH 1 -/* The mask used to set the ALT_UART_SBCR_SBCR register field value. */ -#define ALT_UART_SBCR_SBCR_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_SBCR_SBCR register field value. */ -#define ALT_UART_SBCR_SBCR_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_SBCR_SBCR register field. */ -#define ALT_UART_SBCR_SBCR_RESET 0x0 -/* Extracts the ALT_UART_SBCR_SBCR field value from a register. */ -#define ALT_UART_SBCR_SBCR_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_SBCR_SBCR register field value suitable for setting the register. */ -#define ALT_UART_SBCR_SBCR_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_SBCR. - */ -struct ALT_UART_SBCR_s -{ - uint32_t sbcr : 1; /* Shadow Break Control */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_SBCR. */ -typedef volatile struct ALT_UART_SBCR_s ALT_UART_SBCR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */ -#define ALT_UART_SBCR_OFST 0x90 -/* The address of the ALT_UART_SBCR register. */ -#define ALT_UART_SBCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SBCR_OFST)) - -/* - * Register : Shadow DMA Mode - sdmam - * - * This is a shadow register for the DMA mode bit (FCR[3]). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:---------------- - * [0] | RW | 0x0 | Shadow DMA Mode - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Shadow DMA Mode - sdmam - * - * This can be used to remove the burden of having to store the previously written - * value to the FCR in memory and having to mask this value so that only the DMA - * Mode bit gets updated. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------------|:------|:--------------------------- - * ALT_UART_SDMAM_SDMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode - * ALT_UART_SDMAM_SDMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_SDMAM_SDMAM - * - * Single DMA Transfer Mode - */ -#define ALT_UART_SDMAM_SDMAM_E_SINGLE 0x0 -/* - * Enumerated value for register field ALT_UART_SDMAM_SDMAM - * - * Multiple DMA Transfer Mode - */ -#define ALT_UART_SDMAM_SDMAM_E_MULT 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */ -#define ALT_UART_SDMAM_SDMAM_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */ -#define ALT_UART_SDMAM_SDMAM_MSB 0 -/* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */ -#define ALT_UART_SDMAM_SDMAM_WIDTH 1 -/* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */ -#define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */ -#define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_SDMAM_SDMAM register field. */ -#define ALT_UART_SDMAM_SDMAM_RESET 0x0 -/* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */ -#define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */ -#define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_SDMAM. - */ -struct ALT_UART_SDMAM_s -{ - uint32_t sdmam : 1; /* Shadow DMA Mode */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_SDMAM. */ -typedef volatile struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */ -#define ALT_UART_SDMAM_OFST 0x94 -/* The address of the ALT_UART_SDMAM register. */ -#define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SDMAM_OFST)) - -/* - * Register : Shadow FIFO Enable - sfe - * - * This is a shadow register for the FIFO enable bit [0] of register FCR. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------- - * [0] | RW | 0x0 | Shadow FIFO Enable - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Shadow FIFO Enable - sfe - * - * This can be used to remove the burden of having to store the previously written - * value to the FCR in memory and having to mask this value so that only the FIFO - * enable bit gets updated. This enables/disables the transmit (Tx) and receive (Rx - * ) FIFO's. If this bit is set to zero (disabled) after being enabled then both - * the Tx and Rx controller portion of FIFO's will be reset. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------|:------|:-------------- - * ALT_UART_SFE_SFE_E_DISD | 0x0 | Disable Rx/Tx - * ALT_UART_SFE_SFE_E_END | 0x1 | Enable Rx/Tx - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_SFE_SFE - * - * Disable Rx/Tx - */ -#define ALT_UART_SFE_SFE_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_SFE_SFE - * - * Enable Rx/Tx - */ -#define ALT_UART_SFE_SFE_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */ -#define ALT_UART_SFE_SFE_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */ -#define ALT_UART_SFE_SFE_MSB 0 -/* The width in bits of the ALT_UART_SFE_SFE register field. */ -#define ALT_UART_SFE_SFE_WIDTH 1 -/* The mask used to set the ALT_UART_SFE_SFE register field value. */ -#define ALT_UART_SFE_SFE_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_SFE_SFE register field value. */ -#define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_SFE_SFE register field. */ -#define ALT_UART_SFE_SFE_RESET 0x0 -/* Extracts the ALT_UART_SFE_SFE field value from a register. */ -#define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */ -#define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_SFE. - */ -struct ALT_UART_SFE_s -{ - uint32_t sfe : 1; /* Shadow FIFO Enable */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_SFE. */ -typedef volatile struct ALT_UART_SFE_s ALT_UART_SFE_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_SFE register from the beginning of the component. */ -#define ALT_UART_SFE_OFST 0x98 -/* The address of the ALT_UART_SFE register. */ -#define ALT_UART_SFE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SFE_OFST)) - -/* - * Register : Shadow Rx Trigger - srt - * - * This is a shadow register for the Rx trigger bits (FCR[7:6]). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------ - * [1:0] | RW | 0x0 | Shadow Rx Trigger Bits - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Shadow Rx Trigger Bits - srt - * - * This can be used to remove the burden of having to store the previously written - * value to the FCR in memory and having to mask this value so that only the Rx - * trigger bit gets updated. This is used to select the trigger level in the - * receiver FIFO at which the Received Data Available Interrupt will be generated. - * It also determines when the uart_dma_rx_req_n signal will be asserted when DMA - * Mode (FCR[3]) is set to one. The enum below shows trigger levels that are - * supported. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------|:------|:---------------------- - * ALT_UART_SRT_SRT_E_ONECHAR | 0x0 | one character in fifo - * ALT_UART_SRT_SRT_E_QUARTERFULL | 0x1 | FIFO 1/4 full - * ALT_UART_SRT_SRT_E_HALFFULL | 0x2 | FIFO 1/2 full - * ALT_UART_SRT_SRT_E_FULLLESS2 | 0x3 | FIFO 2 less than full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_SRT_SRT - * - * one character in fifo - */ -#define ALT_UART_SRT_SRT_E_ONECHAR 0x0 -/* - * Enumerated value for register field ALT_UART_SRT_SRT - * - * FIFO 1/4 full - */ -#define ALT_UART_SRT_SRT_E_QUARTERFULL 0x1 -/* - * Enumerated value for register field ALT_UART_SRT_SRT - * - * FIFO 1/2 full - */ -#define ALT_UART_SRT_SRT_E_HALFFULL 0x2 -/* - * Enumerated value for register field ALT_UART_SRT_SRT - * - * FIFO 2 less than full - */ -#define ALT_UART_SRT_SRT_E_FULLLESS2 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */ -#define ALT_UART_SRT_SRT_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */ -#define ALT_UART_SRT_SRT_MSB 1 -/* The width in bits of the ALT_UART_SRT_SRT register field. */ -#define ALT_UART_SRT_SRT_WIDTH 2 -/* The mask used to set the ALT_UART_SRT_SRT register field value. */ -#define ALT_UART_SRT_SRT_SET_MSK 0x00000003 -/* The mask used to clear the ALT_UART_SRT_SRT register field value. */ -#define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc -/* The reset value of the ALT_UART_SRT_SRT register field. */ -#define ALT_UART_SRT_SRT_RESET 0x0 -/* Extracts the ALT_UART_SRT_SRT field value from a register. */ -#define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */ -#define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_SRT. - */ -struct ALT_UART_SRT_s -{ - uint32_t srt : 2; /* Shadow Rx Trigger Bits */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_SRT. */ -typedef volatile struct ALT_UART_SRT_s ALT_UART_SRT_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_SRT register from the beginning of the component. */ -#define ALT_UART_SRT_OFST 0x9c -/* The address of the ALT_UART_SRT register. */ -#define ALT_UART_SRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRT_OFST)) - -/* - * Register : Shadow Tx Empty Trigger - stet - * - * This is a shadow register for the Tx empty trigger bits (FCR[5:4]). - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:----------------------------- - * [1:0] | RW | 0x0 | Shadow Tx Empty Trigger Bits - * [31:2] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Shadow Tx Empty Trigger Bits - stet - * - * This can be used to remove the burden of having to store the previously written - * value to the FCR in memory and having to mask this value so that only the Tx - * empty trigger bit gets updated. This is used to select the empty threshold level - * at which the THRE Interrupts will be generated when the mode is active. These - * threshold levels are also described in. The enum trigger levels are supported. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :---------------------------------|:------|:----------------------- - * ALT_UART_STET_STET_E_FIFOEMPTY | 0x0 | FIFO empty - * ALT_UART_STET_STET_E_TWOCHARS | 0x1 | Two characters in FIFO - * ALT_UART_STET_STET_E_QUARTERFULL | 0x2 | FIFO quarter full - * ALT_UART_STET_STET_E_HALFFULL | 0x3 | FIFO half full - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_STET_STET - * - * FIFO empty - */ -#define ALT_UART_STET_STET_E_FIFOEMPTY 0x0 -/* - * Enumerated value for register field ALT_UART_STET_STET - * - * Two characters in FIFO - */ -#define ALT_UART_STET_STET_E_TWOCHARS 0x1 -/* - * Enumerated value for register field ALT_UART_STET_STET - * - * FIFO quarter full - */ -#define ALT_UART_STET_STET_E_QUARTERFULL 0x2 -/* - * Enumerated value for register field ALT_UART_STET_STET - * - * FIFO half full - */ -#define ALT_UART_STET_STET_E_HALFFULL 0x3 - -/* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */ -#define ALT_UART_STET_STET_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */ -#define ALT_UART_STET_STET_MSB 1 -/* The width in bits of the ALT_UART_STET_STET register field. */ -#define ALT_UART_STET_STET_WIDTH 2 -/* The mask used to set the ALT_UART_STET_STET register field value. */ -#define ALT_UART_STET_STET_SET_MSK 0x00000003 -/* The mask used to clear the ALT_UART_STET_STET register field value. */ -#define ALT_UART_STET_STET_CLR_MSK 0xfffffffc -/* The reset value of the ALT_UART_STET_STET register field. */ -#define ALT_UART_STET_STET_RESET 0x0 -/* Extracts the ALT_UART_STET_STET field value from a register. */ -#define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */ -#define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_STET. - */ -struct ALT_UART_STET_s -{ - uint32_t stet : 2; /* Shadow Tx Empty Trigger Bits */ - uint32_t : 30; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_STET. */ -typedef volatile struct ALT_UART_STET_s ALT_UART_STET_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_STET register from the beginning of the component. */ -#define ALT_UART_STET_OFST 0xa0 -/* The address of the ALT_UART_STET register. */ -#define ALT_UART_STET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STET_OFST)) - -/* - * Register : Halt Tx - htx - * - * Used to halt transmission for testing. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------- - * [0] | RW | 0x0 | Halt Tx Bits - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : Halt Tx Bits - htx - * - * This register is use to halt transmissions for testing, so that the transmit - * FIFO can be filled by the master when FIFO's are enabled. - * - * Note, if FIFO's are not enabled, the setting of the halt Tx register will have - * no effect on operation. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :------------------------|:------|:----------------- - * ALT_UART_HTX_HTX_E_DISD | 0x0 | Halt Tx disabled - * ALT_UART_HTX_HTX_E_END | 0x1 | Halt Tx enabled - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_HTX_HTX - * - * Halt Tx disabled - */ -#define ALT_UART_HTX_HTX_E_DISD 0x0 -/* - * Enumerated value for register field ALT_UART_HTX_HTX - * - * Halt Tx enabled - */ -#define ALT_UART_HTX_HTX_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */ -#define ALT_UART_HTX_HTX_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */ -#define ALT_UART_HTX_HTX_MSB 0 -/* The width in bits of the ALT_UART_HTX_HTX register field. */ -#define ALT_UART_HTX_HTX_WIDTH 1 -/* The mask used to set the ALT_UART_HTX_HTX register field value. */ -#define ALT_UART_HTX_HTX_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_HTX_HTX register field value. */ -#define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_HTX_HTX register field. */ -#define ALT_UART_HTX_HTX_RESET 0x0 -/* Extracts the ALT_UART_HTX_HTX field value from a register. */ -#define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */ -#define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_HTX. - */ -struct ALT_UART_HTX_s -{ - uint32_t htx : 1; /* Halt Tx Bits */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_HTX. */ -typedef volatile struct ALT_UART_HTX_s ALT_UART_HTX_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_HTX register from the beginning of the component. */ -#define ALT_UART_HTX_OFST 0xa4 -/* The address of the ALT_UART_HTX register. */ -#define ALT_UART_HTX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_HTX_OFST)) - -/* - * Register : DMA Software Acknowledge - dmasa - * - * DMA Operation Control - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:------|:------------------------------ - * [0] | W | 0x0 | DMA Software Acknowledge Bits - * [31:1] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : DMA Software Acknowledge Bits - dmasa - * - * This register is used to perform DMA software acknowledge if a transfer needs to - * be terminated due to an error condition. For example, if the DMA disables the - * channel, then the uart should clear its request. This will cause the Tx request, - * Tx single, Rx request and Rx single signals to de-assert. Note that this bit is - * 'self-clearing' and it is not necessary to clear this bit. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */ -#define ALT_UART_DMASA_DMASA_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */ -#define ALT_UART_DMASA_DMASA_MSB 0 -/* The width in bits of the ALT_UART_DMASA_DMASA register field. */ -#define ALT_UART_DMASA_DMASA_WIDTH 1 -/* The mask used to set the ALT_UART_DMASA_DMASA register field value. */ -#define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001 -/* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */ -#define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe -/* The reset value of the ALT_UART_DMASA_DMASA register field. */ -#define ALT_UART_DMASA_DMASA_RESET 0x0 -/* Extracts the ALT_UART_DMASA_DMASA field value from a register. */ -#define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0) -/* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */ -#define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_DMASA. - */ -struct ALT_UART_DMASA_s -{ - uint32_t dmasa : 1; /* DMA Software Acknowledge Bits */ - uint32_t : 31; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_DMASA. */ -typedef volatile struct ALT_UART_DMASA_s ALT_UART_DMASA_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */ -#define ALT_UART_DMASA_OFST 0xa8 -/* The address of the ALT_UART_DMASA register. */ -#define ALT_UART_DMASA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_DMASA_OFST)) - -/* - * Register : Component Parameter Register - cpr - * - * Describes various fixed hardware setups states. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :--------|:-------|:------|:---------------------------------- - * [1:0] | R | 0x2 | APB DATA WIDTH - * [3:2] | ??? | 0x0 | *UNDEFINED* - * [4] | R | 0x1 | Auto Flow Control - * [5] | R | 0x1 | THRE MODE - * [6] | R | 0x0 | SIR MODE Unsupported - * [7] | R | 0x0 | SIR LP MODE Unsupported - * [8] | R | 0x1 | ADDITIONAL FEATURES Supported - * [9] | R | 0x1 | FIFO ACCESS Supported - * [10] | R | 0x1 | FIFO STAT Supported - * [11] | R | 0x1 | SHADOW Supported - * [12] | R | 0x1 | Configuartion ID Register Present - * [13] | R | 0x1 | DMA EXTRA Supported - * [15:14] | ??? | 0x0 | *UNDEFINED* - * [23:16] | R | 0x37 | FIFO Depth - * [31:24] | ??? | 0x0 | *UNDEFINED* - * - */ -/* - * Field : APB DATA WIDTH - apbdatawidth - * - * Fixed to support an ABP data bus width of 32-bits. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------------------|:------|:------------------------- - * ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH - * - * APB Data Width = 32-bits - */ -#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */ -#define ALT_UART_CPR_APBDATAWIDTH_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */ -#define ALT_UART_CPR_APBDATAWIDTH_MSB 1 -/* The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field. */ -#define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2 -/* The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value. */ -#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003 -/* The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value. */ -#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc -/* The reset value of the ALT_UART_CPR_APBDATAWIDTH register field. */ -#define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2 -/* Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register. */ -#define ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0) -/* Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register. */ -#define ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003) - -/* - * Field : Auto Flow Control - afce_mode - * - * Allows auto flow control. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:------------ - * ALT_UART_CPR_AFCE_MOD_E_END | 0x1 | Auto Flow - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_AFCE_MOD - * - * Auto Flow - */ -#define ALT_UART_CPR_AFCE_MOD_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field. */ -#define ALT_UART_CPR_AFCE_MOD_LSB 4 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field. */ -#define ALT_UART_CPR_AFCE_MOD_MSB 4 -/* The width in bits of the ALT_UART_CPR_AFCE_MOD register field. */ -#define ALT_UART_CPR_AFCE_MOD_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_AFCE_MOD register field value. */ -#define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010 -/* The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value. */ -#define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef -/* The reset value of the ALT_UART_CPR_AFCE_MOD register field. */ -#define ALT_UART_CPR_AFCE_MOD_RESET 0x1 -/* Extracts the ALT_UART_CPR_AFCE_MOD field value from a register. */ -#define ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4) -/* Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register. */ -#define ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010) - -/* - * Field : THRE MODE - thre_mode - * - * Programmable Transmitter Hold Register Empty interrupt - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:------------------------------------------ - * ALT_UART_CPR_THRE_MOD_E_END | 0x1 | Programmable Tx Hold Reg. Empty interrupt - * : | | present - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_THRE_MOD - * - * Programmable Tx Hold Reg. Empty interrupt present - */ -#define ALT_UART_CPR_THRE_MOD_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field. */ -#define ALT_UART_CPR_THRE_MOD_LSB 5 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field. */ -#define ALT_UART_CPR_THRE_MOD_MSB 5 -/* The width in bits of the ALT_UART_CPR_THRE_MOD register field. */ -#define ALT_UART_CPR_THRE_MOD_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_THRE_MOD register field value. */ -#define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020 -/* The mask used to clear the ALT_UART_CPR_THRE_MOD register field value. */ -#define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf -/* The reset value of the ALT_UART_CPR_THRE_MOD register field. */ -#define ALT_UART_CPR_THRE_MOD_RESET 0x1 -/* Extracts the ALT_UART_CPR_THRE_MOD field value from a register. */ -#define ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5) -/* Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register. */ -#define ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020) - -/* - * Field : SIR MODE Unsupported - sir_mode - * - * Sir mode not used in this application. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :----------------------------|:------|:----------------------- - * ALT_UART_CPR_SIR_MOD_E_DISD | 0x0 | Sir Mode Not Supported - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_SIR_MOD - * - * Sir Mode Not Supported - */ -#define ALT_UART_CPR_SIR_MOD_E_DISD 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field. */ -#define ALT_UART_CPR_SIR_MOD_LSB 6 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field. */ -#define ALT_UART_CPR_SIR_MOD_MSB 6 -/* The width in bits of the ALT_UART_CPR_SIR_MOD register field. */ -#define ALT_UART_CPR_SIR_MOD_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_SIR_MOD register field value. */ -#define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040 -/* The mask used to clear the ALT_UART_CPR_SIR_MOD register field value. */ -#define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf -/* The reset value of the ALT_UART_CPR_SIR_MOD register field. */ -#define ALT_UART_CPR_SIR_MOD_RESET 0x0 -/* Extracts the ALT_UART_CPR_SIR_MOD field value from a register. */ -#define ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6) -/* Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register. */ -#define ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040) - -/* - * Field : SIR LP MODE Unsupported - sir_lp_mode - * - * LP Sir Mode not used in this application. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------|:------|:-------------------------- - * ALT_UART_CPR_SIR_LP_MOD_E_DISD | 0x0 | LP Sir Mode Not Supported - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD - * - * LP Sir Mode Not Supported - */ -#define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */ -#define ALT_UART_CPR_SIR_LP_MOD_LSB 7 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */ -#define ALT_UART_CPR_SIR_LP_MOD_MSB 7 -/* The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field. */ -#define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value. */ -#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080 -/* The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value. */ -#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f -/* The reset value of the ALT_UART_CPR_SIR_LP_MOD register field. */ -#define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0 -/* Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register. */ -#define ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7) -/* Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register. */ -#define ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080) - -/* - * Field : ADDITIONAL FEATURES Supported - additional_feat - * - * Configures the uart to include fifo status register, shadow registers and - * encoded parameter register. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------------|:------|:------------------------------ - * ALT_UART_CPR_ADDITIONAL_FEAT_E_END | 0x1 | Additional Features Supported - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT - * - * Additional Features Supported - */ -#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ -#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ -#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8 -/* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ -#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */ -#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100 -/* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */ -#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff -/* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */ -#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1 -/* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */ -#define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8) -/* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */ -#define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100) - -/* - * Field : FIFO ACCESS Supported - fifo_access - * - * Configures the peripheral to have a programmable FIFO access mode. This is used - * for test purposes, to allow the receiver FIFO to be written and the transmit - * FIFO to be read when FIFOs are implemented and enabled. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------|:------|:---------------------- - * ALT_UART_CPR_FIFO_ACCESS_E_END | 0x1 | FIFO Access Supported - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS - * - * FIFO Access Supported - */ -#define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */ -#define ALT_UART_CPR_FIFO_ACCESS_LSB 9 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */ -#define ALT_UART_CPR_FIFO_ACCESS_MSB 9 -/* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */ -#define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */ -#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200 -/* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */ -#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff -/* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */ -#define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1 -/* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */ -#define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9) -/* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */ -#define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200) - -/* - * Field : FIFO STAT Supported - fifo_stat - * - * Configures the peripheral to have three additional FIFO status registers. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:-------------------- - * ALT_UART_CPR_FIFO_STAT_E_END | 0x1 | FIFO Stat Supported - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_FIFO_STAT - * - * FIFO Stat Supported - */ -#define ALT_UART_CPR_FIFO_STAT_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */ -#define ALT_UART_CPR_FIFO_STAT_LSB 10 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */ -#define ALT_UART_CPR_FIFO_STAT_MSB 10 -/* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */ -#define ALT_UART_CPR_FIFO_STAT_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */ -#define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400 -/* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */ -#define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff -/* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */ -#define ALT_UART_CPR_FIFO_STAT_RESET 0x1 -/* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */ -#define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10) -/* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */ -#define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400) - -/* - * Field : SHADOW Supported - shadow - * - * Configures the peripheral to have seven additional registers that shadow some of - * the existing register bits that are regularly modified by software. These can be - * used to reduce the software overhead that is introduced by having to perform - * read-modify writes. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------|:------|:----------------- - * ALT_UART_CPR_SHADOW_E_END | 0x1 | Shadow Supported - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_SHADOW - * - * Shadow Supported - */ -#define ALT_UART_CPR_SHADOW_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */ -#define ALT_UART_CPR_SHADOW_LSB 11 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */ -#define ALT_UART_CPR_SHADOW_MSB 11 -/* The width in bits of the ALT_UART_CPR_SHADOW register field. */ -#define ALT_UART_CPR_SHADOW_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_SHADOW register field value. */ -#define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800 -/* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */ -#define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff -/* The reset value of the ALT_UART_CPR_SHADOW register field. */ -#define ALT_UART_CPR_SHADOW_RESET 0x1 -/* Extracts the ALT_UART_CPR_SHADOW field value from a register. */ -#define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11) -/* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */ -#define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800) - -/* - * Field : Configuartion ID Register Present - uart_add_encoded_param - * - * Configures the peripheral to have a configuration identification register. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :--------------------------------------|:------|:-------------------- - * ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END | 0x1 | ID register present - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM - * - * ID register present - */ -#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ -#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ -#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12 -/* The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ -#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */ -#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000 -/* The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */ -#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff -/* The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */ -#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1 -/* Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register. */ -#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12) -/* Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register. */ -#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000) - -/* - * Field : DMA EXTRA Supported - dma_extra - * - * Configures the peripheral to have four additional DMA signals on the interface. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-----------------------------|:------|:-------------------- - * ALT_UART_CPR_DMA_EXTRA_E_END | 0x1 | DMA Extra Supported - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA - * - * DMA Extra Supported - */ -#define ALT_UART_CPR_DMA_EXTRA_E_END 0x1 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */ -#define ALT_UART_CPR_DMA_EXTRA_LSB 13 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */ -#define ALT_UART_CPR_DMA_EXTRA_MSB 13 -/* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */ -#define ALT_UART_CPR_DMA_EXTRA_WIDTH 1 -/* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */ -#define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000 -/* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */ -#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff -/* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */ -#define ALT_UART_CPR_DMA_EXTRA_RESET 0x1 -/* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */ -#define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13) -/* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */ -#define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000) - -/* - * Field : FIFO Depth - fifo_mode - * - * Receiver and Transmitter FIFO depth in bytes. - * - * Field Enumeration Values: - * - * Enum | Value | Description - * :-------------------------------------|:------|:--------------------- - * ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES | 0x80 | FIFO Depth 128 bytes - * - * Field Access Macros: - * - */ -/* - * Enumerated value for register field ALT_UART_CPR_FIFO_MOD - * - * FIFO Depth 128 bytes - */ -#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80 - -/* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field. */ -#define ALT_UART_CPR_FIFO_MOD_LSB 16 -/* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field. */ -#define ALT_UART_CPR_FIFO_MOD_MSB 23 -/* The width in bits of the ALT_UART_CPR_FIFO_MOD register field. */ -#define ALT_UART_CPR_FIFO_MOD_WIDTH 8 -/* The mask used to set the ALT_UART_CPR_FIFO_MOD register field value. */ -#define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000 -/* The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value. */ -#define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff -/* The reset value of the ALT_UART_CPR_FIFO_MOD register field. */ -#define ALT_UART_CPR_FIFO_MOD_RESET 0x37 -/* Extracts the ALT_UART_CPR_FIFO_MOD field value from a register. */ -#define ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16) -/* Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register. */ -#define ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_CPR. - */ -struct ALT_UART_CPR_s -{ - const uint32_t apbdatawidth : 2; /* APB DATA WIDTH */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t afce_mode : 1; /* Auto Flow Control */ - const uint32_t thre_mode : 1; /* THRE MODE */ - const uint32_t sir_mode : 1; /* SIR MODE Unsupported */ - const uint32_t sir_lp_mode : 1; /* SIR LP MODE Unsupported */ - const uint32_t additional_feat : 1; /* ADDITIONAL FEATURES Supported */ - const uint32_t fifo_access : 1; /* FIFO ACCESS Supported */ - const uint32_t fifo_stat : 1; /* FIFO STAT Supported */ - const uint32_t shadow : 1; /* SHADOW Supported */ - const uint32_t uart_add_encoded_param : 1; /* Configuartion ID Register Present */ - const uint32_t dma_extra : 1; /* DMA EXTRA Supported */ - uint32_t : 2; /* *UNDEFINED* */ - const uint32_t fifo_mode : 8; /* FIFO Depth */ - uint32_t : 8; /* *UNDEFINED* */ -}; - -/* The typedef declaration for register ALT_UART_CPR. */ -typedef volatile struct ALT_UART_CPR_s ALT_UART_CPR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_CPR register from the beginning of the component. */ -#define ALT_UART_CPR_OFST 0xf4 -/* The address of the ALT_UART_CPR register. */ -#define ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST)) - -/* - * Register : Component Version - ucv - * - * Used only with Additional Features - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:-----------|:-------------- - * [31:0] | R | 0x3331312a | ASCII version - * - */ -/* - * Field : ASCII version - uart_component_version - * - * ASCII value for each number in the version, followed by *For example 32_30_31_2A - * represents the version 2.01a - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ -#define ALT_UART_UCV_UART_COMPONENT_VER_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ -#define ALT_UART_UCV_UART_COMPONENT_VER_MSB 31 -/* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ -#define ALT_UART_UCV_UART_COMPONENT_VER_WIDTH 32 -/* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VER register field value. */ -#define ALT_UART_UCV_UART_COMPONENT_VER_SET_MSK 0xffffffff -/* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VER register field value. */ -#define ALT_UART_UCV_UART_COMPONENT_VER_CLR_MSK 0x00000000 -/* The reset value of the ALT_UART_UCV_UART_COMPONENT_VER register field. */ -#define ALT_UART_UCV_UART_COMPONENT_VER_RESET 0x3331312a -/* Extracts the ALT_UART_UCV_UART_COMPONENT_VER field value from a register. */ -#define ALT_UART_UCV_UART_COMPONENT_VER_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_UART_UCV_UART_COMPONENT_VER register field value suitable for setting the register. */ -#define ALT_UART_UCV_UART_COMPONENT_VER_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_UCV. - */ -struct ALT_UART_UCV_s -{ - const uint32_t uart_component_version : 32; /* ASCII version */ -}; - -/* The typedef declaration for register ALT_UART_UCV. */ -typedef volatile struct ALT_UART_UCV_s ALT_UART_UCV_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_UCV register from the beginning of the component. */ -#define ALT_UART_UCV_OFST 0xf8 -/* The address of the ALT_UART_UCV register. */ -#define ALT_UART_UCV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_UCV_OFST)) - -/* - * Register : Component Type Register - ctr - * - * Describes a hex value associated with the component. - * - * Register Layout - * - * Bits | Access | Reset | Description - * :-------|:-------|:-----------|:-------------- - * [31:0] | R | 0x44570110 | Peripheral ID - * - */ -/* - * Field : Peripheral ID - peripheral_id - * - * This register contains the peripherals identification code. - * - * Field Access Macros: - * - */ -/* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */ -#define ALT_UART_CTR_PERIPHERAL_ID_LSB 0 -/* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */ -#define ALT_UART_CTR_PERIPHERAL_ID_MSB 31 -/* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */ -#define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32 -/* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */ -#define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff -/* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */ -#define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000 -/* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */ -#define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110 -/* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */ -#define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0) -/* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */ -#define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register ALT_UART_CTR. - */ -struct ALT_UART_CTR_s -{ - const uint32_t peripheral_id : 32; /* Peripheral ID */ -}; - -/* The typedef declaration for register ALT_UART_CTR. */ -typedef volatile struct ALT_UART_CTR_s ALT_UART_CTR_t; -#endif /* __ASSEMBLY__ */ - -/* The byte offset of the ALT_UART_CTR register from the beginning of the component. */ -#define ALT_UART_CTR_OFST 0xfc -/* The address of the ALT_UART_CTR register. */ -#define ALT_UART_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CTR_OFST)) - -#ifndef __ASSEMBLY__ -/* - * WARNING: The C register and register group struct declarations are provided for - * convenience and illustrative purposes. They should, however, be used with - * caution as the C language standard provides no guarantees about the alignment or - * atomicity of device memory accesses. The recommended practice for writing - * hardware drivers is to use the SoCAL access macros and alt_read_word() and - * alt_write_word() functions. - * - * The struct declaration for register group ALT_UART. - */ -struct ALT_UART_s -{ - volatile ALT_UART_RBR_THR_DLL_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */ - volatile ALT_UART_IER_DLH_t ier_dlh; /* ALT_UART_IER_DLH */ - /* Union for registers colocated at base address offset #0x. */ - union - { - volatile ALT_UART_IIR_t iir; /* ALT_UART_IIR */ - volatile ALT_UART_FCR_t fcr; /* ALT_UART_FCR */ - } _u_0x8; - volatile ALT_UART_LCR_t lcr; /* ALT_UART_LCR */ - volatile ALT_UART_MCR_t mcr; /* ALT_UART_MCR */ - volatile ALT_UART_LSR_t lsr; /* ALT_UART_LSR */ - volatile ALT_UART_MSR_t msr; /* ALT_UART_MSR */ - volatile ALT_UART_SCR_t scr; /* ALT_UART_SCR */ - volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */ - volatile ALT_UART_SRBR_t srbr; /* ALT_UART_SRBR */ - volatile ALT_UART_STHR_t sthr; /* ALT_UART_STHR */ - volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */ - volatile ALT_UART_FAR_t far; /* ALT_UART_FAR */ - volatile ALT_UART_TFR_t tfr; /* ALT_UART_TFR */ - volatile ALT_UART_RFW_t RFW; /* ALT_UART_RFW */ - volatile ALT_UART_USR_t usr; /* ALT_UART_USR */ - volatile ALT_UART_TFL_t tfl; /* ALT_UART_TFL */ - volatile ALT_UART_RFL_t rfl; /* ALT_UART_RFL */ - volatile ALT_UART_SRR_t srr; /* ALT_UART_SRR */ - volatile ALT_UART_SRTS_t srts; /* ALT_UART_SRTS */ - volatile ALT_UART_SBCR_t sbcr; /* ALT_UART_SBCR */ - volatile ALT_UART_SDMAM_t sdmam; /* ALT_UART_SDMAM */ - volatile ALT_UART_SFE_t sfe; /* ALT_UART_SFE */ - volatile ALT_UART_SRT_t srt; /* ALT_UART_SRT */ - volatile ALT_UART_STET_t stet; /* ALT_UART_STET */ - volatile ALT_UART_HTX_t htx; /* ALT_UART_HTX */ - volatile ALT_UART_DMASA_t dmasa; /* ALT_UART_DMASA */ - volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */ - volatile ALT_UART_CPR_t cpr; /* ALT_UART_CPR */ - volatile ALT_UART_UCV_t ucv; /* ALT_UART_UCV */ - volatile ALT_UART_CTR_t ctr; /* ALT_UART_CTR */ -}; - -/* The typedef declaration for register group ALT_UART. */ -typedef volatile struct ALT_UART_s ALT_UART_t; -/* The struct declaration for the raw register contents of register group ALT_UART. */ -struct ALT_UART_raw_s -{ - volatile uint32_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */ - volatile uint32_t ier_dlh; /* ALT_UART_IER_DLH */ - /* Union for registers colocated at base address offset #0x. */ - union - { - volatile uint32_t iir; /* ALT_UART_IIR */ - volatile uint32_t fcr; /* ALT_UART_FCR */ - } _u_0x8; - volatile uint32_t lcr; /* ALT_UART_LCR */ - volatile uint32_t mcr; /* ALT_UART_MCR */ - volatile uint32_t lsr; /* ALT_UART_LSR */ - volatile uint32_t msr; /* ALT_UART_MSR */ - volatile uint32_t scr; /* ALT_UART_SCR */ - volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */ - volatile uint32_t srbr; /* ALT_UART_SRBR */ - volatile uint32_t sthr; /* ALT_UART_STHR */ - volatile uint32_t _pad_0x38_0x6f[14]; /* *UNDEFINED* */ - volatile uint32_t far; /* ALT_UART_FAR */ - volatile uint32_t tfr; /* ALT_UART_TFR */ - volatile uint32_t RFW; /* ALT_UART_RFW */ - volatile uint32_t usr; /* ALT_UART_USR */ - volatile uint32_t tfl; /* ALT_UART_TFL */ - volatile uint32_t rfl; /* ALT_UART_RFL */ - volatile uint32_t srr; /* ALT_UART_SRR */ - volatile uint32_t srts; /* ALT_UART_SRTS */ - volatile uint32_t sbcr; /* ALT_UART_SBCR */ - volatile uint32_t sdmam; /* ALT_UART_SDMAM */ - volatile uint32_t sfe; /* ALT_UART_SFE */ - volatile uint32_t srt; /* ALT_UART_SRT */ - volatile uint32_t stet; /* ALT_UART_STET */ - volatile uint32_t htx; /* ALT_UART_HTX */ - volatile uint32_t dmasa; /* ALT_UART_DMASA */ - volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */ - volatile uint32_t cpr; /* ALT_UART_CPR */ - volatile uint32_t ucv; /* ALT_UART_UCV */ - volatile uint32_t ctr; /* ALT_UART_CTR */ -}; - -/* The typedef declaration for the raw register contents of register group ALT_UART. */ -typedef volatile struct ALT_UART_raw_s ALT_UART_raw_t; -#endif /* __ASSEMBLY__ */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_ALT_UART_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/hps.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/hps.h deleted file mode 100644 index c6b312b415..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/hps.h +++ /dev/null @@ -1,8026 +0,0 @@ -/******************************************************************************* -* * -* Copyright 2013 Altera Corporation. All Rights Reserved. * -* * -* Redistribution and use in source and binary forms, with or without * -* modification, are permitted provided that the following conditions are met: * -* * -* 1. Redistributions of source code must retain the above copyright notice, * -* this list of conditions and the following disclaimer. * -* * -* 2. Redistributions in binary form must reproduce the above copyright notice, * -* this list of conditions and the following disclaimer in the documentation * -* and/or other materials provided with the distribution. * -* * -* 3. The name of the author may not be used to endorse or promote products * -* derived from this software without specific prior written permission. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR * -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO * -* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * -* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * -* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * -* * -*******************************************************************************/ - -/* Altera - hps */ - -#ifndef __ALTERA_HPS_H__ -#define __ALTERA_HPS_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#define ALT_HPS_ADDR 0 -/* - * Address Space : ALT_HPS - * - */ -/* - * Component Instance : stm - * - * Instance stm of component ALT_STM. - * - * - */ -/* The address of the ALT_STM_REG register for the ALT_STM instance. */ -#define ALT_STM_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_STM_ADDR) + ALT_STM_REG_OFST)) -/* The base address byte offset for the start of the ALT_STM component. */ -#define ALT_STM_OFST 0xfc000000 -/* The start address of the ALT_STM component. */ -#define ALT_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_STM_OFST)) -/* The lower bound address range of the ALT_STM component. */ -#define ALT_STM_LB_ADDR ALT_STM_ADDR -/* The upper bound address range of the ALT_STM component. */ -#define ALT_STM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_STM_ADDR) + 0x4) - 1)) - - -/* - * Component Instance : dap - * - * Instance dap of component ALT_DAP. - * - * - */ -/* The address of the ALT_DAP_REG register for the ALT_DAP instance. */ -#define ALT_DAP_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DAP_ADDR) + ALT_DAP_REG_OFST)) -/* The base address byte offset for the start of the ALT_DAP component. */ -#define ALT_DAP_OFST 0xff000000 -/* The start address of the ALT_DAP component. */ -#define ALT_DAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DAP_OFST)) -/* The lower bound address range of the ALT_DAP component. */ -#define ALT_DAP_LB_ADDR ALT_DAP_ADDR -/* The upper bound address range of the ALT_DAP component. */ -#define ALT_DAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DAP_ADDR) + 0x4) - 1)) - - -/* - * Component Instance : lwfpgaslaves - * - * Instance lwfpgaslaves of component ALT_LWFPGASLVS. - * - * - */ -/* The base address byte offset for the start of the ALT_LWFPGASLVS component. */ -#define ALT_LWFPGASLVS_OFST 0xff200000 -/* The start address of the ALT_LWFPGASLVS component. */ -#define ALT_LWFPGASLVS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_LWFPGASLVS_OFST)) -/* The lower bound address range of the ALT_LWFPGASLVS component. */ -#define ALT_LWFPGASLVS_LB_ADDR ALT_LWFPGASLVS_ADDR -/* The upper bound address range of the ALT_LWFPGASLVS component. */ -#define ALT_LWFPGASLVS_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWFPGASLVS_ADDR) + 0x200000) - 1)) - - -/* - * Component Instance : lwhps2fpgaregs - * - * Instance lwhps2fpgaregs of component ALT_LWH2F. - * - * - */ -/* - * Register Group Instance : idgrp - * - * Instance idgrp of register group ALT_LWH2F_ID. - * - * - */ -/* The address of the ALT_LWH2F_ID_PERIPH_ID_4 register for the ALT_LWH2F_ID instance. */ -#define ALT_LWH2F_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_4_OFST)) -/* The address of the ALT_LWH2F_ID_PERIPH_ID_0 register for the ALT_LWH2F_ID instance. */ -#define ALT_LWH2F_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_0_OFST)) -/* The address of the ALT_LWH2F_ID_PERIPH_ID_1 register for the ALT_LWH2F_ID instance. */ -#define ALT_LWH2F_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_1_OFST)) -/* The address of the ALT_LWH2F_ID_PERIPH_ID_2 register for the ALT_LWH2F_ID instance. */ -#define ALT_LWH2F_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_2_OFST)) -/* The address of the ALT_LWH2F_ID_PERIPH_ID_3 register for the ALT_LWH2F_ID instance. */ -#define ALT_LWH2F_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_PERIPH_ID_3_OFST)) -/* The address of the ALT_LWH2F_ID_COMP_ID_0 register for the ALT_LWH2F_ID instance. */ -#define ALT_LWH2F_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_0_OFST)) -/* The address of the ALT_LWH2F_ID_COMP_ID_1 register for the ALT_LWH2F_ID instance. */ -#define ALT_LWH2F_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_1_OFST)) -/* The address of the ALT_LWH2F_ID_COMP_ID_2 register for the ALT_LWH2F_ID instance. */ -#define ALT_LWH2F_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_2_OFST)) -/* The address of the ALT_LWH2F_ID_COMP_ID_3 register for the ALT_LWH2F_ID instance. */ -#define ALT_LWH2F_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + ALT_LWH2F_ID_COMP_ID_3_OFST)) -/* The base address byte offset for the start of the ALT_LWH2F_ID component. */ -#define ALT_LWH2F_ID_OFST 0x1000 -/* The start address of the ALT_LWH2F_ID component. */ -#define ALT_LWH2F_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_ID_OFST)) -/* The lower bound address range of the ALT_LWH2F_ID component. */ -#define ALT_LWH2F_ID_LB_ADDR ALT_LWH2F_ID_ADDR -/* The upper bound address range of the ALT_LWH2F_ID component. */ -#define ALT_LWH2F_ID_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_ID_ADDR) + 0x1000) - 1)) - - -/* - * Register Group Instance : mastergrp - * - * Instance mastergrp of register group ALT_LWH2F_MST. - * - * - */ -/* - * Register Group Instance : mastergrp_fpga2hpsregs - * - * Instance mastergrp_fpga2hpsregs of register group ALT_LWH2F_MST_F2H. - * - * - */ -/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_F2H instance. */ -#define ALT_LWH2F_MST_MST_F2H_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_F2H_ADDR) -/* The address of the ALT_LWH2F_AHB_CNTL register for the ALT_LWH2F_MST_MST_F2H instance. */ -#define ALT_LWH2F_MST_MST_F2H_AHB_CNTL_ADDR ALT_LWH2F_AHB_CNTL_ADDR(ALT_LWH2F_MST_MST_F2H_ADDR) -/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_F2H component. */ -#define ALT_LWH2F_MST_MST_F2H_OFST 0x0 -/* The start address of the ALT_LWH2F_MST_MST_F2H component. */ -#define ALT_LWH2F_MST_MST_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_F2H_OFST)) -/* The lower bound address range of the ALT_LWH2F_MST_MST_F2H component. */ -#define ALT_LWH2F_MST_MST_F2H_LB_ADDR ALT_LWH2F_MST_MST_F2H_ADDR -/* The upper bound address range of the ALT_LWH2F_MST_MST_F2H component. */ -#define ALT_LWH2F_MST_MST_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_F2H_ADDR) + 0x48) - 1)) - - -/* - * Register Group Instance : mastergrp_hps2fpgaregs - * - * Instance mastergrp_hps2fpgaregs of register group ALT_LWH2F_MST_H2F. - * - * - */ -/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_H2F instance. */ -#define ALT_LWH2F_MST_MST_H2F_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_H2F_ADDR) -/* The address of the ALT_LWH2F_AHB_CNTL register for the ALT_LWH2F_MST_MST_H2F instance. */ -#define ALT_LWH2F_MST_MST_H2F_AHB_CNTL_ADDR ALT_LWH2F_AHB_CNTL_ADDR(ALT_LWH2F_MST_MST_H2F_ADDR) -/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_H2F component. */ -#define ALT_LWH2F_MST_MST_H2F_OFST 0x1000 -/* The start address of the ALT_LWH2F_MST_MST_H2F component. */ -#define ALT_LWH2F_MST_MST_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_H2F_OFST)) -/* The lower bound address range of the ALT_LWH2F_MST_MST_H2F component. */ -#define ALT_LWH2F_MST_MST_H2F_LB_ADDR ALT_LWH2F_MST_MST_H2F_ADDR -/* The upper bound address range of the ALT_LWH2F_MST_MST_H2F component. */ -#define ALT_LWH2F_MST_MST_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_H2F_ADDR) + 0x48) - 1)) - - -/* - * Register Group Instance : mastergrp_b32 - * - * Instance mastergrp_b32 of register group ALT_LWH2F_MST_B32. - * - * - */ -/* The address of the ALT_LWH2F_FN_MOD_BM_ISS register for the ALT_LWH2F_MST_MST_B32 instance. */ -#define ALT_LWH2F_MST_MST_B32_FN_MOD_BM_ISS_ADDR ALT_LWH2F_FN_MOD_BM_ISS_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) -/* The address of the ALT_LWH2F_WR_TIDEMARK register for the ALT_LWH2F_MST_MST_B32 instance. */ -#define ALT_LWH2F_MST_MST_B32_WR_TIDEMARK_ADDR ALT_LWH2F_WR_TIDEMARK_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) -/* The address of the ALT_LWH2F_FN_MOD register for the ALT_LWH2F_MST_MST_B32 instance. */ -#define ALT_LWH2F_MST_MST_B32_FN_MOD_ADDR ALT_LWH2F_FN_MOD_ADDR(ALT_LWH2F_MST_MST_B32_ADDR) -/* The base address byte offset for the start of the ALT_LWH2F_MST_MST_B32 component. */ -#define ALT_LWH2F_MST_MST_B32_OFST 0x3000 -/* The start address of the ALT_LWH2F_MST_MST_B32 component. */ -#define ALT_LWH2F_MST_MST_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + ALT_LWH2F_MST_MST_B32_OFST)) -/* The lower bound address range of the ALT_LWH2F_MST_MST_B32 component. */ -#define ALT_LWH2F_MST_MST_B32_LB_ADDR ALT_LWH2F_MST_MST_B32_ADDR -/* The upper bound address range of the ALT_LWH2F_MST_MST_B32 component. */ -#define ALT_LWH2F_MST_MST_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_MST_B32_ADDR) + 0x10c) - 1)) - - -/* The base address byte offset for the start of the ALT_LWH2F_MST component. */ -#define ALT_LWH2F_MST_OFST 0x2000 -/* The start address of the ALT_LWH2F_MST component. */ -#define ALT_LWH2F_MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_MST_OFST)) -/* The lower bound address range of the ALT_LWH2F_MST component. */ -#define ALT_LWH2F_MST_LB_ADDR ALT_LWH2F_MST_ADDR -/* The upper bound address range of the ALT_LWH2F_MST component. */ -#define ALT_LWH2F_MST_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_MST_ADDR) + 0x310c) - 1)) - - -/* - * Register Group Instance : slavegrp - * - * Instance slavegrp of register group ALT_LWH2F_SLV. - * - * - */ -/* - * Register Group Instance : slavegrp_b32 - * - * Instance slavegrp_b32 of register group ALT_LWH2F_SLV_B32. - * - * - */ -/* The address of the ALT_LWH2F_FN_MOD register for the ALT_LWH2F_SLV_SLV_B32 instance. */ -#define ALT_LWH2F_SLV_SLV_B32_FN_MOD_ADDR ALT_LWH2F_FN_MOD_ADDR(ALT_LWH2F_SLV_SLV_B32_ADDR) -/* The base address byte offset for the start of the ALT_LWH2F_SLV_SLV_B32 component. */ -#define ALT_LWH2F_SLV_SLV_B32_OFST 0x3000 -/* The start address of the ALT_LWH2F_SLV_SLV_B32 component. */ -#define ALT_LWH2F_SLV_SLV_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_SLV_ADDR) + ALT_LWH2F_SLV_SLV_B32_OFST)) -/* The lower bound address range of the ALT_LWH2F_SLV_SLV_B32 component. */ -#define ALT_LWH2F_SLV_SLV_B32_LB_ADDR ALT_LWH2F_SLV_SLV_B32_ADDR -/* The upper bound address range of the ALT_LWH2F_SLV_SLV_B32 component. */ -#define ALT_LWH2F_SLV_SLV_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_SLV_SLV_B32_ADDR) + 0x10c) - 1)) - - -/* The base address byte offset for the start of the ALT_LWH2F_SLV component. */ -#define ALT_LWH2F_SLV_OFST 0x42000 -/* The start address of the ALT_LWH2F_SLV component. */ -#define ALT_LWH2F_SLV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_LWH2F_ADDR) + ALT_LWH2F_SLV_OFST)) -/* The lower bound address range of the ALT_LWH2F_SLV component. */ -#define ALT_LWH2F_SLV_LB_ADDR ALT_LWH2F_SLV_ADDR -/* The upper bound address range of the ALT_LWH2F_SLV component. */ -#define ALT_LWH2F_SLV_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_SLV_ADDR) + 0x310c) - 1)) - - -/* The base address byte offset for the start of the ALT_LWH2F component. */ -#define ALT_LWH2F_OFST 0xff400000 -/* The start address of the ALT_LWH2F component. */ -#define ALT_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_LWH2F_OFST)) -/* The lower bound address range of the ALT_LWH2F component. */ -#define ALT_LWH2F_LB_ADDR ALT_LWH2F_ADDR -/* The upper bound address range of the ALT_LWH2F component. */ -#define ALT_LWH2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_LWH2F_ADDR) + 0x80000) - 1)) - - -/* - * Component Instance : hps2fpgaregs - * - * Instance hps2fpgaregs of component ALT_H2F. - * - * - */ -/* - * Register Group Instance : idgrp - * - * Instance idgrp of register group ALT_H2F_IDGRP. - * - * - */ -/* The address of the ALT_H2F_ID_PERIPH_ID_4 register for the ALT_H2F_IDGRP instance. */ -#define ALT_H2F_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_4_OFST)) -/* The address of the ALT_H2F_ID_PERIPH_ID_0 register for the ALT_H2F_IDGRP instance. */ -#define ALT_H2F_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_0_OFST)) -/* The address of the ALT_H2F_ID_PERIPH_ID_1 register for the ALT_H2F_IDGRP instance. */ -#define ALT_H2F_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_1_OFST)) -/* The address of the ALT_H2F_ID_PERIPH_ID_2 register for the ALT_H2F_IDGRP instance. */ -#define ALT_H2F_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_2_OFST)) -/* The address of the ALT_H2F_ID_PERIPH_ID_3 register for the ALT_H2F_IDGRP instance. */ -#define ALT_H2F_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_PERIPH_ID_3_OFST)) -/* The address of the ALT_H2F_ID_COMP_ID_0 register for the ALT_H2F_IDGRP instance. */ -#define ALT_H2F_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_0_OFST)) -/* The address of the ALT_H2F_ID_COMP_ID_1 register for the ALT_H2F_IDGRP instance. */ -#define ALT_H2F_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_1_OFST)) -/* The address of the ALT_H2F_ID_COMP_ID_2 register for the ALT_H2F_IDGRP instance. */ -#define ALT_H2F_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_2_OFST)) -/* The address of the ALT_H2F_ID_COMP_ID_3 register for the ALT_H2F_IDGRP instance. */ -#define ALT_H2F_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + ALT_H2F_ID_COMP_ID_3_OFST)) -/* The base address byte offset for the start of the ALT_H2F_IDGRP component. */ -#define ALT_H2F_IDGRP_OFST 0x1000 -/* The start address of the ALT_H2F_IDGRP component. */ -#define ALT_H2F_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_ADDR) + ALT_H2F_IDGRP_OFST)) -/* The lower bound address range of the ALT_H2F_IDGRP component. */ -#define ALT_H2F_IDGRP_LB_ADDR ALT_H2F_IDGRP_ADDR -/* The upper bound address range of the ALT_H2F_IDGRP component. */ -#define ALT_H2F_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_IDGRP_ADDR) + 0x1000) - 1)) - - -/* - * Register Group Instance : mastergrp - * - * Instance mastergrp of register group ALT_H2F_MSTGRP. - * - * - */ -/* - * Register Group Instance : mastergrp_b32 - * - * Instance mastergrp_b32 of register group ALT_H2F_MST_B32. - * - * - */ -/* The address of the ALT_H2F_FN_MOD2 register for the ALT_H2F_MST_MST_B32 instance. */ -#define ALT_H2F_MST_MST_B32_FN_MOD2_ADDR ALT_H2F_FN_MOD2_ADDR(ALT_H2F_MST_MST_B32_ADDR) -/* The address of the ALT_H2F_FN_MOD register for the ALT_H2F_MST_MST_B32 instance. */ -#define ALT_H2F_MST_MST_B32_FN_MOD_ADDR ALT_H2F_FN_MOD_ADDR(ALT_H2F_MST_MST_B32_ADDR) -/* The base address byte offset for the start of the ALT_H2F_MST_MST_B32 component. */ -#define ALT_H2F_MST_MST_B32_OFST 0x0 -/* The start address of the ALT_H2F_MST_MST_B32 component. */ -#define ALT_H2F_MST_MST_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + ALT_H2F_MST_MST_B32_OFST)) -/* The lower bound address range of the ALT_H2F_MST_MST_B32 component. */ -#define ALT_H2F_MST_MST_B32_LB_ADDR ALT_H2F_MST_MST_B32_ADDR -/* The upper bound address range of the ALT_H2F_MST_MST_B32 component. */ -#define ALT_H2F_MST_MST_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MST_MST_B32_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : mastergrp_b128 - * - * Instance mastergrp_b128 of register group ALT_H2F_MST_B128. - * - * - */ -/* The address of the ALT_H2F_FN_MOD2 register for the ALT_H2F_MST_MST_B128 instance. */ -#define ALT_H2F_MST_MST_B128_FN_MOD2_ADDR ALT_H2F_FN_MOD2_ADDR(ALT_H2F_MST_MST_B128_ADDR) -/* The address of the ALT_H2F_FN_MOD register for the ALT_H2F_MST_MST_B128 instance. */ -#define ALT_H2F_MST_MST_B128_FN_MOD_ADDR ALT_H2F_FN_MOD_ADDR(ALT_H2F_MST_MST_B128_ADDR) -/* The base address byte offset for the start of the ALT_H2F_MST_MST_B128 component. */ -#define ALT_H2F_MST_MST_B128_OFST 0x2000 -/* The start address of the ALT_H2F_MST_MST_B128 component. */ -#define ALT_H2F_MST_MST_B128_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + ALT_H2F_MST_MST_B128_OFST)) -/* The lower bound address range of the ALT_H2F_MST_MST_B128 component. */ -#define ALT_H2F_MST_MST_B128_LB_ADDR ALT_H2F_MST_MST_B128_ADDR -/* The upper bound address range of the ALT_H2F_MST_MST_B128 component. */ -#define ALT_H2F_MST_MST_B128_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MST_MST_B128_ADDR) + 0x10c) - 1)) - - -/* The base address byte offset for the start of the ALT_H2F_MSTGRP component. */ -#define ALT_H2F_MSTGRP_OFST 0x2000 -/* The start address of the ALT_H2F_MSTGRP component. */ -#define ALT_H2F_MSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_H2F_ADDR) + ALT_H2F_MSTGRP_OFST)) -/* The lower bound address range of the ALT_H2F_MSTGRP component. */ -#define ALT_H2F_MSTGRP_LB_ADDR ALT_H2F_MSTGRP_ADDR -/* The upper bound address range of the ALT_H2F_MSTGRP component. */ -#define ALT_H2F_MSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_MSTGRP_ADDR) + 0x210c) - 1)) - - -/* The base address byte offset for the start of the ALT_H2F component. */ -#define ALT_H2F_OFST 0xff500000 -/* The start address of the ALT_H2F component. */ -#define ALT_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_H2F_OFST)) -/* The lower bound address range of the ALT_H2F component. */ -#define ALT_H2F_LB_ADDR ALT_H2F_ADDR -/* The upper bound address range of the ALT_H2F component. */ -#define ALT_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_H2F_ADDR) + 0x8000) - 1)) - - -/* - * Component Instance : fpga2hpsregs - * - * Instance fpga2hpsregs of component ALT_F2H. - * - * - */ -/* - * Register Group Instance : idgrp - * - * Instance idgrp of register group ALT_F2H_IDGRP. - * - * - */ -/* The address of the ALT_F2H_ID_PERIPH_ID_4 register for the ALT_F2H_IDGRP instance. */ -#define ALT_F2H_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_4_OFST)) -/* The address of the ALT_F2H_ID_PERIPH_ID_0 register for the ALT_F2H_IDGRP instance. */ -#define ALT_F2H_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_0_OFST)) -/* The address of the ALT_F2H_ID_PERIPH_ID_1 register for the ALT_F2H_IDGRP instance. */ -#define ALT_F2H_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_1_OFST)) -/* The address of the ALT_F2H_ID_PERIPH_ID_2 register for the ALT_F2H_IDGRP instance. */ -#define ALT_F2H_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_2_OFST)) -/* The address of the ALT_F2H_ID_PERIPH_ID_3 register for the ALT_F2H_IDGRP instance. */ -#define ALT_F2H_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_PERIPH_ID_3_OFST)) -/* The address of the ALT_F2H_ID_COMP_ID_0 register for the ALT_F2H_IDGRP instance. */ -#define ALT_F2H_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_0_OFST)) -/* The address of the ALT_F2H_ID_COMP_ID_1 register for the ALT_F2H_IDGRP instance. */ -#define ALT_F2H_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_1_OFST)) -/* The address of the ALT_F2H_ID_COMP_ID_2 register for the ALT_F2H_IDGRP instance. */ -#define ALT_F2H_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_2_OFST)) -/* The address of the ALT_F2H_ID_COMP_ID_3 register for the ALT_F2H_IDGRP instance. */ -#define ALT_F2H_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + ALT_F2H_ID_COMP_ID_3_OFST)) -/* The base address byte offset for the start of the ALT_F2H_IDGRP component. */ -#define ALT_F2H_IDGRP_OFST 0x1000 -/* The start address of the ALT_F2H_IDGRP component. */ -#define ALT_F2H_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_ADDR) + ALT_F2H_IDGRP_OFST)) -/* The lower bound address range of the ALT_F2H_IDGRP component. */ -#define ALT_F2H_IDGRP_LB_ADDR ALT_F2H_IDGRP_ADDR -/* The upper bound address range of the ALT_F2H_IDGRP component. */ -#define ALT_F2H_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_IDGRP_ADDR) + 0x1000) - 1)) - - -/* - * Register Group Instance : slavegrp - * - * Instance slavegrp of register group ALT_F2H_SLVGRP. - * - * - */ -/* - * Register Group Instance : slavegrp_b32 - * - * Instance slavegrp_b32 of register group ALT_F2H_SLV_B32. - * - * - */ -/* The address of the ALT_F2H_FN_MOD2 register for the ALT_F2H_SLV_SLV_B32 instance. */ -#define ALT_F2H_SLV_SLV_B32_FN_MOD2_ADDR ALT_F2H_FN_MOD2_ADDR(ALT_F2H_SLV_SLV_B32_ADDR) -/* The address of the ALT_F2H_FN_MOD register for the ALT_F2H_SLV_SLV_B32 instance. */ -#define ALT_F2H_SLV_SLV_B32_FN_MOD_ADDR ALT_F2H_FN_MOD_ADDR(ALT_F2H_SLV_SLV_B32_ADDR) -/* The base address byte offset for the start of the ALT_F2H_SLV_SLV_B32 component. */ -#define ALT_F2H_SLV_SLV_B32_OFST 0x0 -/* The start address of the ALT_F2H_SLV_SLV_B32 component. */ -#define ALT_F2H_SLV_SLV_B32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + ALT_F2H_SLV_SLV_B32_OFST)) -/* The lower bound address range of the ALT_F2H_SLV_SLV_B32 component. */ -#define ALT_F2H_SLV_SLV_B32_LB_ADDR ALT_F2H_SLV_SLV_B32_ADDR -/* The upper bound address range of the ALT_F2H_SLV_SLV_B32 component. */ -#define ALT_F2H_SLV_SLV_B32_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLV_SLV_B32_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_b128 - * - * Instance slavegrp_b128 of register group ALT_F2H_SLV_B128. - * - * - */ -/* The address of the ALT_F2H_FN_MOD2 register for the ALT_F2H_SLV_SLV_B128 instance. */ -#define ALT_F2H_SLV_SLV_B128_FN_MOD2_ADDR ALT_F2H_FN_MOD2_ADDR(ALT_F2H_SLV_SLV_B128_ADDR) -/* The address of the ALT_F2H_FN_MOD register for the ALT_F2H_SLV_SLV_B128 instance. */ -#define ALT_F2H_SLV_SLV_B128_FN_MOD_ADDR ALT_F2H_FN_MOD_ADDR(ALT_F2H_SLV_SLV_B128_ADDR) -/* The base address byte offset for the start of the ALT_F2H_SLV_SLV_B128 component. */ -#define ALT_F2H_SLV_SLV_B128_OFST 0x2000 -/* The start address of the ALT_F2H_SLV_SLV_B128 component. */ -#define ALT_F2H_SLV_SLV_B128_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + ALT_F2H_SLV_SLV_B128_OFST)) -/* The lower bound address range of the ALT_F2H_SLV_SLV_B128 component. */ -#define ALT_F2H_SLV_SLV_B128_LB_ADDR ALT_F2H_SLV_SLV_B128_ADDR -/* The upper bound address range of the ALT_F2H_SLV_SLV_B128 component. */ -#define ALT_F2H_SLV_SLV_B128_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLV_SLV_B128_ADDR) + 0x10c) - 1)) - - -/* The base address byte offset for the start of the ALT_F2H_SLVGRP component. */ -#define ALT_F2H_SLVGRP_OFST 0x42000 -/* The start address of the ALT_F2H_SLVGRP component. */ -#define ALT_F2H_SLVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_F2H_ADDR) + ALT_F2H_SLVGRP_OFST)) -/* The lower bound address range of the ALT_F2H_SLVGRP component. */ -#define ALT_F2H_SLVGRP_LB_ADDR ALT_F2H_SLVGRP_ADDR -/* The upper bound address range of the ALT_F2H_SLVGRP component. */ -#define ALT_F2H_SLVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_SLVGRP_ADDR) + 0x210c) - 1)) - - -/* The base address byte offset for the start of the ALT_F2H component. */ -#define ALT_F2H_OFST 0xff600000 -/* The start address of the ALT_F2H component. */ -#define ALT_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_F2H_OFST)) -/* The lower bound address range of the ALT_F2H component. */ -#define ALT_F2H_LB_ADDR ALT_F2H_ADDR -/* The upper bound address range of the ALT_F2H component. */ -#define ALT_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_F2H_ADDR) + 0x80000) - 1)) - - -/* - * Component Instance : emac0 - * - * Instance emac0 of component ALT_EMAC. - * - * - */ -/* - * Register Group Instance : gmacgrp - * - * Instance gmacgrp of register group ALT_EMAC_GMAC. - * - * - */ -/* The address of the ALT_EMAC_GMAC_MAC_CFG register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_CFG_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_FRM_FLT_ADDR ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_GMII_ADDR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_GMII_ADDR_ADDR ALT_EMAC_GMAC_GMII_ADDR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_GMII_DATA register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_GMII_DATA_ADDR ALT_EMAC_GMAC_GMII_DATA_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_FLOW_CTL register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_FLOW_CTL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_VLAN_TAG register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_VLAN_TAG_ADDR ALT_EMAC_GMAC_VLAN_TAG_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_VER register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_VER_ADDR ALT_EMAC_GMAC_VER_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_DBG register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_DBG_ADDR ALT_EMAC_GMAC_DBG_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LPI_CTL_STAT_ADDR ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LPI_TMRS_CTL_ADDR ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_INT_STAT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_INT_STAT_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_INT_MSK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR1_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR1_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR2_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR2_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR3_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR3_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR4_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR4_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR5_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR5_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR6_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR6_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR7_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR7_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR8_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR8_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR9_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR9_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR10_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR10_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR11_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR11_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR12_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR12_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR13_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR13_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR14_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR14_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR15_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR15_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_SGMII_RGMII_SMII_CTL_STAT_ADDR ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_CTL register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MMC_CTL_ADDR ALT_EMAC_GMAC_MMC_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MMC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_RX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MMC_TX_INT_ADDR ALT_EMAC_GMAC_MMC_TX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MMC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MMC_TX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TX64OCTETS_GB_ADDR ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXUNICASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXMCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXBCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXUNDERFLOWERROR_ADDR ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXSINGLECOL_G_ADDR ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXMULTICOL_G_ADDR ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXDEFERRED register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXDEFERRED_ADDR ALT_EMAC_GMAC_TXDEFERRED_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXLATECOL register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXLATECOL_ADDR ALT_EMAC_GMAC_TXLATECOL_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXEXESSCOL_ADDR ALT_EMAC_GMAC_TXEXESSCOL_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXCARRIERERR_ADDR ALT_EMAC_GMAC_TXCARRIERERR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXOCTETCNT_ADDR ALT_EMAC_GMAC_TXOCTETCNT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXFRMCOUNT_G_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXEXCESSDEF_ADDR ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXPAUSEFRMS_ADDR ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXVLANFRMS_G_ADDR ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TXOVERSIZE_G_ADDR ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXOCTETCOUNT_G_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXCRCERROR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXCRCERROR_ADDR ALT_EMAC_GMAC_RXCRCERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXALIGNMENTERROR_ADDR ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXRUNTERROR_ADDR ALT_EMAC_GMAC_RXRUNTERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXJABBERERROR_ADDR ALT_EMAC_GMAC_RXJABBERERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXUNDERSIZE_G_ADDR ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXOVERSIZE_G_ADDR ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RX64OCTETS_GB_ADDR ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXUNICASTFRMS_G_ADDR ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXLENERROR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXLENERROR_ADDR ALT_EMAC_GMAC_RXLENERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXOUTOFRANGETYPE_ADDR ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXPAUSEFRMS_ADDR ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXFIFOOVF_ADDR ALT_EMAC_GMAC_RXFIFOOVF_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXVLANFRMS_GB_ADDR ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXWDERROR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXWDERROR_ADDR ALT_EMAC_GMAC_RXWDERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXRCVERROR register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXRCVERROR_ADDR ALT_EMAC_GMAC_RXRCVERROR_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXCTLFRMS_G_ADDR ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MMC_IPC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MMC_IPC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_FRAG_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_UDSBL_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV6_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV6_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV6_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXUDP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXUDP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXTCP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXTCP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXICMP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXICMP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_FRAG_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV4_UDSBL_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV6_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV6_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXIPV6_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXUDP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXUDP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXTCP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXTCPERROCTETS_ADDR ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXICMP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_RXICMP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_L3_L4_CTL0_ADDR ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR4_ADDR0_ADDR ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_L3_L4_CTL1_ADDR ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR4_ADDR1_ADDR ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_L3_L4_CTL2_ADDR ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR4_ADDR2_ADDR ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_L3_L4_CTL3_ADDR ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR4_ADDR3_ADDR ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR0_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR1_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR2_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_LYR3_ADDR3_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_HASH_TABLE_REG0_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_HASH_TABLE_REG1_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_HASH_TABLE_REG2_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_HASH_TABLE_REG3_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_HASH_TABLE_REG4_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_HASH_TABLE_REG5_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_HASH_TABLE_REG6_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_HASH_TABLE_REG7_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_VLAN_INCL_REG_ADDR ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_VLAN_HASH_TABLE_REG_ADDR ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TS_CTL register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TS_CTL_ADDR ALT_EMAC_GMAC_TS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_SUB_SEC_INCREMENT_ADDR ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_SYS_TIME_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_SYS_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_SYS_TIME_SECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TS_ADDEND register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TS_ADDEND_ADDR ALT_EMAC_GMAC_TS_ADDEND_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TGT_TIME_SECS_ADDR ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TGT_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TS_STAT register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_TS_STAT_ADDR ALT_EMAC_GMAC_TS_STAT_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_PPS_CTL register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_PPS_CTL_ADDR ALT_EMAC_GMAC_PPS_CTL_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_AUX_TS_NANOSECS_ADDR ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_AUX_TS_SECS_ADDR ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_PPS0_INTERVAL_ADDR ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_PPS0_WIDTH_ADDR ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR16_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR16_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR17_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR17_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR18_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR18_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR19_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR19_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR20_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR20_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR21_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR21_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR22_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR22_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR23_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR23_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR24_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR24_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR25_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR25_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR26_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR26_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR27_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR27_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR28_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR28_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR29_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR29_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR30_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR30_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR31_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR31_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR32_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR32_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR33_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR33_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR34_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR34_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR35_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR35_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR36_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR36_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR37_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR37_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR38_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR38_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR39_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR39_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR40_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR40_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR41_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR41_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR42_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR42_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR43_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR43_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR44_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR44_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR45_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR45_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR46_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR46_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR47_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR47_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR48_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR48_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR49_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR49_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR50_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR50_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR51_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR51_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR52_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR52_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR53_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR53_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR54_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR54_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR55_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR55_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR56_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR56_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR57_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR57_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR58_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR58_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR59_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR59_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR60_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR60_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR61_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR61_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR62_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR62_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR63_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR63_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR64_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR64_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR65_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR65_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR66_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR66_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR67_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR67_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR68_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR68_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR69_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR69_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR70_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR70_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR71_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR71_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR72_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR72_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR73_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR73_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR74_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR74_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR75_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR75_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR76_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR76_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR77_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR77_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR78_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR78_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR79_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR79_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR80_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR80_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR81_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR81_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR82_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR82_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR83_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR83_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR84_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR84_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR85_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR85_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR86_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR86_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR87_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR87_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR88_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR88_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR89_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR89_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR90_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR90_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR91_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR91_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR92_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR92_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR93_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR93_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR94_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR94_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR95_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR95_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR96_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR96_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR97_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR97_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR98_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR98_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR99_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR99_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR100_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR100_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR101_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR101_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR102_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR102_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR103_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR103_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR104_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR104_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR105_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR105_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR106_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR106_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR107_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR107_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR108_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR108_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR109_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR109_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR110_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR110_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR111_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR111_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR112_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR112_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR113_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR113_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR114_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR114_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR115_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR115_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR116_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR116_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR117_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR117_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR118_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR118_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR119_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR119_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR120_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR120_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR121_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR121_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR122_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR122_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR123_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR123_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR124_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR124_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR125_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR125_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR126_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR126_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR127_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register for the ALT_EMAC0_GMACGRP instance. */ -#define ALT_EMAC0_GMAC_MAC_ADDR127_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(ALT_EMAC0_GMACGRP_ADDR) -/* The base address byte offset for the start of the ALT_EMAC0_GMACGRP component. */ -#define ALT_EMAC0_GMACGRP_OFST 0x0 -/* The start address of the ALT_EMAC0_GMACGRP component. */ -#define ALT_EMAC0_GMACGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC0_ADDR) + ALT_EMAC0_GMACGRP_OFST)) -/* The lower bound address range of the ALT_EMAC0_GMACGRP component. */ -#define ALT_EMAC0_GMACGRP_LB_ADDR ALT_EMAC0_GMACGRP_ADDR -/* The upper bound address range of the ALT_EMAC0_GMACGRP component. */ -#define ALT_EMAC0_GMACGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_GMACGRP_ADDR) + 0xb80) - 1)) - - -/* - * Register Group Instance : dmagrp - * - * Instance dmagrp of register group ALT_EMAC_DMA. - * - * - */ -/* The address of the ALT_EMAC_DMA_BUS_MOD register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_BUS_MOD_ADDR ALT_EMAC_DMA_BUS_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_TX_POLL_DEMAND_ADDR ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_RX_POLL_DEMAND_ADDR ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_RX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_TX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_STAT register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_STAT_ADDR ALT_EMAC_DMA_STAT_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_OP_MOD register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_OP_MOD_ADDR ALT_EMAC_DMA_OP_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_INT_EN register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_INT_EN_ADDR ALT_EMAC_DMA_INT_EN_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_MISSED_FRM_AND_BUF_OVF_CNTR_ADDR ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_RX_INT_WDT register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_RX_INT_WDT_ADDR ALT_EMAC_DMA_RX_INT_WDT_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_AXI_BUS_MOD_ADDR ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_AHB_OR_AXI_STAT_ADDR ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_CUR_HOST_TX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_CUR_HOST_RX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_CUR_HOST_TX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_CUR_HOST_RX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_HW_FEATURE register for the ALT_EMAC0_DMAGRP instance. */ -#define ALT_EMAC0_DMA_HW_FEATURE_ADDR ALT_EMAC_DMA_HW_FEATURE_ADDR(ALT_EMAC0_DMAGRP_ADDR) -/* The base address byte offset for the start of the ALT_EMAC0_DMAGRP component. */ -#define ALT_EMAC0_DMAGRP_OFST 0x1000 -/* The start address of the ALT_EMAC0_DMAGRP component. */ -#define ALT_EMAC0_DMAGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC0_ADDR) + ALT_EMAC0_DMAGRP_OFST)) -/* The lower bound address range of the ALT_EMAC0_DMAGRP component. */ -#define ALT_EMAC0_DMAGRP_LB_ADDR ALT_EMAC0_DMAGRP_ADDR -/* The upper bound address range of the ALT_EMAC0_DMAGRP component. */ -#define ALT_EMAC0_DMAGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_DMAGRP_ADDR) + 0x5c) - 1)) - - -/* The base address byte offset for the start of the ALT_EMAC0 component. */ -#define ALT_EMAC0_OFST 0xff700000 -/* The start address of the ALT_EMAC0 component. */ -#define ALT_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_EMAC0_OFST)) -/* The lower bound address range of the ALT_EMAC0 component. */ -#define ALT_EMAC0_LB_ADDR ALT_EMAC0_ADDR -/* The upper bound address range of the ALT_EMAC0 component. */ -#define ALT_EMAC0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC0_ADDR) + 0x2000) - 1)) - - -/* - * Component Instance : emac1 - * - * Instance emac1 of component ALT_EMAC. - * - * - */ -/* - * Register Group Instance : gmacgrp - * - * Instance gmacgrp of register group ALT_EMAC_GMAC. - * - * - */ -/* The address of the ALT_EMAC_GMAC_MAC_CFG register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_CFG_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_FRM_FLT_ADDR ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_GMII_ADDR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_GMII_ADDR_ADDR ALT_EMAC_GMAC_GMII_ADDR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_GMII_DATA register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_GMII_DATA_ADDR ALT_EMAC_GMAC_GMII_DATA_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_FLOW_CTL register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_FLOW_CTL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_VLAN_TAG register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_VLAN_TAG_ADDR ALT_EMAC_GMAC_VLAN_TAG_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_VER register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_VER_ADDR ALT_EMAC_GMAC_VER_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_DBG register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_DBG_ADDR ALT_EMAC_GMAC_DBG_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LPI_CTL_STAT_ADDR ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LPI_TMRS_CTL_ADDR ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_INT_STAT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_INT_STAT_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_INT_MSK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR1_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR1_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR2_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR2_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR3_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR3_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR4_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR4_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR5_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR5_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR6_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR6_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR7_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR7_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR8_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR8_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR9_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR9_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR10_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR10_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR11_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR11_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR12_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR12_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR13_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR13_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR14_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR14_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR15_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR15_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_SGMII_RGMII_SMII_CTL_STAT_ADDR ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_CTL register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MMC_CTL_ADDR ALT_EMAC_GMAC_MMC_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MMC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_RX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MMC_TX_INT_ADDR ALT_EMAC_GMAC_MMC_TX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MMC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MMC_TX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TX64OCTETS_GB_ADDR ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXUNICASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXMCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXBCASTFRMS_GB_ADDR ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXUNDERFLOWERROR_ADDR ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXSINGLECOL_G_ADDR ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXMULTICOL_G_ADDR ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXDEFERRED register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXDEFERRED_ADDR ALT_EMAC_GMAC_TXDEFERRED_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXLATECOL register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXLATECOL_ADDR ALT_EMAC_GMAC_TXLATECOL_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXEXESSCOL_ADDR ALT_EMAC_GMAC_TXEXESSCOL_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXCARRIERERR_ADDR ALT_EMAC_GMAC_TXCARRIERERR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXOCTETCNT_ADDR ALT_EMAC_GMAC_TXOCTETCNT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXFRMCOUNT_G_ADDR ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXEXCESSDEF_ADDR ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXPAUSEFRMS_ADDR ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXVLANFRMS_G_ADDR ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TXOVERSIZE_G_ADDR ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXFRMCOUNT_GB_ADDR ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXOCTETCOUNT_GB_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXOCTETCOUNT_G_ADDR ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXBCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXMCASTFRMS_G_ADDR ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXCRCERROR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXCRCERROR_ADDR ALT_EMAC_GMAC_RXCRCERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXALIGNMENTERROR_ADDR ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXRUNTERROR_ADDR ALT_EMAC_GMAC_RXRUNTERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXJABBERERROR_ADDR ALT_EMAC_GMAC_RXJABBERERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXUNDERSIZE_G_ADDR ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXOVERSIZE_G_ADDR ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RX64OCTETS_GB_ADDR ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RX65TO127OCTETS_GB_ADDR ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RX128TO255OCTETS_GB_ADDR ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RX256TO511OCTETS_GB_ADDR ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RX512TO1023OCTETS_GB_ADDR ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RX1024TOMAXOCTETS_GB_ADDR ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXUNICASTFRMS_G_ADDR ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXLENERROR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXLENERROR_ADDR ALT_EMAC_GMAC_RXLENERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXOUTOFRANGETYPE_ADDR ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXPAUSEFRMS_ADDR ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXFIFOOVF_ADDR ALT_EMAC_GMAC_RXFIFOOVF_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXVLANFRMS_GB_ADDR ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXWDERROR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXWDERROR_ADDR ALT_EMAC_GMAC_RXWDERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXRCVERROR register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXRCVERROR_ADDR ALT_EMAC_GMAC_RXRCVERROR_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXCTLFRMS_G_ADDR ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MMC_IPC_RX_INT_MSK_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MMC_IPC_RX_INT_ADDR ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_FRAG_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_UDSBL_FRMS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV6_GD_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV6_HDRERR_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV6_NOPAY_FRMS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXUDP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXUDP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXTCP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXTCP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXICMP_GD_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXICMP_ERR_FRMS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_FRAG_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV4_UDSBL_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV6_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV6_HDRERR_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXIPV6_NOPAY_OCTETS_ADDR ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXUDP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXUDP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXTCP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXTCPERROCTETS_ADDR ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXICMP_GD_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_RXICMP_ERR_OCTETS_ADDR ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_L3_L4_CTL0_ADDR ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR4_ADDR0_ADDR ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG0_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_L3_L4_CTL1_ADDR ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR4_ADDR1_ADDR ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG1_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_L3_L4_CTL2_ADDR ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR4_ADDR2_ADDR ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG2_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_L3_L4_CTL3_ADDR ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR4_ADDR3_ADDR ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR0_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR1_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR2_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_LYR3_ADDR3_REG3_ADDR ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_HASH_TABLE_REG0_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_HASH_TABLE_REG1_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_HASH_TABLE_REG2_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_HASH_TABLE_REG3_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_HASH_TABLE_REG4_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_HASH_TABLE_REG5_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_HASH_TABLE_REG6_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_HASH_TABLE_REG7_ADDR ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_VLAN_INCL_REG_ADDR ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_VLAN_HASH_TABLE_REG_ADDR ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TS_CTL register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TS_CTL_ADDR ALT_EMAC_GMAC_TS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_SUB_SEC_INCREMENT_ADDR ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_SYS_TIME_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_SYS_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_SYS_TIME_SECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TS_ADDEND register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TS_ADDEND_ADDR ALT_EMAC_GMAC_TS_ADDEND_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TGT_TIME_SECS_ADDR ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TGT_TIME_NANOSECS_ADDR ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_TS_STAT register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_TS_STAT_ADDR ALT_EMAC_GMAC_TS_STAT_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_PPS_CTL register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_PPS_CTL_ADDR ALT_EMAC_GMAC_PPS_CTL_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_AUX_TS_NANOSECS_ADDR ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_AUX_TS_SECS_ADDR ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_PPS0_INTERVAL_ADDR ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_PPS0_WIDTH_ADDR ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR16_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR16_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR17_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR17_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR18_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR18_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR19_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR19_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR20_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR20_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR21_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR21_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR22_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR22_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR23_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR23_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR24_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR24_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR25_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR25_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR26_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR26_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR27_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR27_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR28_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR28_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR29_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR29_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR30_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR30_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR31_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR31_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR32_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR32_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR33_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR33_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR34_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR34_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR35_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR35_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR36_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR36_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR37_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR37_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR38_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR38_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR39_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR39_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR40_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR40_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR41_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR41_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR42_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR42_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR43_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR43_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR44_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR44_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR45_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR45_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR46_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR46_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR47_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR47_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR48_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR48_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR49_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR49_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR50_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR50_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR51_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR51_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR52_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR52_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR53_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR53_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR54_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR54_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR55_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR55_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR56_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR56_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR57_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR57_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR58_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR58_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR59_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR59_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR60_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR60_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR61_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR61_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR62_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR62_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR63_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR63_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR64_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR64_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR65_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR65_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR66_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR66_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR67_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR67_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR68_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR68_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR69_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR69_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR70_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR70_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR71_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR71_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR72_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR72_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR73_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR73_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR74_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR74_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR75_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR75_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR76_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR76_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR77_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR77_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR78_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR78_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR79_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR79_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR80_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR80_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR81_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR81_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR82_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR82_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR83_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR83_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR84_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR84_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR85_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR85_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR86_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR86_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR87_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR87_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR88_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR88_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR89_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR89_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR90_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR90_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR91_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR91_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR92_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR92_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR93_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR93_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR94_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR94_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR95_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR95_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR96_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR96_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR97_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR97_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR98_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR98_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR99_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR99_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR100_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR100_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR101_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR101_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR102_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR102_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR103_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR103_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR104_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR104_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR105_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR105_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR106_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR106_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR107_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR107_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR108_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR108_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR109_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR109_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR110_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR110_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR111_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR111_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR112_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR112_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR113_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR113_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR114_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR114_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR115_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR115_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR116_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR116_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR117_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR117_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR118_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR118_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR119_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR119_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR120_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR120_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR121_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR121_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR122_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR122_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR123_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR123_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR124_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR124_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR125_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR125_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR126_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR126_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR127_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register for the ALT_EMAC1_GMACGRP instance. */ -#define ALT_EMAC1_GMAC_MAC_ADDR127_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(ALT_EMAC1_GMACGRP_ADDR) -/* The base address byte offset for the start of the ALT_EMAC1_GMACGRP component. */ -#define ALT_EMAC1_GMACGRP_OFST 0x0 -/* The start address of the ALT_EMAC1_GMACGRP component. */ -#define ALT_EMAC1_GMACGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC1_ADDR) + ALT_EMAC1_GMACGRP_OFST)) -/* The lower bound address range of the ALT_EMAC1_GMACGRP component. */ -#define ALT_EMAC1_GMACGRP_LB_ADDR ALT_EMAC1_GMACGRP_ADDR -/* The upper bound address range of the ALT_EMAC1_GMACGRP component. */ -#define ALT_EMAC1_GMACGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_GMACGRP_ADDR) + 0xb80) - 1)) - - -/* - * Register Group Instance : dmagrp - * - * Instance dmagrp of register group ALT_EMAC_DMA. - * - * - */ -/* The address of the ALT_EMAC_DMA_BUS_MOD register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_BUS_MOD_ADDR ALT_EMAC_DMA_BUS_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_TX_POLL_DEMAND_ADDR ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_RX_POLL_DEMAND_ADDR ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_RX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_TX_DESC_LIST_ADDR_ADDR ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_STAT register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_STAT_ADDR ALT_EMAC_DMA_STAT_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_OP_MOD register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_OP_MOD_ADDR ALT_EMAC_DMA_OP_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_INT_EN register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_INT_EN_ADDR ALT_EMAC_DMA_INT_EN_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_MISSED_FRM_AND_BUF_OVF_CNTR_ADDR ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_RX_INT_WDT register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_RX_INT_WDT_ADDR ALT_EMAC_DMA_RX_INT_WDT_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_AXI_BUS_MOD_ADDR ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_AHB_OR_AXI_STAT_ADDR ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_CUR_HOST_TX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_CUR_HOST_RX_DESC_ADDR ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_CUR_HOST_TX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_CUR_HOST_RX_BUF_ADDR_ADDR ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The address of the ALT_EMAC_DMA_HW_FEATURE register for the ALT_EMAC1_DMAGRP instance. */ -#define ALT_EMAC1_DMA_HW_FEATURE_ADDR ALT_EMAC_DMA_HW_FEATURE_ADDR(ALT_EMAC1_DMAGRP_ADDR) -/* The base address byte offset for the start of the ALT_EMAC1_DMAGRP component. */ -#define ALT_EMAC1_DMAGRP_OFST 0x1000 -/* The start address of the ALT_EMAC1_DMAGRP component. */ -#define ALT_EMAC1_DMAGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_EMAC1_ADDR) + ALT_EMAC1_DMAGRP_OFST)) -/* The lower bound address range of the ALT_EMAC1_DMAGRP component. */ -#define ALT_EMAC1_DMAGRP_LB_ADDR ALT_EMAC1_DMAGRP_ADDR -/* The upper bound address range of the ALT_EMAC1_DMAGRP component. */ -#define ALT_EMAC1_DMAGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_DMAGRP_ADDR) + 0x5c) - 1)) - - -/* The base address byte offset for the start of the ALT_EMAC1 component. */ -#define ALT_EMAC1_OFST 0xff702000 -/* The start address of the ALT_EMAC1 component. */ -#define ALT_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_EMAC1_OFST)) -/* The lower bound address range of the ALT_EMAC1 component. */ -#define ALT_EMAC1_LB_ADDR ALT_EMAC1_ADDR -/* The upper bound address range of the ALT_EMAC1 component. */ -#define ALT_EMAC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_EMAC1_ADDR) + 0x2000) - 1)) - - -/* - * Component Instance : sdmmc - * - * Instance sdmmc of component ALT_SDMMC. - * - * - */ -/* The address of the ALT_SDMMC_CTL register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CTL_OFST)) -/* The address of the ALT_SDMMC_PWREN register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_PWREN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_PWREN_OFST)) -/* The address of the ALT_SDMMC_CLKDIV register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_CLKDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKDIV_OFST)) -/* The address of the ALT_SDMMC_CLKSRC register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_CLKSRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKSRC_OFST)) -/* The address of the ALT_SDMMC_CLKENA register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_CLKENA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CLKENA_OFST)) -/* The address of the ALT_SDMMC_TMOUT register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_TMOUT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TMOUT_OFST)) -/* The address of the ALT_SDMMC_CTYPE register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_CTYPE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CTYPE_OFST)) -/* The address of the ALT_SDMMC_BLKSIZ register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_BLKSIZ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BLKSIZ_OFST)) -/* The address of the ALT_SDMMC_BYTCNT register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_BYTCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BYTCNT_OFST)) -/* The address of the ALT_SDMMC_INTMSK register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_INTMSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_INTMSK_OFST)) -/* The address of the ALT_SDMMC_CMDARG register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_CMDARG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CMDARG_OFST)) -/* The address of the ALT_SDMMC_CMD register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_CMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CMD_OFST)) -/* The address of the ALT_SDMMC_RESP0 register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_RESP0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP0_OFST)) -/* The address of the ALT_SDMMC_RESP1 register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_RESP1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP1_OFST)) -/* The address of the ALT_SDMMC_RESP2 register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_RESP2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP2_OFST)) -/* The address of the ALT_SDMMC_RESP3 register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_RESP3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RESP3_OFST)) -/* The address of the ALT_SDMMC_MINTSTS register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_MINTSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_MINTSTS_OFST)) -/* The address of the ALT_SDMMC_RINTSTS register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_RINTSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RINTSTS_OFST)) -/* The address of the ALT_SDMMC_STAT register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_STAT_OFST)) -/* The address of the ALT_SDMMC_FIFOTH register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_FIFOTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_FIFOTH_OFST)) -/* The address of the ALT_SDMMC_CDETECT register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_CDETECT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CDETECT_OFST)) -/* The address of the ALT_SDMMC_WRTPRT register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_WRTPRT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_WRTPRT_OFST)) -/* The address of the ALT_SDMMC_TCBCNT register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_TCBCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TCBCNT_OFST)) -/* The address of the ALT_SDMMC_TBBCNT register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_TBBCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_TBBCNT_OFST)) -/* The address of the ALT_SDMMC_DEBNCE register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_DEBNCE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DEBNCE_OFST)) -/* The address of the ALT_SDMMC_USRID register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_USRID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_USRID_OFST)) -/* The address of the ALT_SDMMC_VERID register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_VERID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_VERID_OFST)) -/* The address of the ALT_SDMMC_HCON register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_HCON_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_HCON_OFST)) -/* The address of the ALT_SDMMC_UHS_REG register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_UHS_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_UHS_REG_OFST)) -/* The address of the ALT_SDMMC_RST_N register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_RST_N_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_RST_N_OFST)) -/* The address of the ALT_SDMMC_BMOD register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_BMOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BMOD_OFST)) -/* The address of the ALT_SDMMC_PLDMND register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_PLDMND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_PLDMND_OFST)) -/* The address of the ALT_SDMMC_DBADDR register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_DBADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DBADDR_OFST)) -/* The address of the ALT_SDMMC_IDSTS register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_IDSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_IDSTS_OFST)) -/* The address of the ALT_SDMMC_IDINTEN register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_IDINTEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_IDINTEN_OFST)) -/* The address of the ALT_SDMMC_DSCADDR register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_DSCADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DSCADDR_OFST)) -/* The address of the ALT_SDMMC_BUFADDR register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_BUFADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BUFADDR_OFST)) -/* The address of the ALT_SDMMC_CARDTHRCTL register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_CARDTHRCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_CARDTHRCTL_OFST)) -/* The address of the ALT_SDMMC_BACK_END_POWER_R register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_BACK_END_POWER_R_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_BACK_END_POWER_R_OFST)) -/* The address of the ALT_SDMMC_DATA register for the ALT_SDMMC instance. */ -#define ALT_SDMMC_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDMMC_ADDR) + ALT_SDMMC_DATA_OFST)) -/* The base address byte offset for the start of the ALT_SDMMC component. */ -#define ALT_SDMMC_OFST 0xff704000 -/* The start address of the ALT_SDMMC component. */ -#define ALT_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SDMMC_OFST)) -/* The lower bound address range of the ALT_SDMMC component. */ -#define ALT_SDMMC_LB_ADDR ALT_SDMMC_ADDR -/* The upper bound address range of the ALT_SDMMC component. */ -#define ALT_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDMMC_ADDR) + 0x400) - 1)) - - -/* - * Component Instance : qspiregs - * - * Instance qspiregs of component ALT_QSPI. - * - * - */ -/* The address of the ALT_QSPI_CFG register for the ALT_QSPI instance. */ -#define ALT_QSPI_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_CFG_OFST)) -/* The address of the ALT_QSPI_DEVRD register for the ALT_QSPI instance. */ -#define ALT_QSPI_DEVRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVRD_OFST)) -/* The address of the ALT_QSPI_DEVWR register for the ALT_QSPI instance. */ -#define ALT_QSPI_DEVWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVWR_OFST)) -/* The address of the ALT_QSPI_DELAY register for the ALT_QSPI instance. */ -#define ALT_QSPI_DELAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DELAY_OFST)) -/* The address of the ALT_QSPI_RDDATACAP register for the ALT_QSPI instance. */ -#define ALT_QSPI_RDDATACAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_RDDATACAP_OFST)) -/* The address of the ALT_QSPI_DEVSZ register for the ALT_QSPI instance. */ -#define ALT_QSPI_DEVSZ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DEVSZ_OFST)) -/* The address of the ALT_QSPI_SRAMPART register for the ALT_QSPI instance. */ -#define ALT_QSPI_SRAMPART_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_SRAMPART_OFST)) -/* The address of the ALT_QSPI_INDADDRTRIG register for the ALT_QSPI instance. */ -#define ALT_QSPI_INDADDRTRIG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDADDRTRIG_OFST)) -/* The address of the ALT_QSPI_DMAPER register for the ALT_QSPI instance. */ -#define ALT_QSPI_DMAPER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_DMAPER_OFST)) -/* The address of the ALT_QSPI_REMAPADDR register for the ALT_QSPI instance. */ -#define ALT_QSPI_REMAPADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_REMAPADDR_OFST)) -/* The address of the ALT_QSPI_MODBIT register for the ALT_QSPI instance. */ -#define ALT_QSPI_MODBIT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_MODBIT_OFST)) -/* The address of the ALT_QSPI_SRAMFILL register for the ALT_QSPI instance. */ -#define ALT_QSPI_SRAMFILL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_SRAMFILL_OFST)) -/* The address of the ALT_QSPI_TXTHRESH register for the ALT_QSPI instance. */ -#define ALT_QSPI_TXTHRESH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_TXTHRESH_OFST)) -/* The address of the ALT_QSPI_RXTHRESH register for the ALT_QSPI instance. */ -#define ALT_QSPI_RXTHRESH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_RXTHRESH_OFST)) -/* The address of the ALT_QSPI_IRQSTAT register for the ALT_QSPI instance. */ -#define ALT_QSPI_IRQSTAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_IRQSTAT_OFST)) -/* The address of the ALT_QSPI_IRQMSK register for the ALT_QSPI instance. */ -#define ALT_QSPI_IRQMSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_IRQMSK_OFST)) -/* The address of the ALT_QSPI_LOWWRPROT register for the ALT_QSPI instance. */ -#define ALT_QSPI_LOWWRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_LOWWRPROT_OFST)) -/* The address of the ALT_QSPI_UPPWRPROT register for the ALT_QSPI instance. */ -#define ALT_QSPI_UPPWRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_UPPWRPROT_OFST)) -/* The address of the ALT_QSPI_WRPROT register for the ALT_QSPI instance. */ -#define ALT_QSPI_WRPROT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_WRPROT_OFST)) -/* The address of the ALT_QSPI_INDRD register for the ALT_QSPI instance. */ -#define ALT_QSPI_INDRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRD_OFST)) -/* The address of the ALT_QSPI_INDRDWATER register for the ALT_QSPI instance. */ -#define ALT_QSPI_INDRDWATER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDWATER_OFST)) -/* The address of the ALT_QSPI_INDRDSTADDR register for the ALT_QSPI instance. */ -#define ALT_QSPI_INDRDSTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDSTADDR_OFST)) -/* The address of the ALT_QSPI_INDRDCNT register for the ALT_QSPI instance. */ -#define ALT_QSPI_INDRDCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDRDCNT_OFST)) -/* The address of the ALT_QSPI_INDWR register for the ALT_QSPI instance. */ -#define ALT_QSPI_INDWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWR_OFST)) -/* The address of the ALT_QSPI_INDWRWATER register for the ALT_QSPI instance. */ -#define ALT_QSPI_INDWRWATER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRWATER_OFST)) -/* The address of the ALT_QSPI_INDWRSTADDR register for the ALT_QSPI instance. */ -#define ALT_QSPI_INDWRSTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRSTADDR_OFST)) -/* The address of the ALT_QSPI_INDWRCNT register for the ALT_QSPI instance. */ -#define ALT_QSPI_INDWRCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_INDWRCNT_OFST)) -/* The address of the ALT_QSPI_FLSHCMD register for the ALT_QSPI instance. */ -#define ALT_QSPI_FLSHCMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMD_OFST)) -/* The address of the ALT_QSPI_FLSHCMDADDR register for the ALT_QSPI instance. */ -#define ALT_QSPI_FLSHCMDADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDADDR_OFST)) -/* The address of the ALT_QSPI_FLSHCMDRDDATALO register for the ALT_QSPI instance. */ -#define ALT_QSPI_FLSHCMDRDDATALO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDRDDATALO_OFST)) -/* The address of the ALT_QSPI_FLSHCMDRDDATAUP register for the ALT_QSPI instance. */ -#define ALT_QSPI_FLSHCMDRDDATAUP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDRDDATAUP_OFST)) -/* The address of the ALT_QSPI_FLSHCMDWRDATALO register for the ALT_QSPI instance. */ -#define ALT_QSPI_FLSHCMDWRDATALO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDWRDATALO_OFST)) -/* The address of the ALT_QSPI_FLSHCMDWRDATAUP register for the ALT_QSPI instance. */ -#define ALT_QSPI_FLSHCMDWRDATAUP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_FLSHCMDWRDATAUP_OFST)) -/* The address of the ALT_QSPI_MODULEID register for the ALT_QSPI instance. */ -#define ALT_QSPI_MODULEID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_QSPI_ADDR) + ALT_QSPI_MODULEID_OFST)) -/* The base address byte offset for the start of the ALT_QSPI component. */ -#define ALT_QSPI_OFST 0xff705000 -/* The start address of the ALT_QSPI component. */ -#define ALT_QSPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_QSPI_OFST)) -/* The lower bound address range of the ALT_QSPI component. */ -#define ALT_QSPI_LB_ADDR ALT_QSPI_ADDR -/* The upper bound address range of the ALT_QSPI component. */ -#define ALT_QSPI_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_QSPI_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : fpgamgrregs - * - * Instance fpgamgrregs of component ALT_FPGAMGR. - * - * - */ -/* The address of the ALT_FPGAMGR_STAT register for the ALT_FPGAMGR instance. */ -#define ALT_FPGAMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_STAT_OFST)) -/* The address of the ALT_FPGAMGR_CTL register for the ALT_FPGAMGR instance. */ -#define ALT_FPGAMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_CTL_OFST)) -/* The address of the ALT_FPGAMGR_DCLKCNT register for the ALT_FPGAMGR instance. */ -#define ALT_FPGAMGR_DCLKCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_DCLKCNT_OFST)) -/* The address of the ALT_FPGAMGR_DCLKSTAT register for the ALT_FPGAMGR instance. */ -#define ALT_FPGAMGR_DCLKSTAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_DCLKSTAT_OFST)) -/* The address of the ALT_FPGAMGR_GPO register for the ALT_FPGAMGR instance. */ -#define ALT_FPGAMGR_GPO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_GPO_OFST)) -/* The address of the ALT_FPGAMGR_GPI register for the ALT_FPGAMGR instance. */ -#define ALT_FPGAMGR_GPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_GPI_OFST)) -/* The address of the ALT_FPGAMGR_MISCI register for the ALT_FPGAMGR instance. */ -#define ALT_FPGAMGR_MISCI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_MISCI_OFST)) -/* - * Register Group Instance : mon - * - * Instance mon of register group ALT_MON. - * - * - */ -/* The address of the ALT_MON_GPIO_INTEN register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_INTEN_ADDR ALT_MON_GPIO_INTEN_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_INTMSK register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_INTMSK_ADDR ALT_MON_GPIO_INTMSK_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_INTTYPE_LEVEL register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_INTTYPE_LEVEL_ADDR ALT_MON_GPIO_INTTYPE_LEVEL_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_INT_POL register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_INT_POL_ADDR ALT_MON_GPIO_INT_POL_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_INTSTAT register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_INTSTAT_ADDR ALT_MON_GPIO_INTSTAT_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_RAW_INTSTAT register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_RAW_INTSTAT_ADDR ALT_MON_GPIO_RAW_INTSTAT_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_PORTA_EOI register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_PORTA_EOI_ADDR ALT_MON_GPIO_PORTA_EOI_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_EXT_PORTA register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_EXT_PORTA_ADDR ALT_MON_GPIO_EXT_PORTA_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_LS_SYNC register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_LS_SYNC_ADDR ALT_MON_GPIO_LS_SYNC_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_VER_ID_CODE register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_VER_ID_CODE_ADDR ALT_MON_GPIO_VER_ID_CODE_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_CFG_REG2 register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_CFG_REG2_ADDR ALT_MON_GPIO_CFG_REG2_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The address of the ALT_MON_GPIO_CFG_REG1 register for the ALT_FPGAMGR_MON instance. */ -#define ALT_FPGAMGR_MON_GPIO_CFG_REG1_ADDR ALT_MON_GPIO_CFG_REG1_ADDR(ALT_FPGAMGR_MON_ADDR) -/* The base address byte offset for the start of the ALT_FPGAMGR_MON component. */ -#define ALT_FPGAMGR_MON_OFST 0x800 -/* The start address of the ALT_FPGAMGR_MON component. */ -#define ALT_FPGAMGR_MON_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGR_ADDR) + ALT_FPGAMGR_MON_OFST)) -/* The lower bound address range of the ALT_FPGAMGR_MON component. */ -#define ALT_FPGAMGR_MON_LB_ADDR ALT_FPGAMGR_MON_ADDR -/* The upper bound address range of the ALT_FPGAMGR_MON component. */ -#define ALT_FPGAMGR_MON_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGR_MON_ADDR) + 0x80) - 1)) - - -/* The base address byte offset for the start of the ALT_FPGAMGR component. */ -#define ALT_FPGAMGR_OFST 0xff706000 -/* The start address of the ALT_FPGAMGR component. */ -#define ALT_FPGAMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_FPGAMGR_OFST)) -/* The lower bound address range of the ALT_FPGAMGR component. */ -#define ALT_FPGAMGR_LB_ADDR ALT_FPGAMGR_ADDR -/* The upper bound address range of the ALT_FPGAMGR component. */ -#define ALT_FPGAMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGR_ADDR) + 0x1000) - 1)) - - -/* - * Component Instance : acpidmap - * - * Instance acpidmap of component ALT_ACPIDMAP. - * - * - */ -/* The address of the ALT_ACPIDMAP_VID2RD register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID2RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2RD_OFST)) -/* The address of the ALT_ACPIDMAP_VID2WR register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID2WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2WR_OFST)) -/* The address of the ALT_ACPIDMAP_VID3RD register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID3RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3RD_OFST)) -/* The address of the ALT_ACPIDMAP_VID3WR register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID3WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3WR_OFST)) -/* The address of the ALT_ACPIDMAP_VID4RD register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID4RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4RD_OFST)) -/* The address of the ALT_ACPIDMAP_VID4WR register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID4WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4WR_OFST)) -/* The address of the ALT_ACPIDMAP_VID5RD register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID5RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5RD_OFST)) -/* The address of the ALT_ACPIDMAP_VID5WR register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID5WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5WR_OFST)) -/* The address of the ALT_ACPIDMAP_VID6RD register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID6RD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6RD_OFST)) -/* The address of the ALT_ACPIDMAP_VID6WR register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID6WR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6WR_OFST)) -/* The address of the ALT_ACPIDMAP_DYNRD register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_DYNRD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNRD_OFST)) -/* The address of the ALT_ACPIDMAP_DYNWR register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_DYNWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNWR_OFST)) -/* The address of the ALT_ACPIDMAP_VID2RD_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID2RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2RD_S_OFST)) -/* The address of the ALT_ACPIDMAP_VID2WR_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID2WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID2WR_S_OFST)) -/* The address of the ALT_ACPIDMAP_VID3RD_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID3RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3RD_S_OFST)) -/* The address of the ALT_ACPIDMAP_VID3WR_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID3WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID3WR_S_OFST)) -/* The address of the ALT_ACPIDMAP_VID4RD_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID4RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4RD_S_OFST)) -/* The address of the ALT_ACPIDMAP_VID4WR_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID4WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID4WR_S_OFST)) -/* The address of the ALT_ACPIDMAP_VID5RD_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID5RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5RD_S_OFST)) -/* The address of the ALT_ACPIDMAP_VID5WR_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID5WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID5WR_S_OFST)) -/* The address of the ALT_ACPIDMAP_VID6RD_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID6RD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6RD_S_OFST)) -/* The address of the ALT_ACPIDMAP_VID6WR_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_VID6WR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_VID6WR_S_OFST)) -/* The address of the ALT_ACPIDMAP_DYNRD_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_DYNRD_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNRD_S_OFST)) -/* The address of the ALT_ACPIDMAP_DYNWR_S register for the ALT_ACPIDMAP instance. */ -#define ALT_ACPIDMAP_DYNWR_S_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + ALT_ACPIDMAP_DYNWR_S_OFST)) -/* The base address byte offset for the start of the ALT_ACPIDMAP component. */ -#define ALT_ACPIDMAP_OFST 0xff707000 -/* The start address of the ALT_ACPIDMAP component. */ -#define ALT_ACPIDMAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_ACPIDMAP_OFST)) -/* The lower bound address range of the ALT_ACPIDMAP component. */ -#define ALT_ACPIDMAP_LB_ADDR ALT_ACPIDMAP_ADDR -/* The upper bound address range of the ALT_ACPIDMAP component. */ -#define ALT_ACPIDMAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_ACPIDMAP_ADDR) + 0x1000) - 1)) - - -/* - * Component Instance : gpio0 - * - * Instance gpio0 of component ALT_GPIO. - * - * - */ -/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO0_ADDR) -/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO0 instance. */ -#define ALT_GPIO0_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO0_ADDR) -/* The base address byte offset for the start of the ALT_GPIO0 component. */ -#define ALT_GPIO0_OFST 0xff708000 -/* The start address of the ALT_GPIO0 component. */ -#define ALT_GPIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO0_OFST)) -/* The lower bound address range of the ALT_GPIO0 component. */ -#define ALT_GPIO0_LB_ADDR ALT_GPIO0_ADDR -/* The upper bound address range of the ALT_GPIO0 component. */ -#define ALT_GPIO0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO0_ADDR) + 0x80) - 1)) - - -/* - * Component Instance : gpio1 - * - * Instance gpio1 of component ALT_GPIO. - * - * - */ -/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO1_ADDR) -/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO1 instance. */ -#define ALT_GPIO1_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO1_ADDR) -/* The base address byte offset for the start of the ALT_GPIO1 component. */ -#define ALT_GPIO1_OFST 0xff709000 -/* The start address of the ALT_GPIO1 component. */ -#define ALT_GPIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO1_OFST)) -/* The lower bound address range of the ALT_GPIO1 component. */ -#define ALT_GPIO1_LB_ADDR ALT_GPIO1_ADDR -/* The upper bound address range of the ALT_GPIO1 component. */ -#define ALT_GPIO1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO1_ADDR) + 0x80) - 1)) - - -/* - * Component Instance : gpio2 - * - * Instance gpio2 of component ALT_GPIO. - * - * - */ -/* The address of the ALT_GPIO_SWPORTA_DR register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_SWPORTA_DR_ADDR ALT_GPIO_SWPORTA_DR_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_SWPORTA_DDR register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_SWPORTA_DDR_ADDR ALT_GPIO_SWPORTA_DDR_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_INTEN register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_INTEN_ADDR ALT_GPIO_INTEN_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_INTMSK register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_INTMSK_ADDR ALT_GPIO_INTMSK_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_INTTYPE_LEVEL register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_INTTYPE_LEVEL_ADDR ALT_GPIO_INTTYPE_LEVEL_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_INT_POL register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_INT_POL_ADDR ALT_GPIO_INT_POL_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_INTSTAT register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_INTSTAT_ADDR ALT_GPIO_INTSTAT_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_RAW_INTSTAT register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_RAW_INTSTAT_ADDR ALT_GPIO_RAW_INTSTAT_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_DEBOUNCE register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_DEBOUNCE_ADDR ALT_GPIO_DEBOUNCE_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_PORTA_EOI register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_PORTA_EOI_ADDR ALT_GPIO_PORTA_EOI_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_EXT_PORTA register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_EXT_PORTA_ADDR ALT_GPIO_EXT_PORTA_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_LS_SYNC register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_LS_SYNC_ADDR ALT_GPIO_LS_SYNC_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_ID_CODE register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_ID_CODE_ADDR ALT_GPIO_ID_CODE_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_VER_ID_CODE register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_VER_ID_CODE_ADDR ALT_GPIO_VER_ID_CODE_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_CFG_REG2 register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_CFG_REG2_ADDR ALT_GPIO_CFG_REG2_ADDR(ALT_GPIO2_ADDR) -/* The address of the ALT_GPIO_CFG_REG1 register for the ALT_GPIO2 instance. */ -#define ALT_GPIO2_CFG_REG1_ADDR ALT_GPIO_CFG_REG1_ADDR(ALT_GPIO2_ADDR) -/* The base address byte offset for the start of the ALT_GPIO2 component. */ -#define ALT_GPIO2_OFST 0xff70a000 -/* The start address of the ALT_GPIO2 component. */ -#define ALT_GPIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_GPIO2_OFST)) -/* The lower bound address range of the ALT_GPIO2 component. */ -#define ALT_GPIO2_LB_ADDR ALT_GPIO2_ADDR -/* The upper bound address range of the ALT_GPIO2 component. */ -#define ALT_GPIO2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_GPIO2_ADDR) + 0x80) - 1)) - - -/* - * Component Instance : l3regs - * - * Instance l3regs of component ALT_L3. - * - * - */ -/* The address of the ALT_L3_REMAP register for the ALT_L3 instance. */ -#define ALT_L3_REMAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_REMAP_OFST)) -/* - * Register Group Instance : secgrp - * - * Instance secgrp of register group ALT_L3_SECGRP. - * - * - */ -/* The address of the ALT_L3_SEC_L4MAIN register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_L4MAIN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4MAIN_OFST)) -/* The address of the ALT_L3_SEC_L4SP register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_L4SP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4SP_OFST)) -/* The address of the ALT_L3_SEC_L4MP register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_L4MP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4MP_OFST)) -/* The address of the ALT_L3_SEC_L4OSC1 register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_L4OSC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4OSC1_OFST)) -/* The address of the ALT_L3_SEC_L4SPIM register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_L4SPIM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_L4SPIM_OFST)) -/* The address of the ALT_L3_SEC_STM register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_STM_OFST)) -/* The address of the ALT_L3_SEC_LWH2F register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_LWH2F_OFST)) -/* The address of the ALT_L3_SEC_USB1 register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_USB1_OFST)) -/* The address of the ALT_L3_SEC_NANDDATA register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_NANDDATA_OFST)) -/* The address of the ALT_L3_SEC_USB0 register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_USB0_OFST)) -/* The address of the ALT_L3_SEC_NAND register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_NAND_OFST)) -/* The address of the ALT_L3_SEC_QSPIDATA register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_QSPIDATA_OFST)) -/* The address of the ALT_L3_SEC_FPGAMGRDATA register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_FPGAMGRDATA_OFST)) -/* The address of the ALT_L3_SEC_H2F register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_H2F_OFST)) -/* The address of the ALT_L3_SEC_ACP register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_ACP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_ACP_OFST)) -/* The address of the ALT_L3_SEC_ROM register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_ROM_OFST)) -/* The address of the ALT_L3_SEC_OCRAM register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_OCRAM_OFST)) -/* The address of the ALT_L3_SEC_SDRDATA register for the ALT_L3_SECGRP instance. */ -#define ALT_L3_SEC_SDRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + ALT_L3_SEC_SDRDATA_OFST)) -/* The base address byte offset for the start of the ALT_L3_SECGRP component. */ -#define ALT_L3_SECGRP_OFST 0x8 -/* The start address of the ALT_L3_SECGRP component. */ -#define ALT_L3_SECGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_SECGRP_OFST)) -/* The lower bound address range of the ALT_L3_SECGRP component. */ -#define ALT_L3_SECGRP_LB_ADDR ALT_L3_SECGRP_ADDR -/* The upper bound address range of the ALT_L3_SECGRP component. */ -#define ALT_L3_SECGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SECGRP_ADDR) + 0x9c) - 1)) - - -/* - * Register Group Instance : idgrp - * - * Instance idgrp of register group ALT_L3_IDGRP. - * - * - */ -/* The address of the ALT_L3_ID_PERIPH_ID_4 register for the ALT_L3_IDGRP instance. */ -#define ALT_L3_ID_PERIPH_ID_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_4_OFST)) -/* The address of the ALT_L3_ID_PERIPH_ID_0 register for the ALT_L3_IDGRP instance. */ -#define ALT_L3_ID_PERIPH_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_0_OFST)) -/* The address of the ALT_L3_ID_PERIPH_ID_1 register for the ALT_L3_IDGRP instance. */ -#define ALT_L3_ID_PERIPH_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_1_OFST)) -/* The address of the ALT_L3_ID_PERIPH_ID_2 register for the ALT_L3_IDGRP instance. */ -#define ALT_L3_ID_PERIPH_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_2_OFST)) -/* The address of the ALT_L3_ID_PERIPH_ID_3 register for the ALT_L3_IDGRP instance. */ -#define ALT_L3_ID_PERIPH_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_PERIPH_ID_3_OFST)) -/* The address of the ALT_L3_ID_COMP_ID_0 register for the ALT_L3_IDGRP instance. */ -#define ALT_L3_ID_COMP_ID_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_0_OFST)) -/* The address of the ALT_L3_ID_COMP_ID_1 register for the ALT_L3_IDGRP instance. */ -#define ALT_L3_ID_COMP_ID_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_1_OFST)) -/* The address of the ALT_L3_ID_COMP_ID_2 register for the ALT_L3_IDGRP instance. */ -#define ALT_L3_ID_COMP_ID_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_2_OFST)) -/* The address of the ALT_L3_ID_COMP_ID_3 register for the ALT_L3_IDGRP instance. */ -#define ALT_L3_ID_COMP_ID_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + ALT_L3_ID_COMP_ID_3_OFST)) -/* The base address byte offset for the start of the ALT_L3_IDGRP component. */ -#define ALT_L3_IDGRP_OFST 0x1000 -/* The start address of the ALT_L3_IDGRP component. */ -#define ALT_L3_IDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_IDGRP_OFST)) -/* The lower bound address range of the ALT_L3_IDGRP component. */ -#define ALT_L3_IDGRP_LB_ADDR ALT_L3_IDGRP_ADDR -/* The upper bound address range of the ALT_L3_IDGRP component. */ -#define ALT_L3_IDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_IDGRP_ADDR) + 0x1000) - 1)) - - -/* - * Register Group Instance : mastergrp - * - * Instance mastergrp of register group ALT_L3_MSTGRP. - * - * - */ -/* - * Register Group Instance : mastergrp_l4main - * - * Instance mastergrp_l4main of register group ALT_L3_MST_L4MAIN. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4MAIN instance. */ -#define ALT_L3_MST_MST_L4MAIN_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4MAIN_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_L4MAIN component. */ -#define ALT_L3_MST_MST_L4MAIN_OFST 0x0 -/* The start address of the ALT_L3_MST_MST_L4MAIN component. */ -#define ALT_L3_MST_MST_L4MAIN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4MAIN_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_L4MAIN component. */ -#define ALT_L3_MST_MST_L4MAIN_LB_ADDR ALT_L3_MST_MST_L4MAIN_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_L4MAIN component. */ -#define ALT_L3_MST_MST_L4MAIN_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4MAIN_ADDR) + 0xc) - 1)) - - -/* - * Register Group Instance : mastergrp_l4sp - * - * Instance mastergrp_l4sp of register group ALT_L3_MST_L4SP. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4SP instance. */ -#define ALT_L3_MST_MST_L4SP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4SP_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_L4SP component. */ -#define ALT_L3_MST_MST_L4SP_OFST 0x1000 -/* The start address of the ALT_L3_MST_MST_L4SP component. */ -#define ALT_L3_MST_MST_L4SP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4SP_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_L4SP component. */ -#define ALT_L3_MST_MST_L4SP_LB_ADDR ALT_L3_MST_MST_L4SP_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_L4SP component. */ -#define ALT_L3_MST_MST_L4SP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4SP_ADDR) + 0xc) - 1)) - - -/* - * Register Group Instance : mastergrp_l4mp - * - * Instance mastergrp_l4mp of register group ALT_L3_MST_L4MP. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4MP instance. */ -#define ALT_L3_MST_MST_L4MP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4MP_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_L4MP component. */ -#define ALT_L3_MST_MST_L4MP_OFST 0x2000 -/* The start address of the ALT_L3_MST_MST_L4MP component. */ -#define ALT_L3_MST_MST_L4MP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4MP_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_L4MP component. */ -#define ALT_L3_MST_MST_L4MP_LB_ADDR ALT_L3_MST_MST_L4MP_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_L4MP component. */ -#define ALT_L3_MST_MST_L4MP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4MP_ADDR) + 0xc) - 1)) - - -/* - * Register Group Instance : mastergrp_l4osc1 - * - * Instance mastergrp_l4osc1 of register group ALT_L3_MST_L4OSC1. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4OSC1 instance. */ -#define ALT_L3_MST_MST_L4OSC1_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4OSC1_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_L4OSC1 component. */ -#define ALT_L3_MST_MST_L4OSC1_OFST 0x3000 -/* The start address of the ALT_L3_MST_MST_L4OSC1 component. */ -#define ALT_L3_MST_MST_L4OSC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4OSC1_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_L4OSC1 component. */ -#define ALT_L3_MST_MST_L4OSC1_LB_ADDR ALT_L3_MST_MST_L4OSC1_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_L4OSC1 component. */ -#define ALT_L3_MST_MST_L4OSC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4OSC1_ADDR) + 0xc) - 1)) - - -/* - * Register Group Instance : mastergrp_l4spim - * - * Instance mastergrp_l4spim of register group ALT_L3_MST_L4SPIM. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_L4SPIM instance. */ -#define ALT_L3_MST_MST_L4SPIM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_L4SPIM_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_L4SPIM component. */ -#define ALT_L3_MST_MST_L4SPIM_OFST 0x4000 -/* The start address of the ALT_L3_MST_MST_L4SPIM component. */ -#define ALT_L3_MST_MST_L4SPIM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_L4SPIM_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_L4SPIM component. */ -#define ALT_L3_MST_MST_L4SPIM_LB_ADDR ALT_L3_MST_MST_L4SPIM_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_L4SPIM component. */ -#define ALT_L3_MST_MST_L4SPIM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_L4SPIM_ADDR) + 0xc) - 1)) - - -/* - * Register Group Instance : mastergrp_stm - * - * Instance mastergrp_stm of register group ALT_L3_MST_STM. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_STM instance. */ -#define ALT_L3_MST_MST_STM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_STM_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_STM instance. */ -#define ALT_L3_MST_MST_STM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_STM_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_STM component. */ -#define ALT_L3_MST_MST_STM_OFST 0x5000 -/* The start address of the ALT_L3_MST_MST_STM component. */ -#define ALT_L3_MST_MST_STM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_STM_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_STM component. */ -#define ALT_L3_MST_MST_STM_LB_ADDR ALT_L3_MST_MST_STM_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_STM component. */ -#define ALT_L3_MST_MST_STM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_STM_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : mastergrp_lwhps2fpga - * - * Instance mastergrp_lwhps2fpga of register group ALT_L3_MST_LWH2F. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_LWH2F instance. */ -#define ALT_L3_MST_MST_LWH2F_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_LWH2F_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_LWH2F instance. */ -#define ALT_L3_MST_MST_LWH2F_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_LWH2F_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_LWH2F component. */ -#define ALT_L3_MST_MST_LWH2F_OFST 0x6000 -/* The start address of the ALT_L3_MST_MST_LWH2F component. */ -#define ALT_L3_MST_MST_LWH2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_LWH2F_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_LWH2F component. */ -#define ALT_L3_MST_MST_LWH2F_LB_ADDR ALT_L3_MST_MST_LWH2F_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_LWH2F component. */ -#define ALT_L3_MST_MST_LWH2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_LWH2F_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : mastergrp_usb1 - * - * Instance mastergrp_usb1 of register group ALT_L3_MST_USB1. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_USB1 instance. */ -#define ALT_L3_MST_MST_USB1_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_USB1_ADDR) -/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_USB1 instance. */ -#define ALT_L3_MST_MST_USB1_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_USB1_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_USB1 component. */ -#define ALT_L3_MST_MST_USB1_OFST 0x8000 -/* The start address of the ALT_L3_MST_MST_USB1 component. */ -#define ALT_L3_MST_MST_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_USB1_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_USB1 component. */ -#define ALT_L3_MST_MST_USB1_LB_ADDR ALT_L3_MST_MST_USB1_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_USB1 component. */ -#define ALT_L3_MST_MST_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_USB1_ADDR) + 0x48) - 1)) - - -/* - * Register Group Instance : mastergrp_nanddata - * - * Instance mastergrp_nanddata of register group ALT_L3_MST_NANDDATA. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_NANDDATA instance. */ -#define ALT_L3_MST_MST_NANDDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_NANDDATA_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_NANDDATA instance. */ -#define ALT_L3_MST_MST_NANDDATA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_NANDDATA_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_NANDDATA component. */ -#define ALT_L3_MST_MST_NANDDATA_OFST 0x9000 -/* The start address of the ALT_L3_MST_MST_NANDDATA component. */ -#define ALT_L3_MST_MST_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_NANDDATA_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_NANDDATA component. */ -#define ALT_L3_MST_MST_NANDDATA_LB_ADDR ALT_L3_MST_MST_NANDDATA_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_NANDDATA component. */ -#define ALT_L3_MST_MST_NANDDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_NANDDATA_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : mastergrp_usb0 - * - * Instance mastergrp_usb0 of register group ALT_L3_MST_USB0. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_USB0 instance. */ -#define ALT_L3_MST_MST_USB0_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_USB0_ADDR) -/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_USB0 instance. */ -#define ALT_L3_MST_MST_USB0_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_USB0_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_USB0 component. */ -#define ALT_L3_MST_MST_USB0_OFST 0x1e000 -/* The start address of the ALT_L3_MST_MST_USB0 component. */ -#define ALT_L3_MST_MST_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_USB0_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_USB0 component. */ -#define ALT_L3_MST_MST_USB0_LB_ADDR ALT_L3_MST_MST_USB0_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_USB0 component. */ -#define ALT_L3_MST_MST_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_USB0_ADDR) + 0x48) - 1)) - - -/* - * Register Group Instance : mastergrp_nandregs - * - * Instance mastergrp_nandregs of register group ALT_L3_MST_NAND. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_NAND instance. */ -#define ALT_L3_MST_MST_NAND_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_NAND_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_NAND instance. */ -#define ALT_L3_MST_MST_NAND_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_NAND_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_NAND component. */ -#define ALT_L3_MST_MST_NAND_OFST 0x1f000 -/* The start address of the ALT_L3_MST_MST_NAND component. */ -#define ALT_L3_MST_MST_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_NAND_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_NAND component. */ -#define ALT_L3_MST_MST_NAND_LB_ADDR ALT_L3_MST_MST_NAND_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_NAND component. */ -#define ALT_L3_MST_MST_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_NAND_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : mastergrp_qspidata - * - * Instance mastergrp_qspidata of register group ALT_L3_MST_QSPIDATA. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_QSPIDATA instance. */ -#define ALT_L3_MST_MST_QSPIDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_QSPIDATA_ADDR) -/* The address of the ALT_L3_AHB_CNTL register for the ALT_L3_MST_MST_QSPIDATA instance. */ -#define ALT_L3_MST_MST_QSPIDATA_AHB_CNTL_ADDR ALT_L3_AHB_CNTL_ADDR(ALT_L3_MST_MST_QSPIDATA_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_QSPIDATA component. */ -#define ALT_L3_MST_MST_QSPIDATA_OFST 0x20000 -/* The start address of the ALT_L3_MST_MST_QSPIDATA component. */ -#define ALT_L3_MST_MST_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_QSPIDATA_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_QSPIDATA component. */ -#define ALT_L3_MST_MST_QSPIDATA_LB_ADDR ALT_L3_MST_MST_QSPIDATA_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_QSPIDATA component. */ -#define ALT_L3_MST_MST_QSPIDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_QSPIDATA_ADDR) + 0x48) - 1)) - - -/* - * Register Group Instance : mastergrp_fpgamgrdata - * - * Instance mastergrp_fpgamgrdata of register group ALT_L3_MST_FPGAMGRDATA. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ -#define ALT_L3_MST_MST_FPGAMGRDATA_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) -/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ -#define ALT_L3_MST_MST_FPGAMGRDATA_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_FPGAMGRDATA instance. */ -#define ALT_L3_MST_MST_FPGAMGRDATA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_FPGAMGRDATA_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_FPGAMGRDATA component. */ -#define ALT_L3_MST_MST_FPGAMGRDATA_OFST 0x21000 -/* The start address of the ALT_L3_MST_MST_FPGAMGRDATA component. */ -#define ALT_L3_MST_MST_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_FPGAMGRDATA_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_FPGAMGRDATA component. */ -#define ALT_L3_MST_MST_FPGAMGRDATA_LB_ADDR ALT_L3_MST_MST_FPGAMGRDATA_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_FPGAMGRDATA component. */ -#define ALT_L3_MST_MST_FPGAMGRDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_FPGAMGRDATA_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : mastergrp_hps2fpga - * - * Instance mastergrp_hps2fpga of register group ALT_L3_MST_H2F. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_H2F instance. */ -#define ALT_L3_MST_MST_H2F_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_H2F_ADDR) -/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_H2F instance. */ -#define ALT_L3_MST_MST_H2F_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_H2F_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_H2F instance. */ -#define ALT_L3_MST_MST_H2F_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_H2F_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_H2F component. */ -#define ALT_L3_MST_MST_H2F_OFST 0x22000 -/* The start address of the ALT_L3_MST_MST_H2F component. */ -#define ALT_L3_MST_MST_H2F_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_H2F_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_H2F component. */ -#define ALT_L3_MST_MST_H2F_LB_ADDR ALT_L3_MST_MST_H2F_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_H2F component. */ -#define ALT_L3_MST_MST_H2F_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_H2F_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : mastergrp_acp - * - * Instance mastergrp_acp of register group ALT_L3_MST_ACP. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_ACP instance. */ -#define ALT_L3_MST_MST_ACP_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_ACP_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_ACP instance. */ -#define ALT_L3_MST_MST_ACP_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_ACP_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_ACP component. */ -#define ALT_L3_MST_MST_ACP_OFST 0x23000 -/* The start address of the ALT_L3_MST_MST_ACP component. */ -#define ALT_L3_MST_MST_ACP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_ACP_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_ACP component. */ -#define ALT_L3_MST_MST_ACP_LB_ADDR ALT_L3_MST_MST_ACP_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_ACP component. */ -#define ALT_L3_MST_MST_ACP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_ACP_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : mastergrp_rom - * - * Instance mastergrp_rom of register group ALT_L3_MST_ROM. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_ROM instance. */ -#define ALT_L3_MST_MST_ROM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_ROM_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_ROM instance. */ -#define ALT_L3_MST_MST_ROM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_ROM_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_ROM component. */ -#define ALT_L3_MST_MST_ROM_OFST 0x24000 -/* The start address of the ALT_L3_MST_MST_ROM component. */ -#define ALT_L3_MST_MST_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_ROM_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_ROM component. */ -#define ALT_L3_MST_MST_ROM_LB_ADDR ALT_L3_MST_MST_ROM_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_ROM component. */ -#define ALT_L3_MST_MST_ROM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_ROM_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : mastergrp_ocram - * - * Instance mastergrp_ocram of register group ALT_L3_MST_OCRAM. - * - * - */ -/* The address of the ALT_L3_FN_MOD_BM_ISS register for the ALT_L3_MST_MST_OCRAM instance. */ -#define ALT_L3_MST_MST_OCRAM_FN_MOD_BM_ISS_ADDR ALT_L3_FN_MOD_BM_ISS_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) -/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_MST_MST_OCRAM instance. */ -#define ALT_L3_MST_MST_OCRAM_WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_MST_MST_OCRAM instance. */ -#define ALT_L3_MST_MST_OCRAM_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_MST_MST_OCRAM_ADDR) -/* The base address byte offset for the start of the ALT_L3_MST_MST_OCRAM component. */ -#define ALT_L3_MST_MST_OCRAM_OFST 0x25000 -/* The start address of the ALT_L3_MST_MST_OCRAM component. */ -#define ALT_L3_MST_MST_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + ALT_L3_MST_MST_OCRAM_OFST)) -/* The lower bound address range of the ALT_L3_MST_MST_OCRAM component. */ -#define ALT_L3_MST_MST_OCRAM_LB_ADDR ALT_L3_MST_MST_OCRAM_ADDR -/* The upper bound address range of the ALT_L3_MST_MST_OCRAM component. */ -#define ALT_L3_MST_MST_OCRAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MST_MST_OCRAM_ADDR) + 0x10c) - 1)) - - -/* The base address byte offset for the start of the ALT_L3_MSTGRP component. */ -#define ALT_L3_MSTGRP_OFST 0x2000 -/* The start address of the ALT_L3_MSTGRP component. */ -#define ALT_L3_MSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_MSTGRP_OFST)) -/* The lower bound address range of the ALT_L3_MSTGRP component. */ -#define ALT_L3_MSTGRP_LB_ADDR ALT_L3_MSTGRP_ADDR -/* The upper bound address range of the ALT_L3_MSTGRP component. */ -#define ALT_L3_MSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_MSTGRP_ADDR) + 0x2510c) - 1)) - - -/* - * Register Group Instance : slavegrp - * - * Instance slavegrp of register group ALT_L3_SLVGRP. - * - * - */ -/* - * Register Group Instance : slavegrp_dap - * - * Instance slavegrp_dap of register group ALT_L3_SLV_DAP. - * - * - */ -/* The address of the ALT_L3_FN_MOD2 register for the ALT_L3_SLV_SLV_DAP instance. */ -#define ALT_L3_SLV_SLV_DAP_FN_MOD2_ADDR ALT_L3_FN_MOD2_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) -/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_DAP instance. */ -#define ALT_L3_SLV_SLV_DAP_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_DAP instance. */ -#define ALT_L3_SLV_SLV_DAP_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_DAP instance. */ -#define ALT_L3_SLV_SLV_DAP_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_DAP instance. */ -#define ALT_L3_SLV_SLV_DAP_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_DAP_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_DAP component. */ -#define ALT_L3_SLV_SLV_DAP_OFST 0x0 -/* The start address of the ALT_L3_SLV_SLV_DAP component. */ -#define ALT_L3_SLV_SLV_DAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_DAP_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_DAP component. */ -#define ALT_L3_SLV_SLV_DAP_LB_ADDR ALT_L3_SLV_SLV_DAP_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_DAP component. */ -#define ALT_L3_SLV_SLV_DAP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_DAP_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_mpu - * - * Instance slavegrp_mpu of register group ALT_L3_SLV_MPU. - * - * - */ -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_MPU instance. */ -#define ALT_L3_SLV_SLV_MPU_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_MPU instance. */ -#define ALT_L3_SLV_SLV_MPU_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_MPU instance. */ -#define ALT_L3_SLV_SLV_MPU_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_MPU_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_MPU component. */ -#define ALT_L3_SLV_SLV_MPU_OFST 0x1000 -/* The start address of the ALT_L3_SLV_SLV_MPU component. */ -#define ALT_L3_SLV_SLV_MPU_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_MPU_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_MPU component. */ -#define ALT_L3_SLV_SLV_MPU_LB_ADDR ALT_L3_SLV_SLV_MPU_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_MPU component. */ -#define ALT_L3_SLV_SLV_MPU_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_MPU_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_sdmmc - * - * Instance slavegrp_sdmmc of register group ALT_L3_SLV_SDMMC. - * - * - */ -/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_SDMMC instance. */ -#define ALT_L3_SLV_SLV_SDMMC_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_SDMMC instance. */ -#define ALT_L3_SLV_SLV_SDMMC_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_SDMMC instance. */ -#define ALT_L3_SLV_SLV_SDMMC_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_SDMMC instance. */ -#define ALT_L3_SLV_SLV_SDMMC_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_SDMMC_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_SDMMC component. */ -#define ALT_L3_SLV_SLV_SDMMC_OFST 0x2000 -/* The start address of the ALT_L3_SLV_SLV_SDMMC component. */ -#define ALT_L3_SLV_SLV_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_SDMMC_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_SDMMC component. */ -#define ALT_L3_SLV_SLV_SDMMC_LB_ADDR ALT_L3_SLV_SLV_SDMMC_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_SDMMC component. */ -#define ALT_L3_SLV_SLV_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_SDMMC_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_dma - * - * Instance slavegrp_dma of register group ALT_L3_SLV_DMA. - * - * - */ -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_DMA instance. */ -#define ALT_L3_SLV_SLV_DMA_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_DMA instance. */ -#define ALT_L3_SLV_SLV_DMA_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_DMA instance. */ -#define ALT_L3_SLV_SLV_DMA_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_DMA_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_DMA component. */ -#define ALT_L3_SLV_SLV_DMA_OFST 0x3000 -/* The start address of the ALT_L3_SLV_SLV_DMA component. */ -#define ALT_L3_SLV_SLV_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_DMA_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_DMA component. */ -#define ALT_L3_SLV_SLV_DMA_LB_ADDR ALT_L3_SLV_SLV_DMA_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_DMA component. */ -#define ALT_L3_SLV_SLV_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_DMA_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_fpga2hps - * - * Instance slavegrp_fpga2hps of register group ALT_L3_SLV_F2H. - * - * - */ -/* The address of the ALT_L3_WR_TIDEMARK register for the ALT_L3_SLV_SLV_F2H instance. */ -#define ALT_L3_SLV_SLV_FPGA2WR_TIDEMARK_ADDR ALT_L3_WR_TIDEMARK_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_F2H instance. */ -#define ALT_L3_SLV_SLV_FPGA2RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_F2H instance. */ -#define ALT_L3_SLV_SLV_FPGA2WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_F2H instance. */ -#define ALT_L3_SLV_SLV_FPGA2FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_F2H_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_F2H component. */ -#define ALT_L3_SLV_SLV_F2H_OFST 0x4000 -/* The start address of the ALT_L3_SLV_SLV_F2H component. */ -#define ALT_L3_SLV_SLV_F2H_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_F2H_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_F2H component. */ -#define ALT_L3_SLV_SLV_F2H_LB_ADDR ALT_L3_SLV_SLV_F2H_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_F2H component. */ -#define ALT_L3_SLV_SLV_F2H_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_F2H_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_etr - * - * Instance slavegrp_etr of register group ALT_L3_SLV_ETR. - * - * - */ -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_ETR instance. */ -#define ALT_L3_SLV_SLV_ETR_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_ETR instance. */ -#define ALT_L3_SLV_SLV_ETR_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_ETR instance. */ -#define ALT_L3_SLV_SLV_ETR_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_ETR_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_ETR component. */ -#define ALT_L3_SLV_SLV_ETR_OFST 0x5000 -/* The start address of the ALT_L3_SLV_SLV_ETR component. */ -#define ALT_L3_SLV_SLV_ETR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_ETR_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_ETR component. */ -#define ALT_L3_SLV_SLV_ETR_LB_ADDR ALT_L3_SLV_SLV_ETR_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_ETR component. */ -#define ALT_L3_SLV_SLV_ETR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_ETR_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_emac0 - * - * Instance slavegrp_emac0 of register group ALT_L3_SLV_EMAC0. - * - * - */ -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_EMAC0 instance. */ -#define ALT_L3_SLV_SLV_EMAC0_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_EMAC0 instance. */ -#define ALT_L3_SLV_SLV_EMAC0_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_EMAC0 instance. */ -#define ALT_L3_SLV_SLV_EMAC0_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_EMAC0_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_EMAC0 component. */ -#define ALT_L3_SLV_SLV_EMAC0_OFST 0x6000 -/* The start address of the ALT_L3_SLV_SLV_EMAC0 component. */ -#define ALT_L3_SLV_SLV_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_EMAC0_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_EMAC0 component. */ -#define ALT_L3_SLV_SLV_EMAC0_LB_ADDR ALT_L3_SLV_SLV_EMAC0_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_EMAC0 component. */ -#define ALT_L3_SLV_SLV_EMAC0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_EMAC0_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_emac1 - * - * Instance slavegrp_emac1 of register group ALT_L3_SLV_EMAC1. - * - * - */ -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_EMAC1 instance. */ -#define ALT_L3_SLV_SLV_EMAC1_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_EMAC1 instance. */ -#define ALT_L3_SLV_SLV_EMAC1_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_EMAC1 instance. */ -#define ALT_L3_SLV_SLV_EMAC1_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_EMAC1_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_EMAC1 component. */ -#define ALT_L3_SLV_SLV_EMAC1_OFST 0x7000 -/* The start address of the ALT_L3_SLV_SLV_EMAC1 component. */ -#define ALT_L3_SLV_SLV_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_EMAC1_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_EMAC1 component. */ -#define ALT_L3_SLV_SLV_EMAC1_LB_ADDR ALT_L3_SLV_SLV_EMAC1_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_EMAC1 component. */ -#define ALT_L3_SLV_SLV_EMAC1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_EMAC1_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_usb0 - * - * Instance slavegrp_usb0 of register group ALT_L3_SLV_USB0. - * - * - */ -/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_USB0 instance. */ -#define ALT_L3_SLV_SLV_USB0_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_USB0 instance. */ -#define ALT_L3_SLV_SLV_USB0_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_USB0 instance. */ -#define ALT_L3_SLV_SLV_USB0_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_USB0 instance. */ -#define ALT_L3_SLV_SLV_USB0_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_USB0_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_USB0 component. */ -#define ALT_L3_SLV_SLV_USB0_OFST 0x8000 -/* The start address of the ALT_L3_SLV_SLV_USB0 component. */ -#define ALT_L3_SLV_SLV_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_USB0_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_USB0 component. */ -#define ALT_L3_SLV_SLV_USB0_LB_ADDR ALT_L3_SLV_SLV_USB0_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_USB0 component. */ -#define ALT_L3_SLV_SLV_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_USB0_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_nand - * - * Instance slavegrp_nand of register group ALT_L3_SLV_NAND. - * - * - */ -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_NAND instance. */ -#define ALT_L3_SLV_SLV_NAND_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_NAND instance. */ -#define ALT_L3_SLV_SLV_NAND_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_NAND instance. */ -#define ALT_L3_SLV_SLV_NAND_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_NAND_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_NAND component. */ -#define ALT_L3_SLV_SLV_NAND_OFST 0x9000 -/* The start address of the ALT_L3_SLV_SLV_NAND component. */ -#define ALT_L3_SLV_SLV_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_NAND_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_NAND component. */ -#define ALT_L3_SLV_SLV_NAND_LB_ADDR ALT_L3_SLV_SLV_NAND_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_NAND component. */ -#define ALT_L3_SLV_SLV_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_NAND_ADDR) + 0x10c) - 1)) - - -/* - * Register Group Instance : slavegrp_usb1 - * - * Instance slavegrp_usb1 of register group ALT_L3_SLV_USB1. - * - * - */ -/* The address of the ALT_L3_FN_MOD_AHB register for the ALT_L3_SLV_SLV_USB1 instance. */ -#define ALT_L3_SLV_SLV_USB1_FN_MOD_AHB_ADDR ALT_L3_FN_MOD_AHB_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) -/* The address of the ALT_L3_RD_QOS register for the ALT_L3_SLV_SLV_USB1 instance. */ -#define ALT_L3_SLV_SLV_USB1_RD_QOS_ADDR ALT_L3_RD_QOS_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) -/* The address of the ALT_L3_WR_QOS register for the ALT_L3_SLV_SLV_USB1 instance. */ -#define ALT_L3_SLV_SLV_USB1_WR_QOS_ADDR ALT_L3_WR_QOS_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) -/* The address of the ALT_L3_FN_MOD register for the ALT_L3_SLV_SLV_USB1 instance. */ -#define ALT_L3_SLV_SLV_USB1_FN_MOD_ADDR ALT_L3_FN_MOD_ADDR(ALT_L3_SLV_SLV_USB1_ADDR) -/* The base address byte offset for the start of the ALT_L3_SLV_SLV_USB1 component. */ -#define ALT_L3_SLV_SLV_USB1_OFST 0xa000 -/* The start address of the ALT_L3_SLV_SLV_USB1 component. */ -#define ALT_L3_SLV_SLV_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + ALT_L3_SLV_SLV_USB1_OFST)) -/* The lower bound address range of the ALT_L3_SLV_SLV_USB1 component. */ -#define ALT_L3_SLV_SLV_USB1_LB_ADDR ALT_L3_SLV_SLV_USB1_ADDR -/* The upper bound address range of the ALT_L3_SLV_SLV_USB1 component. */ -#define ALT_L3_SLV_SLV_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLV_SLV_USB1_ADDR) + 0x10c) - 1)) - - -/* The base address byte offset for the start of the ALT_L3_SLVGRP component. */ -#define ALT_L3_SLVGRP_OFST 0x42000 -/* The start address of the ALT_L3_SLVGRP component. */ -#define ALT_L3_SLVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_L3_ADDR) + ALT_L3_SLVGRP_OFST)) -/* The lower bound address range of the ALT_L3_SLVGRP component. */ -#define ALT_L3_SLVGRP_LB_ADDR ALT_L3_SLVGRP_ADDR -/* The upper bound address range of the ALT_L3_SLVGRP component. */ -#define ALT_L3_SLVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_SLVGRP_ADDR) + 0xa10c) - 1)) - - -/* The base address byte offset for the start of the ALT_L3 component. */ -#define ALT_L3_OFST 0xff800000 -/* The start address of the ALT_L3 component. */ -#define ALT_L3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L3_OFST)) -/* The lower bound address range of the ALT_L3 component. */ -#define ALT_L3_LB_ADDR ALT_L3_ADDR -/* The upper bound address range of the ALT_L3 component. */ -#define ALT_L3_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L3_ADDR) + 0x80000) - 1)) - - -/* - * Component Instance : nanddata - * - * Instance nanddata of component ALT_NANDDATA. - * - * - */ -/* The base address byte offset for the start of the ALT_NANDDATA component. */ -#define ALT_NANDDATA_OFST 0xff900000 -/* The start address of the ALT_NANDDATA component. */ -#define ALT_NANDDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_NANDDATA_OFST)) -/* The lower bound address range of the ALT_NANDDATA component. */ -#define ALT_NANDDATA_LB_ADDR ALT_NANDDATA_ADDR -/* The upper bound address range of the ALT_NANDDATA component. */ -#define ALT_NANDDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NANDDATA_ADDR) + 0x100000) - 1)) - - -/* - * Component Instance : qspidata - * - * Instance qspidata of component ALT_QSPIDATA. - * - * - */ -/* The base address byte offset for the start of the ALT_QSPIDATA component. */ -#define ALT_QSPIDATA_OFST 0xffa00000 -/* The start address of the ALT_QSPIDATA component. */ -#define ALT_QSPIDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_QSPIDATA_OFST)) -/* The lower bound address range of the ALT_QSPIDATA component. */ -#define ALT_QSPIDATA_LB_ADDR ALT_QSPIDATA_ADDR -/* The upper bound address range of the ALT_QSPIDATA component. */ -#define ALT_QSPIDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_QSPIDATA_ADDR) + 0x100000) - 1)) - - -/* - * Component Instance : usb0 - * - * Instance usb0 of component ALT_USB. - * - * - */ -/* - * Register Group Instance : globgrp - * - * Instance globgrp of register group ALT_USB_GLOB. - * - * - */ -/* The address of the ALT_USB_GLOB_GOTGCTL register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GOTGCTL_ADDR ALT_USB_GLOB_GOTGCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GOTGINT register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GOTGINT_ADDR ALT_USB_GLOB_GOTGINT_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GAHBCFG register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GAHBCFG_ADDR ALT_USB_GLOB_GAHBCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GUSBCFG register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GUSBCFG_ADDR ALT_USB_GLOB_GUSBCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GRSTCTL register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GRSTCTL_ADDR ALT_USB_GLOB_GRSTCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GINTSTS register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GINTSTS_ADDR ALT_USB_GLOB_GINTSTS_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GINTMSK register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GINTMSK_ADDR ALT_USB_GLOB_GINTMSK_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GRXSTSR register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GRXSTSR_ADDR ALT_USB_GLOB_GRXSTSR_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GRXSTSP register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GRXSTSP_ADDR ALT_USB_GLOB_GRXSTSP_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GRXFSIZ register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GRXFSIZ_ADDR ALT_USB_GLOB_GRXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GNPTXFSIZ register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GNPTXFSIZ_ADDR ALT_USB_GLOB_GNPTXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GNPTXSTS register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GNPTXSTS_ADDR ALT_USB_GLOB_GNPTXSTS_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GPVNDCTL register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GPVNDCTL_ADDR ALT_USB_GLOB_GPVNDCTL_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GGPIO register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GGPIO_ADDR ALT_USB_GLOB_GGPIO_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GUID register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GUID_ADDR ALT_USB_GLOB_GUID_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GSNPSID register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GSNPSID_ADDR ALT_USB_GLOB_GSNPSID_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GHWCFG1 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GHWCFG1_ADDR ALT_USB_GLOB_GHWCFG1_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GHWCFG2 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GHWCFG2_ADDR ALT_USB_GLOB_GHWCFG2_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GHWCFG3 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GHWCFG3_ADDR ALT_USB_GLOB_GHWCFG3_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GHWCFG4 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GHWCFG4_ADDR ALT_USB_GLOB_GHWCFG4_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GDFIFOCFG register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_GDFIFOCFG_ADDR ALT_USB_GLOB_GDFIFOCFG_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_HPTXFSIZ register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_HPTXFSIZ_ADDR ALT_USB_GLOB_HPTXFSIZ_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF1 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF1_ADDR ALT_USB_GLOB_DIEPTXF1_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF2 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF2_ADDR ALT_USB_GLOB_DIEPTXF2_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF3 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF3_ADDR ALT_USB_GLOB_DIEPTXF3_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF4 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF4_ADDR ALT_USB_GLOB_DIEPTXF4_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF5 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF5_ADDR ALT_USB_GLOB_DIEPTXF5_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF6 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF6_ADDR ALT_USB_GLOB_DIEPTXF6_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF7 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF7_ADDR ALT_USB_GLOB_DIEPTXF7_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF8 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF8_ADDR ALT_USB_GLOB_DIEPTXF8_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF9 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF9_ADDR ALT_USB_GLOB_DIEPTXF9_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF10 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF10_ADDR ALT_USB_GLOB_DIEPTXF10_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF11 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF11_ADDR ALT_USB_GLOB_DIEPTXF11_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF12 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF12_ADDR ALT_USB_GLOB_DIEPTXF12_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF13 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF13_ADDR ALT_USB_GLOB_DIEPTXF13_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF14 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF14_ADDR ALT_USB_GLOB_DIEPTXF14_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF15 register for the ALT_USB0_GLOBGRP instance. */ -#define ALT_USB0_GLOB_DIEPTXF15_ADDR ALT_USB_GLOB_DIEPTXF15_ADDR(ALT_USB0_GLOBGRP_ADDR) -/* The base address byte offset for the start of the ALT_USB0_GLOBGRP component. */ -#define ALT_USB0_GLOBGRP_OFST 0x0 -/* The start address of the ALT_USB0_GLOBGRP component. */ -#define ALT_USB0_GLOBGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_GLOBGRP_OFST)) -/* The lower bound address range of the ALT_USB0_GLOBGRP component. */ -#define ALT_USB0_GLOBGRP_LB_ADDR ALT_USB0_GLOBGRP_ADDR -/* The upper bound address range of the ALT_USB0_GLOBGRP component. */ -#define ALT_USB0_GLOBGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_GLOBGRP_ADDR) + 0x140) - 1)) - - -/* - * Register Group Instance : hostgrp - * - * Instance hostgrp of register group ALT_USB_HOST. - * - * - */ -/* The address of the ALT_USB_HOST_HCFG register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCFG_ADDR ALT_USB_HOST_HCFG_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HFIR register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HFIR_ADDR ALT_USB_HOST_HFIR_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HFNUM register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HFNUM_ADDR ALT_USB_HOST_HFNUM_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HPTXSTS register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HPTXSTS_ADDR ALT_USB_HOST_HPTXSTS_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HAINT register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HAINT_ADDR ALT_USB_HOST_HAINT_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HAINTMSK register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HAINTMSK_ADDR ALT_USB_HOST_HAINTMSK_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HFLBADDR register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HFLBADDR_ADDR ALT_USB_HOST_HFLBADDR_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HPRT register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HPRT_ADDR ALT_USB_HOST_HPRT_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR0 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR0_ADDR ALT_USB_HOST_HCCHAR0_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT0 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT0_ADDR ALT_USB_HOST_HCSPLT0_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT0 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT0_ADDR ALT_USB_HOST_HCINT0_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK0 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK0_ADDR ALT_USB_HOST_HCINTMSK0_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ0 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ0_ADDR ALT_USB_HOST_HCTSIZ0_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA0 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA0_ADDR ALT_USB_HOST_HCDMA0_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB0 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB0_ADDR ALT_USB_HOST_HCDMAB0_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR1 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR1_ADDR ALT_USB_HOST_HCCHAR1_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT1 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT1_ADDR ALT_USB_HOST_HCSPLT1_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT1 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT1_ADDR ALT_USB_HOST_HCINT1_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK1 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK1_ADDR ALT_USB_HOST_HCINTMSK1_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ1 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ1_ADDR ALT_USB_HOST_HCTSIZ1_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA1 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA1_ADDR ALT_USB_HOST_HCDMA1_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB1 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB1_ADDR ALT_USB_HOST_HCDMAB1_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR2 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR2_ADDR ALT_USB_HOST_HCCHAR2_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT2 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT2_ADDR ALT_USB_HOST_HCSPLT2_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT2 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT2_ADDR ALT_USB_HOST_HCINT2_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK2 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK2_ADDR ALT_USB_HOST_HCINTMSK2_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ2 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ2_ADDR ALT_USB_HOST_HCTSIZ2_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA2 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA2_ADDR ALT_USB_HOST_HCDMA2_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB2 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB2_ADDR ALT_USB_HOST_HCDMAB2_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR3 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR3_ADDR ALT_USB_HOST_HCCHAR3_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT3 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT3_ADDR ALT_USB_HOST_HCSPLT3_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT3 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT3_ADDR ALT_USB_HOST_HCINT3_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK3 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK3_ADDR ALT_USB_HOST_HCINTMSK3_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ3 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ3_ADDR ALT_USB_HOST_HCTSIZ3_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA3 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA3_ADDR ALT_USB_HOST_HCDMA3_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB3 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB3_ADDR ALT_USB_HOST_HCDMAB3_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR4 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR4_ADDR ALT_USB_HOST_HCCHAR4_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT4 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT4_ADDR ALT_USB_HOST_HCSPLT4_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT4 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT4_ADDR ALT_USB_HOST_HCINT4_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK4 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK4_ADDR ALT_USB_HOST_HCINTMSK4_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ4 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ4_ADDR ALT_USB_HOST_HCTSIZ4_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA4 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA4_ADDR ALT_USB_HOST_HCDMA4_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB4 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB4_ADDR ALT_USB_HOST_HCDMAB4_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR5 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR5_ADDR ALT_USB_HOST_HCCHAR5_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT5 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT5_ADDR ALT_USB_HOST_HCSPLT5_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT5 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT5_ADDR ALT_USB_HOST_HCINT5_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK5 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK5_ADDR ALT_USB_HOST_HCINTMSK5_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ5 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ5_ADDR ALT_USB_HOST_HCTSIZ5_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA5 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA5_ADDR ALT_USB_HOST_HCDMA5_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB5 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB5_ADDR ALT_USB_HOST_HCDMAB5_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR6 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR6_ADDR ALT_USB_HOST_HCCHAR6_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT6 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT6_ADDR ALT_USB_HOST_HCSPLT6_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT6 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT6_ADDR ALT_USB_HOST_HCINT6_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK6 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK6_ADDR ALT_USB_HOST_HCINTMSK6_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ6 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ6_ADDR ALT_USB_HOST_HCTSIZ6_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA6 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA6_ADDR ALT_USB_HOST_HCDMA6_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB6 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB6_ADDR ALT_USB_HOST_HCDMAB6_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR7 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR7_ADDR ALT_USB_HOST_HCCHAR7_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT7 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT7_ADDR ALT_USB_HOST_HCSPLT7_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT7 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT7_ADDR ALT_USB_HOST_HCINT7_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK7 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK7_ADDR ALT_USB_HOST_HCINTMSK7_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ7 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ7_ADDR ALT_USB_HOST_HCTSIZ7_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA7 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA7_ADDR ALT_USB_HOST_HCDMA7_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB7 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB7_ADDR ALT_USB_HOST_HCDMAB7_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR8 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR8_ADDR ALT_USB_HOST_HCCHAR8_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT8 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT8_ADDR ALT_USB_HOST_HCSPLT8_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT8 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT8_ADDR ALT_USB_HOST_HCINT8_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK8 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK8_ADDR ALT_USB_HOST_HCINTMSK8_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ8 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ8_ADDR ALT_USB_HOST_HCTSIZ8_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA8 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA8_ADDR ALT_USB_HOST_HCDMA8_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB8 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB8_ADDR ALT_USB_HOST_HCDMAB8_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR9 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR9_ADDR ALT_USB_HOST_HCCHAR9_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT9 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT9_ADDR ALT_USB_HOST_HCSPLT9_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT9 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT9_ADDR ALT_USB_HOST_HCINT9_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK9 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK9_ADDR ALT_USB_HOST_HCINTMSK9_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ9 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ9_ADDR ALT_USB_HOST_HCTSIZ9_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA9 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA9_ADDR ALT_USB_HOST_HCDMA9_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB9 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB9_ADDR ALT_USB_HOST_HCDMAB9_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR10 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR10_ADDR ALT_USB_HOST_HCCHAR10_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT10 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT10_ADDR ALT_USB_HOST_HCSPLT10_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT10 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT10_ADDR ALT_USB_HOST_HCINT10_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK10 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK10_ADDR ALT_USB_HOST_HCINTMSK10_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ10 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ10_ADDR ALT_USB_HOST_HCTSIZ10_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA10 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA10_ADDR ALT_USB_HOST_HCDMA10_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB10 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB10_ADDR ALT_USB_HOST_HCDMAB10_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR11 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR11_ADDR ALT_USB_HOST_HCCHAR11_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT11 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT11_ADDR ALT_USB_HOST_HCSPLT11_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT11 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT11_ADDR ALT_USB_HOST_HCINT11_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK11 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK11_ADDR ALT_USB_HOST_HCINTMSK11_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ11 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ11_ADDR ALT_USB_HOST_HCTSIZ11_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA11 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA11_ADDR ALT_USB_HOST_HCDMA11_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB11 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB11_ADDR ALT_USB_HOST_HCDMAB11_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR12 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR12_ADDR ALT_USB_HOST_HCCHAR12_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT12 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT12_ADDR ALT_USB_HOST_HCSPLT12_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT12 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT12_ADDR ALT_USB_HOST_HCINT12_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK12 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK12_ADDR ALT_USB_HOST_HCINTMSK12_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ12 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ12_ADDR ALT_USB_HOST_HCTSIZ12_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA12 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA12_ADDR ALT_USB_HOST_HCDMA12_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB12 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB12_ADDR ALT_USB_HOST_HCDMAB12_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR13 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR13_ADDR ALT_USB_HOST_HCCHAR13_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT13 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT13_ADDR ALT_USB_HOST_HCSPLT13_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT13 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT13_ADDR ALT_USB_HOST_HCINT13_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK13 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK13_ADDR ALT_USB_HOST_HCINTMSK13_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ13 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ13_ADDR ALT_USB_HOST_HCTSIZ13_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA13 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA13_ADDR ALT_USB_HOST_HCDMA13_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB13 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB13_ADDR ALT_USB_HOST_HCDMAB13_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR14 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR14_ADDR ALT_USB_HOST_HCCHAR14_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT14 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT14_ADDR ALT_USB_HOST_HCSPLT14_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT14 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT14_ADDR ALT_USB_HOST_HCINT14_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK14 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK14_ADDR ALT_USB_HOST_HCINTMSK14_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ14 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ14_ADDR ALT_USB_HOST_HCTSIZ14_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA14 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA14_ADDR ALT_USB_HOST_HCDMA14_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB14 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB14_ADDR ALT_USB_HOST_HCDMAB14_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR15 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCCHAR15_ADDR ALT_USB_HOST_HCCHAR15_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT15 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCSPLT15_ADDR ALT_USB_HOST_HCSPLT15_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT15 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINT15_ADDR ALT_USB_HOST_HCINT15_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK15 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCINTMSK15_ADDR ALT_USB_HOST_HCINTMSK15_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ15 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCTSIZ15_ADDR ALT_USB_HOST_HCTSIZ15_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA15 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMA15_ADDR ALT_USB_HOST_HCDMA15_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB15 register for the ALT_USB0_HOSTGRP instance. */ -#define ALT_USB0_HOST_HCDMAB15_ADDR ALT_USB_HOST_HCDMAB15_ADDR(ALT_USB0_HOSTGRP_ADDR) -/* The base address byte offset for the start of the ALT_USB0_HOSTGRP component. */ -#define ALT_USB0_HOSTGRP_OFST 0x400 -/* The start address of the ALT_USB0_HOSTGRP component. */ -#define ALT_USB0_HOSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_HOSTGRP_OFST)) -/* The lower bound address range of the ALT_USB0_HOSTGRP component. */ -#define ALT_USB0_HOSTGRP_LB_ADDR ALT_USB0_HOSTGRP_ADDR -/* The upper bound address range of the ALT_USB0_HOSTGRP component. */ -#define ALT_USB0_HOSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_HOSTGRP_ADDR) + 0x2fc) - 1)) - - -/* - * Register Group Instance : devgrp - * - * Instance devgrp of register group ALT_USB_DEV. - * - * - */ -/* The address of the ALT_USB_DEV_DCFG register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DCFG_ADDR ALT_USB_DEV_DCFG_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DCTL register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DCTL_ADDR ALT_USB_DEV_DCTL_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DSTS register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DSTS_ADDR ALT_USB_DEV_DSTS_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPMSK register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPMSK_ADDR ALT_USB_DEV_DIEPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPMSK register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPMSK_ADDR ALT_USB_DEV_DOEPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DAINT register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DAINT_ADDR ALT_USB_DEV_DAINT_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DAINTMSK register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DAINTMSK_ADDR ALT_USB_DEV_DAINTMSK_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DVBUSDIS register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DVBUSDIS_ADDR ALT_USB_DEV_DVBUSDIS_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DVBUSPULSE register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DVBUSPULSE_ADDR ALT_USB_DEV_DVBUSPULSE_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTHRCTL register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTHRCTL_ADDR ALT_USB_DEV_DTHRCTL_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPEMPMSK register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPEMPMSK_ADDR ALT_USB_DEV_DIEPEMPMSK_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL0_ADDR ALT_USB_DEV_DIEPCTL0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT0_ADDR ALT_USB_DEV_DIEPINT0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ0_ADDR ALT_USB_DEV_DIEPTSIZ0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA0_ADDR ALT_USB_DEV_DIEPDMA0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS0_ADDR ALT_USB_DEV_DTXFSTS0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB0_ADDR ALT_USB_DEV_DIEPDMAB0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL1_ADDR ALT_USB_DEV_DIEPCTL1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT1_ADDR ALT_USB_DEV_DIEPINT1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ1_ADDR ALT_USB_DEV_DIEPTSIZ1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA1_ADDR ALT_USB_DEV_DIEPDMA1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS1_ADDR ALT_USB_DEV_DTXFSTS1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB1_ADDR ALT_USB_DEV_DIEPDMAB1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL2_ADDR ALT_USB_DEV_DIEPCTL2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT2_ADDR ALT_USB_DEV_DIEPINT2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ2_ADDR ALT_USB_DEV_DIEPTSIZ2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA2_ADDR ALT_USB_DEV_DIEPDMA2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS2_ADDR ALT_USB_DEV_DTXFSTS2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB2_ADDR ALT_USB_DEV_DIEPDMAB2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL3_ADDR ALT_USB_DEV_DIEPCTL3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT3_ADDR ALT_USB_DEV_DIEPINT3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ3_ADDR ALT_USB_DEV_DIEPTSIZ3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA3_ADDR ALT_USB_DEV_DIEPDMA3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS3_ADDR ALT_USB_DEV_DTXFSTS3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB3_ADDR ALT_USB_DEV_DIEPDMAB3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL4_ADDR ALT_USB_DEV_DIEPCTL4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT4_ADDR ALT_USB_DEV_DIEPINT4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ4_ADDR ALT_USB_DEV_DIEPTSIZ4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA4_ADDR ALT_USB_DEV_DIEPDMA4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS4_ADDR ALT_USB_DEV_DTXFSTS4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB4_ADDR ALT_USB_DEV_DIEPDMAB4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL5_ADDR ALT_USB_DEV_DIEPCTL5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT5_ADDR ALT_USB_DEV_DIEPINT5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ5_ADDR ALT_USB_DEV_DIEPTSIZ5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA5_ADDR ALT_USB_DEV_DIEPDMA5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS5_ADDR ALT_USB_DEV_DTXFSTS5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB5_ADDR ALT_USB_DEV_DIEPDMAB5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL6_ADDR ALT_USB_DEV_DIEPCTL6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT6_ADDR ALT_USB_DEV_DIEPINT6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ6_ADDR ALT_USB_DEV_DIEPTSIZ6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA6_ADDR ALT_USB_DEV_DIEPDMA6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS6_ADDR ALT_USB_DEV_DTXFSTS6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB6_ADDR ALT_USB_DEV_DIEPDMAB6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL7_ADDR ALT_USB_DEV_DIEPCTL7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT7_ADDR ALT_USB_DEV_DIEPINT7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ7_ADDR ALT_USB_DEV_DIEPTSIZ7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA7_ADDR ALT_USB_DEV_DIEPDMA7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS7_ADDR ALT_USB_DEV_DTXFSTS7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB7_ADDR ALT_USB_DEV_DIEPDMAB7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL8_ADDR ALT_USB_DEV_DIEPCTL8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT8_ADDR ALT_USB_DEV_DIEPINT8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ8_ADDR ALT_USB_DEV_DIEPTSIZ8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA8_ADDR ALT_USB_DEV_DIEPDMA8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS8_ADDR ALT_USB_DEV_DTXFSTS8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB8_ADDR ALT_USB_DEV_DIEPDMAB8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL9_ADDR ALT_USB_DEV_DIEPCTL9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT9_ADDR ALT_USB_DEV_DIEPINT9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ9_ADDR ALT_USB_DEV_DIEPTSIZ9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA9_ADDR ALT_USB_DEV_DIEPDMA9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS9_ADDR ALT_USB_DEV_DTXFSTS9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB9_ADDR ALT_USB_DEV_DIEPDMAB9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL10_ADDR ALT_USB_DEV_DIEPCTL10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT10_ADDR ALT_USB_DEV_DIEPINT10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ10_ADDR ALT_USB_DEV_DIEPTSIZ10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA10_ADDR ALT_USB_DEV_DIEPDMA10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS10_ADDR ALT_USB_DEV_DTXFSTS10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB10_ADDR ALT_USB_DEV_DIEPDMAB10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL11_ADDR ALT_USB_DEV_DIEPCTL11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT11_ADDR ALT_USB_DEV_DIEPINT11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ11_ADDR ALT_USB_DEV_DIEPTSIZ11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA11_ADDR ALT_USB_DEV_DIEPDMA11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS11_ADDR ALT_USB_DEV_DTXFSTS11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB11_ADDR ALT_USB_DEV_DIEPDMAB11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL12_ADDR ALT_USB_DEV_DIEPCTL12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT12_ADDR ALT_USB_DEV_DIEPINT12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ12_ADDR ALT_USB_DEV_DIEPTSIZ12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA12_ADDR ALT_USB_DEV_DIEPDMA12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS12_ADDR ALT_USB_DEV_DTXFSTS12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB12_ADDR ALT_USB_DEV_DIEPDMAB12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL13_ADDR ALT_USB_DEV_DIEPCTL13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT13_ADDR ALT_USB_DEV_DIEPINT13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ13_ADDR ALT_USB_DEV_DIEPTSIZ13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA13_ADDR ALT_USB_DEV_DIEPDMA13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS13_ADDR ALT_USB_DEV_DTXFSTS13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB13_ADDR ALT_USB_DEV_DIEPDMAB13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL14_ADDR ALT_USB_DEV_DIEPCTL14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT14_ADDR ALT_USB_DEV_DIEPINT14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ14_ADDR ALT_USB_DEV_DIEPTSIZ14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA14_ADDR ALT_USB_DEV_DIEPDMA14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS14_ADDR ALT_USB_DEV_DTXFSTS14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB14_ADDR ALT_USB_DEV_DIEPDMAB14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPCTL15_ADDR ALT_USB_DEV_DIEPCTL15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPINT15_ADDR ALT_USB_DEV_DIEPINT15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPTSIZ15_ADDR ALT_USB_DEV_DIEPTSIZ15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMA15_ADDR ALT_USB_DEV_DIEPDMA15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DTXFSTS15_ADDR ALT_USB_DEV_DTXFSTS15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DIEPDMAB15_ADDR ALT_USB_DEV_DIEPDMAB15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL0_ADDR ALT_USB_DEV_DOEPCTL0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT0_ADDR ALT_USB_DEV_DOEPINT0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ0_ADDR ALT_USB_DEV_DOEPTSIZ0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA0_ADDR ALT_USB_DEV_DOEPDMA0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB0 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB0_ADDR ALT_USB_DEV_DOEPDMAB0_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL1_ADDR ALT_USB_DEV_DOEPCTL1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT1_ADDR ALT_USB_DEV_DOEPINT1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ1_ADDR ALT_USB_DEV_DOEPTSIZ1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA1_ADDR ALT_USB_DEV_DOEPDMA1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB1 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB1_ADDR ALT_USB_DEV_DOEPDMAB1_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL2_ADDR ALT_USB_DEV_DOEPCTL2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT2_ADDR ALT_USB_DEV_DOEPINT2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ2_ADDR ALT_USB_DEV_DOEPTSIZ2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA2_ADDR ALT_USB_DEV_DOEPDMA2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB2 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB2_ADDR ALT_USB_DEV_DOEPDMAB2_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL3_ADDR ALT_USB_DEV_DOEPCTL3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT3_ADDR ALT_USB_DEV_DOEPINT3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ3_ADDR ALT_USB_DEV_DOEPTSIZ3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA3_ADDR ALT_USB_DEV_DOEPDMA3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB3 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB3_ADDR ALT_USB_DEV_DOEPDMAB3_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL4_ADDR ALT_USB_DEV_DOEPCTL4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT4_ADDR ALT_USB_DEV_DOEPINT4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ4_ADDR ALT_USB_DEV_DOEPTSIZ4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA4_ADDR ALT_USB_DEV_DOEPDMA4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB4 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB4_ADDR ALT_USB_DEV_DOEPDMAB4_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL5_ADDR ALT_USB_DEV_DOEPCTL5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT5_ADDR ALT_USB_DEV_DOEPINT5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ5_ADDR ALT_USB_DEV_DOEPTSIZ5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA5_ADDR ALT_USB_DEV_DOEPDMA5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB5 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB5_ADDR ALT_USB_DEV_DOEPDMAB5_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL6_ADDR ALT_USB_DEV_DOEPCTL6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT6_ADDR ALT_USB_DEV_DOEPINT6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ6_ADDR ALT_USB_DEV_DOEPTSIZ6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA6_ADDR ALT_USB_DEV_DOEPDMA6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB6 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB6_ADDR ALT_USB_DEV_DOEPDMAB6_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL7_ADDR ALT_USB_DEV_DOEPCTL7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT7_ADDR ALT_USB_DEV_DOEPINT7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ7_ADDR ALT_USB_DEV_DOEPTSIZ7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA7_ADDR ALT_USB_DEV_DOEPDMA7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB7 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB7_ADDR ALT_USB_DEV_DOEPDMAB7_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL8_ADDR ALT_USB_DEV_DOEPCTL8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT8_ADDR ALT_USB_DEV_DOEPINT8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ8_ADDR ALT_USB_DEV_DOEPTSIZ8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA8_ADDR ALT_USB_DEV_DOEPDMA8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB8 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB8_ADDR ALT_USB_DEV_DOEPDMAB8_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL9_ADDR ALT_USB_DEV_DOEPCTL9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT9_ADDR ALT_USB_DEV_DOEPINT9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ9_ADDR ALT_USB_DEV_DOEPTSIZ9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA9_ADDR ALT_USB_DEV_DOEPDMA9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB9 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB9_ADDR ALT_USB_DEV_DOEPDMAB9_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL10_ADDR ALT_USB_DEV_DOEPCTL10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT10_ADDR ALT_USB_DEV_DOEPINT10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ10_ADDR ALT_USB_DEV_DOEPTSIZ10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA10_ADDR ALT_USB_DEV_DOEPDMA10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB10 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB10_ADDR ALT_USB_DEV_DOEPDMAB10_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL11_ADDR ALT_USB_DEV_DOEPCTL11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT11_ADDR ALT_USB_DEV_DOEPINT11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ11_ADDR ALT_USB_DEV_DOEPTSIZ11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA11_ADDR ALT_USB_DEV_DOEPDMA11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB11 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB11_ADDR ALT_USB_DEV_DOEPDMAB11_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL12_ADDR ALT_USB_DEV_DOEPCTL12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT12_ADDR ALT_USB_DEV_DOEPINT12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ12_ADDR ALT_USB_DEV_DOEPTSIZ12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA12_ADDR ALT_USB_DEV_DOEPDMA12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB12 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB12_ADDR ALT_USB_DEV_DOEPDMAB12_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL13_ADDR ALT_USB_DEV_DOEPCTL13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT13_ADDR ALT_USB_DEV_DOEPINT13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ13_ADDR ALT_USB_DEV_DOEPTSIZ13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA13_ADDR ALT_USB_DEV_DOEPDMA13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB13 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB13_ADDR ALT_USB_DEV_DOEPDMAB13_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL14_ADDR ALT_USB_DEV_DOEPCTL14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT14_ADDR ALT_USB_DEV_DOEPINT14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ14_ADDR ALT_USB_DEV_DOEPTSIZ14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA14_ADDR ALT_USB_DEV_DOEPDMA14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB14 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB14_ADDR ALT_USB_DEV_DOEPDMAB14_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPCTL15_ADDR ALT_USB_DEV_DOEPCTL15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPINT15_ADDR ALT_USB_DEV_DOEPINT15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPTSIZ15_ADDR ALT_USB_DEV_DOEPTSIZ15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMA15_ADDR ALT_USB_DEV_DOEPDMA15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB15 register for the ALT_USB0_DEVGRP instance. */ -#define ALT_USB0_DEV_DOEPDMAB15_ADDR ALT_USB_DEV_DOEPDMAB15_ADDR(ALT_USB0_DEVGRP_ADDR) -/* The base address byte offset for the start of the ALT_USB0_DEVGRP component. */ -#define ALT_USB0_DEVGRP_OFST 0x800 -/* The start address of the ALT_USB0_DEVGRP component. */ -#define ALT_USB0_DEVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_DEVGRP_OFST)) -/* The lower bound address range of the ALT_USB0_DEVGRP component. */ -#define ALT_USB0_DEVGRP_LB_ADDR ALT_USB0_DEVGRP_ADDR -/* The upper bound address range of the ALT_USB0_DEVGRP component. */ -#define ALT_USB0_DEVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_DEVGRP_ADDR) + 0x500) - 1)) - - -/* - * Register Group Instance : pwrclkgrp - * - * Instance pwrclkgrp of register group ALT_USB_PWRCLK. - * - * - */ -/* The address of the ALT_USB_PWRCLK_PCGCCTL register for the ALT_USB0_PWRCLKGRP instance. */ -#define ALT_USB0_PWRCLK_PCGCCTL_ADDR ALT_USB_PWRCLK_PCGCCTL_ADDR(ALT_USB0_PWRCLKGRP_ADDR) -/* The base address byte offset for the start of the ALT_USB0_PWRCLKGRP component. */ -#define ALT_USB0_PWRCLKGRP_OFST 0xe00 -/* The start address of the ALT_USB0_PWRCLKGRP component. */ -#define ALT_USB0_PWRCLKGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB0_ADDR) + ALT_USB0_PWRCLKGRP_OFST)) -/* The lower bound address range of the ALT_USB0_PWRCLKGRP component. */ -#define ALT_USB0_PWRCLKGRP_LB_ADDR ALT_USB0_PWRCLKGRP_ADDR -/* The upper bound address range of the ALT_USB0_PWRCLKGRP component. */ -#define ALT_USB0_PWRCLKGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_PWRCLKGRP_ADDR) + 0x4) - 1)) - - -/* The base address byte offset for the start of the ALT_USB0 component. */ -#define ALT_USB0_OFST 0xffb00000 -/* The start address of the ALT_USB0 component. */ -#define ALT_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_USB0_OFST)) -/* The lower bound address range of the ALT_USB0 component. */ -#define ALT_USB0_LB_ADDR ALT_USB0_ADDR -/* The upper bound address range of the ALT_USB0 component. */ -#define ALT_USB0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB0_ADDR) + 0x40000) - 1)) - - -/* - * Component Instance : usb1 - * - * Instance usb1 of component ALT_USB. - * - * - */ -/* - * Register Group Instance : globgrp - * - * Instance globgrp of register group ALT_USB_GLOB. - * - * - */ -/* The address of the ALT_USB_GLOB_GOTGCTL register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GOTGCTL_ADDR ALT_USB_GLOB_GOTGCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GOTGINT register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GOTGINT_ADDR ALT_USB_GLOB_GOTGINT_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GAHBCFG register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GAHBCFG_ADDR ALT_USB_GLOB_GAHBCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GUSBCFG register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GUSBCFG_ADDR ALT_USB_GLOB_GUSBCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GRSTCTL register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GRSTCTL_ADDR ALT_USB_GLOB_GRSTCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GINTSTS register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GINTSTS_ADDR ALT_USB_GLOB_GINTSTS_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GINTMSK register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GINTMSK_ADDR ALT_USB_GLOB_GINTMSK_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GRXSTSR register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GRXSTSR_ADDR ALT_USB_GLOB_GRXSTSR_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GRXSTSP register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GRXSTSP_ADDR ALT_USB_GLOB_GRXSTSP_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GRXFSIZ register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GRXFSIZ_ADDR ALT_USB_GLOB_GRXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GNPTXFSIZ register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GNPTXFSIZ_ADDR ALT_USB_GLOB_GNPTXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GNPTXSTS register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GNPTXSTS_ADDR ALT_USB_GLOB_GNPTXSTS_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GPVNDCTL register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GPVNDCTL_ADDR ALT_USB_GLOB_GPVNDCTL_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GGPIO register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GGPIO_ADDR ALT_USB_GLOB_GGPIO_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GUID register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GUID_ADDR ALT_USB_GLOB_GUID_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GSNPSID register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GSNPSID_ADDR ALT_USB_GLOB_GSNPSID_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GHWCFG1 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GHWCFG1_ADDR ALT_USB_GLOB_GHWCFG1_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GHWCFG2 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GHWCFG2_ADDR ALT_USB_GLOB_GHWCFG2_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GHWCFG3 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GHWCFG3_ADDR ALT_USB_GLOB_GHWCFG3_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GHWCFG4 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GHWCFG4_ADDR ALT_USB_GLOB_GHWCFG4_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_GDFIFOCFG register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_GDFIFOCFG_ADDR ALT_USB_GLOB_GDFIFOCFG_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_HPTXFSIZ register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_HPTXFSIZ_ADDR ALT_USB_GLOB_HPTXFSIZ_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF1 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF1_ADDR ALT_USB_GLOB_DIEPTXF1_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF2 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF2_ADDR ALT_USB_GLOB_DIEPTXF2_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF3 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF3_ADDR ALT_USB_GLOB_DIEPTXF3_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF4 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF4_ADDR ALT_USB_GLOB_DIEPTXF4_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF5 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF5_ADDR ALT_USB_GLOB_DIEPTXF5_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF6 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF6_ADDR ALT_USB_GLOB_DIEPTXF6_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF7 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF7_ADDR ALT_USB_GLOB_DIEPTXF7_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF8 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF8_ADDR ALT_USB_GLOB_DIEPTXF8_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF9 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF9_ADDR ALT_USB_GLOB_DIEPTXF9_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF10 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF10_ADDR ALT_USB_GLOB_DIEPTXF10_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF11 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF11_ADDR ALT_USB_GLOB_DIEPTXF11_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF12 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF12_ADDR ALT_USB_GLOB_DIEPTXF12_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF13 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF13_ADDR ALT_USB_GLOB_DIEPTXF13_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF14 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF14_ADDR ALT_USB_GLOB_DIEPTXF14_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The address of the ALT_USB_GLOB_DIEPTXF15 register for the ALT_USB1_GLOBGRP instance. */ -#define ALT_USB1_GLOB_DIEPTXF15_ADDR ALT_USB_GLOB_DIEPTXF15_ADDR(ALT_USB1_GLOBGRP_ADDR) -/* The base address byte offset for the start of the ALT_USB1_GLOBGRP component. */ -#define ALT_USB1_GLOBGRP_OFST 0x0 -/* The start address of the ALT_USB1_GLOBGRP component. */ -#define ALT_USB1_GLOBGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_GLOBGRP_OFST)) -/* The lower bound address range of the ALT_USB1_GLOBGRP component. */ -#define ALT_USB1_GLOBGRP_LB_ADDR ALT_USB1_GLOBGRP_ADDR -/* The upper bound address range of the ALT_USB1_GLOBGRP component. */ -#define ALT_USB1_GLOBGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_GLOBGRP_ADDR) + 0x140) - 1)) - - -/* - * Register Group Instance : hostgrp - * - * Instance hostgrp of register group ALT_USB_HOST. - * - * - */ -/* The address of the ALT_USB_HOST_HCFG register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCFG_ADDR ALT_USB_HOST_HCFG_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HFIR register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HFIR_ADDR ALT_USB_HOST_HFIR_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HFNUM register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HFNUM_ADDR ALT_USB_HOST_HFNUM_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HPTXSTS register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HPTXSTS_ADDR ALT_USB_HOST_HPTXSTS_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HAINT register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HAINT_ADDR ALT_USB_HOST_HAINT_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HAINTMSK register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HAINTMSK_ADDR ALT_USB_HOST_HAINTMSK_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HFLBADDR register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HFLBADDR_ADDR ALT_USB_HOST_HFLBADDR_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HPRT register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HPRT_ADDR ALT_USB_HOST_HPRT_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR0 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR0_ADDR ALT_USB_HOST_HCCHAR0_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT0 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT0_ADDR ALT_USB_HOST_HCSPLT0_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT0 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT0_ADDR ALT_USB_HOST_HCINT0_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK0 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK0_ADDR ALT_USB_HOST_HCINTMSK0_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ0 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ0_ADDR ALT_USB_HOST_HCTSIZ0_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA0 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA0_ADDR ALT_USB_HOST_HCDMA0_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB0 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB0_ADDR ALT_USB_HOST_HCDMAB0_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR1 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR1_ADDR ALT_USB_HOST_HCCHAR1_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT1 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT1_ADDR ALT_USB_HOST_HCSPLT1_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT1 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT1_ADDR ALT_USB_HOST_HCINT1_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK1 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK1_ADDR ALT_USB_HOST_HCINTMSK1_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ1 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ1_ADDR ALT_USB_HOST_HCTSIZ1_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA1 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA1_ADDR ALT_USB_HOST_HCDMA1_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB1 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB1_ADDR ALT_USB_HOST_HCDMAB1_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR2 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR2_ADDR ALT_USB_HOST_HCCHAR2_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT2 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT2_ADDR ALT_USB_HOST_HCSPLT2_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT2 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT2_ADDR ALT_USB_HOST_HCINT2_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK2 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK2_ADDR ALT_USB_HOST_HCINTMSK2_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ2 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ2_ADDR ALT_USB_HOST_HCTSIZ2_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA2 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA2_ADDR ALT_USB_HOST_HCDMA2_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB2 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB2_ADDR ALT_USB_HOST_HCDMAB2_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR3 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR3_ADDR ALT_USB_HOST_HCCHAR3_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT3 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT3_ADDR ALT_USB_HOST_HCSPLT3_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT3 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT3_ADDR ALT_USB_HOST_HCINT3_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK3 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK3_ADDR ALT_USB_HOST_HCINTMSK3_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ3 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ3_ADDR ALT_USB_HOST_HCTSIZ3_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA3 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA3_ADDR ALT_USB_HOST_HCDMA3_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB3 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB3_ADDR ALT_USB_HOST_HCDMAB3_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR4 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR4_ADDR ALT_USB_HOST_HCCHAR4_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT4 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT4_ADDR ALT_USB_HOST_HCSPLT4_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT4 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT4_ADDR ALT_USB_HOST_HCINT4_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK4 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK4_ADDR ALT_USB_HOST_HCINTMSK4_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ4 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ4_ADDR ALT_USB_HOST_HCTSIZ4_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA4 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA4_ADDR ALT_USB_HOST_HCDMA4_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB4 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB4_ADDR ALT_USB_HOST_HCDMAB4_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR5 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR5_ADDR ALT_USB_HOST_HCCHAR5_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT5 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT5_ADDR ALT_USB_HOST_HCSPLT5_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT5 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT5_ADDR ALT_USB_HOST_HCINT5_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK5 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK5_ADDR ALT_USB_HOST_HCINTMSK5_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ5 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ5_ADDR ALT_USB_HOST_HCTSIZ5_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA5 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA5_ADDR ALT_USB_HOST_HCDMA5_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB5 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB5_ADDR ALT_USB_HOST_HCDMAB5_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR6 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR6_ADDR ALT_USB_HOST_HCCHAR6_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT6 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT6_ADDR ALT_USB_HOST_HCSPLT6_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT6 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT6_ADDR ALT_USB_HOST_HCINT6_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK6 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK6_ADDR ALT_USB_HOST_HCINTMSK6_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ6 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ6_ADDR ALT_USB_HOST_HCTSIZ6_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA6 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA6_ADDR ALT_USB_HOST_HCDMA6_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB6 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB6_ADDR ALT_USB_HOST_HCDMAB6_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR7 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR7_ADDR ALT_USB_HOST_HCCHAR7_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT7 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT7_ADDR ALT_USB_HOST_HCSPLT7_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT7 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT7_ADDR ALT_USB_HOST_HCINT7_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK7 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK7_ADDR ALT_USB_HOST_HCINTMSK7_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ7 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ7_ADDR ALT_USB_HOST_HCTSIZ7_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA7 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA7_ADDR ALT_USB_HOST_HCDMA7_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB7 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB7_ADDR ALT_USB_HOST_HCDMAB7_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR8 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR8_ADDR ALT_USB_HOST_HCCHAR8_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT8 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT8_ADDR ALT_USB_HOST_HCSPLT8_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT8 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT8_ADDR ALT_USB_HOST_HCINT8_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK8 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK8_ADDR ALT_USB_HOST_HCINTMSK8_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ8 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ8_ADDR ALT_USB_HOST_HCTSIZ8_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA8 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA8_ADDR ALT_USB_HOST_HCDMA8_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB8 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB8_ADDR ALT_USB_HOST_HCDMAB8_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR9 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR9_ADDR ALT_USB_HOST_HCCHAR9_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT9 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT9_ADDR ALT_USB_HOST_HCSPLT9_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT9 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT9_ADDR ALT_USB_HOST_HCINT9_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK9 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK9_ADDR ALT_USB_HOST_HCINTMSK9_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ9 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ9_ADDR ALT_USB_HOST_HCTSIZ9_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA9 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA9_ADDR ALT_USB_HOST_HCDMA9_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB9 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB9_ADDR ALT_USB_HOST_HCDMAB9_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR10 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR10_ADDR ALT_USB_HOST_HCCHAR10_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT10 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT10_ADDR ALT_USB_HOST_HCSPLT10_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT10 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT10_ADDR ALT_USB_HOST_HCINT10_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK10 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK10_ADDR ALT_USB_HOST_HCINTMSK10_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ10 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ10_ADDR ALT_USB_HOST_HCTSIZ10_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA10 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA10_ADDR ALT_USB_HOST_HCDMA10_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB10 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB10_ADDR ALT_USB_HOST_HCDMAB10_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR11 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR11_ADDR ALT_USB_HOST_HCCHAR11_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT11 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT11_ADDR ALT_USB_HOST_HCSPLT11_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT11 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT11_ADDR ALT_USB_HOST_HCINT11_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK11 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK11_ADDR ALT_USB_HOST_HCINTMSK11_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ11 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ11_ADDR ALT_USB_HOST_HCTSIZ11_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA11 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA11_ADDR ALT_USB_HOST_HCDMA11_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB11 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB11_ADDR ALT_USB_HOST_HCDMAB11_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR12 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR12_ADDR ALT_USB_HOST_HCCHAR12_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT12 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT12_ADDR ALT_USB_HOST_HCSPLT12_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT12 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT12_ADDR ALT_USB_HOST_HCINT12_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK12 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK12_ADDR ALT_USB_HOST_HCINTMSK12_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ12 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ12_ADDR ALT_USB_HOST_HCTSIZ12_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA12 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA12_ADDR ALT_USB_HOST_HCDMA12_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB12 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB12_ADDR ALT_USB_HOST_HCDMAB12_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR13 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR13_ADDR ALT_USB_HOST_HCCHAR13_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT13 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT13_ADDR ALT_USB_HOST_HCSPLT13_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT13 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT13_ADDR ALT_USB_HOST_HCINT13_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK13 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK13_ADDR ALT_USB_HOST_HCINTMSK13_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ13 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ13_ADDR ALT_USB_HOST_HCTSIZ13_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA13 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA13_ADDR ALT_USB_HOST_HCDMA13_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB13 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB13_ADDR ALT_USB_HOST_HCDMAB13_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR14 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR14_ADDR ALT_USB_HOST_HCCHAR14_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT14 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT14_ADDR ALT_USB_HOST_HCSPLT14_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT14 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT14_ADDR ALT_USB_HOST_HCINT14_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK14 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK14_ADDR ALT_USB_HOST_HCINTMSK14_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ14 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ14_ADDR ALT_USB_HOST_HCTSIZ14_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA14 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA14_ADDR ALT_USB_HOST_HCDMA14_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB14 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB14_ADDR ALT_USB_HOST_HCDMAB14_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCCHAR15 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCCHAR15_ADDR ALT_USB_HOST_HCCHAR15_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCSPLT15 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCSPLT15_ADDR ALT_USB_HOST_HCSPLT15_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINT15 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINT15_ADDR ALT_USB_HOST_HCINT15_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCINTMSK15 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCINTMSK15_ADDR ALT_USB_HOST_HCINTMSK15_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCTSIZ15 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCTSIZ15_ADDR ALT_USB_HOST_HCTSIZ15_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMA15 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMA15_ADDR ALT_USB_HOST_HCDMA15_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The address of the ALT_USB_HOST_HCDMAB15 register for the ALT_USB1_HOSTGRP instance. */ -#define ALT_USB1_HOST_HCDMAB15_ADDR ALT_USB_HOST_HCDMAB15_ADDR(ALT_USB1_HOSTGRP_ADDR) -/* The base address byte offset for the start of the ALT_USB1_HOSTGRP component. */ -#define ALT_USB1_HOSTGRP_OFST 0x400 -/* The start address of the ALT_USB1_HOSTGRP component. */ -#define ALT_USB1_HOSTGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_HOSTGRP_OFST)) -/* The lower bound address range of the ALT_USB1_HOSTGRP component. */ -#define ALT_USB1_HOSTGRP_LB_ADDR ALT_USB1_HOSTGRP_ADDR -/* The upper bound address range of the ALT_USB1_HOSTGRP component. */ -#define ALT_USB1_HOSTGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_HOSTGRP_ADDR) + 0x2fc) - 1)) - - -/* - * Register Group Instance : devgrp - * - * Instance devgrp of register group ALT_USB_DEV. - * - * - */ -/* The address of the ALT_USB_DEV_DCFG register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DCFG_ADDR ALT_USB_DEV_DCFG_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DCTL register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DCTL_ADDR ALT_USB_DEV_DCTL_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DSTS register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DSTS_ADDR ALT_USB_DEV_DSTS_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPMSK register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPMSK_ADDR ALT_USB_DEV_DIEPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPMSK register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPMSK_ADDR ALT_USB_DEV_DOEPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DAINT register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DAINT_ADDR ALT_USB_DEV_DAINT_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DAINTMSK register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DAINTMSK_ADDR ALT_USB_DEV_DAINTMSK_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DVBUSDIS register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DVBUSDIS_ADDR ALT_USB_DEV_DVBUSDIS_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DVBUSPULSE register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DVBUSPULSE_ADDR ALT_USB_DEV_DVBUSPULSE_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTHRCTL register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTHRCTL_ADDR ALT_USB_DEV_DTHRCTL_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPEMPMSK register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPEMPMSK_ADDR ALT_USB_DEV_DIEPEMPMSK_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL0_ADDR ALT_USB_DEV_DIEPCTL0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT0_ADDR ALT_USB_DEV_DIEPINT0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ0_ADDR ALT_USB_DEV_DIEPTSIZ0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA0_ADDR ALT_USB_DEV_DIEPDMA0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS0_ADDR ALT_USB_DEV_DTXFSTS0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB0_ADDR ALT_USB_DEV_DIEPDMAB0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL1_ADDR ALT_USB_DEV_DIEPCTL1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT1_ADDR ALT_USB_DEV_DIEPINT1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ1_ADDR ALT_USB_DEV_DIEPTSIZ1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA1_ADDR ALT_USB_DEV_DIEPDMA1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS1_ADDR ALT_USB_DEV_DTXFSTS1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB1_ADDR ALT_USB_DEV_DIEPDMAB1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL2_ADDR ALT_USB_DEV_DIEPCTL2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT2_ADDR ALT_USB_DEV_DIEPINT2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ2_ADDR ALT_USB_DEV_DIEPTSIZ2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA2_ADDR ALT_USB_DEV_DIEPDMA2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS2_ADDR ALT_USB_DEV_DTXFSTS2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB2_ADDR ALT_USB_DEV_DIEPDMAB2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL3_ADDR ALT_USB_DEV_DIEPCTL3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT3_ADDR ALT_USB_DEV_DIEPINT3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ3_ADDR ALT_USB_DEV_DIEPTSIZ3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA3_ADDR ALT_USB_DEV_DIEPDMA3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS3_ADDR ALT_USB_DEV_DTXFSTS3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB3_ADDR ALT_USB_DEV_DIEPDMAB3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL4_ADDR ALT_USB_DEV_DIEPCTL4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT4_ADDR ALT_USB_DEV_DIEPINT4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ4_ADDR ALT_USB_DEV_DIEPTSIZ4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA4_ADDR ALT_USB_DEV_DIEPDMA4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS4_ADDR ALT_USB_DEV_DTXFSTS4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB4_ADDR ALT_USB_DEV_DIEPDMAB4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL5_ADDR ALT_USB_DEV_DIEPCTL5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT5_ADDR ALT_USB_DEV_DIEPINT5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ5_ADDR ALT_USB_DEV_DIEPTSIZ5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA5_ADDR ALT_USB_DEV_DIEPDMA5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS5_ADDR ALT_USB_DEV_DTXFSTS5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB5_ADDR ALT_USB_DEV_DIEPDMAB5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL6_ADDR ALT_USB_DEV_DIEPCTL6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT6_ADDR ALT_USB_DEV_DIEPINT6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ6_ADDR ALT_USB_DEV_DIEPTSIZ6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA6_ADDR ALT_USB_DEV_DIEPDMA6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS6_ADDR ALT_USB_DEV_DTXFSTS6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB6_ADDR ALT_USB_DEV_DIEPDMAB6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL7_ADDR ALT_USB_DEV_DIEPCTL7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT7_ADDR ALT_USB_DEV_DIEPINT7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ7_ADDR ALT_USB_DEV_DIEPTSIZ7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA7_ADDR ALT_USB_DEV_DIEPDMA7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS7_ADDR ALT_USB_DEV_DTXFSTS7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB7_ADDR ALT_USB_DEV_DIEPDMAB7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL8_ADDR ALT_USB_DEV_DIEPCTL8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT8_ADDR ALT_USB_DEV_DIEPINT8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ8_ADDR ALT_USB_DEV_DIEPTSIZ8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA8_ADDR ALT_USB_DEV_DIEPDMA8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS8_ADDR ALT_USB_DEV_DTXFSTS8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB8_ADDR ALT_USB_DEV_DIEPDMAB8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL9_ADDR ALT_USB_DEV_DIEPCTL9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT9_ADDR ALT_USB_DEV_DIEPINT9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ9_ADDR ALT_USB_DEV_DIEPTSIZ9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA9_ADDR ALT_USB_DEV_DIEPDMA9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS9_ADDR ALT_USB_DEV_DTXFSTS9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB9_ADDR ALT_USB_DEV_DIEPDMAB9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL10_ADDR ALT_USB_DEV_DIEPCTL10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT10_ADDR ALT_USB_DEV_DIEPINT10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ10_ADDR ALT_USB_DEV_DIEPTSIZ10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA10_ADDR ALT_USB_DEV_DIEPDMA10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS10_ADDR ALT_USB_DEV_DTXFSTS10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB10_ADDR ALT_USB_DEV_DIEPDMAB10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL11_ADDR ALT_USB_DEV_DIEPCTL11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT11_ADDR ALT_USB_DEV_DIEPINT11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ11_ADDR ALT_USB_DEV_DIEPTSIZ11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA11_ADDR ALT_USB_DEV_DIEPDMA11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS11_ADDR ALT_USB_DEV_DTXFSTS11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB11_ADDR ALT_USB_DEV_DIEPDMAB11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL12_ADDR ALT_USB_DEV_DIEPCTL12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT12_ADDR ALT_USB_DEV_DIEPINT12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ12_ADDR ALT_USB_DEV_DIEPTSIZ12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA12_ADDR ALT_USB_DEV_DIEPDMA12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS12_ADDR ALT_USB_DEV_DTXFSTS12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB12_ADDR ALT_USB_DEV_DIEPDMAB12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL13_ADDR ALT_USB_DEV_DIEPCTL13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT13_ADDR ALT_USB_DEV_DIEPINT13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ13_ADDR ALT_USB_DEV_DIEPTSIZ13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA13_ADDR ALT_USB_DEV_DIEPDMA13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS13_ADDR ALT_USB_DEV_DTXFSTS13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB13_ADDR ALT_USB_DEV_DIEPDMAB13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL14_ADDR ALT_USB_DEV_DIEPCTL14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT14_ADDR ALT_USB_DEV_DIEPINT14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ14_ADDR ALT_USB_DEV_DIEPTSIZ14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA14_ADDR ALT_USB_DEV_DIEPDMA14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS14_ADDR ALT_USB_DEV_DTXFSTS14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB14_ADDR ALT_USB_DEV_DIEPDMAB14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPCTL15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPCTL15_ADDR ALT_USB_DEV_DIEPCTL15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPINT15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPINT15_ADDR ALT_USB_DEV_DIEPINT15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPTSIZ15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPTSIZ15_ADDR ALT_USB_DEV_DIEPTSIZ15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMA15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMA15_ADDR ALT_USB_DEV_DIEPDMA15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DTXFSTS15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DTXFSTS15_ADDR ALT_USB_DEV_DTXFSTS15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DIEPDMAB15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DIEPDMAB15_ADDR ALT_USB_DEV_DIEPDMAB15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL0_ADDR ALT_USB_DEV_DOEPCTL0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT0_ADDR ALT_USB_DEV_DOEPINT0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ0_ADDR ALT_USB_DEV_DOEPTSIZ0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA0_ADDR ALT_USB_DEV_DOEPDMA0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB0 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB0_ADDR ALT_USB_DEV_DOEPDMAB0_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL1_ADDR ALT_USB_DEV_DOEPCTL1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT1_ADDR ALT_USB_DEV_DOEPINT1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ1_ADDR ALT_USB_DEV_DOEPTSIZ1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA1_ADDR ALT_USB_DEV_DOEPDMA1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB1 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB1_ADDR ALT_USB_DEV_DOEPDMAB1_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL2_ADDR ALT_USB_DEV_DOEPCTL2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT2_ADDR ALT_USB_DEV_DOEPINT2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ2_ADDR ALT_USB_DEV_DOEPTSIZ2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA2_ADDR ALT_USB_DEV_DOEPDMA2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB2 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB2_ADDR ALT_USB_DEV_DOEPDMAB2_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL3_ADDR ALT_USB_DEV_DOEPCTL3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT3_ADDR ALT_USB_DEV_DOEPINT3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ3_ADDR ALT_USB_DEV_DOEPTSIZ3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA3_ADDR ALT_USB_DEV_DOEPDMA3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB3 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB3_ADDR ALT_USB_DEV_DOEPDMAB3_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL4_ADDR ALT_USB_DEV_DOEPCTL4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT4_ADDR ALT_USB_DEV_DOEPINT4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ4_ADDR ALT_USB_DEV_DOEPTSIZ4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA4_ADDR ALT_USB_DEV_DOEPDMA4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB4 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB4_ADDR ALT_USB_DEV_DOEPDMAB4_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL5_ADDR ALT_USB_DEV_DOEPCTL5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT5_ADDR ALT_USB_DEV_DOEPINT5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ5_ADDR ALT_USB_DEV_DOEPTSIZ5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA5_ADDR ALT_USB_DEV_DOEPDMA5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB5 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB5_ADDR ALT_USB_DEV_DOEPDMAB5_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL6_ADDR ALT_USB_DEV_DOEPCTL6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT6_ADDR ALT_USB_DEV_DOEPINT6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ6_ADDR ALT_USB_DEV_DOEPTSIZ6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA6_ADDR ALT_USB_DEV_DOEPDMA6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB6 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB6_ADDR ALT_USB_DEV_DOEPDMAB6_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL7_ADDR ALT_USB_DEV_DOEPCTL7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT7_ADDR ALT_USB_DEV_DOEPINT7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ7_ADDR ALT_USB_DEV_DOEPTSIZ7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA7_ADDR ALT_USB_DEV_DOEPDMA7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB7 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB7_ADDR ALT_USB_DEV_DOEPDMAB7_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL8_ADDR ALT_USB_DEV_DOEPCTL8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT8_ADDR ALT_USB_DEV_DOEPINT8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ8_ADDR ALT_USB_DEV_DOEPTSIZ8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA8_ADDR ALT_USB_DEV_DOEPDMA8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB8 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB8_ADDR ALT_USB_DEV_DOEPDMAB8_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL9_ADDR ALT_USB_DEV_DOEPCTL9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT9_ADDR ALT_USB_DEV_DOEPINT9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ9_ADDR ALT_USB_DEV_DOEPTSIZ9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA9_ADDR ALT_USB_DEV_DOEPDMA9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB9 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB9_ADDR ALT_USB_DEV_DOEPDMAB9_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL10_ADDR ALT_USB_DEV_DOEPCTL10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT10_ADDR ALT_USB_DEV_DOEPINT10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ10_ADDR ALT_USB_DEV_DOEPTSIZ10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA10_ADDR ALT_USB_DEV_DOEPDMA10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB10 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB10_ADDR ALT_USB_DEV_DOEPDMAB10_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL11_ADDR ALT_USB_DEV_DOEPCTL11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT11_ADDR ALT_USB_DEV_DOEPINT11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ11_ADDR ALT_USB_DEV_DOEPTSIZ11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA11_ADDR ALT_USB_DEV_DOEPDMA11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB11 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB11_ADDR ALT_USB_DEV_DOEPDMAB11_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL12_ADDR ALT_USB_DEV_DOEPCTL12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT12_ADDR ALT_USB_DEV_DOEPINT12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ12_ADDR ALT_USB_DEV_DOEPTSIZ12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA12_ADDR ALT_USB_DEV_DOEPDMA12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB12 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB12_ADDR ALT_USB_DEV_DOEPDMAB12_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL13_ADDR ALT_USB_DEV_DOEPCTL13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT13_ADDR ALT_USB_DEV_DOEPINT13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ13_ADDR ALT_USB_DEV_DOEPTSIZ13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA13_ADDR ALT_USB_DEV_DOEPDMA13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB13 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB13_ADDR ALT_USB_DEV_DOEPDMAB13_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL14_ADDR ALT_USB_DEV_DOEPCTL14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT14_ADDR ALT_USB_DEV_DOEPINT14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ14_ADDR ALT_USB_DEV_DOEPTSIZ14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA14_ADDR ALT_USB_DEV_DOEPDMA14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB14 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB14_ADDR ALT_USB_DEV_DOEPDMAB14_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPCTL15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPCTL15_ADDR ALT_USB_DEV_DOEPCTL15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPINT15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPINT15_ADDR ALT_USB_DEV_DOEPINT15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPTSIZ15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPTSIZ15_ADDR ALT_USB_DEV_DOEPTSIZ15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMA15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMA15_ADDR ALT_USB_DEV_DOEPDMA15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The address of the ALT_USB_DEV_DOEPDMAB15 register for the ALT_USB1_DEVGRP instance. */ -#define ALT_USB1_DEV_DOEPDMAB15_ADDR ALT_USB_DEV_DOEPDMAB15_ADDR(ALT_USB1_DEVGRP_ADDR) -/* The base address byte offset for the start of the ALT_USB1_DEVGRP component. */ -#define ALT_USB1_DEVGRP_OFST 0x800 -/* The start address of the ALT_USB1_DEVGRP component. */ -#define ALT_USB1_DEVGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_DEVGRP_OFST)) -/* The lower bound address range of the ALT_USB1_DEVGRP component. */ -#define ALT_USB1_DEVGRP_LB_ADDR ALT_USB1_DEVGRP_ADDR -/* The upper bound address range of the ALT_USB1_DEVGRP component. */ -#define ALT_USB1_DEVGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_DEVGRP_ADDR) + 0x500) - 1)) - - -/* - * Register Group Instance : pwrclkgrp - * - * Instance pwrclkgrp of register group ALT_USB_PWRCLK. - * - * - */ -/* The address of the ALT_USB_PWRCLK_PCGCCTL register for the ALT_USB1_PWRCLKGRP instance. */ -#define ALT_USB1_PWRCLK_PCGCCTL_ADDR ALT_USB_PWRCLK_PCGCCTL_ADDR(ALT_USB1_PWRCLKGRP_ADDR) -/* The base address byte offset for the start of the ALT_USB1_PWRCLKGRP component. */ -#define ALT_USB1_PWRCLKGRP_OFST 0xe00 -/* The start address of the ALT_USB1_PWRCLKGRP component. */ -#define ALT_USB1_PWRCLKGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_USB1_ADDR) + ALT_USB1_PWRCLKGRP_OFST)) -/* The lower bound address range of the ALT_USB1_PWRCLKGRP component. */ -#define ALT_USB1_PWRCLKGRP_LB_ADDR ALT_USB1_PWRCLKGRP_ADDR -/* The upper bound address range of the ALT_USB1_PWRCLKGRP component. */ -#define ALT_USB1_PWRCLKGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_PWRCLKGRP_ADDR) + 0x4) - 1)) - - -/* The base address byte offset for the start of the ALT_USB1 component. */ -#define ALT_USB1_OFST 0xffb40000 -/* The start address of the ALT_USB1 component. */ -#define ALT_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_USB1_OFST)) -/* The lower bound address range of the ALT_USB1 component. */ -#define ALT_USB1_LB_ADDR ALT_USB1_ADDR -/* The upper bound address range of the ALT_USB1 component. */ -#define ALT_USB1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_USB1_ADDR) + 0x40000) - 1)) - - -/* - * Component Instance : nandregs - * - * Instance nandregs of component ALT_NAND. - * - * - */ -/* - * Register Group Instance : config - * - * Instance config of register group ALT_NAND_CFG. - * - * - */ -/* The address of the ALT_NAND_CFG_DEVICE_RST register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_DEVICE_RST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_RST_OFST)) -/* The address of the ALT_NAND_CFG_TFR_SPARE_REG register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_TFR_SPARE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TFR_SPARE_REG_OFST)) -/* The address of the ALT_NAND_CFG_LD_WAIT_CNT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_LD_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_LD_WAIT_CNT_OFST)) -/* The address of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST)) -/* The address of the ALT_NAND_CFG_ERASE_WAIT_CNT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_ERASE_WAIT_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ERASE_WAIT_CNT_OFST)) -/* The address of the ALT_NAND_CFG_INT_MON_CYCCNT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_INT_MON_CYCCNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_INT_MON_CYCCNT_OFST)) -/* The address of the ALT_NAND_CFG_RB_PIN_END register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_RB_PIN_END_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RB_PIN_END_OFST)) -/* The address of the ALT_NAND_CFG_MULTIPLANE_OP register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_MULTIPLANE_OP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_OP_OFST)) -/* The address of the ALT_NAND_CFG_MULTIPLANE_RD_EN register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_MULTIPLANE_RD_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST)) -/* The address of the ALT_NAND_CFG_COPYBACK_DIS register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_COPYBACK_DIS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_COPYBACK_DIS_OFST)) -/* The address of the ALT_NAND_CFG_CACHE_WR_EN register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_CACHE_WR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CACHE_WR_EN_OFST)) -/* The address of the ALT_NAND_CFG_CACHE_RD_EN register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_CACHE_RD_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CACHE_RD_EN_OFST)) -/* The address of the ALT_NAND_CFG_PREFETCH_MOD register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_PREFETCH_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PREFETCH_MOD_OFST)) -/* The address of the ALT_NAND_CFG_CHIP_EN_DONT_CARE register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST)) -/* The address of the ALT_NAND_CFG_ECC_EN register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_ECC_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ECC_EN_OFST)) -/* The address of the ALT_NAND_CFG_GLOB_INT_EN register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_GLOB_INT_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_GLOB_INT_EN_OFST)) -/* The address of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST)) -/* The address of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST)) -/* The address of the ALT_NAND_CFG_RE_2_WE register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_RE_2_WE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RE_2_WE_OFST)) -/* The address of the ALT_NAND_CFG_ACC_CLKS register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_ACC_CLKS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ACC_CLKS_OFST)) -/* The address of the ALT_NAND_CFG_NUMBER_OF_PLANES register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_NUMBER_OF_PLANES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_NUMBER_OF_PLANES_OFST)) -/* The address of the ALT_NAND_CFG_PAGES_PER_BLOCK register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_PAGES_PER_BLOCK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_PAGES_PER_BLOCK_OFST)) -/* The address of the ALT_NAND_CFG_DEVICE_WIDTH register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_DEVICE_WIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_WIDTH_OFST)) -/* The address of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST)) -/* The address of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST)) -/* The address of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST)) -/* The address of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST)) -/* The address of the ALT_NAND_CFG_ECC_CORRECTION register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_ECC_CORRECTION_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_ECC_CORRECTION_OFST)) -/* The address of the ALT_NAND_CFG_RD_MOD register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_RD_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RD_MOD_OFST)) -/* The address of the ALT_NAND_CFG_WR_MOD register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_WR_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WR_MOD_OFST)) -/* The address of the ALT_NAND_CFG_COPYBACK_MOD register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_COPYBACK_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_COPYBACK_MOD_OFST)) -/* The address of the ALT_NAND_CFG_RDWR_EN_LO_CNT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_RDWR_EN_LO_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST)) -/* The address of the ALT_NAND_CFG_RDWR_EN_HI_CNT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_RDWR_EN_HI_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST)) -/* The address of the ALT_NAND_CFG_MAX_RD_DELAY register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_MAX_RD_DELAY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_MAX_RD_DELAY_OFST)) -/* The address of the ALT_NAND_CFG_CS_SETUP_CNT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_CS_SETUP_CNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_CS_SETUP_CNT_OFST)) -/* The address of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST)) -/* The address of the ALT_NAND_CFG_SPARE_AREA_MARKER register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_SPARE_AREA_MARKER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_SPARE_AREA_MARKER_OFST)) -/* The address of the ALT_NAND_CFG_DEVICES_CONNECTED register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_DEVICES_CONNECTED_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DEVICES_CONNECTED_OFST)) -/* The address of the ALT_NAND_CFG_DIE_MSK register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_DIE_MSK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_DIE_MSK_OFST)) -/* The address of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST)) -/* The address of the ALT_NAND_CFG_WR_PROTECT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_WR_PROTECT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WR_PROTECT_OFST)) -/* The address of the ALT_NAND_CFG_RE_2_RE register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_RE_2_RE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_RE_2_RE_OFST)) -/* The address of the ALT_NAND_CFG_POR_RST_COUNT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_POR_RST_COUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_POR_RST_COUNT_OFST)) -/* The address of the ALT_NAND_CFG_WD_RST_COUNT register for the ALT_NAND_CFG instance. */ -#define ALT_NAND_CFG_WD_RST_COUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_CFG_ADDR) + ALT_NAND_CFG_WD_RST_COUNT_OFST)) -/* The base address byte offset for the start of the ALT_NAND_CFG component. */ -#define ALT_NAND_CFG_OFST 0x0 -/* The start address of the ALT_NAND_CFG component. */ -#define ALT_NAND_CFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_CFG_OFST)) -/* The lower bound address range of the ALT_NAND_CFG component. */ -#define ALT_NAND_CFG_LB_ADDR ALT_NAND_CFG_ADDR -/* The upper bound address range of the ALT_NAND_CFG component. */ -#define ALT_NAND_CFG_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_CFG_ADDR) + 0x2b4) - 1)) - - -/* - * Register Group Instance : param - * - * Instance param of register group ALT_NAND_PARAM. - * - * - */ -/* The address of the ALT_NAND_PARAM_MANUFACTURER_ID register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_MANUFACTURER_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_MANUFACTURER_ID_OFST)) -/* The address of the ALT_NAND_PARAM_DEVICE_ID register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_DEVICE_ID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_ID_OFST)) -/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_0 register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_DEVICE_PARAM_0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_0_OFST)) -/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_1 register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_DEVICE_PARAM_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_1_OFST)) -/* The address of the ALT_NAND_PARAM_DEVICE_PARAM_2 register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_DEVICE_PARAM_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_DEVICE_PARAM_2_OFST)) -/* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST)) -/* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST)) -/* The address of the ALT_NAND_PARAM_REVISION register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_REVISION_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_REVISION_OFST)) -/* The address of the ALT_NAND_PARAM_ONFI_DEV_FEATURES register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST)) -/* The address of the ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST)) -/* The address of the ALT_NAND_PARAM_ONFI_TIMING_MOD register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_ONFI_TIMING_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST)) -/* The address of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST)) -/* The address of the ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST)) -/* The address of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST)) -/* The address of the ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST)) -/* The address of the ALT_NAND_PARAM_FEATURES register for the ALT_NAND_PARAM instance. */ -#define ALT_NAND_PARAM_FEATURES_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + ALT_NAND_PARAM_FEATURES_OFST)) -/* The base address byte offset for the start of the ALT_NAND_PARAM component. */ -#define ALT_NAND_PARAM_OFST 0x300 -/* The start address of the ALT_NAND_PARAM component. */ -#define ALT_NAND_PARAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_PARAM_OFST)) -/* The lower bound address range of the ALT_NAND_PARAM component. */ -#define ALT_NAND_PARAM_LB_ADDR ALT_NAND_PARAM_ADDR -/* The upper bound address range of the ALT_NAND_PARAM component. */ -#define ALT_NAND_PARAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_PARAM_ADDR) + 0xf4) - 1)) - - -/* - * Register Group Instance : status - * - * Instance status of register group ALT_NAND_STAT. - * - * - */ -/* The address of the ALT_NAND_STAT_TFR_MOD register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_TFR_MOD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_TFR_MOD_OFST)) -/* The address of the ALT_NAND_STAT_INTR_STAT0 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_INTR_STAT0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT0_OFST)) -/* The address of the ALT_NAND_STAT_INTR_EN0 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_INTR_EN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN0_OFST)) -/* The address of the ALT_NAND_STAT_PAGE_CNT0 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_PAGE_CNT0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT0_OFST)) -/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_ERR_PAGE_ADDR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST)) -/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST)) -/* The address of the ALT_NAND_STAT_INTR_STAT1 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_INTR_STAT1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT1_OFST)) -/* The address of the ALT_NAND_STAT_INTR_EN1 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_INTR_EN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN1_OFST)) -/* The address of the ALT_NAND_STAT_PAGE_CNT1 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_PAGE_CNT1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT1_OFST)) -/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_ERR_PAGE_ADDR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST)) -/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST)) -/* The address of the ALT_NAND_STAT_INTR_STAT2 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_INTR_STAT2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT2_OFST)) -/* The address of the ALT_NAND_STAT_INTR_EN2 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_INTR_EN2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN2_OFST)) -/* The address of the ALT_NAND_STAT_PAGE_CNT2 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_PAGE_CNT2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT2_OFST)) -/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_ERR_PAGE_ADDR2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST)) -/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST)) -/* The address of the ALT_NAND_STAT_INTR_STAT3 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_INTR_STAT3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_STAT3_OFST)) -/* The address of the ALT_NAND_STAT_INTR_EN3 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_INTR_EN3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_INTR_EN3_OFST)) -/* The address of the ALT_NAND_STAT_PAGE_CNT3 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_PAGE_CNT3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_PAGE_CNT3_OFST)) -/* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_ERR_PAGE_ADDR3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST)) -/* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register for the ALT_NAND_STAT instance. */ -#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_STAT_ADDR) + ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST)) -/* The base address byte offset for the start of the ALT_NAND_STAT component. */ -#define ALT_NAND_STAT_OFST 0x400 -/* The start address of the ALT_NAND_STAT component. */ -#define ALT_NAND_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_STAT_OFST)) -/* The lower bound address range of the ALT_NAND_STAT component. */ -#define ALT_NAND_STAT_LB_ADDR ALT_NAND_STAT_ADDR -/* The upper bound address range of the ALT_NAND_STAT component. */ -#define ALT_NAND_STAT_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_STAT_ADDR) + 0x144) - 1)) - - -/* - * Register Group Instance : ecc - * - * Instance ecc of register group ALT_NAND_ECC. - * - * - */ -/* The address of the ALT_NAND_ECC_ECCCORINFO_B01 register for the ALT_NAND_ECC instance. */ -#define ALT_NAND_ECC_ECCCORINFO_B01_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ECC_ADDR) + ALT_NAND_ECC_ECCCORINFO_B01_OFST)) -/* The address of the ALT_NAND_ECC_ECCCORINFO_B23 register for the ALT_NAND_ECC instance. */ -#define ALT_NAND_ECC_ECCCORINFO_B23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ECC_ADDR) + ALT_NAND_ECC_ECCCORINFO_B23_OFST)) -/* The base address byte offset for the start of the ALT_NAND_ECC component. */ -#define ALT_NAND_ECC_OFST 0x650 -/* The start address of the ALT_NAND_ECC component. */ -#define ALT_NAND_ECC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_ECC_OFST)) -/* The lower bound address range of the ALT_NAND_ECC component. */ -#define ALT_NAND_ECC_LB_ADDR ALT_NAND_ECC_ADDR -/* The upper bound address range of the ALT_NAND_ECC component. */ -#define ALT_NAND_ECC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_ECC_ADDR) + 0x14) - 1)) - - -/* - * Register Group Instance : dma - * - * Instance dma of register group ALT_NAND_DMA. - * - * - */ -/* The address of the ALT_NAND_DMA_DMA_EN register for the ALT_NAND_DMA instance. */ -#define ALT_NAND_DMA_DMA_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_EN_OFST)) -/* The address of the ALT_NAND_DMA_DMA_INTR register for the ALT_NAND_DMA instance. */ -#define ALT_NAND_DMA_DMA_INTR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_INTR_OFST)) -/* The address of the ALT_NAND_DMA_DMA_INTR_EN register for the ALT_NAND_DMA instance. */ -#define ALT_NAND_DMA_DMA_INTR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_DMA_INTR_EN_OFST)) -/* The address of the ALT_NAND_DMA_TGT_ERR_ADDR_LO register for the ALT_NAND_DMA instance. */ -#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST)) -/* The address of the ALT_NAND_DMA_TGT_ERR_ADDR_HI register for the ALT_NAND_DMA instance. */ -#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST)) -/* The address of the ALT_NAND_DMA_FLSH_BURST_LEN register for the ALT_NAND_DMA instance. */ -#define ALT_NAND_DMA_FLSH_BURST_LEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_FLSH_BURST_LEN_OFST)) -/* The address of the ALT_NAND_DMA_INTRLV register for the ALT_NAND_DMA instance. */ -#define ALT_NAND_DMA_INTRLV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_INTRLV_OFST)) -/* The address of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register for the ALT_NAND_DMA instance. */ -#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST)) -/* The address of the ALT_NAND_DMA_LUN_STAT_CMD register for the ALT_NAND_DMA instance. */ -#define ALT_NAND_DMA_LUN_STAT_CMD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_DMA_ADDR) + ALT_NAND_DMA_LUN_STAT_CMD_OFST)) -/* The base address byte offset for the start of the ALT_NAND_DMA component. */ -#define ALT_NAND_DMA_OFST 0x700 -/* The start address of the ALT_NAND_DMA component. */ -#define ALT_NAND_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_NAND_ADDR) + ALT_NAND_DMA_OFST)) -/* The lower bound address range of the ALT_NAND_DMA component. */ -#define ALT_NAND_DMA_LB_ADDR ALT_NAND_DMA_ADDR -/* The upper bound address range of the ALT_NAND_DMA component. */ -#define ALT_NAND_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_DMA_ADDR) + 0xa4) - 1)) - - -/* The base address byte offset for the start of the ALT_NAND component. */ -#define ALT_NAND_OFST 0xffb80000 -/* The start address of the ALT_NAND component. */ -#define ALT_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_NAND_OFST)) -/* The lower bound address range of the ALT_NAND component. */ -#define ALT_NAND_LB_ADDR ALT_NAND_ADDR -/* The upper bound address range of the ALT_NAND component. */ -#define ALT_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_NAND_ADDR) + 0x800) - 1)) - - -/* - * Component Instance : fpgamgrdata - * - * Instance fpgamgrdata of component ALT_FPGAMGRDATA. - * - * - */ -/* The address of the ALT_FPGAMGRDATA_DATA register for the ALT_FPGAMGRDATA instance. */ -#define ALT_FPGAMGRDATA_DATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_FPGAMGRDATA_ADDR) + ALT_FPGAMGRDATA_DATA_OFST)) -/* The base address byte offset for the start of the ALT_FPGAMGRDATA component. */ -#define ALT_FPGAMGRDATA_OFST 0xffb90000 -/* The start address of the ALT_FPGAMGRDATA component. */ -#define ALT_FPGAMGRDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_FPGAMGRDATA_OFST)) -/* The lower bound address range of the ALT_FPGAMGRDATA component. */ -#define ALT_FPGAMGRDATA_LB_ADDR ALT_FPGAMGRDATA_ADDR -/* The upper bound address range of the ALT_FPGAMGRDATA component. */ -#define ALT_FPGAMGRDATA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_FPGAMGRDATA_ADDR) + 0x4) - 1)) - - -/* - * Component Instance : can0 - * - * Instance can0 of component ALT_CAN. - * - * - */ -/* - * Register Group Instance : protogrp - * - * Instance protogrp of register group ALT_CAN_PROTO. - * - * - */ -/* The address of the ALT_CAN_PROTO_CCTL register for the ALT_CAN0_PROTOGRP instance. */ -#define ALT_CAN0_PROTO_CCTL_ADDR ALT_CAN_PROTO_CCTL_ADDR(ALT_CAN0_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CSTS register for the ALT_CAN0_PROTOGRP instance. */ -#define ALT_CAN0_PROTO_CSTS_ADDR ALT_CAN_PROTO_CSTS_ADDR(ALT_CAN0_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CERC register for the ALT_CAN0_PROTOGRP instance. */ -#define ALT_CAN0_PROTO_CERC_ADDR ALT_CAN_PROTO_CERC_ADDR(ALT_CAN0_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CBT register for the ALT_CAN0_PROTOGRP instance. */ -#define ALT_CAN0_PROTO_CBT_ADDR ALT_CAN_PROTO_CBT_ADDR(ALT_CAN0_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CIR register for the ALT_CAN0_PROTOGRP instance. */ -#define ALT_CAN0_PROTO_CIR_ADDR ALT_CAN_PROTO_CIR_ADDR(ALT_CAN0_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CTR register for the ALT_CAN0_PROTOGRP instance. */ -#define ALT_CAN0_PROTO_CTR_ADDR ALT_CAN_PROTO_CTR_ADDR(ALT_CAN0_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CFR register for the ALT_CAN0_PROTOGRP instance. */ -#define ALT_CAN0_PROTO_CFR_ADDR ALT_CAN_PROTO_CFR_ADDR(ALT_CAN0_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CRR register for the ALT_CAN0_PROTOGRP instance. */ -#define ALT_CAN0_PROTO_CRR_ADDR ALT_CAN_PROTO_CRR_ADDR(ALT_CAN0_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_HWS register for the ALT_CAN0_PROTOGRP instance. */ -#define ALT_CAN0_PROTO_HWS_ADDR ALT_CAN_PROTO_HWS_ADDR(ALT_CAN0_PROTOGRP_ADDR) -/* The base address byte offset for the start of the ALT_CAN0_PROTOGRP component. */ -#define ALT_CAN0_PROTOGRP_OFST 0x0 -/* The start address of the ALT_CAN0_PROTOGRP component. */ -#define ALT_CAN0_PROTOGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_PROTOGRP_OFST)) -/* The lower bound address range of the ALT_CAN0_PROTOGRP component. */ -#define ALT_CAN0_PROTOGRP_LB_ADDR ALT_CAN0_PROTOGRP_ADDR -/* The upper bound address range of the ALT_CAN0_PROTOGRP component. */ -#define ALT_CAN0_PROTOGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_PROTOGRP_ADDR) + 0x28) - 1)) - - -/* - * Register Group Instance : msghandgrp - * - * Instance msghandgrp of register group ALT_CAN_MSGHAND. - * - * - */ -/* The address of the ALT_CAN_MSGHAND_MOTRX register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOTRX_ADDR ALT_CAN_MSGHAND_MOTRX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOTRA register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOTRA_ADDR ALT_CAN_MSGHAND_MOTRA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOTRB register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOTRB_ADDR ALT_CAN_MSGHAND_MOTRB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOTRC register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOTRC_ADDR ALT_CAN_MSGHAND_MOTRC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOTRD register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOTRD_ADDR ALT_CAN_MSGHAND_MOTRD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDX register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MONDX_ADDR ALT_CAN_MSGHAND_MONDX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDA register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MONDA_ADDR ALT_CAN_MSGHAND_MONDA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDB register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MONDB_ADDR ALT_CAN_MSGHAND_MONDB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDC register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MONDC_ADDR ALT_CAN_MSGHAND_MONDC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDD register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MONDD_ADDR ALT_CAN_MSGHAND_MONDD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPX register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOIPX_ADDR ALT_CAN_MSGHAND_MOIPX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPA register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOIPA_ADDR ALT_CAN_MSGHAND_MOIPA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPB register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOIPB_ADDR ALT_CAN_MSGHAND_MOIPB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPC register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOIPC_ADDR ALT_CAN_MSGHAND_MOIPC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPD register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOIPD_ADDR ALT_CAN_MSGHAND_MOIPD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALX register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOVALX_ADDR ALT_CAN_MSGHAND_MOVALX_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALA register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOVALA_ADDR ALT_CAN_MSGHAND_MOVALA_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALB register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOVALB_ADDR ALT_CAN_MSGHAND_MOVALB_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALC register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOVALC_ADDR ALT_CAN_MSGHAND_MOVALC_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALD register for the ALT_CAN0_MSGHANDGRP instance. */ -#define ALT_CAN0_MSGHAND_MOVALD_ADDR ALT_CAN_MSGHAND_MOVALD_ADDR(ALT_CAN0_MSGHANDGRP_ADDR) -/* The base address byte offset for the start of the ALT_CAN0_MSGHANDGRP component. */ -#define ALT_CAN0_MSGHANDGRP_OFST 0x84 -/* The start address of the ALT_CAN0_MSGHANDGRP component. */ -#define ALT_CAN0_MSGHANDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_MSGHANDGRP_OFST)) -/* The lower bound address range of the ALT_CAN0_MSGHANDGRP component. */ -#define ALT_CAN0_MSGHANDGRP_LB_ADDR ALT_CAN0_MSGHANDGRP_ADDR -/* The upper bound address range of the ALT_CAN0_MSGHANDGRP component. */ -#define ALT_CAN0_MSGHANDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_MSGHANDGRP_ADDR) + 0x50) - 1)) - - -/* - * Register Group Instance : msgifgrp - * - * Instance msgifgrp of register group ALT_CAN_MSGIF. - * - * - */ -/* The address of the ALT_CAN_MSGIF_IF1CMR register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF1CMR_ADDR ALT_CAN_MSGIF_IF1CMR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1MSK register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF1MSK_ADDR ALT_CAN_MSGIF_IF1MSK_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1ARB register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF1ARB_ADDR ALT_CAN_MSGIF_IF1ARB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1MCTR register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF1MCTR_ADDR ALT_CAN_MSGIF_IF1MCTR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1DA register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF1DA_ADDR ALT_CAN_MSGIF_IF1DA_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1DB register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF1DB_ADDR ALT_CAN_MSGIF_IF1DB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2CMR register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF2CMR_ADDR ALT_CAN_MSGIF_IF2CMR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2MSK register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF2MSK_ADDR ALT_CAN_MSGIF_IF2MSK_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2ARB register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF2ARB_ADDR ALT_CAN_MSGIF_IF2ARB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2MCTR register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF2MCTR_ADDR ALT_CAN_MSGIF_IF2MCTR_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2DA register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF2DA_ADDR ALT_CAN_MSGIF_IF2DA_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2DB register for the ALT_CAN0_MSGIFGRP instance. */ -#define ALT_CAN0_MSGIF_IF2DB_ADDR ALT_CAN_MSGIF_IF2DB_ADDR(ALT_CAN0_MSGIFGRP_ADDR) -/* The base address byte offset for the start of the ALT_CAN0_MSGIFGRP component. */ -#define ALT_CAN0_MSGIFGRP_OFST 0x100 -/* The start address of the ALT_CAN0_MSGIFGRP component. */ -#define ALT_CAN0_MSGIFGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN0_ADDR) + ALT_CAN0_MSGIFGRP_OFST)) -/* The lower bound address range of the ALT_CAN0_MSGIFGRP component. */ -#define ALT_CAN0_MSGIFGRP_LB_ADDR ALT_CAN0_MSGIFGRP_ADDR -/* The upper bound address range of the ALT_CAN0_MSGIFGRP component. */ -#define ALT_CAN0_MSGIFGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_MSGIFGRP_ADDR) + 0x38) - 1)) - - -/* The base address byte offset for the start of the ALT_CAN0 component. */ -#define ALT_CAN0_OFST 0xffc00000 -/* The start address of the ALT_CAN0 component. */ -#define ALT_CAN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CAN0_OFST)) -/* The lower bound address range of the ALT_CAN0 component. */ -#define ALT_CAN0_LB_ADDR ALT_CAN0_ADDR -/* The upper bound address range of the ALT_CAN0 component. */ -#define ALT_CAN0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN0_ADDR) + 0x200) - 1)) - - -/* - * Component Instance : can1 - * - * Instance can1 of component ALT_CAN. - * - * - */ -/* - * Register Group Instance : protogrp - * - * Instance protogrp of register group ALT_CAN_PROTO. - * - * - */ -/* The address of the ALT_CAN_PROTO_CCTL register for the ALT_CAN1_PROTOGRP instance. */ -#define ALT_CAN1_PROTO_CCTL_ADDR ALT_CAN_PROTO_CCTL_ADDR(ALT_CAN1_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CSTS register for the ALT_CAN1_PROTOGRP instance. */ -#define ALT_CAN1_PROTO_CSTS_ADDR ALT_CAN_PROTO_CSTS_ADDR(ALT_CAN1_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CERC register for the ALT_CAN1_PROTOGRP instance. */ -#define ALT_CAN1_PROTO_CERC_ADDR ALT_CAN_PROTO_CERC_ADDR(ALT_CAN1_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CBT register for the ALT_CAN1_PROTOGRP instance. */ -#define ALT_CAN1_PROTO_CBT_ADDR ALT_CAN_PROTO_CBT_ADDR(ALT_CAN1_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CIR register for the ALT_CAN1_PROTOGRP instance. */ -#define ALT_CAN1_PROTO_CIR_ADDR ALT_CAN_PROTO_CIR_ADDR(ALT_CAN1_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CTR register for the ALT_CAN1_PROTOGRP instance. */ -#define ALT_CAN1_PROTO_CTR_ADDR ALT_CAN_PROTO_CTR_ADDR(ALT_CAN1_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CFR register for the ALT_CAN1_PROTOGRP instance. */ -#define ALT_CAN1_PROTO_CFR_ADDR ALT_CAN_PROTO_CFR_ADDR(ALT_CAN1_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_CRR register for the ALT_CAN1_PROTOGRP instance. */ -#define ALT_CAN1_PROTO_CRR_ADDR ALT_CAN_PROTO_CRR_ADDR(ALT_CAN1_PROTOGRP_ADDR) -/* The address of the ALT_CAN_PROTO_HWS register for the ALT_CAN1_PROTOGRP instance. */ -#define ALT_CAN1_PROTO_HWS_ADDR ALT_CAN_PROTO_HWS_ADDR(ALT_CAN1_PROTOGRP_ADDR) -/* The base address byte offset for the start of the ALT_CAN1_PROTOGRP component. */ -#define ALT_CAN1_PROTOGRP_OFST 0x0 -/* The start address of the ALT_CAN1_PROTOGRP component. */ -#define ALT_CAN1_PROTOGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_PROTOGRP_OFST)) -/* The lower bound address range of the ALT_CAN1_PROTOGRP component. */ -#define ALT_CAN1_PROTOGRP_LB_ADDR ALT_CAN1_PROTOGRP_ADDR -/* The upper bound address range of the ALT_CAN1_PROTOGRP component. */ -#define ALT_CAN1_PROTOGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_PROTOGRP_ADDR) + 0x28) - 1)) - - -/* - * Register Group Instance : msghandgrp - * - * Instance msghandgrp of register group ALT_CAN_MSGHAND. - * - * - */ -/* The address of the ALT_CAN_MSGHAND_MOTRX register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOTRX_ADDR ALT_CAN_MSGHAND_MOTRX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOTRA register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOTRA_ADDR ALT_CAN_MSGHAND_MOTRA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOTRB register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOTRB_ADDR ALT_CAN_MSGHAND_MOTRB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOTRC register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOTRC_ADDR ALT_CAN_MSGHAND_MOTRC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOTRD register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOTRD_ADDR ALT_CAN_MSGHAND_MOTRD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDX register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MONDX_ADDR ALT_CAN_MSGHAND_MONDX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDA register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MONDA_ADDR ALT_CAN_MSGHAND_MONDA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDB register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MONDB_ADDR ALT_CAN_MSGHAND_MONDB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDC register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MONDC_ADDR ALT_CAN_MSGHAND_MONDC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MONDD register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MONDD_ADDR ALT_CAN_MSGHAND_MONDD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPX register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOIPX_ADDR ALT_CAN_MSGHAND_MOIPX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPA register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOIPA_ADDR ALT_CAN_MSGHAND_MOIPA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPB register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOIPB_ADDR ALT_CAN_MSGHAND_MOIPB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPC register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOIPC_ADDR ALT_CAN_MSGHAND_MOIPC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOIPD register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOIPD_ADDR ALT_CAN_MSGHAND_MOIPD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALX register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOVALX_ADDR ALT_CAN_MSGHAND_MOVALX_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALA register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOVALA_ADDR ALT_CAN_MSGHAND_MOVALA_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALB register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOVALB_ADDR ALT_CAN_MSGHAND_MOVALB_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALC register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOVALC_ADDR ALT_CAN_MSGHAND_MOVALC_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The address of the ALT_CAN_MSGHAND_MOVALD register for the ALT_CAN1_MSGHANDGRP instance. */ -#define ALT_CAN1_MSGHAND_MOVALD_ADDR ALT_CAN_MSGHAND_MOVALD_ADDR(ALT_CAN1_MSGHANDGRP_ADDR) -/* The base address byte offset for the start of the ALT_CAN1_MSGHANDGRP component. */ -#define ALT_CAN1_MSGHANDGRP_OFST 0x84 -/* The start address of the ALT_CAN1_MSGHANDGRP component. */ -#define ALT_CAN1_MSGHANDGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_MSGHANDGRP_OFST)) -/* The lower bound address range of the ALT_CAN1_MSGHANDGRP component. */ -#define ALT_CAN1_MSGHANDGRP_LB_ADDR ALT_CAN1_MSGHANDGRP_ADDR -/* The upper bound address range of the ALT_CAN1_MSGHANDGRP component. */ -#define ALT_CAN1_MSGHANDGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_MSGHANDGRP_ADDR) + 0x50) - 1)) - - -/* - * Register Group Instance : msgifgrp - * - * Instance msgifgrp of register group ALT_CAN_MSGIF. - * - * - */ -/* The address of the ALT_CAN_MSGIF_IF1CMR register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF1CMR_ADDR ALT_CAN_MSGIF_IF1CMR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1MSK register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF1MSK_ADDR ALT_CAN_MSGIF_IF1MSK_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1ARB register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF1ARB_ADDR ALT_CAN_MSGIF_IF1ARB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1MCTR register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF1MCTR_ADDR ALT_CAN_MSGIF_IF1MCTR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1DA register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF1DA_ADDR ALT_CAN_MSGIF_IF1DA_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF1DB register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF1DB_ADDR ALT_CAN_MSGIF_IF1DB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2CMR register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF2CMR_ADDR ALT_CAN_MSGIF_IF2CMR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2MSK register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF2MSK_ADDR ALT_CAN_MSGIF_IF2MSK_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2ARB register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF2ARB_ADDR ALT_CAN_MSGIF_IF2ARB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2MCTR register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF2MCTR_ADDR ALT_CAN_MSGIF_IF2MCTR_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2DA register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF2DA_ADDR ALT_CAN_MSGIF_IF2DA_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The address of the ALT_CAN_MSGIF_IF2DB register for the ALT_CAN1_MSGIFGRP instance. */ -#define ALT_CAN1_MSGIF_IF2DB_ADDR ALT_CAN_MSGIF_IF2DB_ADDR(ALT_CAN1_MSGIFGRP_ADDR) -/* The base address byte offset for the start of the ALT_CAN1_MSGIFGRP component. */ -#define ALT_CAN1_MSGIFGRP_OFST 0x100 -/* The start address of the ALT_CAN1_MSGIFGRP component. */ -#define ALT_CAN1_MSGIFGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CAN1_ADDR) + ALT_CAN1_MSGIFGRP_OFST)) -/* The lower bound address range of the ALT_CAN1_MSGIFGRP component. */ -#define ALT_CAN1_MSGIFGRP_LB_ADDR ALT_CAN1_MSGIFGRP_ADDR -/* The upper bound address range of the ALT_CAN1_MSGIFGRP component. */ -#define ALT_CAN1_MSGIFGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_MSGIFGRP_ADDR) + 0x38) - 1)) - - -/* The base address byte offset for the start of the ALT_CAN1 component. */ -#define ALT_CAN1_OFST 0xffc01000 -/* The start address of the ALT_CAN1 component. */ -#define ALT_CAN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CAN1_OFST)) -/* The lower bound address range of the ALT_CAN1 component. */ -#define ALT_CAN1_LB_ADDR ALT_CAN1_ADDR -/* The upper bound address range of the ALT_CAN1 component. */ -#define ALT_CAN1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CAN1_ADDR) + 0x200) - 1)) - - -/* - * Component Instance : uart0 - * - * Instance uart0 of component ALT_UART. - * - * - */ -/* The address of the ALT_UART_RBR_THR_DLL register for the ALT_UART0 instance. */ -#define ALT_UART0_RBR_THR_DLL_ADDR ALT_UART_RBR_THR_DLL_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_IER_DLH register for the ALT_UART0 instance. */ -#define ALT_UART0_IER_DLH_ADDR ALT_UART_IER_DLH_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_IIR register for the ALT_UART0 instance. */ -#define ALT_UART0_IIR_ADDR ALT_UART_IIR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_FCR register for the ALT_UART0 instance. */ -#define ALT_UART0_FCR_ADDR ALT_UART_FCR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_LCR register for the ALT_UART0 instance. */ -#define ALT_UART0_LCR_ADDR ALT_UART_LCR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_MCR register for the ALT_UART0 instance. */ -#define ALT_UART0_MCR_ADDR ALT_UART_MCR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_LSR register for the ALT_UART0 instance. */ -#define ALT_UART0_LSR_ADDR ALT_UART_LSR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_MSR register for the ALT_UART0 instance. */ -#define ALT_UART0_MSR_ADDR ALT_UART_MSR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_SCR register for the ALT_UART0 instance. */ -#define ALT_UART0_SCR_ADDR ALT_UART_SCR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_SRBR register for the ALT_UART0 instance. */ -#define ALT_UART0_SRBR_ADDR ALT_UART_SRBR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_STHR register for the ALT_UART0 instance. */ -#define ALT_UART0_STHR_ADDR ALT_UART_STHR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_FAR register for the ALT_UART0 instance. */ -#define ALT_UART0_FAR_ADDR ALT_UART_FAR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_TFR register for the ALT_UART0 instance. */ -#define ALT_UART0_TFR_ADDR ALT_UART_TFR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_RFW register for the ALT_UART0 instance. */ -#define ALT_UART0_RFW_ADDR ALT_UART_RFW_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_USR register for the ALT_UART0 instance. */ -#define ALT_UART0_USR_ADDR ALT_UART_USR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_TFL register for the ALT_UART0 instance. */ -#define ALT_UART0_TFL_ADDR ALT_UART_TFL_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_RFL register for the ALT_UART0 instance. */ -#define ALT_UART0_RFL_ADDR ALT_UART_RFL_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_SRR register for the ALT_UART0 instance. */ -#define ALT_UART0_SRR_ADDR ALT_UART_SRR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_SRTS register for the ALT_UART0 instance. */ -#define ALT_UART0_SRTS_ADDR ALT_UART_SRTS_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_SBCR register for the ALT_UART0 instance. */ -#define ALT_UART0_SBCR_ADDR ALT_UART_SBCR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_SDMAM register for the ALT_UART0 instance. */ -#define ALT_UART0_SDMAM_ADDR ALT_UART_SDMAM_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_SFE register for the ALT_UART0 instance. */ -#define ALT_UART0_SFE_ADDR ALT_UART_SFE_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_SRT register for the ALT_UART0 instance. */ -#define ALT_UART0_SRT_ADDR ALT_UART_SRT_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_STET register for the ALT_UART0 instance. */ -#define ALT_UART0_STET_ADDR ALT_UART_STET_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_HTX register for the ALT_UART0 instance. */ -#define ALT_UART0_HTX_ADDR ALT_UART_HTX_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_DMASA register for the ALT_UART0 instance. */ -#define ALT_UART0_DMASA_ADDR ALT_UART_DMASA_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_CPR register for the ALT_UART0 instance. */ -#define ALT_UART0_CPR_ADDR ALT_UART_CPR_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_UCV register for the ALT_UART0 instance. */ -#define ALT_UART0_UCV_ADDR ALT_UART_UCV_ADDR(ALT_UART0_ADDR) -/* The address of the ALT_UART_CTR register for the ALT_UART0 instance. */ -#define ALT_UART0_CTR_ADDR ALT_UART_CTR_ADDR(ALT_UART0_ADDR) -/* The base address byte offset for the start of the ALT_UART0 component. */ -#define ALT_UART0_OFST 0xffc02000 -/* The start address of the ALT_UART0 component. */ -#define ALT_UART0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_UART0_OFST)) -/* The lower bound address range of the ALT_UART0 component. */ -#define ALT_UART0_LB_ADDR ALT_UART0_ADDR -/* The upper bound address range of the ALT_UART0 component. */ -#define ALT_UART0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_UART0_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : uart1 - * - * Instance uart1 of component ALT_UART. - * - * - */ -/* The address of the ALT_UART_RBR_THR_DLL register for the ALT_UART1 instance. */ -#define ALT_UART1_RBR_THR_DLL_ADDR ALT_UART_RBR_THR_DLL_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_IER_DLH register for the ALT_UART1 instance. */ -#define ALT_UART1_IER_DLH_ADDR ALT_UART_IER_DLH_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_IIR register for the ALT_UART1 instance. */ -#define ALT_UART1_IIR_ADDR ALT_UART_IIR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_FCR register for the ALT_UART1 instance. */ -#define ALT_UART1_FCR_ADDR ALT_UART_FCR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_LCR register for the ALT_UART1 instance. */ -#define ALT_UART1_LCR_ADDR ALT_UART_LCR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_MCR register for the ALT_UART1 instance. */ -#define ALT_UART1_MCR_ADDR ALT_UART_MCR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_LSR register for the ALT_UART1 instance. */ -#define ALT_UART1_LSR_ADDR ALT_UART_LSR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_MSR register for the ALT_UART1 instance. */ -#define ALT_UART1_MSR_ADDR ALT_UART_MSR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_SCR register for the ALT_UART1 instance. */ -#define ALT_UART1_SCR_ADDR ALT_UART_SCR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_SRBR register for the ALT_UART1 instance. */ -#define ALT_UART1_SRBR_ADDR ALT_UART_SRBR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_STHR register for the ALT_UART1 instance. */ -#define ALT_UART1_STHR_ADDR ALT_UART_STHR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_FAR register for the ALT_UART1 instance. */ -#define ALT_UART1_FAR_ADDR ALT_UART_FAR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_TFR register for the ALT_UART1 instance. */ -#define ALT_UART1_TFR_ADDR ALT_UART_TFR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_RFW register for the ALT_UART1 instance. */ -#define ALT_UART1_RFW_ADDR ALT_UART_RFW_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_USR register for the ALT_UART1 instance. */ -#define ALT_UART1_USR_ADDR ALT_UART_USR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_TFL register for the ALT_UART1 instance. */ -#define ALT_UART1_TFL_ADDR ALT_UART_TFL_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_RFL register for the ALT_UART1 instance. */ -#define ALT_UART1_RFL_ADDR ALT_UART_RFL_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_SRR register for the ALT_UART1 instance. */ -#define ALT_UART1_SRR_ADDR ALT_UART_SRR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_SRTS register for the ALT_UART1 instance. */ -#define ALT_UART1_SRTS_ADDR ALT_UART_SRTS_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_SBCR register for the ALT_UART1 instance. */ -#define ALT_UART1_SBCR_ADDR ALT_UART_SBCR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_SDMAM register for the ALT_UART1 instance. */ -#define ALT_UART1_SDMAM_ADDR ALT_UART_SDMAM_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_SFE register for the ALT_UART1 instance. */ -#define ALT_UART1_SFE_ADDR ALT_UART_SFE_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_SRT register for the ALT_UART1 instance. */ -#define ALT_UART1_SRT_ADDR ALT_UART_SRT_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_STET register for the ALT_UART1 instance. */ -#define ALT_UART1_STET_ADDR ALT_UART_STET_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_HTX register for the ALT_UART1 instance. */ -#define ALT_UART1_HTX_ADDR ALT_UART_HTX_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_DMASA register for the ALT_UART1 instance. */ -#define ALT_UART1_DMASA_ADDR ALT_UART_DMASA_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_CPR register for the ALT_UART1 instance. */ -#define ALT_UART1_CPR_ADDR ALT_UART_CPR_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_UCV register for the ALT_UART1 instance. */ -#define ALT_UART1_UCV_ADDR ALT_UART_UCV_ADDR(ALT_UART1_ADDR) -/* The address of the ALT_UART_CTR register for the ALT_UART1 instance. */ -#define ALT_UART1_CTR_ADDR ALT_UART_CTR_ADDR(ALT_UART1_ADDR) -/* The base address byte offset for the start of the ALT_UART1 component. */ -#define ALT_UART1_OFST 0xffc03000 -/* The start address of the ALT_UART1 component. */ -#define ALT_UART1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_UART1_OFST)) -/* The lower bound address range of the ALT_UART1 component. */ -#define ALT_UART1_LB_ADDR ALT_UART1_ADDR -/* The upper bound address range of the ALT_UART1 component. */ -#define ALT_UART1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_UART1_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : i2c0 - * - * Instance i2c0 of component ALT_I2C. - * - * - */ -/* The address of the ALT_I2C_CON register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_TAR register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_SAR register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_RX_TL register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_TX_TL register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_EN register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_STAT register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_TXFLR register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_RXFLR register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C0_ADDR) -/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C0 instance. */ -#define ALT_I2C0_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C0_ADDR) -/* The base address byte offset for the start of the ALT_I2C0 component. */ -#define ALT_I2C0_OFST 0xffc04000 -/* The start address of the ALT_I2C0 component. */ -#define ALT_I2C0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C0_OFST)) -/* The lower bound address range of the ALT_I2C0 component. */ -#define ALT_I2C0_LB_ADDR ALT_I2C0_ADDR -/* The upper bound address range of the ALT_I2C0 component. */ -#define ALT_I2C0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C0_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : i2c1 - * - * Instance i2c1 of component ALT_I2C. - * - * - */ -/* The address of the ALT_I2C_CON register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_TAR register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_SAR register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_RX_TL register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_TX_TL register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_EN register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_STAT register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_TXFLR register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_RXFLR register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C1_ADDR) -/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C1 instance. */ -#define ALT_I2C1_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C1_ADDR) -/* The base address byte offset for the start of the ALT_I2C1 component. */ -#define ALT_I2C1_OFST 0xffc05000 -/* The start address of the ALT_I2C1 component. */ -#define ALT_I2C1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C1_OFST)) -/* The lower bound address range of the ALT_I2C1 component. */ -#define ALT_I2C1_LB_ADDR ALT_I2C1_ADDR -/* The upper bound address range of the ALT_I2C1 component. */ -#define ALT_I2C1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C1_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : i2c2 - * - * Instance i2c2 of component ALT_I2C. - * - * - */ -/* The address of the ALT_I2C_CON register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_TAR register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_SAR register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_RX_TL register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_TX_TL register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_EN register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_STAT register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_TXFLR register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_RXFLR register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C2_ADDR) -/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C2 instance. */ -#define ALT_I2C2_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C2_ADDR) -/* The base address byte offset for the start of the ALT_I2C2 component. */ -#define ALT_I2C2_OFST 0xffc06000 -/* The start address of the ALT_I2C2 component. */ -#define ALT_I2C2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C2_OFST)) -/* The lower bound address range of the ALT_I2C2 component. */ -#define ALT_I2C2_LB_ADDR ALT_I2C2_ADDR -/* The upper bound address range of the ALT_I2C2 component. */ -#define ALT_I2C2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C2_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : i2c3 - * - * Instance i2c3 of component ALT_I2C. - * - * - */ -/* The address of the ALT_I2C_CON register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CON_ADDR ALT_I2C_CON_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_TAR register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_TAR_ADDR ALT_I2C_TAR_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_SAR register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_SAR_ADDR ALT_I2C_SAR_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_DATA_CMD register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_DATA_CMD_ADDR ALT_I2C_DATA_CMD_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_SS_SCL_HCNT register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_SS_SCL_HCNT_ADDR ALT_I2C_SS_SCL_HCNT_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_SS_SCL_LCNT register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_SS_SCL_LCNT_ADDR ALT_I2C_SS_SCL_LCNT_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_FS_SCL_HCNT register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_FS_SCL_HCNT_ADDR ALT_I2C_FS_SCL_HCNT_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_FS_SCL_LCNT register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_FS_SCL_LCNT_ADDR ALT_I2C_FS_SCL_LCNT_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_INTR_STAT register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_INTR_STAT_ADDR ALT_I2C_INTR_STAT_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_INTR_MSK register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_INTR_MSK_ADDR ALT_I2C_INTR_MSK_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_RAW_INTR_STAT register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_RAW_INTR_STAT_ADDR ALT_I2C_RAW_INTR_STAT_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_RX_TL register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_RX_TL_ADDR ALT_I2C_RX_TL_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_TX_TL register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_TX_TL_ADDR ALT_I2C_TX_TL_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_INTR register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_INTR_ADDR ALT_I2C_CLR_INTR_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_RX_UNDER register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_RX_UNDER_ADDR ALT_I2C_CLR_RX_UNDER_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_RX_OVER register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_RX_OVER_ADDR ALT_I2C_CLR_RX_OVER_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_TX_OVER register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_TX_OVER_ADDR ALT_I2C_CLR_TX_OVER_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_RD_REQ register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_RD_REQ_ADDR ALT_I2C_CLR_RD_REQ_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_TX_ABRT register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_TX_ABRT_ADDR ALT_I2C_CLR_TX_ABRT_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_RX_DONE register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_RX_DONE_ADDR ALT_I2C_CLR_RX_DONE_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_ACTIVITY register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_ACTIVITY_ADDR ALT_I2C_CLR_ACTIVITY_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_STOP_DET register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_STOP_DET_ADDR ALT_I2C_CLR_STOP_DET_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_START_DET register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_START_DET_ADDR ALT_I2C_CLR_START_DET_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_CLR_GEN_CALL register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_CLR_GEN_CALL_ADDR ALT_I2C_CLR_GEN_CALL_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_EN register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_EN_ADDR ALT_I2C_EN_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_STAT register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_STAT_ADDR ALT_I2C_STAT_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_TXFLR register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_TXFLR_ADDR ALT_I2C_TXFLR_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_RXFLR register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_RXFLR_ADDR ALT_I2C_RXFLR_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_SDA_HOLD register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_SDA_HOLD_ADDR ALT_I2C_SDA_HOLD_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_TX_ABRT_SRC register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_TX_ABRT_SRC_ADDR ALT_I2C_TX_ABRT_SRC_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_SLV_DATA_NACK_ONLY_ADDR ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_DMA_CR register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_DMA_CR_ADDR ALT_I2C_DMA_CR_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_DMA_TDLR register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_DMA_TDLR_ADDR ALT_I2C_DMA_TDLR_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_DMA_RDLR register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_DMA_RDLR_ADDR ALT_I2C_DMA_RDLR_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_SDA_SETUP register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_SDA_SETUP_ADDR ALT_I2C_SDA_SETUP_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_ACK_GENERAL_CALL register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_ACK_GENERAL_CALL_ADDR ALT_I2C_ACK_GENERAL_CALL_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_EN_STAT register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_EN_STAT_ADDR ALT_I2C_EN_STAT_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_FS_SPKLEN register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_FS_SPKLEN_ADDR ALT_I2C_FS_SPKLEN_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_COMP_PARAM_1 register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_COMP_PARAM_1_ADDR ALT_I2C_COMP_PARAM_1_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_COMP_VER register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_COMP_VER_ADDR ALT_I2C_COMP_VER_ADDR(ALT_I2C3_ADDR) -/* The address of the ALT_I2C_COMP_TYPE register for the ALT_I2C3 instance. */ -#define ALT_I2C3_IC_COMP_TYPE_ADDR ALT_I2C_COMP_TYPE_ADDR(ALT_I2C3_ADDR) -/* The base address byte offset for the start of the ALT_I2C3 component. */ -#define ALT_I2C3_OFST 0xffc07000 -/* The start address of the ALT_I2C3 component. */ -#define ALT_I2C3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_I2C3_OFST)) -/* The lower bound address range of the ALT_I2C3 component. */ -#define ALT_I2C3_LB_ADDR ALT_I2C3_ADDR -/* The upper bound address range of the ALT_I2C3 component. */ -#define ALT_I2C3_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_I2C3_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : sptimer0 - * - * Instance sptimer0 of component ALT_TMR. - * - * - */ -/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_SPTMR0 instance. */ -#define ALT_SPTMR0_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_SPTMR0_ADDR) -/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_SPTMR0 instance. */ -#define ALT_SPTMR0_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_SPTMR0_ADDR) -/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_SPTMR0 instance. */ -#define ALT_SPTMR0_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_SPTMR0_ADDR) -/* The address of the ALT_TMR_TMR1EOI register for the ALT_SPTMR0 instance. */ -#define ALT_SPTMR0_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_SPTMR0_ADDR) -/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_SPTMR0 instance. */ -#define ALT_SPTMR0_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_SPTMR0_ADDR) -/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_SPTMR0 instance. */ -#define ALT_SPTMR0_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_SPTMR0_ADDR) -/* The address of the ALT_TMR_TMRSEOI register for the ALT_SPTMR0 instance. */ -#define ALT_SPTMR0_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_SPTMR0_ADDR) -/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_SPTMR0 instance. */ -#define ALT_SPTMR0_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_SPTMR0_ADDR) -/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_SPTMR0 instance. */ -#define ALT_SPTMR0_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_SPTMR0_ADDR) -/* The base address byte offset for the start of the ALT_SPTMR0 component. */ -#define ALT_SPTMR0_OFST 0xffc08000 -/* The start address of the ALT_SPTMR0 component. */ -#define ALT_SPTMR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPTMR0_OFST)) -/* The lower bound address range of the ALT_SPTMR0 component. */ -#define ALT_SPTMR0_LB_ADDR ALT_SPTMR0_ADDR -/* The upper bound address range of the ALT_SPTMR0 component. */ -#define ALT_SPTMR0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPTMR0_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : sptimer1 - * - * Instance sptimer1 of component ALT_TMR. - * - * - */ -/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_SPTMR1 instance. */ -#define ALT_SPTMR1_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_SPTMR1_ADDR) -/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_SPTMR1 instance. */ -#define ALT_SPTMR1_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_SPTMR1_ADDR) -/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_SPTMR1 instance. */ -#define ALT_SPTMR1_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_SPTMR1_ADDR) -/* The address of the ALT_TMR_TMR1EOI register for the ALT_SPTMR1 instance. */ -#define ALT_SPTMR1_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_SPTMR1_ADDR) -/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_SPTMR1 instance. */ -#define ALT_SPTMR1_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_SPTMR1_ADDR) -/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_SPTMR1 instance. */ -#define ALT_SPTMR1_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_SPTMR1_ADDR) -/* The address of the ALT_TMR_TMRSEOI register for the ALT_SPTMR1 instance. */ -#define ALT_SPTMR1_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_SPTMR1_ADDR) -/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_SPTMR1 instance. */ -#define ALT_SPTMR1_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_SPTMR1_ADDR) -/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_SPTMR1 instance. */ -#define ALT_SPTMR1_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_SPTMR1_ADDR) -/* The base address byte offset for the start of the ALT_SPTMR1 component. */ -#define ALT_SPTMR1_OFST 0xffc09000 -/* The start address of the ALT_SPTMR1 component. */ -#define ALT_SPTMR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPTMR1_OFST)) -/* The lower bound address range of the ALT_SPTMR1 component. */ -#define ALT_SPTMR1_LB_ADDR ALT_SPTMR1_ADDR -/* The upper bound address range of the ALT_SPTMR1 component. */ -#define ALT_SPTMR1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPTMR1_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : sdr - * - * Instance sdr of component ALT_SDR. - * - * - */ -/* - * Register Group Instance : ctrlgrp - * - * Instance ctrlgrp of register group ALT_SDR_CTL. - * - * - */ -/* The address of the ALT_SDR_CTL_CTLCFG register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_CTLCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTLCFG_OFST)) -/* The address of the ALT_SDR_CTL_DRAMTIMING1 register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMTIMING1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING1_OFST)) -/* The address of the ALT_SDR_CTL_DRAMTIMING2 register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMTIMING2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING2_OFST)) -/* The address of the ALT_SDR_CTL_DRAMTIMING3 register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMTIMING3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING3_OFST)) -/* The address of the ALT_SDR_CTL_DRAMTIMING4 register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMTIMING4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMTIMING4_OFST)) -/* The address of the ALT_SDR_CTL_LOWPWRTIMING register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_LOWPWRTIMING_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWRTIMING_OFST)) -/* The address of the ALT_SDR_CTL_DRAMODT register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMODT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMODT_OFST)) -/* The address of the ALT_SDR_CTL_DRAMADDRW register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMADDRW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMADDRW_OFST)) -/* The address of the ALT_SDR_CTL_DRAMIFWIDTH register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMIFWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMIFWIDTH_OFST)) -/* The address of the ALT_SDR_CTL_DRAMDEVWIDTH register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMDEVWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMDEVWIDTH_OFST)) -/* The address of the ALT_SDR_CTL_DRAMSTS register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMSTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMSTS_OFST)) -/* The address of the ALT_SDR_CTL_DRAMINTR register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DRAMINTR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DRAMINTR_OFST)) -/* The address of the ALT_SDR_CTL_SBECOUNT register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_SBECOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_SBECOUNT_OFST)) -/* The address of the ALT_SDR_CTL_DBECOUNT register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DBECOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DBECOUNT_OFST)) -/* The address of the ALT_SDR_CTL_ERRADDR register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_ERRADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_ERRADDR_OFST)) -/* The address of the ALT_SDR_CTL_DROPCOUNT register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DROPCOUNT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DROPCOUNT_OFST)) -/* The address of the ALT_SDR_CTL_DROPADDR register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_DROPADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_DROPADDR_OFST)) -/* The address of the ALT_SDR_CTL_LOWPWREQ register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_LOWPWREQ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWREQ_OFST)) -/* The address of the ALT_SDR_CTL_LOWPWRACK register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_LOWPWRACK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_LOWPWRACK_OFST)) -/* The address of the ALT_SDR_CTL_STATICCFG register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_STATICCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_STATICCFG_OFST)) -/* The address of the ALT_SDR_CTL_CTLWIDTH register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_CTLWIDTH_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTLWIDTH_OFST)) -/* The address of the ALT_SDR_CTL_PORTCFG register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_PORTCFG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PORTCFG_OFST)) -/* The address of the ALT_SDR_CTL_FPGAPORTRST register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_FPGAPORTRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_FPGAPORTRST_OFST)) -/* The address of the ALT_SDR_CTL_PROTPORTDEFAULT register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_PROTPORTDEFAULT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTPORTDEFAULT_OFST)) -/* The address of the ALT_SDR_CTL_PROTRULEADDR register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_PROTRULEADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEADDR_OFST)) -/* The address of the ALT_SDR_CTL_PROTRULEID register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_PROTRULEID_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEID_OFST)) -/* The address of the ALT_SDR_CTL_PROTRULEDATA register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_PROTRULEDATA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULEDATA_OFST)) -/* The address of the ALT_SDR_CTL_PROTRULERDWR register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_PROTRULERDWR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_PROTRULERDWR_OFST)) -/* The address of the ALT_SDR_CTL_QOSLOWPRI register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_QOSLOWPRI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSLOWPRI_OFST)) -/* The address of the ALT_SDR_CTL_QOSHIGHPRI register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_QOSHIGHPRI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSHIGHPRI_OFST)) -/* The address of the ALT_SDR_CTL_QOSPRIORITYEN register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_QOSPRIORITYEN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_QOSPRIORITYEN_OFST)) -/* The address of the ALT_SDR_CTL_MPPRIORITY register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_MPPRIORITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_MPPRIORITY_OFST)) -/* The address of the ALT_SDR_CTL_REMAPPRIORITY register for the ALT_SDR_CTL instance. */ -#define ALT_SDR_CTL_REMAPPRIORITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_REMAPPRIORITY_OFST)) -/* - * Register Group Instance : ctrlgrp_mpweight - * - * Instance ctrlgrp_mpweight of register group ALT_SDR_CTL_MPWT. - * - * - */ -/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ -#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_0_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) -/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ -#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_1_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) -/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ -#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_2_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) -/* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register for the ALT_SDR_CTL_CTL_MPWEIGHT instance. */ -#define ALT_SDR_CTL_CTL_MPWEIGHT_MPWEIGHT_3_4_ADDR ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) -/* The base address byte offset for the start of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ -#define ALT_SDR_CTL_CTL_MPWEIGHT_OFST 0xb0 -/* The start address of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ -#define ALT_SDR_CTL_CTL_MPWEIGHT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_CTL_ADDR) + ALT_SDR_CTL_CTL_MPWEIGHT_OFST)) -/* The lower bound address range of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ -#define ALT_SDR_CTL_CTL_MPWEIGHT_LB_ADDR ALT_SDR_CTL_CTL_MPWEIGHT_ADDR -/* The upper bound address range of the ALT_SDR_CTL_CTL_MPWEIGHT component. */ -#define ALT_SDR_CTL_CTL_MPWEIGHT_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_CTL_CTL_MPWEIGHT_ADDR) + 0x10) - 1)) - - -/* The base address byte offset for the start of the ALT_SDR_CTL component. */ -#define ALT_SDR_CTL_OFST 0x5000 -/* The start address of the ALT_SDR_CTL component. */ -#define ALT_SDR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SDR_ADDR) + ALT_SDR_CTL_OFST)) -/* The lower bound address range of the ALT_SDR_CTL component. */ -#define ALT_SDR_CTL_LB_ADDR ALT_SDR_CTL_ADDR -/* The upper bound address range of the ALT_SDR_CTL component. */ -#define ALT_SDR_CTL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_CTL_ADDR) + 0x1000) - 1)) - - -/* The base address byte offset for the start of the ALT_SDR component. */ -#define ALT_SDR_OFST 0xffc20000 -/* The start address of the ALT_SDR component. */ -#define ALT_SDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SDR_OFST)) -/* The lower bound address range of the ALT_SDR component. */ -#define ALT_SDR_LB_ADDR ALT_SDR_ADDR -/* The upper bound address range of the ALT_SDR component. */ -#define ALT_SDR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SDR_ADDR) + 0x20000) - 1)) - - -/* - * Component Instance : osc1timer0 - * - * Instance osc1timer0 of component ALT_TMR. - * - * - */ -/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_OSC1TMR0 instance. */ -#define ALT_OSC1TMR0_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_OSC1TMR0_ADDR) -/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_OSC1TMR0 instance. */ -#define ALT_OSC1TMR0_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_OSC1TMR0_ADDR) -/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_OSC1TMR0 instance. */ -#define ALT_OSC1TMR0_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_OSC1TMR0_ADDR) -/* The address of the ALT_TMR_TMR1EOI register for the ALT_OSC1TMR0 instance. */ -#define ALT_OSC1TMR0_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_OSC1TMR0_ADDR) -/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_OSC1TMR0 instance. */ -#define ALT_OSC1TMR0_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_OSC1TMR0_ADDR) -/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_OSC1TMR0 instance. */ -#define ALT_OSC1TMR0_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_OSC1TMR0_ADDR) -/* The address of the ALT_TMR_TMRSEOI register for the ALT_OSC1TMR0 instance. */ -#define ALT_OSC1TMR0_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_OSC1TMR0_ADDR) -/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_OSC1TMR0 instance. */ -#define ALT_OSC1TMR0_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_OSC1TMR0_ADDR) -/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_OSC1TMR0 instance. */ -#define ALT_OSC1TMR0_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_OSC1TMR0_ADDR) -/* The base address byte offset for the start of the ALT_OSC1TMR0 component. */ -#define ALT_OSC1TMR0_OFST 0xffd00000 -/* The start address of the ALT_OSC1TMR0 component. */ -#define ALT_OSC1TMR0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OSC1TMR0_OFST)) -/* The lower bound address range of the ALT_OSC1TMR0 component. */ -#define ALT_OSC1TMR0_LB_ADDR ALT_OSC1TMR0_ADDR -/* The upper bound address range of the ALT_OSC1TMR0 component. */ -#define ALT_OSC1TMR0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OSC1TMR0_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : osc1timer1 - * - * Instance osc1timer1 of component ALT_TMR. - * - * - */ -/* The address of the ALT_TMR_TMR1LDCOUNT register for the ALT_OSC1TMR1 instance. */ -#define ALT_OSC1TMR1_TMR1LDCOUNT_ADDR ALT_TMR_TMR1LDCOUNT_ADDR(ALT_OSC1TMR1_ADDR) -/* The address of the ALT_TMR_TMR1CURVAL register for the ALT_OSC1TMR1 instance. */ -#define ALT_OSC1TMR1_TMR1CURVAL_ADDR ALT_TMR_TMR1CURVAL_ADDR(ALT_OSC1TMR1_ADDR) -/* The address of the ALT_TMR_TMR1CTLREG register for the ALT_OSC1TMR1 instance. */ -#define ALT_OSC1TMR1_TMR1CTLREG_ADDR ALT_TMR_TMR1CTLREG_ADDR(ALT_OSC1TMR1_ADDR) -/* The address of the ALT_TMR_TMR1EOI register for the ALT_OSC1TMR1 instance. */ -#define ALT_OSC1TMR1_TMR1EOI_ADDR ALT_TMR_TMR1EOI_ADDR(ALT_OSC1TMR1_ADDR) -/* The address of the ALT_TMR_TMR1INTSTAT register for the ALT_OSC1TMR1 instance. */ -#define ALT_OSC1TMR1_TMR1INTSTAT_ADDR ALT_TMR_TMR1INTSTAT_ADDR(ALT_OSC1TMR1_ADDR) -/* The address of the ALT_TMR_TMRSINTSTAT register for the ALT_OSC1TMR1 instance. */ -#define ALT_OSC1TMR1_TMRSINTSTAT_ADDR ALT_TMR_TMRSINTSTAT_ADDR(ALT_OSC1TMR1_ADDR) -/* The address of the ALT_TMR_TMRSEOI register for the ALT_OSC1TMR1 instance. */ -#define ALT_OSC1TMR1_TMRSEOI_ADDR ALT_TMR_TMRSEOI_ADDR(ALT_OSC1TMR1_ADDR) -/* The address of the ALT_TMR_TMRSRAWINTSTAT register for the ALT_OSC1TMR1 instance. */ -#define ALT_OSC1TMR1_TMRSRAWINTSTAT_ADDR ALT_TMR_TMRSRAWINTSTAT_ADDR(ALT_OSC1TMR1_ADDR) -/* The address of the ALT_TMR_TMRSCOMPVER register for the ALT_OSC1TMR1 instance. */ -#define ALT_OSC1TMR1_TMRSCOMPVER_ADDR ALT_TMR_TMRSCOMPVER_ADDR(ALT_OSC1TMR1_ADDR) -/* The base address byte offset for the start of the ALT_OSC1TMR1 component. */ -#define ALT_OSC1TMR1_OFST 0xffd01000 -/* The start address of the ALT_OSC1TMR1 component. */ -#define ALT_OSC1TMR1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OSC1TMR1_OFST)) -/* The lower bound address range of the ALT_OSC1TMR1 component. */ -#define ALT_OSC1TMR1_LB_ADDR ALT_OSC1TMR1_ADDR -/* The upper bound address range of the ALT_OSC1TMR1 component. */ -#define ALT_OSC1TMR1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OSC1TMR1_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : l4wd0 - * - * Instance l4wd0 of component ALT_L4WD. - * - * - */ -/* The address of the ALT_L4WD_CR register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_WDT_CR_ADDR ALT_L4WD_CR_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_TORR register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_WDT_TORR_ADDR ALT_L4WD_TORR_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_CCVR register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_WDT_CCVR_ADDR ALT_L4WD_CCVR_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_CRR register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_WDT_CRR_ADDR ALT_L4WD_CRR_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_STAT register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_WDT_STAT_ADDR ALT_L4WD_STAT_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_EOI register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_WDT_EOI_ADDR ALT_L4WD_EOI_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_CP_WDT_USER_TOP_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_CP_WDT_USER_TOP_INIT_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_CD_WDT_TOP_RST register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_CD_WDT_TOP_RST_ADDR ALT_L4WD_CD_WDT_TOP_RST_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_CP_WDT_CNT_RST register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_CP_WDT_CNT_RST_ADDR ALT_L4WD_CP_WDT_CNT_RST_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_COMP_PARAM_1 register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_WDT_COMP_PARAM_1_ADDR ALT_L4WD_COMP_PARAM_1_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_COMP_VER register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_WDT_COMP_VER_ADDR ALT_L4WD_COMP_VER_ADDR(ALT_L4WD0_ADDR) -/* The address of the ALT_L4WD_COMP_TYPE register for the ALT_L4WD0 instance. */ -#define ALT_L4WD0_WDT_COMP_TYPE_ADDR ALT_L4WD_COMP_TYPE_ADDR(ALT_L4WD0_ADDR) -/* The base address byte offset for the start of the ALT_L4WD0 component. */ -#define ALT_L4WD0_OFST 0xffd02000 -/* The start address of the ALT_L4WD0 component. */ -#define ALT_L4WD0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L4WD0_OFST)) -/* The lower bound address range of the ALT_L4WD0 component. */ -#define ALT_L4WD0_LB_ADDR ALT_L4WD0_ADDR -/* The upper bound address range of the ALT_L4WD0 component. */ -#define ALT_L4WD0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L4WD0_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : l4wd1 - * - * Instance l4wd1 of component ALT_L4WD. - * - * - */ -/* The address of the ALT_L4WD_CR register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_WDT_CR_ADDR ALT_L4WD_CR_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_TORR register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_WDT_TORR_ADDR ALT_L4WD_TORR_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_CCVR register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_WDT_CCVR_ADDR ALT_L4WD_CCVR_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_CRR register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_WDT_CRR_ADDR ALT_L4WD_CRR_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_STAT register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_WDT_STAT_ADDR ALT_L4WD_STAT_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_EOI register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_WDT_EOI_ADDR ALT_L4WD_EOI_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_CP_WDT_USER_TOP_MAX register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_CP_WDT_USER_TOP_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_MAX_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_CP_WDT_USER_TOP_INIT_MAX_ADDR ALT_L4WD_CP_WDT_USER_TOP_INIT_MAX_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_CD_WDT_TOP_RST register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_CD_WDT_TOP_RST_ADDR ALT_L4WD_CD_WDT_TOP_RST_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_CP_WDT_CNT_RST register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_CP_WDT_CNT_RST_ADDR ALT_L4WD_CP_WDT_CNT_RST_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_COMP_PARAM_1 register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_WDT_COMP_PARAM_1_ADDR ALT_L4WD_COMP_PARAM_1_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_COMP_VER register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_WDT_COMP_VER_ADDR ALT_L4WD_COMP_VER_ADDR(ALT_L4WD1_ADDR) -/* The address of the ALT_L4WD_COMP_TYPE register for the ALT_L4WD1 instance. */ -#define ALT_L4WD1_WDT_COMP_TYPE_ADDR ALT_L4WD_COMP_TYPE_ADDR(ALT_L4WD1_ADDR) -/* The base address byte offset for the start of the ALT_L4WD1 component. */ -#define ALT_L4WD1_OFST 0xffd03000 -/* The start address of the ALT_L4WD1 component. */ -#define ALT_L4WD1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_L4WD1_OFST)) -/* The lower bound address range of the ALT_L4WD1 component. */ -#define ALT_L4WD1_LB_ADDR ALT_L4WD1_ADDR -/* The upper bound address range of the ALT_L4WD1 component. */ -#define ALT_L4WD1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_L4WD1_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : clkmgr - * - * Instance clkmgr of component ALT_CLKMGR. - * - * - */ -/* The address of the ALT_CLKMGR_CTL register for the ALT_CLKMGR instance. */ -#define ALT_CLKMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_CTL_OFST)) -/* The address of the ALT_CLKMGR_BYPASS register for the ALT_CLKMGR instance. */ -#define ALT_CLKMGR_BYPASS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_BYPASS_OFST)) -/* The address of the ALT_CLKMGR_INTER register for the ALT_CLKMGR instance. */ -#define ALT_CLKMGR_INTER_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_INTER_OFST)) -/* The address of the ALT_CLKMGR_INTREN register for the ALT_CLKMGR instance. */ -#define ALT_CLKMGR_INTREN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_INTREN_OFST)) -/* The address of the ALT_CLKMGR_DBCTL register for the ALT_CLKMGR instance. */ -#define ALT_CLKMGR_DBCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_DBCTL_OFST)) -/* The address of the ALT_CLKMGR_STAT register for the ALT_CLKMGR instance. */ -#define ALT_CLKMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_STAT_OFST)) -/* - * Register Group Instance : mainpllgrp - * - * Instance mainpllgrp of register group ALT_CLKMGR_MAINPLL. - * - * - */ -/* The address of the ALT_CLKMGR_MAINPLL_VCO register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_VCO_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_MISC register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_MISC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MISC_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_MPUCLK register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_MPUCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MPUCLK_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_MAINCLK register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_MAINCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINCLK_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_DBGATCLK register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_DBGATCLK_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_MAINQSPICLK register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_EN register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_EN_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_MAINDIV register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_MAINDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_MAINDIV_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_DBGDIV register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_DBGDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_DBGDIV_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_TRACEDIV register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_TRACEDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_TRACEDIV_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_L4SRC register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_L4SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_L4SRC_OFST)) -/* The address of the ALT_CLKMGR_MAINPLL_STAT register for the ALT_CLKMGR_MAINPLL instance. */ -#define ALT_CLKMGR_MAINPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + ALT_CLKMGR_MAINPLL_STAT_OFST)) -/* The base address byte offset for the start of the ALT_CLKMGR_MAINPLL component. */ -#define ALT_CLKMGR_MAINPLL_OFST 0x40 -/* The start address of the ALT_CLKMGR_MAINPLL component. */ -#define ALT_CLKMGR_MAINPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_MAINPLL_OFST)) -/* The lower bound address range of the ALT_CLKMGR_MAINPLL component. */ -#define ALT_CLKMGR_MAINPLL_LB_ADDR ALT_CLKMGR_MAINPLL_ADDR -/* The upper bound address range of the ALT_CLKMGR_MAINPLL component. */ -#define ALT_CLKMGR_MAINPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_MAINPLL_ADDR) + 0x40) - 1)) - - -/* - * Register Group Instance : perpllgrp - * - * Instance perpllgrp of register group ALT_CLKMGR_PERPLL. - * - * - */ -/* The address of the ALT_CLKMGR_PERPLL_VCO register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_VCO_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_MISC register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_MISC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_MISC_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_EMAC0CLK register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EMAC0CLK_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_EMAC1CLK register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EMAC1CLK_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_PERQSPICLK register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERQSPICLK_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_PERBASECLK register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_PERBASECLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_PERBASECLK_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_S2FUSER1CLK register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_EN register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_EN_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_DIV register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_DIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_DIV_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_GPIODIV register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_GPIODIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_GPIODIV_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_SRC register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_SRC_OFST)) -/* The address of the ALT_CLKMGR_PERPLL_STAT register for the ALT_CLKMGR_PERPLL instance. */ -#define ALT_CLKMGR_PERPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + ALT_CLKMGR_PERPLL_STAT_OFST)) -/* The base address byte offset for the start of the ALT_CLKMGR_PERPLL component. */ -#define ALT_CLKMGR_PERPLL_OFST 0x80 -/* The start address of the ALT_CLKMGR_PERPLL component. */ -#define ALT_CLKMGR_PERPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_PERPLL_OFST)) -/* The lower bound address range of the ALT_CLKMGR_PERPLL component. */ -#define ALT_CLKMGR_PERPLL_LB_ADDR ALT_CLKMGR_PERPLL_ADDR -/* The upper bound address range of the ALT_CLKMGR_PERPLL component. */ -#define ALT_CLKMGR_PERPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_PERPLL_ADDR) + 0x40) - 1)) - - -/* - * Register Group Instance : sdrpllgrp - * - * Instance sdrpllgrp of register group ALT_CLKMGR_SDRPLL. - * - * - */ -/* The address of the ALT_CLKMGR_SDRPLL_VCO register for the ALT_CLKMGR_SDRPLL instance. */ -#define ALT_CLKMGR_SDRPLL_VCO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_VCO_OFST)) -/* The address of the ALT_CLKMGR_SDRPLL_CTL register for the ALT_CLKMGR_SDRPLL instance. */ -#define ALT_CLKMGR_SDRPLL_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_CTL_OFST)) -/* The address of the ALT_CLKMGR_SDRPLL_DDRDQSCLK register for the ALT_CLKMGR_SDRPLL instance. */ -#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST)) -/* The address of the ALT_CLKMGR_SDRPLL_DDR2XDQSCLK register for the ALT_CLKMGR_SDRPLL instance. */ -#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST)) -/* The address of the ALT_CLKMGR_SDRPLL_DDRDQCLK register for the ALT_CLKMGR_SDRPLL instance. */ -#define ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST)) -/* The address of the ALT_CLKMGR_SDRPLL_S2FUSER2CLK register for the ALT_CLKMGR_SDRPLL instance. */ -#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST)) -/* The address of the ALT_CLKMGR_SDRPLL_EN register for the ALT_CLKMGR_SDRPLL instance. */ -#define ALT_CLKMGR_SDRPLL_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_EN_OFST)) -/* The address of the ALT_CLKMGR_SDRPLL_STAT register for the ALT_CLKMGR_SDRPLL instance. */ -#define ALT_CLKMGR_SDRPLL_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + ALT_CLKMGR_SDRPLL_STAT_OFST)) -/* The base address byte offset for the start of the ALT_CLKMGR_SDRPLL component. */ -#define ALT_CLKMGR_SDRPLL_OFST 0xc0 -/* The start address of the ALT_CLKMGR_SDRPLL component. */ -#define ALT_CLKMGR_SDRPLL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_SDRPLL_OFST)) -/* The lower bound address range of the ALT_CLKMGR_SDRPLL component. */ -#define ALT_CLKMGR_SDRPLL_LB_ADDR ALT_CLKMGR_SDRPLL_ADDR -/* The upper bound address range of the ALT_CLKMGR_SDRPLL component. */ -#define ALT_CLKMGR_SDRPLL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_SDRPLL_ADDR) + 0x20) - 1)) - - -/* The base address byte offset for the start of the ALT_CLKMGR component. */ -#define ALT_CLKMGR_OFST 0xffd04000 -/* The start address of the ALT_CLKMGR component. */ -#define ALT_CLKMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_CLKMGR_OFST)) -/* The lower bound address range of the ALT_CLKMGR component. */ -#define ALT_CLKMGR_LB_ADDR ALT_CLKMGR_ADDR -/* The upper bound address range of the ALT_CLKMGR component. */ -#define ALT_CLKMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_CLKMGR_ADDR) + 0x200) - 1)) - - -/* - * Component Instance : rstmgr - * - * Instance rstmgr of component ALT_RSTMGR. - * - * - */ -/* The address of the ALT_RSTMGR_STAT register for the ALT_RSTMGR instance. */ -#define ALT_RSTMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_STAT_OFST)) -/* The address of the ALT_RSTMGR_CTL register for the ALT_RSTMGR instance. */ -#define ALT_RSTMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_CTL_OFST)) -/* The address of the ALT_RSTMGR_COUNTS register for the ALT_RSTMGR instance. */ -#define ALT_RSTMGR_COUNTS_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_COUNTS_OFST)) -/* The address of the ALT_RSTMGR_MPUMODRST register for the ALT_RSTMGR instance. */ -#define ALT_RSTMGR_MPUMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_MPUMODRST_OFST)) -/* The address of the ALT_RSTMGR_PERMODRST register for the ALT_RSTMGR instance. */ -#define ALT_RSTMGR_PERMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_PERMODRST_OFST)) -/* The address of the ALT_RSTMGR_PER2MODRST register for the ALT_RSTMGR instance. */ -#define ALT_RSTMGR_PER2MODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_PER2MODRST_OFST)) -/* The address of the ALT_RSTMGR_BRGMODRST register for the ALT_RSTMGR instance. */ -#define ALT_RSTMGR_BRGMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_BRGMODRST_OFST)) -/* The address of the ALT_RSTMGR_MISCMODRST register for the ALT_RSTMGR instance. */ -#define ALT_RSTMGR_MISCMODRST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_RSTMGR_ADDR) + ALT_RSTMGR_MISCMODRST_OFST)) -/* The base address byte offset for the start of the ALT_RSTMGR component. */ -#define ALT_RSTMGR_OFST 0xffd05000 -/* The start address of the ALT_RSTMGR component. */ -#define ALT_RSTMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_RSTMGR_OFST)) -/* The lower bound address range of the ALT_RSTMGR component. */ -#define ALT_RSTMGR_LB_ADDR ALT_RSTMGR_ADDR -/* The upper bound address range of the ALT_RSTMGR component. */ -#define ALT_RSTMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_RSTMGR_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : sysmgr - * - * Instance sysmgr of component ALT_SYSMGR. - * - * - */ -/* The address of the ALT_SYSMGR_SILICONID1 register for the ALT_SYSMGR instance. */ -#define ALT_SYSMGR_SILICONID1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SILICONID1_OFST)) -/* The address of the ALT_SYSMGR_SILICONID2 register for the ALT_SYSMGR instance. */ -#define ALT_SYSMGR_SILICONID2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SILICONID2_OFST)) -/* The address of the ALT_SYSMGR_WDDBG register for the ALT_SYSMGR instance. */ -#define ALT_SYSMGR_WDDBG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_WDDBG_OFST)) -/* The address of the ALT_SYSMGR_BOOT register for the ALT_SYSMGR instance. */ -#define ALT_SYSMGR_BOOT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_BOOT_OFST)) -/* The address of the ALT_SYSMGR_HPSINFO register for the ALT_SYSMGR instance. */ -#define ALT_SYSMGR_HPSINFO_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_HPSINFO_OFST)) -/* The address of the ALT_SYSMGR_PARITYINJ register for the ALT_SYSMGR instance. */ -#define ALT_SYSMGR_PARITYINJ_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_PARITYINJ_OFST)) -/* - * Register Group Instance : fpgaintfgrp - * - * Instance fpgaintfgrp of register group ALT_SYSMGR_FPGAINTF. - * - * - */ -/* The address of the ALT_SYSMGR_FPGAINTF_GBL register for the ALT_SYSMGR_FPGAINTF instance. */ -#define ALT_SYSMGR_FPGAINTF_GBL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_GBL_OFST)) -/* The address of the ALT_SYSMGR_FPGAINTF_INDIV register for the ALT_SYSMGR_FPGAINTF instance. */ -#define ALT_SYSMGR_FPGAINTF_INDIV_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_INDIV_OFST)) -/* The address of the ALT_SYSMGR_FPGAINTF_MODULE register for the ALT_SYSMGR_FPGAINTF instance. */ -#define ALT_SYSMGR_FPGAINTF_MODULE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + ALT_SYSMGR_FPGAINTF_MODULE_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_FPGAINTF component. */ -#define ALT_SYSMGR_FPGAINTF_OFST 0x20 -/* The start address of the ALT_SYSMGR_FPGAINTF component. */ -#define ALT_SYSMGR_FPGAINTF_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_FPGAINTF_OFST)) -/* The lower bound address range of the ALT_SYSMGR_FPGAINTF component. */ -#define ALT_SYSMGR_FPGAINTF_LB_ADDR ALT_SYSMGR_FPGAINTF_ADDR -/* The upper bound address range of the ALT_SYSMGR_FPGAINTF component. */ -#define ALT_SYSMGR_FPGAINTF_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_FPGAINTF_ADDR) + 0x10) - 1)) - - -/* - * Register Group Instance : scanmgrgrp - * - * Instance scanmgrgrp of register group ALT_SYSMGR_SCANMGR. - * - * - */ -/* The address of the ALT_SYSMGR_SCANMGR_CTL register for the ALT_SYSMGR_SCANMGR instance. */ -#define ALT_SYSMGR_SCANMGR_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SCANMGR_ADDR) + ALT_SYSMGR_SCANMGR_CTL_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_SCANMGR component. */ -#define ALT_SYSMGR_SCANMGR_OFST 0x30 -/* The start address of the ALT_SYSMGR_SCANMGR component. */ -#define ALT_SYSMGR_SCANMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SCANMGR_OFST)) -/* The lower bound address range of the ALT_SYSMGR_SCANMGR component. */ -#define ALT_SYSMGR_SCANMGR_LB_ADDR ALT_SYSMGR_SCANMGR_ADDR -/* The upper bound address range of the ALT_SYSMGR_SCANMGR component. */ -#define ALT_SYSMGR_SCANMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_SCANMGR_ADDR) + 0x4) - 1)) - - -/* - * Register Group Instance : frzctrl - * - * Instance frzctrl of register group ALT_SYSMGR_FRZCTL. - * - * - */ -/* The address of the ALT_SYSMGR_FRZCTL_VIOCTL register for the ALT_SYSMGR_FRZCTL instance. */ -#define ALT_SYSMGR_FRZCTL_VIOCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_VIOCTL_OFST)) -/* The address of the ALT_SYSMGR_FRZCTL_HIOCTL register for the ALT_SYSMGR_FRZCTL instance. */ -#define ALT_SYSMGR_FRZCTL_HIOCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_HIOCTL_OFST)) -/* The address of the ALT_SYSMGR_FRZCTL_SRC register for the ALT_SYSMGR_FRZCTL instance. */ -#define ALT_SYSMGR_FRZCTL_SRC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_SRC_OFST)) -/* The address of the ALT_SYSMGR_FRZCTL_HWCTL register for the ALT_SYSMGR_FRZCTL instance. */ -#define ALT_SYSMGR_FRZCTL_HWCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + ALT_SYSMGR_FRZCTL_HWCTL_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_FRZCTL component. */ -#define ALT_SYSMGR_FRZCTL_OFST 0x40 -/* The start address of the ALT_SYSMGR_FRZCTL component. */ -#define ALT_SYSMGR_FRZCTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_FRZCTL_OFST)) -/* The lower bound address range of the ALT_SYSMGR_FRZCTL component. */ -#define ALT_SYSMGR_FRZCTL_LB_ADDR ALT_SYSMGR_FRZCTL_ADDR -/* The upper bound address range of the ALT_SYSMGR_FRZCTL component. */ -#define ALT_SYSMGR_FRZCTL_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_FRZCTL_ADDR) + 0x20) - 1)) - - -/* - * Register Group Instance : emacgrp - * - * Instance emacgrp of register group ALT_SYSMGR_EMAC. - * - * - */ -/* The address of the ALT_SYSMGR_EMAC_CTL register for the ALT_SYSMGR_EMAC instance. */ -#define ALT_SYSMGR_EMAC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + ALT_SYSMGR_EMAC_CTL_OFST)) -/* The address of the ALT_SYSMGR_EMAC_L3MST register for the ALT_SYSMGR_EMAC instance. */ -#define ALT_SYSMGR_EMAC_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + ALT_SYSMGR_EMAC_L3MST_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_EMAC component. */ -#define ALT_SYSMGR_EMAC_OFST 0x60 -/* The start address of the ALT_SYSMGR_EMAC component. */ -#define ALT_SYSMGR_EMAC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_EMAC_OFST)) -/* The lower bound address range of the ALT_SYSMGR_EMAC component. */ -#define ALT_SYSMGR_EMAC_LB_ADDR ALT_SYSMGR_EMAC_ADDR -/* The upper bound address range of the ALT_SYSMGR_EMAC component. */ -#define ALT_SYSMGR_EMAC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_EMAC_ADDR) + 0x10) - 1)) - - -/* - * Register Group Instance : dmagrp - * - * Instance dmagrp of register group ALT_SYSMGR_DMA. - * - * - */ -/* The address of the ALT_SYSMGR_DMA_CTL register for the ALT_SYSMGR_DMA instance. */ -#define ALT_SYSMGR_DMA_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + ALT_SYSMGR_DMA_CTL_OFST)) -/* The address of the ALT_SYSMGR_DMA_PERSECURITY register for the ALT_SYSMGR_DMA instance. */ -#define ALT_SYSMGR_DMA_PERSECURITY_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + ALT_SYSMGR_DMA_PERSECURITY_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_DMA component. */ -#define ALT_SYSMGR_DMA_OFST 0x70 -/* The start address of the ALT_SYSMGR_DMA component. */ -#define ALT_SYSMGR_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_DMA_OFST)) -/* The lower bound address range of the ALT_SYSMGR_DMA component. */ -#define ALT_SYSMGR_DMA_LB_ADDR ALT_SYSMGR_DMA_ADDR -/* The upper bound address range of the ALT_SYSMGR_DMA component. */ -#define ALT_SYSMGR_DMA_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_DMA_ADDR) + 0x8) - 1)) - - -/* - * Register Group Instance : iswgrp - * - * Instance iswgrp of register group ALT_SYSMGR_ISW. - * - * - */ -/* The address of the ALT_SYSMGR_ISW_HANDOFF register for the ALT_SYSMGR_ISW instance. */ -#define ALT_SYSMGR_ISW_HANDOFF_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ISW_ADDR) + ALT_SYSMGR_ISW_HANDOFF_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_ISW component. */ -#define ALT_SYSMGR_ISW_OFST 0x80 -/* The start address of the ALT_SYSMGR_ISW component. */ -#define ALT_SYSMGR_ISW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ISW_OFST)) -/* The lower bound address range of the ALT_SYSMGR_ISW component. */ -#define ALT_SYSMGR_ISW_LB_ADDR ALT_SYSMGR_ISW_ADDR -/* The upper bound address range of the ALT_SYSMGR_ISW component. */ -#define ALT_SYSMGR_ISW_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ISW_ADDR) + 0x20) - 1)) - - -/* - * Register Group Instance : romcodegrp - * - * Instance romcodegrp of register group ALT_SYSMGR_ROMCODE. - * - * - */ -/* The address of the ALT_SYSMGR_ROMCODE_CTL register for the ALT_SYSMGR_ROMCODE instance. */ -#define ALT_SYSMGR_ROMCODE_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_CTL_OFST)) -/* The address of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register for the ALT_SYSMGR_ROMCODE instance. */ -#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST)) -/* The address of the ALT_SYSMGR_ROMCODE_INITSWSTATE register for the ALT_SYSMGR_ROMCODE instance. */ -#define ALT_SYSMGR_ROMCODE_INITSWSTATE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST)) -/* The address of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register for the ALT_SYSMGR_ROMCODE instance. */ -#define ALT_SYSMGR_ROMCODE_INITSWLASTLD_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST)) -/* The address of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register for the ALT_SYSMGR_ROMCODE instance. */ -#define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST)) -/* - * Register Group Instance : romcodegrp_warmramgrp - * - * Instance romcodegrp_warmramgrp of register group ALT_SYSMGR_ROMCODE_WARMRAM. - * - * - */ -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ -#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_EN_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ -#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_DATASTART_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ -#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_LEN_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ -#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_EXECUTION_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) -/* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register for the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP instance. */ -#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAM_CRC_ADDR ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) -/* The base address byte offset for the start of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ -#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_OFST 0x20 -/* The start address of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ -#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_OFST)) -/* The lower bound address range of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ -#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_LB_ADDR ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR -/* The upper bound address range of the ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP component. */ -#define ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ROMCODE_WARMRAMGRP_ADDR) + 0x20) - 1)) - - -/* The base address byte offset for the start of the ALT_SYSMGR_ROMCODE component. */ -#define ALT_SYSMGR_ROMCODE_OFST 0xc0 -/* The start address of the ALT_SYSMGR_ROMCODE component. */ -#define ALT_SYSMGR_ROMCODE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ROMCODE_OFST)) -/* The lower bound address range of the ALT_SYSMGR_ROMCODE component. */ -#define ALT_SYSMGR_ROMCODE_LB_ADDR ALT_SYSMGR_ROMCODE_ADDR -/* The upper bound address range of the ALT_SYSMGR_ROMCODE component. */ -#define ALT_SYSMGR_ROMCODE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMCODE_ADDR) + 0x40) - 1)) - - -/* - * Register Group Instance : romhwgrp - * - * Instance romhwgrp of register group ALT_SYSMGR_ROMHW. - * - * - */ -/* The address of the ALT_SYSMGR_ROMHW_CTL register for the ALT_SYSMGR_ROMHW instance. */ -#define ALT_SYSMGR_ROMHW_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ROMHW_ADDR) + ALT_SYSMGR_ROMHW_CTL_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_ROMHW component. */ -#define ALT_SYSMGR_ROMHW_OFST 0x100 -/* The start address of the ALT_SYSMGR_ROMHW component. */ -#define ALT_SYSMGR_ROMHW_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ROMHW_OFST)) -/* The lower bound address range of the ALT_SYSMGR_ROMHW component. */ -#define ALT_SYSMGR_ROMHW_LB_ADDR ALT_SYSMGR_ROMHW_ADDR -/* The upper bound address range of the ALT_SYSMGR_ROMHW component. */ -#define ALT_SYSMGR_ROMHW_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ROMHW_ADDR) + 0x4) - 1)) - - -/* - * Register Group Instance : sdmmcgrp - * - * Instance sdmmcgrp of register group ALT_SYSMGR_SDMMC. - * - * - */ -/* The address of the ALT_SYSMGR_SDMMC_CTL register for the ALT_SYSMGR_SDMMC instance. */ -#define ALT_SYSMGR_SDMMC_CTL_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + ALT_SYSMGR_SDMMC_CTL_OFST)) -/* The address of the ALT_SYSMGR_SDMMC_L3MST register for the ALT_SYSMGR_SDMMC instance. */ -#define ALT_SYSMGR_SDMMC_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + ALT_SYSMGR_SDMMC_L3MST_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_SDMMC component. */ -#define ALT_SYSMGR_SDMMC_OFST 0x108 -/* The start address of the ALT_SYSMGR_SDMMC component. */ -#define ALT_SYSMGR_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_SDMMC_OFST)) -/* The lower bound address range of the ALT_SYSMGR_SDMMC component. */ -#define ALT_SYSMGR_SDMMC_LB_ADDR ALT_SYSMGR_SDMMC_ADDR -/* The upper bound address range of the ALT_SYSMGR_SDMMC component. */ -#define ALT_SYSMGR_SDMMC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_SDMMC_ADDR) + 0x8) - 1)) - - -/* - * Register Group Instance : nandgrp - * - * Instance nandgrp of register group ALT_SYSMGR_NAND. - * - * - */ -/* The address of the ALT_SYSMGR_NAND_BOOTSTRAP register for the ALT_SYSMGR_NAND instance. */ -#define ALT_SYSMGR_NAND_BOOTSTRAP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + ALT_SYSMGR_NAND_BOOTSTRAP_OFST)) -/* The address of the ALT_SYSMGR_NAND_L3MST register for the ALT_SYSMGR_NAND instance. */ -#define ALT_SYSMGR_NAND_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + ALT_SYSMGR_NAND_L3MST_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_NAND component. */ -#define ALT_SYSMGR_NAND_OFST 0x110 -/* The start address of the ALT_SYSMGR_NAND component. */ -#define ALT_SYSMGR_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_NAND_OFST)) -/* The lower bound address range of the ALT_SYSMGR_NAND component. */ -#define ALT_SYSMGR_NAND_LB_ADDR ALT_SYSMGR_NAND_ADDR -/* The upper bound address range of the ALT_SYSMGR_NAND component. */ -#define ALT_SYSMGR_NAND_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_NAND_ADDR) + 0x8) - 1)) - - -/* - * Register Group Instance : usbgrp - * - * Instance usbgrp of register group ALT_SYSMGR_USB. - * - * - */ -/* The address of the ALT_SYSMGR_USB_L3MST register for the ALT_SYSMGR_USB instance. */ -#define ALT_SYSMGR_USB_L3MST_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_USB_ADDR) + ALT_SYSMGR_USB_L3MST_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_USB component. */ -#define ALT_SYSMGR_USB_OFST 0x118 -/* The start address of the ALT_SYSMGR_USB component. */ -#define ALT_SYSMGR_USB_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_USB_OFST)) -/* The lower bound address range of the ALT_SYSMGR_USB component. */ -#define ALT_SYSMGR_USB_LB_ADDR ALT_SYSMGR_USB_ADDR -/* The upper bound address range of the ALT_SYSMGR_USB component. */ -#define ALT_SYSMGR_USB_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_USB_ADDR) + 0x4) - 1)) - - -/* - * Register Group Instance : eccgrp - * - * Instance eccgrp of register group ALT_SYSMGR_ECC. - * - * - */ -/* The address of the ALT_SYSMGR_ECC_L2 register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_L2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_L2_OFST)) -/* The address of the ALT_SYSMGR_ECC_OCRAM register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_OCRAM_OFST)) -/* The address of the ALT_SYSMGR_ECC_USB0 register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_USB0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_USB0_OFST)) -/* The address of the ALT_SYSMGR_ECC_USB1 register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_USB1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_USB1_OFST)) -/* The address of the ALT_SYSMGR_ECC_EMAC0 register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_EMAC0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_EMAC0_OFST)) -/* The address of the ALT_SYSMGR_ECC_EMAC1 register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_EMAC1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_EMAC1_OFST)) -/* The address of the ALT_SYSMGR_ECC_DMA register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_DMA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_DMA_OFST)) -/* The address of the ALT_SYSMGR_ECC_CAN0 register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_CAN0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_CAN0_OFST)) -/* The address of the ALT_SYSMGR_ECC_CAN1 register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_CAN1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_CAN1_OFST)) -/* The address of the ALT_SYSMGR_ECC_NAND register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_NAND_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_NAND_OFST)) -/* The address of the ALT_SYSMGR_ECC_QSPI register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_QSPI_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_QSPI_OFST)) -/* The address of the ALT_SYSMGR_ECC_SDMMC register for the ALT_SYSMGR_ECC instance. */ -#define ALT_SYSMGR_ECC_SDMMC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + ALT_SYSMGR_ECC_SDMMC_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_ECC component. */ -#define ALT_SYSMGR_ECC_OFST 0x140 -/* The start address of the ALT_SYSMGR_ECC component. */ -#define ALT_SYSMGR_ECC_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_ECC_OFST)) -/* The lower bound address range of the ALT_SYSMGR_ECC component. */ -#define ALT_SYSMGR_ECC_LB_ADDR ALT_SYSMGR_ECC_ADDR -/* The upper bound address range of the ALT_SYSMGR_ECC component. */ -#define ALT_SYSMGR_ECC_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ECC_ADDR) + 0x40) - 1)) - - -/* - * Register Group Instance : pinmuxgrp - * - * Instance pinmuxgrp of register group ALT_SYSMGR_PINMUX. - * - * - */ -/* The address of the ALT_SYSMGR_PINMUX_EMACIO0 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO0_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO1 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO1_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO2 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO2_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO3 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO3_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO4 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO4_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO5 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO5_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO6 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO6_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO7 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO7_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO8 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO8_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO9 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO9_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO10 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO10_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO11 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO11_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO12 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO12_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO13 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO13_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO14 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO14_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO15 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO15_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO16 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO16_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO17 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO17_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO18 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO18_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_EMACIO19 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_EMACIO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_EMACIO19_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO0 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO0_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO1 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO1_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO2 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO2_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO3 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO3_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO4 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO4_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO5 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO5_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO6 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO6_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO7 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO7_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO8 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO8_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO9 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO9_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO10 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO10_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_FLSHIO11 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_FLSHIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_FLSHIO11_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO0 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO0_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO1 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO1_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO2 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO2_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO3 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO3_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO4 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO4_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO5 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO5_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO6 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO6_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO7 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO7_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO8 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO8_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO9 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO9_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO10 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO10_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO11 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO11_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO12 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO12_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO13 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO13_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO14 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO14_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO15 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO15_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO16 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO16_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO17 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO17_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO18 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO18_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO19 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO19_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO20 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO20_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO21 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO21_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO22 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO22_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO22_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO23 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO23_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO24 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO24_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO24_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO25 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO25_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO25_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO26 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO26_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO26_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO27 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO27_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO27_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO28 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO28_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO28_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO29 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO29_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO29_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO30 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO30_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO30_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GENERALIO31 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GENERALIO31_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GENERALIO31_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO0 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO0_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO1 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO1_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO2 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO2_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO3 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO3_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO4 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO4_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO5 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO5_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO6 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO6_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO7 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO7_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO8 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO8_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO9 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO9_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO10 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO10_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO11 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO11_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO12 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO12_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO13 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO13_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO14 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO14_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO15 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO15_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO16 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO16_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO17 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO17_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO18 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO18_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO19 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO19_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO20 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO20_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED1IO21 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED1IO21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED1IO21_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO0 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO0_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO1 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO1_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO2 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO2_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO3 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO3_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO4 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO4_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO5 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO5_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO6 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO6_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_MIXED2IO7 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_MIXED2IO7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_MIXED2IO7_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX48 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX48_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX48_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX49 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX49_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX49_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX50 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX50_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX50_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX51 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX51_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX51_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX52 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX52_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX52_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX53 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX53_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX53_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX54 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX54_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX54_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX55 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX55_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX55_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX56 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX56_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX56_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX57 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX57_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX57_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX58 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX58_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX58_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX59 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX59_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX59_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX60 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX60_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX60_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX61 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX61_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX61_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX62 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX62_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX62_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX63 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX63_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX63_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX64 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX64_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX64_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX65 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX65_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX65_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX66 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX66_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX66_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX67 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX67_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX67_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX68 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX68_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX68_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX69 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX69_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX69_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLINMUX70 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLINMUX70_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLINMUX70_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX0 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX0_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX1 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX1_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX2 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX2_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX3 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX3_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX4 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX4_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX5 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX5_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX6 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX6_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX7 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX7_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX8 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX8_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX9 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX9_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX10 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX10_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX11 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX11_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX12 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX12_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX13 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX13_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX13_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX14 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX14_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX14_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX15 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX15_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX15_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX16 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX16_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX16_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX17 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX17_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX17_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX18 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX18_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX18_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX19 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX19_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX19_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX20 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX20_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX20_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX21 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX21_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX21_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX22 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX22_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX22_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX23 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX23_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX23_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX24 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX24_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX24_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX25 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX25_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX25_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX26 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX26_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX26_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX27 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX27_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX27_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX28 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX28_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX28_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX29 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX29_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX29_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX30 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX30_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX30_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX31 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX31_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX31_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX32 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX32_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX32_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX33 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX33_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX33_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX34 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX34_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX34_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX35 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX35_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX35_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX36 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX36_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX36_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX37 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX37_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX37_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX38 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX38_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX38_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX39 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX39_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX39_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX40 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX40_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX40_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX41 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX41_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX41_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX42 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX42_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX42_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX43 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX43_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX43_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX44 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX44_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX44_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX45 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX45_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX45_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX46 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX46_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX46_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX47 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX47_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX47_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX48 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX48_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX48_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX49 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX49_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX49_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX50 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX50_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX50_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX51 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX51_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX51_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX52 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX52_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX52_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX53 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX53_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX53_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX54 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX54_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX54_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX55 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX55_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX55_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX56 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX56_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX56_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX57 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX57_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX57_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX58 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX58_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX58_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX59 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX59_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX59_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX60 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX60_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX60_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX61 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX61_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX61_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX62 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX62_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX62_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX63 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX63_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX63_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX64 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX64_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX64_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX65 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX65_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX65_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX66 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX66_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX66_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX67 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX67_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX67_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX68 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX68_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX68_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX69 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX69_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX69_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_GPLMUX70 register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_GPLMUX70_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_GPLMUX70_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_NANDUSEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_I2C0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_I2C3USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_I2C2USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_I2C1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST)) -/* The address of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register for the ALT_SYSMGR_PINMUX instance. */ -#define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST)) -/* The base address byte offset for the start of the ALT_SYSMGR_PINMUX component. */ -#define ALT_SYSMGR_PINMUX_OFST 0x400 -/* The start address of the ALT_SYSMGR_PINMUX component. */ -#define ALT_SYSMGR_PINMUX_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SYSMGR_ADDR) + ALT_SYSMGR_PINMUX_OFST)) -/* The lower bound address range of the ALT_SYSMGR_PINMUX component. */ -#define ALT_SYSMGR_PINMUX_LB_ADDR ALT_SYSMGR_PINMUX_ADDR -/* The upper bound address range of the ALT_SYSMGR_PINMUX component. */ -#define ALT_SYSMGR_PINMUX_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_PINMUX_ADDR) + 0x400) - 1)) - - -/* The base address byte offset for the start of the ALT_SYSMGR component. */ -#define ALT_SYSMGR_OFST 0xffd08000 -/* The start address of the ALT_SYSMGR component. */ -#define ALT_SYSMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SYSMGR_OFST)) -/* The lower bound address range of the ALT_SYSMGR component. */ -#define ALT_SYSMGR_LB_ADDR ALT_SYSMGR_ADDR -/* The upper bound address range of the ALT_SYSMGR component. */ -#define ALT_SYSMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SYSMGR_ADDR) + 0x4000) - 1)) - - -/* - * Component Instance : dmanonsecure - * - * Instance dmanonsecure of component ALT_DMANONSECURE. - * - * - */ -/* The address of the ALT_DMANONSECURE_REG register for the ALT_DMANONSECURE instance. */ -#define ALT_DMANONSECURE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DMANONSECURE_ADDR) + ALT_DMANONSECURE_REG_OFST)) -/* The base address byte offset for the start of the ALT_DMANONSECURE component. */ -#define ALT_DMANONSECURE_OFST 0xffe00000 -/* The start address of the ALT_DMANONSECURE component. */ -#define ALT_DMANONSECURE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DMANONSECURE_OFST)) -/* The lower bound address range of the ALT_DMANONSECURE component. */ -#define ALT_DMANONSECURE_LB_ADDR ALT_DMANONSECURE_ADDR -/* The upper bound address range of the ALT_DMANONSECURE component. */ -#define ALT_DMANONSECURE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DMANONSECURE_ADDR) + 0x4) - 1)) - - -/* - * Component Instance : dmasecure - * - * Instance dmasecure of component ALT_DMASECURE. - * - * - */ -/* The address of the ALT_DMASECURE_REG register for the ALT_DMASECURE instance. */ -#define ALT_DMASECURE_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_DMASECURE_ADDR) + ALT_DMASECURE_REG_OFST)) -/* The base address byte offset for the start of the ALT_DMASECURE component. */ -#define ALT_DMASECURE_OFST 0xffe01000 -/* The start address of the ALT_DMASECURE component. */ -#define ALT_DMASECURE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_DMASECURE_OFST)) -/* The lower bound address range of the ALT_DMASECURE component. */ -#define ALT_DMASECURE_LB_ADDR ALT_DMASECURE_ADDR -/* The upper bound address range of the ALT_DMASECURE component. */ -#define ALT_DMASECURE_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_DMASECURE_ADDR) + 0x4) - 1)) - - -/* - * Component Instance : spis0 - * - * Instance spis0 of component ALT_SPIS. - * - * - */ -/* The address of the ALT_SPIS_CTLR0 register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_CTLR0_ADDR ALT_SPIS_CTLR0_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_SPIENR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_SPIENR_ADDR ALT_SPIS_SPIENR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_MWCR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_MWCR_ADDR ALT_SPIS_MWCR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_TXFTLR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_TXFTLR_ADDR ALT_SPIS_TXFTLR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_RXFTLR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_RXFTLR_ADDR ALT_SPIS_RXFTLR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_TXFLR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_TXFLR_ADDR ALT_SPIS_TXFLR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_RXFLR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_RXFLR_ADDR ALT_SPIS_RXFLR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_SR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_SR_ADDR ALT_SPIS_SR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_IMR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_IMR_ADDR ALT_SPIS_IMR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_ISR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_ISR_ADDR ALT_SPIS_ISR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_RISR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_RISR_ADDR ALT_SPIS_RISR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_TXOICR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_TXOICR_ADDR ALT_SPIS_TXOICR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_RXOICR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_RXOICR_ADDR ALT_SPIS_RXOICR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_RXUICR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_RXUICR_ADDR ALT_SPIS_RXUICR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_ICR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_ICR_ADDR ALT_SPIS_ICR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_DMACR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_DMACR_ADDR ALT_SPIS_DMACR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_DMATDLR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_DMATDLR_ADDR ALT_SPIS_DMATDLR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_DMARDLR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_DMARDLR_ADDR ALT_SPIS_DMARDLR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_IDR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_IDR_ADDR ALT_SPIS_IDR_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_SPI_VER_ID register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_SPI_VER_ID_ADDR ALT_SPIS_SPI_VER_ID_ADDR(ALT_SPIS0_ADDR) -/* The address of the ALT_SPIS_DR register for the ALT_SPIS0 instance. */ -#define ALT_SPIS0_DR_ADDR ALT_SPIS_DR_ADDR(ALT_SPIS0_ADDR) -/* The base address byte offset for the start of the ALT_SPIS0 component. */ -#define ALT_SPIS0_OFST 0xffe02000 -/* The start address of the ALT_SPIS0 component. */ -#define ALT_SPIS0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIS0_OFST)) -/* The lower bound address range of the ALT_SPIS0 component. */ -#define ALT_SPIS0_LB_ADDR ALT_SPIS0_ADDR -/* The upper bound address range of the ALT_SPIS0 component. */ -#define ALT_SPIS0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIS0_ADDR) + 0x80) - 1)) - - -/* - * Component Instance : spis1 - * - * Instance spis1 of component ALT_SPIS. - * - * - */ -/* The address of the ALT_SPIS_CTLR0 register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_CTLR0_ADDR ALT_SPIS_CTLR0_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_SPIENR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_SPIENR_ADDR ALT_SPIS_SPIENR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_MWCR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_MWCR_ADDR ALT_SPIS_MWCR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_TXFTLR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_TXFTLR_ADDR ALT_SPIS_TXFTLR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_RXFTLR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_RXFTLR_ADDR ALT_SPIS_RXFTLR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_TXFLR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_TXFLR_ADDR ALT_SPIS_TXFLR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_RXFLR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_RXFLR_ADDR ALT_SPIS_RXFLR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_SR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_SR_ADDR ALT_SPIS_SR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_IMR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_IMR_ADDR ALT_SPIS_IMR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_ISR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_ISR_ADDR ALT_SPIS_ISR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_RISR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_RISR_ADDR ALT_SPIS_RISR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_TXOICR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_TXOICR_ADDR ALT_SPIS_TXOICR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_RXOICR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_RXOICR_ADDR ALT_SPIS_RXOICR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_RXUICR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_RXUICR_ADDR ALT_SPIS_RXUICR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_ICR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_ICR_ADDR ALT_SPIS_ICR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_DMACR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_DMACR_ADDR ALT_SPIS_DMACR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_DMATDLR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_DMATDLR_ADDR ALT_SPIS_DMATDLR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_DMARDLR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_DMARDLR_ADDR ALT_SPIS_DMARDLR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_IDR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_IDR_ADDR ALT_SPIS_IDR_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_SPI_VER_ID register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_SPI_VER_ID_ADDR ALT_SPIS_SPI_VER_ID_ADDR(ALT_SPIS1_ADDR) -/* The address of the ALT_SPIS_DR register for the ALT_SPIS1 instance. */ -#define ALT_SPIS1_DR_ADDR ALT_SPIS_DR_ADDR(ALT_SPIS1_ADDR) -/* The base address byte offset for the start of the ALT_SPIS1 component. */ -#define ALT_SPIS1_OFST 0xffe03000 -/* The start address of the ALT_SPIS1 component. */ -#define ALT_SPIS1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIS1_OFST)) -/* The lower bound address range of the ALT_SPIS1 component. */ -#define ALT_SPIS1_LB_ADDR ALT_SPIS1_ADDR -/* The upper bound address range of the ALT_SPIS1 component. */ -#define ALT_SPIS1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIS1_ADDR) + 0x80) - 1)) - - -/* - * Component Instance : spim0 - * - * Instance spim0 of component ALT_SPIM. - * - * - */ -/* The address of the ALT_SPIM_CTLR0 register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_CTLR0_ADDR ALT_SPIM_CTLR0_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_CTLR1 register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_CTLR1_ADDR ALT_SPIM_CTLR1_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_SPIENR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_SPIENR_ADDR ALT_SPIM_SPIENR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_MWCR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_MWCR_ADDR ALT_SPIM_MWCR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_SER register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_SER_ADDR ALT_SPIM_SER_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_BAUDR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_BAUDR_ADDR ALT_SPIM_BAUDR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_TXFTLR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_TXFTLR_ADDR ALT_SPIM_TXFTLR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_RXFTLR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_RXFTLR_ADDR ALT_SPIM_RXFTLR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_TXFLR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_TXFLR_ADDR ALT_SPIM_TXFLR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_RXFLR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_RXFLR_ADDR ALT_SPIM_RXFLR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_SR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_SR_ADDR ALT_SPIM_SR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_IMR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_IMR_ADDR ALT_SPIM_IMR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_ISR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_ISR_ADDR ALT_SPIM_ISR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_RISR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_RISR_ADDR ALT_SPIM_RISR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_TXOICR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_TXOICR_ADDR ALT_SPIM_TXOICR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_RXOICR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_RXOICR_ADDR ALT_SPIM_RXOICR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_RXUICR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_RXUICR_ADDR ALT_SPIM_RXUICR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_ICR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_ICR_ADDR ALT_SPIM_ICR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_DMACR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_DMACR_ADDR ALT_SPIM_DMACR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_DMATDLR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_DMATDLR_ADDR ALT_SPIM_DMATDLR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_DMARDLR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_DMARDLR_ADDR ALT_SPIM_DMARDLR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_IDR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_IDR_ADDR ALT_SPIM_IDR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_SPI_VER_ID register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_SPI_VER_ID_ADDR ALT_SPIM_SPI_VER_ID_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_DR register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_DR_ADDR ALT_SPIM_DR_ADDR(ALT_SPIM0_ADDR) -/* The address of the ALT_SPIM_RX_SMPL_DLY register for the ALT_SPIM0 instance. */ -#define ALT_SPIM0_RX_SMPL_DLY_ADDR ALT_SPIM_RX_SMPL_DLY_ADDR(ALT_SPIM0_ADDR) -/* The base address byte offset for the start of the ALT_SPIM0 component. */ -#define ALT_SPIM0_OFST 0xfff00000 -/* The start address of the ALT_SPIM0 component. */ -#define ALT_SPIM0_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIM0_OFST)) -/* The lower bound address range of the ALT_SPIM0 component. */ -#define ALT_SPIM0_LB_ADDR ALT_SPIM0_ADDR -/* The upper bound address range of the ALT_SPIM0 component. */ -#define ALT_SPIM0_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIM0_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : spim1 - * - * Instance spim1 of component ALT_SPIM. - * - * - */ -/* The address of the ALT_SPIM_CTLR0 register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_CTLR0_ADDR ALT_SPIM_CTLR0_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_CTLR1 register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_CTLR1_ADDR ALT_SPIM_CTLR1_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_SPIENR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_SPIENR_ADDR ALT_SPIM_SPIENR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_MWCR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_MWCR_ADDR ALT_SPIM_MWCR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_SER register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_SER_ADDR ALT_SPIM_SER_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_BAUDR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_BAUDR_ADDR ALT_SPIM_BAUDR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_TXFTLR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_TXFTLR_ADDR ALT_SPIM_TXFTLR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_RXFTLR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_RXFTLR_ADDR ALT_SPIM_RXFTLR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_TXFLR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_TXFLR_ADDR ALT_SPIM_TXFLR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_RXFLR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_RXFLR_ADDR ALT_SPIM_RXFLR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_SR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_SR_ADDR ALT_SPIM_SR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_IMR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_IMR_ADDR ALT_SPIM_IMR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_ISR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_ISR_ADDR ALT_SPIM_ISR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_RISR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_RISR_ADDR ALT_SPIM_RISR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_TXOICR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_TXOICR_ADDR ALT_SPIM_TXOICR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_RXOICR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_RXOICR_ADDR ALT_SPIM_RXOICR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_RXUICR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_RXUICR_ADDR ALT_SPIM_RXUICR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_ICR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_ICR_ADDR ALT_SPIM_ICR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_DMACR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_DMACR_ADDR ALT_SPIM_DMACR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_DMATDLR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_DMATDLR_ADDR ALT_SPIM_DMATDLR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_DMARDLR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_DMARDLR_ADDR ALT_SPIM_DMARDLR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_IDR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_IDR_ADDR ALT_SPIM_IDR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_SPI_VER_ID register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_SPI_VER_ID_ADDR ALT_SPIM_SPI_VER_ID_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_DR register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_DR_ADDR ALT_SPIM_DR_ADDR(ALT_SPIM1_ADDR) -/* The address of the ALT_SPIM_RX_SMPL_DLY register for the ALT_SPIM1 instance. */ -#define ALT_SPIM1_RX_SMPL_DLY_ADDR ALT_SPIM_RX_SMPL_DLY_ADDR(ALT_SPIM1_ADDR) -/* The base address byte offset for the start of the ALT_SPIM1 component. */ -#define ALT_SPIM1_OFST 0xfff01000 -/* The start address of the ALT_SPIM1 component. */ -#define ALT_SPIM1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SPIM1_OFST)) -/* The lower bound address range of the ALT_SPIM1 component. */ -#define ALT_SPIM1_LB_ADDR ALT_SPIM1_ADDR -/* The upper bound address range of the ALT_SPIM1 component. */ -#define ALT_SPIM1_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SPIM1_ADDR) + 0x100) - 1)) - - -/* - * Component Instance : scanmgr - * - * Instance scanmgr of component ALT_SCANMGR. - * - * - */ -/* The address of the ALT_SCANMGR_STAT register for the ALT_SCANMGR instance. */ -#define ALT_SCANMGR_STAT_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_STAT_OFST)) -/* The address of the ALT_SCANMGR_EN register for the ALT_SCANMGR instance. */ -#define ALT_SCANMGR_EN_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_EN_OFST)) -/* The address of the ALT_SCANMGR_FIFOSINGLEBYTE register for the ALT_SCANMGR instance. */ -#define ALT_SCANMGR_FIFOSINGLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOSINGLEBYTE_OFST)) -/* The address of the ALT_SCANMGR_FIFODOUBLEBYTE register for the ALT_SCANMGR instance. */ -#define ALT_SCANMGR_FIFODOUBLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFODOUBLEBYTE_OFST)) -/* The address of the ALT_SCANMGR_FIFOTRIPLEBYTE register for the ALT_SCANMGR instance. */ -#define ALT_SCANMGR_FIFOTRIPLEBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOTRIPLEBYTE_OFST)) -/* The address of the ALT_SCANMGR_FIFOQUADBYTE register for the ALT_SCANMGR instance. */ -#define ALT_SCANMGR_FIFOQUADBYTE_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_SCANMGR_ADDR) + ALT_SCANMGR_FIFOQUADBYTE_OFST)) -/* The base address byte offset for the start of the ALT_SCANMGR component. */ -#define ALT_SCANMGR_OFST 0xfff02000 -/* The start address of the ALT_SCANMGR component. */ -#define ALT_SCANMGR_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_SCANMGR_OFST)) -/* The lower bound address range of the ALT_SCANMGR component. */ -#define ALT_SCANMGR_LB_ADDR ALT_SCANMGR_ADDR -/* The upper bound address range of the ALT_SCANMGR component. */ -#define ALT_SCANMGR_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_SCANMGR_ADDR) + 0x20) - 1)) - - -/* - * Component Instance : rom - * - * Instance rom of component ALT_ROM. - * - * - */ -/* The base address byte offset for the start of the ALT_ROM component. */ -#define ALT_ROM_OFST 0xfffd0000 -/* The start address of the ALT_ROM component. */ -#define ALT_ROM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_ROM_OFST)) -/* The lower bound address range of the ALT_ROM component. */ -#define ALT_ROM_LB_ADDR ALT_ROM_ADDR -/* The upper bound address range of the ALT_ROM component. */ -#define ALT_ROM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_ROM_ADDR) + 0x10000) - 1)) - - -/* - * Component Instance : mpuscu - * - * Instance mpuscu of component ALT_MPUSCU. - * - * - */ -/* The address of the ALT_MPUSCU_REG register for the ALT_MPUSCU instance. */ -#define ALT_MPUSCU_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUSCU_ADDR) + ALT_MPUSCU_REG_OFST)) -/* The base address byte offset for the start of the ALT_MPUSCU component. */ -#define ALT_MPUSCU_OFST 0xfffec000 -/* The start address of the ALT_MPUSCU component. */ -#define ALT_MPUSCU_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_MPUSCU_OFST)) -/* The lower bound address range of the ALT_MPUSCU component. */ -#define ALT_MPUSCU_LB_ADDR ALT_MPUSCU_ADDR -/* The upper bound address range of the ALT_MPUSCU component. */ -#define ALT_MPUSCU_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_MPUSCU_ADDR) + 0x4) - 1)) - - -/* - * Component Instance : mpul2 - * - * Instance mpul2 of component ALT_MPUL2. - * - * - */ -/* The address of the ALT_MPUL2_REG register for the ALT_MPUL2 instance. */ -#define ALT_MPUL2_REG_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_ADDR) + ALT_MPUL2_REG_OFST)) -/* The base address byte offset for the start of the ALT_MPUL2 component. */ -#define ALT_MPUL2_OFST 0xfffef000 -/* The start address of the ALT_MPUL2 component. */ -#define ALT_MPUL2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_MPUL2_OFST)) -/* The lower bound address range of the ALT_MPUL2 component. */ -#define ALT_MPUL2_LB_ADDR ALT_MPUL2_ADDR -/* The upper bound address range of the ALT_MPUL2 component. */ -#define ALT_MPUL2_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_MPUL2_ADDR) + 0x4) - 1)) - - -/* - * Component Instance : ocram - * - * Instance ocram of component ALT_OCRAM. - * - * - */ -/* The base address byte offset for the start of the ALT_OCRAM component. */ -#define ALT_OCRAM_OFST 0xffff0000 -/* The start address of the ALT_OCRAM component. */ -#define ALT_OCRAM_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_OCRAM_OFST)) -/* The lower bound address range of the ALT_OCRAM component. */ -#define ALT_OCRAM_LB_ADDR ALT_OCRAM_ADDR -/* The upper bound address range of the ALT_OCRAM component. */ -#define ALT_OCRAM_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_OCRAM_ADDR) + 0x10000) - 1)) - - -/* - * Address Space : ALT_HPS - * - * Address Map - * - * Address Range | Component - * :------------------------|:----------------- - * 0x00000000 - 0xfbffffff | Undefined - * 0xfc000000 - 0xfc000003 | ALT_STM - * 0xfc000004 - 0xfeffffff | Undefined - * 0xff000000 - 0xff000003 | ALT_DAP - * 0xff000004 - 0xff1fffff | Undefined - * 0xff200000 - 0xff3fffff | ALT_LWFPGASLVS - * 0xff400000 - 0xff47ffff | ALT_LWH2F - * 0xff480000 - 0xff4fffff | Undefined - * 0xff500000 - 0xff507fff | ALT_H2F - * 0xff508000 - 0xff5fffff | Undefined - * 0xff600000 - 0xff67ffff | ALT_F2H - * 0xff680000 - 0xff6fffff | Undefined - * 0xff700000 - 0xff701fff | ALT_EMAC0 - * 0xff702000 - 0xff703fff | ALT_EMAC1 - * 0xff704000 - 0xff7043ff | ALT_SDMMC - * 0xff704400 - 0xff704fff | Undefined - * 0xff705000 - 0xff7050ff | ALT_QSPI - * 0xff705100 - 0xff705fff | Undefined - * 0xff706000 - 0xff706fff | ALT_FPGAMGR - * 0xff707000 - 0xff707fff | ALT_ACPIDMAP - * 0xff708000 - 0xff70807f | ALT_GPIO0 - * 0xff708080 - 0xff708fff | Undefined - * 0xff709000 - 0xff70907f | ALT_GPIO1 - * 0xff709080 - 0xff709fff | Undefined - * 0xff70a000 - 0xff70a07f | ALT_GPIO2 - * 0xff70a080 - 0xff7fffff | Undefined - * 0xff800000 - 0xff87ffff | ALT_L3 - * 0xff880000 - 0xff8fffff | Undefined - * 0xff900000 - 0xff9fffff | ALT_NANDDATA - * 0xffa00000 - 0xffafffff | ALT_QSPIDATA - * 0xffb00000 - 0xffb3ffff | ALT_USB0 - * 0xffb40000 - 0xffb7ffff | ALT_USB1 - * 0xffb80000 - 0xffb807ff | ALT_NAND - * 0xffb80800 - 0xffb8ffff | Undefined - * 0xffb90000 - 0xffb90003 | ALT_FPGAMGRDATA - * 0xffb90004 - 0xffbfffff | Undefined - * 0xffc00000 - 0xffc001ff | ALT_CAN0 - * 0xffc00200 - 0xffc00fff | Undefined - * 0xffc01000 - 0xffc011ff | ALT_CAN1 - * 0xffc01200 - 0xffc01fff | Undefined - * 0xffc02000 - 0xffc020ff | ALT_UART0 - * 0xffc02100 - 0xffc02fff | Undefined - * 0xffc03000 - 0xffc030ff | ALT_UART1 - * 0xffc03100 - 0xffc03fff | Undefined - * 0xffc04000 - 0xffc040ff | ALT_I2C0 - * 0xffc04100 - 0xffc04fff | Undefined - * 0xffc05000 - 0xffc050ff | ALT_I2C1 - * 0xffc05100 - 0xffc05fff | Undefined - * 0xffc06000 - 0xffc060ff | ALT_I2C2 - * 0xffc06100 - 0xffc06fff | Undefined - * 0xffc07000 - 0xffc070ff | ALT_I2C3 - * 0xffc07100 - 0xffc07fff | Undefined - * 0xffc08000 - 0xffc080ff | ALT_SPTMR0 - * 0xffc08100 - 0xffc08fff | Undefined - * 0xffc09000 - 0xffc090ff | ALT_SPTMR1 - * 0xffc09100 - 0xffc1ffff | Undefined - * 0xffc20000 - 0xffc3ffff | ALT_SDR - * 0xffc40000 - 0xffcfffff | Undefined - * 0xffd00000 - 0xffd000ff | ALT_OSC1TMR0 - * 0xffd00100 - 0xffd00fff | Undefined - * 0xffd01000 - 0xffd010ff | ALT_OSC1TMR1 - * 0xffd01100 - 0xffd01fff | Undefined - * 0xffd02000 - 0xffd020ff | ALT_L4WD0 - * 0xffd02100 - 0xffd02fff | Undefined - * 0xffd03000 - 0xffd030ff | ALT_L4WD1 - * 0xffd03100 - 0xffd03fff | Undefined - * 0xffd04000 - 0xffd041ff | ALT_CLKMGR - * 0xffd04200 - 0xffd04fff | Undefined - * 0xffd05000 - 0xffd050ff | ALT_RSTMGR - * 0xffd05100 - 0xffd07fff | Undefined - * 0xffd08000 - 0xffd0bfff | ALT_SYSMGR - * 0xffd0c000 - 0xffdfffff | Undefined - * 0xffe00000 - 0xffe00003 | ALT_DMANONSECURE - * 0xffe00004 - 0xffe00fff | Undefined - * 0xffe01000 - 0xffe01003 | ALT_DMASECURE - * 0xffe01004 - 0xffe01fff | Undefined - * 0xffe02000 - 0xffe0207f | ALT_SPIS0 - * 0xffe02080 - 0xffe02fff | Undefined - * 0xffe03000 - 0xffe0307f | ALT_SPIS1 - * 0xffe03080 - 0xffefffff | Undefined - * 0xfff00000 - 0xfff000ff | ALT_SPIM0 - * 0xfff00100 - 0xfff00fff | Undefined - * 0xfff01000 - 0xfff010ff | ALT_SPIM1 - * 0xfff01100 - 0xfff01fff | Undefined - * 0xfff02000 - 0xfff0201f | ALT_SCANMGR - * 0xfff02020 - 0xfffcffff | Undefined - * 0xfffd0000 - 0xfffdffff | ALT_ROM - * 0xfffe0000 - 0xfffebfff | Undefined - * 0xfffec000 - 0xfffec003 | ALT_MPUSCU - * 0xfffec004 - 0xfffeefff | Undefined - * 0xfffef000 - 0xfffef003 | ALT_MPUL2 - * 0xfffef004 - 0xfffeffff | Undefined - * 0xffff0000 - 0xffffffff | ALT_OCRAM - */ - -#ifdef __ASSEMBLY__ -#define ALT_CAST(type, ptr) ptr -#else /* __ASSEMBLY__ */ -#define ALT_CAST(type, ptr) ((type) (ptr)) -#endif /* __ASSEMBLY__ */ -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_HPS_H__ */ - diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h deleted file mode 100644 index f6090cd0ca..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h +++ /dev/null @@ -1,259 +0,0 @@ -/****************************************************************************** - * - * Copyright 2013 Altera Corporation. All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO - * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - ******************************************************************************/ - - -/*! \file Altera - ALT_SOCAL */ - -#ifndef __ALTERA_SOCAL_H__ -#define __ALTERA_SOCAL_H__ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#include <cstddef> -#include <cstdbool> -#include <cstdint> -#else /* __cplusplus */ -#include <stddef.h> -#include <stdbool.h> -#include <stdint.h> -#endif /* __cplusplus */ -#endif /* __ASSEMBLY__ */ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/*! - * \addtogroup ALT_SOCAL_UTIL SoCAL Utilities - * - * This file contains utility and support functions for the Altera SoCAL. - * @{ - */ - -#ifdef __ASSEMBLY__ -#define ALT_CAST(type, ptr) ptr -#else /* __ASSEMBLY__ */ -/*! Cast the pointer to specified pointer type. - * - * Note: This macro expands to \e ptr value only for assembler language - * targets. - * - * \param type The pointer type to cast to - * \param ptr The pointer to apply the type cast to - */ -#define ALT_CAST(type, ptr) ((type) (ptr)) -#endif /* __ASSEMBLY__ */ - -/*! - * \addtogroup ALT_SOCAL_UTIL_RW_FUNC SoCAL Memory Read/Write Utilities - * - * This section implements read and write functionality for various - * memory untis. The memory unit terms used for these functions are - * consistent with those used in the ARM Architecture Reference Manual - * ARMv7-A and ARMv7-R edition manual. The terms used for units of memory are: - * - * Unit of Memory | Abbreviation | Size in Bits - * :---------------|:-------------|:------------: - * Byte | byte | 8 - * Half Word | hword | 16 - * Word | word | 32 - * Double Word | dword | 64 - * - * @{ - */ - -/*! Write the 8 bit byte to the destination address in device memory. - * \param dest - Write destination pointer address - * \param src - 8 bit data byte to write to memory - */ -#define alt_write_byte(dest, src) (*ALT_CAST(volatile uint8_t *, (dest)) = (src)) - -/*! Read and return the 8 bit byte from the source address in device memory. - * \param src Read source pointer address - * \returns 8 bit data byte value - */ -#define alt_read_byte(src) (*ALT_CAST(volatile uint8_t *, (src))) - -/*! Write the 16 bit half word to the destination address in device memory. - * \param dest - Write destination pointer address - * \param src - 16 bit data half word to write to memory - */ -#define alt_write_hword(dest, src) (*ALT_CAST(volatile uint16_t *, (dest)) = (src)) - -/*! Read and return the 16 bit half word from the source address in device memory. - * \param src Read source pointer address - * \returns 16 bit data half word value - */ -#define alt_read_hword(src) (*ALT_CAST(volatile uint16_t *, (src))) - -/*! Write the 32 bit word to the destination address in device memory. - * \param dest - Write destination pointer address - * \param src - 32 bit data word to write to memory - */ -#define alt_write_word(dest, src) (*ALT_CAST(volatile uint32_t *, (dest)) = (src)) - -/*! Read and return the 32 bit word from the source address in device memory. - * \param src Read source pointer address - * \returns 32 bit data word value - */ -#define alt_read_word(src) (*ALT_CAST(volatile uint32_t *, (src))) - -/*! Write the 64 bit double word to the destination address in device memory. - * \param dest - Write destination pointer address - * \param src - 64 bit data double word to write to memory - */ -#define alt_write_dword(dest, src) (*ALT_CAST(volatile uint64_t *, (dest)) = (src)) - -/*! Read and return the 64 bit double word from the source address in device memory. - * \param src Read source pointer address - * \returns 64 bit data double word value - */ -#define alt_read_dword(src) (*ALT_CAST(volatile uint64_t *, (src))) - -/*! @} */ - -/*! - * \addtogroup ALT_SOCAL_UTIL_SC_FUNC SoCAL Memory Bit Set/Clr/XOR/Replace Utilities - * - * This section implements useful macros to set, clear, change, and replace - * selected bits within a word in memory or a memory-mapped register. - * @{ - * - */ - -/*! Set selected bits in the 8 bit byte at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to set in destination byte - */ -#define alt_setbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) | (bits))) - -/*! Clear selected bits in the 8 bit byte at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to clear in destination byte - */ -#define alt_clrbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) & ~(bits))) - -/*! Change or toggle selected bits in the 8 bit byte at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to change in destination byte - */ -#define alt_xorbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) ^ (bits))) - -/*! Replace selected bits in the 8 bit byte at the destination address in device memory. - * \param dest - Destination pointer address - * \param msk - Bits to replace in destination byte - * \param src - Source bits to write to cleared bits in destination byte - */ -#define alt_replbits_byte(dest, msk, src) (alt_write_byte(dest,(alt_read_byte(dest) & ~(msk)) | ((src) & (msk)))) - -/*! Set selected bits in the 16 bit halfword at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to set in destination halfword - */ -#define alt_setbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) | (bits))) - -/*! Clear selected bits in the 16 bit halfword at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to clear in destination halfword - */ -#define alt_clrbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) & ~(bits))) - -/*! Change or toggle selected bits in the 16 bit halfword at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to change in destination halfword - */ -#define alt_xorbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) ^ (bits))) - -/*! Replace selected bits in the 16 bit halfword at the destination address in device memory. - * \param dest - Destination pointer address - * \param msk - Bits to replace in destination halfword - * \param src - Source bits to write to cleared bits in destination halfword - */ -#define alt_replbits_hword(dest, msk, src) (alt_write_hword(dest,(alt_read_hword(dest) & ~(msk)) | ((src) & (msk)))) - -/*! Set selected bits in the 32 bit word at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to set in destination word - */ -#define alt_setbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) | (bits))) - -/*! Clear selected bits in the 32 bit word at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to clear in destination word - */ -#define alt_clrbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) & ~(bits))) - -/*! Change or toggle selected bits in the 32 bit word at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to change in destination word - */ -#define alt_xorbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) ^ (bits))) - -/*! Replace selected bits in the 32 bit word at the destination address in device memory. - * \param dest - Destination pointer address - * \param msk - Bits to replace in destination word - * \param src - Source bits to write to cleared bits in destination word - */ -#define alt_replbits_word(dest, msk, src) (alt_write_word(dest,(alt_read_word(dest) & ~(msk)) | ((src) & (msk)))) - -/*! Set selected bits in the 64 bit doubleword at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to set in destination doubleword - */ -#define alt_setbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) | (bits))) - -/*! Clear selected bits in the 64 bit doubleword at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to clear in destination doubleword - */ -#define alt_clrbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) & ~(bits))) - -/*! Change or toggle selected bits in the 64 bit doubleword at the destination address in device memory. - * \param dest - Destination pointer address - * \param bits - Bits to change in destination doubleword - */ -#define alt_xorbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) ^ (bits))) - -/*! Replace selected bits in the 64 bit doubleword at the destination address in device memory. - * \param dest - Destination pointer address - * \param msk - Bits to replace in destination doubleword - * \param src - Source bits to write to cleared bits in destination word - */ -#define alt_replbits_dword(dest, msk, src) (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk)))) - -/*! @} */ - -/*! @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* __ALTERA_SOCAL_H__ */ |