diff options
Diffstat (limited to 'c/src/exec/score/cpu')
233 files changed, 0 insertions, 46744 deletions
diff --git a/c/src/exec/score/cpu/.cvsignore b/c/src/exec/score/cpu/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/Makefile.am b/c/src/exec/score/cpu/Makefile.am deleted file mode 100644 index 3e84557494..0000000000 --- a/c/src/exec/score/cpu/Makefile.am +++ /dev/null @@ -1,13 +0,0 @@ -## -## $Id$ -## - - -SUBDIRS = $(RTEMS_CPU) - -## FIXME: this does not work -## DIST_SUBDIRS = \ -## a29k hppa1.1 i386 i960 m68k mips64orion no_cpu powerpc sh sparc unix - -include $(top_srcdir)/automake/subdirs.am -include $(top_srcdir)/automake/local.am diff --git a/c/src/exec/score/cpu/a29k/.cvsignore b/c/src/exec/score/cpu/a29k/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/a29k/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/a29k/ChangeLog b/c/src/exec/score/cpu/a29k/ChangeLog deleted file mode 100644 index 0b516b2df7..0000000000 --- a/c/src/exec/score/cpu/a29k/ChangeLog +++ /dev/null @@ -1,124 +0,0 @@ -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Filled in something that was marked XXX. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: Use cpuopts.h instead of targopts.h. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/a29ktypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-25 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/a29k.h, rtems/score/cpu.h: Switched to using - cpuopts.h not targopts.h to reduce dependency on BSP. - -2000-09-22 Joel Sherrill <joel@OARcorp.com> - - * amd.ah, cpu.c, cpu_asm.S, register.ah, sig.S, rtems/score/cpu.h: - Updated and fixed minor things. Commented out offensive assembly - and made applications link. - -2000-09-22 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am, cpu_asm.S, psmacro.ah, rtems/score/cpu.h: - First attempt to compile with GNU tools. Minor modifications - to compile enough to get to assembler errors. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am, remove duplicate includes. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/a29k/Makefile.am b/c/src/exec/score/cpu/a29k/Makefile.am deleted file mode 100644 index 113d0cd348..0000000000 --- a/c/src/exec/score/cpu/a29k/Makefile.am +++ /dev/null @@ -1,55 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = amd.ah asm.h pswmacro.ah register.ah -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/a29k.h \ - rtems/score/types.h \ - rtems/score/cpu.h \ - rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S sig.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S sig.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/a29k/amd.ah b/c/src/exec/score/cpu/a29k/amd.ah deleted file mode 100644 index 84a749edea..0000000000 --- a/c/src/exec/score/cpu/a29k/amd.ah +++ /dev/null @@ -1,534 +0,0 @@ -#if 0 - -; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Initialization values for registers after RESET -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; -: /* $Id$ */ -;* File information and includes. - -#endif - .file "amd.ah" - .ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI" - - - -; -;* AMD PROCESSOR SPECIFIC VALUES... -; - -; -;* Processor revision levels... -; - -; PRL values: 31-28 27-24 -; Am29000 0 x -; Am29005 1 x -; Am29050 2 x -; Am29035 3 x -; Am29030 4 x -; Am29200 5 x -; Am29205 5 1x -; Am29240 6 0 -; Manx 7 0 -; Cougar 8 0 - - - .equ AM29000_PRL, 0x00 - - .equ AM29005_PRL, 0x10 - - .equ AM29050_PRL, 0x20 - - .equ AM29035_PRL, 0x30 - - .equ AM29030_PRL, 0x40 - - .equ AM29200_PRL, 0x50 - - .equ AM29205_PRL, 0x58 - - .equ AM29240_PRL, 0x60 - - .equ AM29040_PRL, 0x70 - - .equ MANX_PRL, 0x70 - - .equ COUGAR_PRL, 0x80 - -; -;* data structures sizes. -; - .equ CFGINFO_SIZE, 16*4 - - .equ PGMINFO_SIZE, 16*4 - - .equ VARARGS_SPACE, 16*4 - - .equ WINDOWSIZE, 0x80 -; -;* Am29027 Mode registers -; - - .equ Am29027Mode1, 0x0fc00820 - - .equ Am29027Mode2, 0x00001375 - - - -;* Processor Based Equates and Defines - - .equ SIG_SYNC, -1 - - .equ ENABLE, (SM) - - .equ DISABLE, (ENABLE | DI | DA) - - .equ DISABLE_FZ, (FZ | ENABLE | DI | DA) - - .equ CLR_TRAP, (FZ | DA) - - .equ InitOPS, (TD | SM | (3<<IMShift) | DI | DA) - - .equ InitCPS, (TD | SM | (0<<IMShift) | DI | DA) - - .equ InitCPS1, (TD | SM | (0<<IMShift) | DI ) - - .equ CPS_TMR, (SM | (0<<IMShift) | DI) - - .equ CPS_INT0, (TD | SM | (0<<IMShift)) - - .equ CPS_TMRINT0, (SM | (0<<IMShift)) - - .equ InitCFG, 0x0 - - .equ InitRBP, (B0|B1|B2|B3|B4|B5) - - .equ TMC_VALUE, 0xFFFFFF - - .equ TMR_VALUE, (IE | TMC_VALUE) - - - - - - -;* 29205 specific (internal) peripheral initialization constants. - -; Current Processor Status (CPS) Register. -; Old Processor Status Register (OPS). - - .equ DA, 0x00001 - .equ DI, 0x00002 - .equ IMShift,0x2 - .equ SM, 0x00010 - .equ PI, 0x00020 - .equ PD, 0x00040 - .equ WM, 0x00080 - .equ RE, 0x00100 - .equ LK, 0x00200 - .equ FZ, 0x00400 - .equ TU, 0x00800 - .equ TP, 0x01000 - .equ TE, 0x02000 - .equ IP, 0x04000 - .equ CA, 0x08000 - .equ MM, 0x10000 - .equ TD, 0x20000 - -; Configuration Register (CFG) - - .equ CD, 0x01 - .equ CP, 0x02 - .equ BO, 0x04 - .equ RV, 0x08 - .equ VF, 0x10 - .equ DW, 0x20 - .equ CO, 0x40 - .equ EE, 0x80 - .equ IDShift, 8 - .equ CFG_ID, 0x100 - .equ ILShift, 9 - .equ CFG_ILMask, 0x600 - .equ DDShift, 11 - .equ CFG_DD, 0x800 - .equ DLShift, 12 - .equ CFG_DLMask, 0x3000 - .equ PCEShift, 14 - .equ CFG_PCE, 0x4000 - .equ PMBShift, 16 - .equ D16, 0x8000 - .equ TBOShift, 23 - .equ PRLShift, 24 - -; Channel Control Register (CHC) - - .equ CV, 0x1 - .equ NN, 0x2 - .equ TRShift, 2 - .equ TF, 0x400 - .equ PER, 0x800 - .equ LA, 0x1000 - .equ ST, 0x2000 - .equ ML, 0x4000 - .equ LS, 0x8000 - .equ CRShift, 16 - .equ CNTLShift, 24 - .equ CEShift, 31 - .equ WBERShift, 31 - -; Register Bank Protect (RBP) - .equ B0, 0x1 - .equ B1, 0x2 - .equ B2, 0x4 - .equ B3, 0x8 - .equ B4, 0x10 - .equ B5, 0x20 - .equ B6, 0x40 - .equ B7, 0x80 - .equ B8, 0x100 - .equ B9, 0x200 - .equ B10, 0x400 - .equ B11, 0x800 - .equ B12, 0x1000 - .equ B13, 0x2000 - .equ B14, 0x4000 - .equ B15, 0x8000 - -; Timer Counter - - .equ TCVMask, 0xffffff - -; Timer Reload Register - - .equ IE, 0x1000000 - .equ IN, 0x2000000 - .equ OV, 0x4000000 - .equ TRVMAsk, 0xffffff - -; MMU Configuration - - .equ PSShift, 8 - .equ PS0Shift, 8 - .equ PS1Shift, 12 - -; LRU Recommendation (LRU) - .equ LRUMask, 0xff - -; Reason Vector (RSN) - .equ RSNMask, 0xff - -; Region Mapping Address (RMA0 | RMA1) - .equ PBAMask,0xffff - .equ VBAShift, 16 - -; Region Mapping Control (RMC0 | RMC1) - .equ TIDMask, 0xff - .equ RMC_UE, 0x100 - .equ RMC_UW, 0x200 - .equ RMC_UR, 0x400 - .equ RMC_SE, 0x800 - .equ RMC_SW, 0x1000 - .equ RMC_SR, 0x2000 - .equ RMC_VE, 0x4000 - .equ RMC_IO, 0x10000 - .equ RGSShift, 17 - .equ RMC_PGMShift, 22 - -; Instruction breakpoint Control (IBC0 | IBC1) - .equ BPIDMask, 0xff - .equ BTE, 0x100 - .equ BRM, 0x200 - .equ IBC_BSY, 0x400 - .equ BEN, 0x800 - .equ BHO, 0x1000 - -; Cache Data Register (CDR) - .equ CDR_US, 0x1 - .equ P, 0x2 - .equ CDR_V, 0x4 - .equ IATAGShift, 20 - -; Cache Interface Register (CIR) - .equ CPTRShift, 2 - .equ CIR_RW, 0x1000000 - .equ FSELShift, 28 - -; Indirect Pointer A, B, C (IPA, IPB, IPC) - .equ IPShift, 2 - -; ALU Status (ALU) - .equ FCMask, 0x1F - .equ BPShift, 5 - .equ C, 0x80 - .equ Z, 0x100 - .equ N, 0x200 - .equ ALU_V, 0x400 - .equ DF, 0x800 - -; Byte Pointer - .equ BPMask, 0x3 - -; Load/Store Count Remaining (CR) - .equ CRMask, 0xff - -; Floating Point Environment (FPE) - .equ NM, 0x1 - .equ RM, 0x2 - .equ VM, 0x4 - .equ UM, 0x8 - .equ XM, 0x10 - .equ DM, 0x20 - .equ FRMShift, 6 - .equ FF, 0x100 - .equ ACFShift, 9 - -; Integer Environment (INTE) - .equ MO, 0x1 - .equ DO, 0x2 - -; Floating Point Status (FPS) - .equ NS, 0x1 - .equ RS, 0x2 - .equ VS, 0x4 - .equ FPS_US, 0x8 - .equ XS, 0x10 - .equ DS, 0x20 - .equ NT, 0x100 - .equ RT, 0x200 - .equ VT, 0x400 - .equ UT, 0x800 - .equ XT, 0x1000 - .equ DT, 0x2000 - -; Exception Opcode (EXOP) - .equ IOPMask, 0xff - -; TLB Entry Word 0 -; .equ TIDMask, 0xff already defined above - .equ TLB_UE, 0x100 - .equ TLB_UW, 0x200 - .equ TLB_UR, 0x400 - .equ TLB_SE, 0x800 - .equ TLB_SW, 0x1000 - .equ TLB_SR, 0x2000 - .equ TLB_VE, 0x4000 - .equ VTAGShift, 15 - -; TLB Entry Word 1 - .equ TLB_IO, 0x1 - .equ U, 0x2 - .equ TLB_PGMShift, 6 - .equ RPNShift, 10 - -; Am29200 ROM Control bits. - .equ RMCT_DW0Shift, 29 - .equ RMCT_DW1Shift, 21 - .equ RMCT_DW2Shift, 13 - .equ RMCT_DW3Shift, 5 - -; Am29200 DRAM Control bits. - .equ DW3, (1<<18) - .equ DW2, (1<<22) - .equ DW1, (1<<26) - .equ DW0, (1<<30) - - ; Internal peripheral address assignments. - .equ RMCT, 0x80000000 - .equ RMCF, 0x80000004 - .equ DRCT, 0x80000008 - .equ DRCF, 0x8000000C - .equ DRM0, 0x80000010 - .equ DRM1, 0x80000014 - .equ DRM2, 0x80000018 - .equ DRM3, 0x8000001C - .equ PIACT0, 0x80000020 - .equ PIACT1, 0x80000020 - .equ ICT, 0x80000028 - .equ DMCT0, 0x80000030 - .equ DMAD0, 0x80000034 - .ifdef revA - .equ TAD0, 0x80000036 - .equ TCN0, 0x8000003A - .else - .equ TAD0, 0x80000070 ; default - .equ TCN0, 0x8000003C ; default - .endif - .equ DMCN0, 0x80000038 - .equ DMCT1, 0x80000040 - .equ DMAD1, 0x80000044 - .equ DMCN1, 0x80000048 - .equ SPCT, 0x80000080 - .equ SPST, 0x80000084 - .equ SPTH, 0x80000088 - .equ SPRB, 0x8000008C - .equ BAUD, 0x80000090 - .equ PPCT, 0x800000C0 - .equ PPST, 0x800000C1 - .equ PPDT, 0x800000C4 - .equ POCT, 0x800000D0 - .equ PIN, 0x800000D4 - .equ POUT, 0x800000D8 - .equ POEN, 0x800000DC - .equ VCT, 0x800000E0 - .equ TOP, 0x800000E4 - .equ SIDE, 0x800000E8 - .equ VDT, 0x800000EC - - ; Interrupt Controller Register bits. - .equ TXDI, (1<<5) - .equ RXDI, (1<<6) - .equ RXSI, (1<<7) - .equ PPI, (1<<11) - .equ DMA1I, (1<<13) - .equ DMA0I, (1<<14) - .equ IOPIMask, (0xFF<<16) - .equ VDI, (1<<27) - .equ ICT200_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI) - .equ ICT205_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI) - - ; Serial port Initialization bits - .equ NO_PARITY, 0 - - - ; SPST bits - .equ THREShift, 22 - -;* REGISTER Addresses - - .equ ROMCntlRegAddr, 0x80000000 - - .equ ROMCfgRegAddr, 0x80000004 - - .equ DRAMCntlRegAddr, 0x80000008 - - .equ DRAMCfgRegAddr, 0x8000000C - - .equ DRAMMap0RegAddr, 0x80000010 - - .equ DRAMMap1RegAddr, 0x80000014 - - .equ DRAMMap2RegAddr, 0x80000018 - - .equ DRAMMap3RegAddr, 0x8000001C - - .equ PIACntl0RegAddr, 0x80000020 - - .equ PIACntl1RegAddr, 0x80000024 - - .equ INTRCntlRegAddr, 0x80000028 - - .equ DMACntl0RegAddr, 0x80000030 - - .equ DMACntl1RegAddr, 0x80000040 - - .equ SERPortCntlRegAddr, 0x80000080 - - .equ SERPortStatRegAddr, 0x80000084 - - .equ SERPortTHLDRegAddr, 0x80000088 - - .equ SERPortRbufRegAddr, 0x8000008C - - .equ SERPortBaudRegAddr, 0x80000090 - - .equ PARPortCntlRegAddr, 0x800000C0 - - .equ PIOCntlRegAddr, 0x800000D0 - - .equ PIOInpRegAddr, 0x800000D4 - - .equ PIOOutRegAddr, 0x800000D8 - - .equ PIOOutEnaRegAddr, 0x800000DC - - .equ VCTCntlRegAddr, 0x800000E0 - -; -;* Control constants -; - -;* AM29030 Timer related constants. - - .equ TMR_IE, 0x01000000 - - .equ TMR_IN, 0x02000000 - - .equ TMR_OV, 0x04000000 - - .equ TMC_INITCNT, 1613 - -; -;* System initialization values. -; - - .equ __os_version, 0x0001 ; - - .equ STACKSize, 0x8000 ; - - .equ PGMExecMode, 0x0000 ; - - .equ TSTCK_OFST, 28 * 4 - - .equ CSTCK_OFST, 29 * 4 - - .equ TMSTCK_OFST, 30 * 4 - - .equ CMSTCK_OFST, 31 * 4 - - .equ CTXSW_OK, 0xA55A ; ctx switch ok - - .set NV_STARTOFST, 0x20 ; 32 bytes - - .set NV_BAUDOFST, 0x00 ; 00 bytes - - .set reg_cir, 29 - - .set reg_cdr, 30 - - .equ MSG_BUFSIZE, 0x1000 ; serial buffer size - - .equ ILLOPTRAP, 0 - - .equ UATRAP, 1 - - .equ PVTRAP, 5 - - .equ UITLBMISSTRAP, 8 - - .equ UDTLBMISSTRAP, 9 - - .equ TIMERTRAP, 14 - - .equ TRACETRAP, 15 - - .equ XLINXTRAP, 16 - - .equ SERIALTRAP, 17 - - .equ SLOWTMRTRAP, 18 - - .equ PORTTRAP, 19 - - .equ SVSCTRAP, 80 - - .equ SVSCTRAP1, 81 - - .equ V_CACHETRAP, 66 ; - - .equ V_SETSERVICE, 67 ; - - .equ INIT_TIMER, 100 - - .equ DISABLE_TIMER, 101 - - .equ GET_TIMER, 102 - - .equ CLEAR_TIMER, 103 - - .equ V_SPILL, 64 - - .equ V_FILL, 65 - - .equ SIGDFL, 105 diff --git a/c/src/exec/score/cpu/a29k/asm.h b/c/src/exec/score/cpu/a29k/asm.h deleted file mode 100644 index 51e77ec194..0000000000 --- a/c/src/exec/score/cpu/a29k/asm.h +++ /dev/null @@ -1,101 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * !!! THIS FILE DOES NOT APPEAR TO HAVE BEEN USED IN THE 29K PORT !!! - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1989-1997 - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __A29K_ASM_h -#define __A29K_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/asm.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/a29k/configure.ac b/c/src/exec/score/cpu/a29k/configure.ac deleted file mode 100644 index 8139f18a04..0000000000 --- a/c/src/exec/score/cpu/a29k/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-a29k],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/a29k/cpu.c b/c/src/exec/score/cpu/a29k/cpu.c deleted file mode 100644 index 158f680d4e..0000000000 --- a/c/src/exec/score/cpu/a29k/cpu.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * AMD 29K CPU Dependent Source - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -#ifndef lint -static char _sccsid[] = "@(#)cpu.c 10/21/96 1.8\n"; -#endif - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/thread.h> -#include <stdio.h> -#include <stdlib.h> - -void a29k_ISR_Handler(unsigned32 vector); - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch)() /* ignored on this CPU */ -) -{ - unsigned int i; - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; - - for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ ) - { - _ISR_Vector_table[i] = (proc_ptr)NULL; - } -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 cps; - - /* - * This routine returns the current interrupt level. - */ - cps = a29k_getops(); - if (cps & (TD|DI)) - return 1; - else - return 0; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -extern void intr14( void ); -extern void intr18( void ); -extern void intr19( void ); - -/* just to link with GNU tools JRS 09/22/2000 */ -asm (".global V_SPILL, V_FILL" ); -asm (".global V_EPI_OS, V_BSD_OS" ); - -asm (".equ V_SPILL, 64" ); -asm (".equ V_FILL, 65" ); - -asm (".equ V_BSD_OS, 66" ); -asm (".equ V_EPI_OS, 69" ); - -/* end of just to link with GNU tools */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - switch( vector ) - { -/* where is this code? JRS */ -#if 0 - case 14: - _settrap( vector, intr14 ); - break; - case 18: - _settrap( vector, intr18 ); - break; - case 19: - _settrap( vector, intr19 ); - break; -#endif - - default: - break; - } -} - - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - { - } - /* insert your "halt" instruction here */ ; -} - -void a29k_fatal_error( unsigned32 error ) -{ - printf("\n\nfatal error %d, rebooting!!!\n",error ); - exit(error); -} - - /* - * This discussion ignores a lot of the ugly details in a real - * implementation such as saving enough registers/state to be - * able to do something real. Keep in mind that the goal is - * to invoke a user's ISR handler which is written in C and - * uses a certain set of registers. - * - * Also note that the exact order is to a large extent flexible. - * Hardware will dictate a sequence for a certain subset of - * _ISR_Handler while requirements for setting - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - * - */ - -void a29k_ISR_Handler(unsigned32 vector) -{ - _ISR_Nest_level++; - _Thread_Dispatch_disable_level++; - if ( _ISR_Vector_table[ vector ] ) - (*_ISR_Vector_table[ vector ])( vector ); - --_Thread_Dispatch_disable_level; - --_ISR_Nest_level; - if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level && - (_Context_Switch_necessary || _ISR_Signals_to_thread_executing )) - _Thread_Dispatch(); - return; -} diff --git a/c/src/exec/score/cpu/a29k/cpu_asm.S b/c/src/exec/score/cpu/a29k/cpu_asm.S deleted file mode 100644 index cc35e79ee3..0000000000 --- a/c/src/exec/score/cpu/a29k/cpu_asm.S +++ /dev/null @@ -1,522 +0,0 @@ -;/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s -; * -; * Author: Craig Lebakken <craigl@transition.com> -; * -; * COPYRIGHT (c) 1996 by Transition Networks Inc. -; * -; * To anyone who acknowledges that this file is provided "AS IS" -; * without any express or implied warranty: -; * permission to use, copy, modify, and distribute this file -; * for any purpose is hereby granted without fee, provided that -; * the above copyright notice and this notice appears in all -; * copies, and that the name of Transition Networks not be used in -; * advertising or publicity pertaining to distribution of the -; * software without specific, written prior permission. -; * Transition Networks makes no representations about the suitability -; * of this software for any purpose. -; * -; * -; * This file contains the basic algorithms for all assembly code used -; * in an specific CPU port of RTEMS. These algorithms must be implemented -; * in assembly language -; * -; * NOTE: This is supposed to be a .S or .s file NOT a C file. -; * -; * COPYRIGHT (c) 1989-1999. -; * On-Line Applications Research Corporation (OAR). -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.OARcorp.com/rtems/license.html. -; * -; * $Id$ -; */ - -;/* -; * This is supposed to be an assembly file. This means that system.h -; * and cpu.h should not be included in a "real" cpu_asm file. An -; * implementation in assembly should include "cpu_asm.h> -; */ - -;#include <cpu_asm.h> -#include <register.ah> -#include <amd.ah> -#include <pswmacro.ah> -; .extern _bsp_exit -; -; push a register onto the struct - .macro spush, sp, reg - store 0, 0, reg, sp ; push register - add sp, sp, 4 ; adjust stack pointer - .endm -; push a register onto the struct - .macro spushsr, sp, reg, sr - mfsr reg, sr - store 0, 0, reg, sp ; push register - add sp, sp, 4 ; adjust stack pointer - .endm -; pop a register from the struct - .macro spop, reg, sp - load 0, 0, reg, sp - add sp,sp,4 - .endm -; pop a special register from the struct - .macro spopsr, sreg, reg, sp - load 0, 0, reg, sp - mtsr sreg, reg - add sp,sp,4 - .endm -; -;/* -; * _CPU_Context_save_fp_context -; * -; * This routine is responsible for saving the FP context -; * at *fp_context_ptr. If the point to load the FP context -; * from is changed then the pointer is modified by this routine. -; * -; * Sometimes a macro implementation of this is in cpu.h which dereferences -; * the ** and a similarly named routine in this file is passed something -; * like a (Context_Control_fp *). The general rule on making this decision -; * is to avoid writing assembly language. -; */ - -;#if 0 -;void _CPU_Context_save_fp( -; void **fp_context_ptr -;) -;{ -;} -;#endif - .global _CPU_Context_save_fp -_CPU_Context_save_fp: - jmpi lr0 - nop - -;/* -; * _CPU_Context_restore_fp_context -; * -; * This routine is responsible for restoring the FP context -; * at *fp_context_ptr. If the point to load the FP context -; * from is changed then the pointer is modified by this routine. -; * -; * Sometimes a macro implementation of this is in cpu.h which dereferences -; * the ** and a similarly named routine in this file is passed something -; * like a (Context_Control_fp *). The general rule on making this decision -; * is to avoid writing assembly language. -; */ - -;#if 0 -;void _CPU_Context_restore_fp( -; void **fp_context_ptr -;) -;{ -;} -;#endif - .global __CPU_Context_restore_fp -__CPU_Context_restore_fp: - jmpi lr0 - nop - -;/* _CPU_Context_switch -; * -; * This routine performs a normal non-FP context switch. -; */ -;#if 0 -;void _CPU_Context_switch( -; Context_Control *run, -; Context_Control *heir -;) -;{ -;} -;#endif - .global __CPU_Context_switch -__CPU_Context_switch: - asneq 106, gr1, gr1 ; syscall - jmpi lr0 ; - nop ; - - - - .global _a29k_context_switch_sup -_a29k_context_switch_sup: -#if 0 - add pcb,lr2,0 - add kt1,lr3,0 ;move heir pointer to safe location - constn it0,SIG_SYNC - spush pcb,it0 - spush pcb,gr1 - spush pcb,rab ;push rab - spushsr pcb,it0,pc0 ;push specials - spushsr pcb,it0,pc1 - add pcb,pcb,1*4 ;space pc2 - spushsr pcb,it0,CHA ;push CHA - spushsr pcb,it0,CHD ;push CHD - spushsr pcb,it0,CHC ;push CHC - add pcb,pcb,1*4 ;space for alu - spushsr pcb,it0,ops ;push OPS - mfsr kt0,cps ;current status - const it1,FZ ;FZ constant - andn it1,kt0,it1 ;clear FZ bit - mtsr cps,it1 ;cps without FZ - add pcb,pcb,1*4 ;space for tav - mtsrim chc,0 ;possible DERR -; - spush pcb,lr1 ;push R-stack - spush pcb,rfb ; support - spush pcb,msp ;push M-stack pnt. -; - add pcb,pcb,3*4 ;space for floating point -; spush pcb,FPStat0 ;floating point -; spush pcb,FPStat1 -; spush pcb,FPStat2 -; - add pcb,pcb,4*4 ;space for IPA..Q -; - mtsrim cr,29-1 - storem 0,0,gr96,pcb ;push gr96-124, optional - add pcb,pcb,29*4 ;space for gr96-124 -; - sub it0,rfb,gr1 ;get bytes in cache - srl it0,it0,2 ;adjust to words - sub it0,it0,1 - spush pcb,it0 - mtsr cr,it0 - storem 0,0,lr0,pcb ;save lr0-rfb -; -context_restore: - add pcb,kt1,0 ;pcb=heir - add pcb,pcb,4 ;space for signal num - spop gr1,pcb ;restore freeze registers - add gr1,gr1,0 ;alu op - add pcb,pcb,9*4 ;move past freeze registers - add pcb,pcb,1*4 ;space for tav - spop lr1,pcb - spop rfb,pcb - spop msp,pcb -; spop FPStat0,pcb -; spop FPStat1,pcb -; spop FPStat2,pcb - add pcb,pcb,3*4 ;space for floating point - add pcb,pcb,4*4 ;space for IPA..Q - mtsrim cr,29-1 - loadm 0,0,gr96,pcb ;pop gr96-gr124 - add pcb,pcb,29*4 ;space for gr96-124 - - spop it1,pcb ;pop locals count - mtsr cr,it1 - loadm 0,0,lr0,pcb ;load locals - - add pcb,kt1,0 ;pcb=heir - mtsr cps,kt0 ;cps with FZ - nop - add pcb,pcb,4 ;space for signal num - spop gr1,pcb ;restore freeze registers - add gr1,gr1,0 ;alu op - spop rab,pcb - spopsr pc0,it1,pcb - spopsr pc1,it1,pcb - add pcb,pcb,4 ;space for pc2 - spopsr CHA,it1,pcb - spopsr CHD,it1,pcb - spopsr CHC,it1,pcb - add pcb,pcb,4 ;space for alu - spopsr ops,it1,pcb - nop - iret -#endif - - -;/* -; * _CPU_Context_restore -; * -; * This routine is generally used only to restart self in an -; * efficient manner. It may simply be a label in _CPU_Context_switch. -; * -; * NOTE: May be unnecessary to reload some registers. -; */ -;#if 0 -;void _CPU_Context_restore( -; Context_Control *new_context -;) -;{ -;} -;#endif - - .global __CPU_Context_restore -__CPU_Context_restore: -#if 0 - asneq 107, gr1, gr1 ; syscall - jmpi lr0 ; - nop ; - - .global _a29k_context_restore_sup -_a29k_context_restore_sup: - add kt1,lr2,0 ;kt1 = restore context - mfsr kt0,cps ;current status - const it1,FZ ;FZ constant - andn it1,kt0,it1 ;clear FZ bit - mtsr cps,it1 ;cps without FZ - jmp context_restore - nop - - .global _a29k_context_save_sup -_a29k_context_save_sup: - add pcb,lr2,0 - constn it0,SIG_SYNC - spush pcb,it0 - spush pcb,gr1 - spush pcb,rab ;push rab - spushsr pcb,it0,pc0 ;push specials - spushsr pcb,it0,pc1 - add pcb,pcb,1*4 ;space pc2 - spushsr pcb,it0,CHA ;push CHA - spushsr pcb,it0,CHD ;push CHD - spushsr pcb,it0,CHC ;push CHC - add pcb,pcb,1*4 ;space for alu - spushsr pcb,it0,ops ;push OPS - mfsr it0,cps ;current status -SaveFZState it1,it2 - add pcb,pcb,1*4 ;space for tav - mtsrim chc,0 ;possible DERR -; - spush pcb,lr1 ;push R-stack - spush pcb,rfb ; support - spush pcb,msp ;push M-stack pnt. -; - spush pcb,FPStat0 ;floating point - spush pcb,FPStat1 - spush pcb,FPStat2 -; - add pcb,pcb,4*4 ;space for IPA..Q -; - mtsrim cr,29-1 - storem 0,0,gr96,pcb ;push gr96-124, optional - add pcb,pcb,29*4 ;space for gr96-124 -; - sub kt0,rfb,gr1 ;get bytes in cache - srl kt0,kt0,2 ;adjust to words - sub kt0,kt0,1 - spush pcb,kt0 ;push number of words - mtsr cr,kt0 - storem 0,0,lr0,pcb ;save lr0-rfb -; - mtsr cps,it0 ;cps with FZ -RestoreFZState it1,it2 - - nop - nop - nop -; - iret -; -#endif - - .global __CPU_Context_save -__CPU_Context_save: -#if 0 - asneq 108, gr1, gr1 ; syscall - jmpi lr0 ; - nop ; -#endif - - -;/* void __ISR_Handler() -; * -; * This routine provides the RTEMS interrupt management. -; * -; */ - -;#if 0 -;void _ISR_Handler() -;{ -; /* -; * This discussion ignores a lot of the ugly details in a real -; * implementation such as saving enough registers/state to be -; * able to do something real. Keep in mind that the goal is -; * to invoke a user's ISR handler which is written in C and -; * uses a certain set of registers. -; * -; * Also note that the exact order is to a large extent flexible. -; * Hardware will dictate a sequence for a certain subset of -; * _ISR_Handler while requirements for setting -; */ - -; /* -; * At entry to "common" _ISR_Handler, the vector number must be -; * available. On some CPUs the hardware puts either the vector -; * number or the offset into the vector table for this ISR in a -; * known place. If the hardware does not give us this information, -; * then the assembly portion of RTEMS for this port will contain -; * a set of distinct interrupt entry points which somehow place -; * the vector number in a known place (which is safe if another -; * interrupt nests this one) and branches to _ISR_Handler. -; * -; * save some or all context on stack -; * may need to save some special interrupt information for exit -; * -; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) -; * if ( _ISR_Nest_level == 0 ) -; * switch to software interrupt stack -; * #endif -; * -; * _ISR_Nest_level++; -; * -; * _Thread_Dispatch_disable_level++; -; * -; * (*_ISR_Vector_table[ vector ])( vector ); -; * -; * --_ISR_Nest_level; -; * -; * if ( _ISR_Nest_level ) -; * goto the label "exit interrupt (simple case)" -; * -; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) -; * restore stack -; * #endif -; * -; * if ( !_Context_Switch_necessary ) -; * goto the label "exit interrupt (simple case)" -; * -; * if ( !_ISR_Signals_to_thread_executing ) -; * goto the label "exit interrupt (simple case)" -; * -; * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch -; * -; * prepare to get out of interrupt -; * return from interrupt (maybe to _ISR_Dispatch) -; * -; * LABEL "exit interrupt (simple case): -; * prepare to get out of interrupt -; * return from interrupt -; */ -;} -;#endif -; .global __ISR_Handler -;__ISR_Handler: -; jmpi lr0 -; nop - - .global _a29k_getops -_a29k_getops: -#if 0 - asneq 113, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_getops_sup -_a29k_getops_sup: -#if 0 - mfsr gr96, ops ; caller wants ops - iret - nop -#endif - - .global _a29k_disable -_a29k_disable: -#if 0 - asneq 110, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_disable_sup -_a29k_disable_sup: -#if 0 - mfsr kt0, ops - add gr96, kt0, 0 ; return ops to caller - const kt1, (DI | TD) - consth kt1, (DI | TD) - or kt1, kt0, kt1 - mtsr ops, kt1 - iret - nop -#endif - - .global _a29k_disable_all -_a29k_disable_all: -#if 0 - asneq 112, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_disable_all_sup -_a29k_disable_all_sup: -#if 0 - mfsr kt0, ops - const kt1, (DI | TD) - consth kt1, (DI | TD) - or kt1, kt0, kt1 - mtsr ops, kt1 - iret - nop -#endif - - .global _a29k_enable_all -_a29k_enable_all: -#if 0 - asneq 111, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_enable_all_sup -_a29k_enable_all_sup: -#if 0 - mfsr kt0, ops - const kt1, (DI | TD) - consth kt1, (DI | TD) - andn kt1, kt0, kt1 - mtsr ops, kt1 - iret - nop -#endif - - .global _a29k_enable -_a29k_enable: -#if 0 - asneq 109, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_enable_sup -_a29k_enable_sup: -#if 0 - mfsr kt0, ops - const kt1, (DI | TD) - consth kt1, (DI | TD) - and kt3, lr2, kt1 - andn kt0, kt0, kt1 - or kt1, kt0, kt3 - mtsr ops, kt1 - iret - nop -#endif - - .global _a29k_halt -_a29k_halt: -#if 0 - halt - jmp _a29k_halt - nop -#endif - - .global _a29k_super_mode -_a29k_super_mode: -#if 0 - mfsr gr96, ops - or gr96, gr96, 0x10 - mtsr ops, gr96 - iret - nop -#endif - - .global _a29k_as70 -_a29k_as70: -#if 0 - asneq 70,gr96,gr96 - jmpi lr0 - nop -#endif diff --git a/c/src/exec/score/cpu/a29k/pswmacro.ah b/c/src/exec/score/cpu/a29k/pswmacro.ah deleted file mode 100644 index 12f6dc6abd..0000000000 --- a/c/src/exec/score/cpu/a29k/pswmacro.ah +++ /dev/null @@ -1,442 +0,0 @@ -; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; macros: Do_install and init_TLB -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; /* $Id$ */ - -;* File information and includes. - - .file "macro.ah" - .ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI" - - - .macro CONST32, RegName, RegValue - const RegName, RegValue - consth RegName, RegValue - .endm - - .macro CONSTX, RegName, RegValue - .if (RegValue) <= 0x0000ffff - const RegName, RegValue - .else - const RegName, RegValue - consth RegName, RegValue - .endif - .endm - - .macro PRODEV, RegName - srl RegName, RegName, 24 - .endm - -; -;* MACRO TO INSTALL VECTOR TABLE ENTRIES -; - -;* Assumes vector table address in v0 - - .macro _setvec, trapnum, trapaddr - mfsr v0, vab ; - const v2, trapnum ; - sll v1, v2, 2 ; - add v1, v1, v0 ; v0 has location of vector tab - - const v2, trapaddr ; - consth v2, trapaddr ; - store 0, 0, v2, v1 ; - nop ; - .endm - - .macro syscall, name - const tav, HIF_@name ; - asneq V_SYSCALL, gr1, gr1 ; - nop ; - nop ; - .endm - - - -;* MACRO TO INSTALL VECTOR TABLE ENTRIES - - .macro Do_Install, V_Number, V_Address - const lr4, V_Address - consth lr4, V_Address - const lr3, V_Number * 4 - consth lr3, V_Number * 4 - call lr0, V_Install - nop - .endm - - .macro Do_InstallX, V_Number, V_Address - const lr4, V_Address - consth lr4, V_Address - const lr3, V_Number * 4 - consth lr3, V_Number * 4 - call lr0, V_InstallX - nop - .endm - - - -; push a register onto the stack - .macro pushreg, reg, sp - sub sp, sp, 4 ; adjust stack pointer - store 0, 0, reg, sp ; push register - .endm - - .macro push, sp, reg - sub sp, sp, 4 - store 0, 0, reg, sp - .endm - -; pop the register from stack - .macro popreg, reg, sp - load 0, 0, reg, sp ; pop register - add sp, sp, 4 ; adjust stack pointer - .endm - .macro pop, reg, sp - load 0, 0, reg, sp - add sp, sp, 4 - .endm - -; push a special register onto stack - .macro pushspcl, spcl, tmpreg, sp - sub sp, sp, 4 ; adjust stack pointer - mfsr tmpreg, spcl ; get spcl reg - store 0, 0, tmpreg, sp ; push onto stack - .endm - - .macro pushsr, sp, reg, sreg - mfsr reg, sreg - sub sp, sp, 4 - store 0, 0, reg, sp - .endm - -; pop a special register from stack - .macro popspcl, spcl, tmpreg, sp - load 0, 0, tmpreg, sp ; pop from stack - add sp, sp, 4 ; adjust stack pointer - mtsr spcl, tmpreg ; set spcl reg - .endm - - .macro popsr, sreg, reg, sp - load 0, 0, reg, sp - add sp, sp, 4 - mtsr sreg, reg - .endm - -; -; save freeze mode registers on memory stack. -; - - .macro SaveFZState, tmp1, tmp2 - - ; save freeze mode registers. - - pushspcl pc0, tmp1, msp - pushspcl pc1, tmp1, msp - pushspcl alu, tmp1, msp - - pushspcl cha, tmp1, msp - pushspcl chd, tmp1, msp - pushspcl chc, tmp1, msp - - pushspcl ops, tmp1, msp - - ; turn freeze off - - const tmp2, FZ - mfsr tmp1, cps - andn tmp1, tmp1, tmp2 - mtsr cps, tmp1 - .endm - -; restore freeze mode registers from memory stack. - - .macro RestoreFZState, tmp1, tmp2 - - ; turn freeze on - - const tmp2, (FZ|DI|DA) - mfsr tmp1, cps - or tmp1, tmp1, tmp2 - mtsr cps, tmp1 - - ; restore freeze mode registers. - - popspcl ops, tmp1, msp - popspcl chc, tmp1, msp - popspcl chd, tmp1, msp - popspcl cha, tmp1, msp - popspcl alu, tmp1, msp - popspcl pc1, tmp1, msp - popspcl pc0, tmp1, msp - .endm - -; -;* -; - .equ WS, 512 ; window size - .equ RALLOC, 4 * 4 ; stack alloc for C - .equ SIGCTX_UM_SIZE, 40 * 4 ; - .equ SIGCTX_RFB, (38) * 4 ; user mode saved - .equ SIGCTX_SM_SIZE, 12 * 4 ; - .equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ; - - .macro sup_sv - add it2, trapreg, 0 ; transfer signal # - sub msp, msp, 4 ; - store 0, 0, it2, msp ; save signal number - sub msp, msp, 4 ; push gr1 - - store 0, 0, gr1, msp ; - sub msp, msp, 4 ; push rab - store 0, 0, rab, msp ; - const it0, WS ; Window size - - sub rab, rfb, it0 ; set rab = rfb-512 - pushsr msp, it0, PC0 ; save program counter0 - pushsr msp, it0, PC1 ; save program counter1 - pushsr msp, it0, PC2 ; save program counter2 - - pushsr msp, it0, CHA ; save channel address - pushsr msp, it0, CHD ; save channel data - pushsr msp, it0, CHC ; save channel control - pushsr msp, it0, ALU ; save alu - - pushsr msp, it0, OPS ; save ops - sub msp, msp, 4 ; - store 0, 0, tav, msp ; push tav - mtsrim chc, 0 ; no loadm/storem - - mfsr it0, ops ; get ops value - const it1, (TD | DI) ; disable interrupts - consth it1, (TD | DI) ; disable interrupts - or it0, it0, it1 ; set bits - - mtsr ops, it0 ; set new ops - const it0, _sigcode ; signal handler - consth it0, _sigcode ; signal handler - mtsr pc1, it0 ; store pc1 - - add it1, it0, 4 ; next addr - mtsr pc0, it1 ; store pc1 location - iret ; return - nop ; ALIGN - .endm - - .macro sig_return - mfsr it0, cps ; get processor status - const it1, FZ|DA ; Freeze + traps disable - or it0, it0, it1 ; to set FZ+DA - mtsr cps, it0 ; in freeze mode - - load 0, 0, tav, msp ; restore tav - add msp, msp, 4 ; - - popsr OPS,it0, msp ; - popsr ALU,it0, msp ; - popsr CHC,it0, msp ; - popsr CHD,it0, msp ; - - popsr CHA,it0, msp ; - popsr PC2,it0, msp ; - popsr PC1,it0, msp ; - popsr PC0,it0, msp ; - - load 0, 0, rab, msp ; - add msp, msp, 4 ; - load 0, 0, it0, msp ; - add gr1, it0, 0 ; pop rsp - - add msp, msp, 8 ; discount signal # - iret - .endm - - .macro repair_R_stack - add v0, msp, SIGCTX_GR1 ; interrupted gr1 - load 0, 0, v2, v0 ; - add v0, msp, SIGCTX_RFB ; - load 0, 0, v3, v0 ; interupted rfb - - const v1, WS ; - sub v1, v3, v1 ; rfb-512 - cpltu v0, v2, v1 ; test gr1 < rfb-512 - jmpf v0, $1 ; - - add gr1, rab, 0 ; - add v2, v1, 0 ; set LB = rfb-512 -$1: -;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill -;* if no, LB=gr1 interrupted cache < 126 registers - cpleu v0, v2, rfb ; test LB<=rfb - jmpf v0, $2 ; - nop ; - add v2, rfb, 0 ; -$2: - cpeq v0, v3, rfb ; fill rfb->rfb - jmpt v0, $3 ; if rfb==rfb - const tav, (0x80<<2) ; prepare for fill - or tav, tav, v2 ; - - mtsr IPA, tav ; IPA=LA<<2 - sub tav, v3, gr98 ; cache fill LA->rfb - srl tav, tav, 2 ; convert to words - sub tav, tav, 1 ; - - mtsr cr, tav ; - loadm 0, 0, gr0, v2 ; fill from LA->rfb -$3: - add rfb, v3, 0 ; move rfb upto rfb - sub rab, v1, 0 ; assign rab to rfb-512 - - add v0, msp, SIGCTX_GR1 ; - load 0, 0, v2, v0 ; v0 = interrupted gr1 - add gr1, v2, 0 ; move gr1 upto gr1 - nop ; - .endm - - .macro repair_regs - mtsrim cr, 29 - 1 ; to restore locals - loadm 0, 0, v0, msp ; - add msp, msp, 29*4 ; - popsr Q, tav, msp ; - - popsr IPC, tav, msp ; - popsr IPB, tav, msp ; - popsr IPA, tav, msp ; - pop FPStat3, msp ; floating point regs - - pop FPStat2, msp ; floating point regs - pop FPStat1, msp ; floating point regs - pop FPStat0, msp ; floating point regs - - add msp, msp, 3*4 ; R-stack repaired - .endm - -; -;*HIF related... -; - - - - -; send the message in bufaddr to Montip. - .macro SendMessageToMontip, bufaddr - const lr2, bufaddr -$1: - call lr0, _msg_send - consth lr2, bufaddr - cpeq gr96, gr96, 0 - jmpf gr96, $1 - const lr2, bufaddr - .endm - -; build a HIF_CALL message in bufaddr to send to montip. - .macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2 - const tmp1, bufaddr - consth tmp1, bufaddr - const tmp2, HIF_CALL_MSGCODE - store 0, 0, tmp2, tmp1 ; msg code - add tmp1, tmp1, 4 - const tmp2, HIF_CALL_MSGLEN - store 0, 0, tmp2, tmp1 ; msg len - add tmp1, tmp1, 4 - store 0, 0, gr121, tmp1 ; service number - add tmp1, tmp1, 4 - store 0, 0, lr2, tmp1 ; lr2 - add tmp1, tmp1, 4 - store 0, 0, lr3, tmp1 ; lr3 - add tmp1, tmp1, 4 - store 0, 0, lr4, tmp1 ; lr4 - .endm - -; -;* -;* All the funky AMD style macros go in here...simply for -;* compatility -; -; - .macro IMPORT, symbol - .extern symbol - .endm - - .macro GLOBAL, symbol - .global symbol - .endm - - .macro USESECT, name, type - .sect name, type - .use name - .endm - - .macro SECTION, name, type - .sect name, type - .endm - - .macro FUNC, fname, lineno - .global fname -fname: - .endm - - .macro ENDFUNC, fname, lineno - .endm - -;*************************************LONG - .macro LONG, varname -varname: - .block 4 - .endm - -;*************************************UNSIGNED LONG - .macro ULONG, varname -varname: - .block 4 - .endm - -;*************************************SHORT - .macro SHORT, varname -varname: - .block 2 - .endm - -;*************************************CHAR - .macro CHAR, varname -varname: - .block 1 - .endm - -;*************************************LONGARRAY - .macro LONGARRAY, name, count -name: - .block count*4 - .endm - -;*************************************SHORTARRAY - - .macro SHORTARRAY, name, count -name: - .block count*2 - .endm - -;*************************************CHARARRAY - - .macro CHARARRAY, name, count -name: - .block count - .endm - - -;*************************************VOID_FPTR - - .macro VOID_FPTR, name -name: - .block 4 - .endm diff --git a/c/src/exec/score/cpu/a29k/register.ah b/c/src/exec/score/cpu/a29k/register.ah deleted file mode 100644 index 853e6ef049..0000000000 --- a/c/src/exec/score/cpu/a29k/register.ah +++ /dev/null @@ -1,217 +0,0 @@ -; /* @(#)register.ah 1.1 96/05/23 08:56:57, TEI */ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; naming of various registers -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; /* $Id$ */ - -;* File information and includes. - - .file "register.ah" - .ident "@(#)register.ah 1.1 96/05/23 08:56:57, TEI\n" - -;* Register Stack pointer and frame pointer registers. - -/* The assembly language is supposed to be Sierra High-C */ -#if 0 - .extern Rrsp, Rfp - - .reg regsp, %%Rrsp - .reg fp, %%Rfp - - - .extern RTrapReg - .extern Rtrapreg - - .reg TrapReg, %%RTrapReg - .reg trapreg, %%Rtrapreg - - -;* Operating system Interrupt handler registers (gr64-gr67) - - .extern ROSint0, ROSint1, ROSint2, ROSint3 - - .reg OSint0, %%ROSint0 - .reg OSint1, %%ROSint1 - .reg OSint2, %%ROSint2 - .reg OSint3, %%ROSint3 - - .reg it0, %%ROSint0 - .reg it1, %%ROSint1 - .reg it2, %%ROSint2 - .reg it3, %%ROSint3 - - - -;* Operating system temporary (or scratch) registers (gr68-gr79) - - .extern ROStmp0, ROStmp1, ROStmp2, ROStmp3 - .extern ROStmp4, ROStmp5, ROStmp6, ROStmp7 - .extern ROStmp8, ROStmp9, ROStmp10, ROStmp11 - - .reg OStmp0, %%ROStmp0 - .reg OStmp1, %%ROStmp1 - .reg OStmp2, %%ROStmp2 - .reg OStmp3, %%ROStmp3 - - .reg OStmp4, %%ROStmp4 - .reg OStmp5, %%ROStmp5 - .reg OStmp6, %%ROStmp6 - .reg OStmp7, %%ROStmp7 - - .reg OStmp8, %%ROStmp8 - .reg OStmp9, %%ROStmp9 - .reg OStmp10, %%ROStmp10 - .reg OStmp11, %%ROStmp11 - - - .reg kt0, %%ROStmp0 - .reg kt1, %%ROStmp1 - .reg kt2, %%ROStmp2 - .reg kt3, %%ROStmp3 - - .reg kt4, %%ROStmp4 - .reg kt5, %%ROStmp5 - .reg kt6, %%ROStmp6 - .reg kt7, %%ROStmp7 - - .reg kt8, %%ROStmp8 - .reg kt9, %%ROStmp9 - .reg kt10, %%ROStmp10 - .reg kt11, %%ROStmp11 - - - .reg TempReg0, %%ROSint0 - .reg TempReg1, %%ROSint1 - .reg TempReg2, %%ROSint2 - .reg TempReg3, %%ROSint3 - - .reg TempReg4, %%ROStmp0 - .reg TempReg5, %%ROStmp1 - .reg TempReg6, %%ROStmp2 - .reg TempReg7, %%ROStmp3 - - .reg TempReg8, %%ROStmp4 - .reg TempReg9, %%ROStmp5 - .reg TempReg10, %%ROStmp6 - .reg TempReg11, %%ROStmp7 - - .reg TempReg12, %%ROStmp8 - .reg TempReg13, %%ROStmp9 - .reg TempReg14, %%ROStmp10 - .reg TempReg15, %%ROStmp11 - - -;* Assigned static registers - - .extern RSpillAddrReg, RFillAddrReg, RSignalAddrReg - .extern Rpcb, Retc - .extern RTimerExt, RTimerUtil, RLEDReg, RERRReg - .extern Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb - .extern Retx, Rety, Retz - - - .reg SpillAddrReg, %%RSpillAddrReg - .reg FillAddrReg, %%RFillAddrReg - .reg SignalAddrReg, %%RSignalAddrReg - .reg pcb, %%Rpcb - - .reg etx, %%Retx - .reg ety, %%Rety - .reg etz, %%Retz - .reg eta, %%Reta - - .reg etb, %%Retb - .reg etc, %%Retc - .reg TimerExt, %%RTimerExt - .reg TimerUtil, %%RTimerUtil - - .reg LEDReg, %%RLEDReg - .reg ERRReg, %%RERRReg - - - .reg et0, %%Ret0 - .reg et1, %%Ret1 - .reg et2, %%Ret2 - .reg et3, %%Ret3 - - .reg et4, %%Ret4 - .reg et5, %%Ret5 - .reg et6, %%Ret6 - .reg et7, %%Ret7 - -; - .equ SCB1REG_NUM, 88 - .reg SCB1REG_PTR, %%Ret0 - -; The floating point trap handlers need a few static registers - - .extern RFPStat0, RFPStat1, RFPStat2, RFPStat3 - .extern Rheapptr, RHeapPtr, RArgvPtr - - .reg FPStat0, %%RFPStat0 - .reg FPStat1, %%RFPStat1 - .reg FPStat2, %%RFPStat2 - .reg FPStat3, %%RFPStat3 - - .reg heapptr, %%Rheapptr - .reg HeapPtr, %%RHeapPtr - .reg ArgvPtr, %%RArgvPtr - - .extern RXLINXReg, RVMBCReg, RUARTReg, RETHERReg - - .reg XLINXReg, %%RXLINXReg - .reg VMBCReg, %%RVMBCReg - .reg UARTReg, %%RUARTReg - .reg ETHERReg, %%RXLINXReg - -;* Compiler and programmer registers. (gr96-gr127) - - .extern Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9 - .extern Rv10, Rv11, Rv12, Rv13, Rv14, Rv15 - - .reg v0, %%Rv0 - .reg v1, %%Rv1 - .reg v2, %%Rv2 - .reg v3, %%Rv3 - - .reg v4, %%Rv4 - .reg v5, %%Rv5 - .reg v6, %%Rv6 - .reg v7, %%Rv7 - - .reg v8, %%Rv8 - .reg v9, %%Rv9 - .reg v10, %%Rv10 - .reg v11, %%Rv11 - - .reg v12, %%Rv12 - .reg v13, %%Rv13 - .reg v14, %%Rv14 - .reg v15, %%Rv15 - - .extern Rtv0, Rtv1, Rtv2, Rtv3, Rtv4 - - .reg tv0, %%Rtv0 - .reg tv1, %%Rtv1 - .reg tv2, %%Rtv2 - .reg tv3, %%Rtv3 - .reg tv4, %%Rtv4 - -; **************************************************************************** -; For uatrap -; register definitions -- since this trap handler must allow for -; nested traps and interrupts such as TLB miss, protection violation, -; or Data Access Exception, and these trap handlers use the shared -; Temp registers, we must maintain our own that are safe over user- -; mode loads and stores. The following must be assigned global -; registers which are not used in INTR[0-3], TRAP[0-1], TLB miss, -; TLB protection violation, or data exception trap handlers. - -; .reg cha_cpy, OStmp4 ; copy of CHA -; .reg chd_cpy, OStmp5 ; copy of CHD -; .reg chc_cpy, OStmp6 ; copy of CHC -; .reg LTemp0, OStmp7 ; local temp 0 -; .reg LTemp1, OStmp8 ; local temp 1 - -; **************************************************************************** -#endif diff --git a/c/src/exec/score/cpu/a29k/rtems/.cvsignore b/c/src/exec/score/cpu/a29k/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/a29k/rtems/score/.cvsignore b/c/src/exec/score/cpu/a29k/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/a29k/rtems/score/a29k.h b/c/src/exec/score/cpu/a29k/rtems/score/a29k.h deleted file mode 100644 index 99a2626202..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/a29k.h +++ /dev/null @@ -1,78 +0,0 @@ -/* a29k.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ -/* @(#)a29k.h 10/21/96 1.3 */ - -#ifndef _INCLUDE_A29K_h -#define _INCLUDE_A29K_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#define A29K_HAS_FPU 0 -#define CPU_MODEL_NAME "a29xxx" - -/* - * Moving toward multilib with no attempt to distinguish - * multilib features in gcc. - */ - -#if 0 -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define A29K_HAS_FPU 0 - -#elif defined(a29205) - -#define CPU_MODEL_NAME "a29205" -#define A29K_HAS_FPU 0 - -#else - -#error "Unsupported CPU Model" - -#endif -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "AMD 29K" - -/* - * Some bits in the CPS: - */ -#define TD 0x20000 -#define DI 0x00002 - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_A29K_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/a29k/rtems/score/cpu.h b/c/src/exec/score/cpu/a29k/rtems/score/cpu.h deleted file mode 100644 index 10c7be3b3f..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/cpu.h +++ /dev/null @@ -1,1008 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the AMD 29K - * processor. - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.c: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -/* @(#)cpu.h 10/21/96 1.11 */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/a29k.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -extern unsigned int a29k_disable( void ); -extern void a29k_enable( unsigned int cookie ); -extern unsigned int a29k_getops( void ); -extern void a29k_getops_sup( void ); -extern void a29k_disable_sup( void ); -extern void a29k_enable_sup( void ); -extern void a29k_disable_all( void ); -extern void a29k_disable_all_sup( void ); -extern void a29k_enable_all( void ); -extern void a29k_enable_all_sup( void ); -extern void a29k_halt( void ); -extern void a29k_fatal_error( unsigned32 error ); -extern void a29k_as70( void ); -extern void a29k_super_mode( void ); -extern void a29k_context_switch_sup(void); -extern void a29k_context_restore_sup(void); -extern void a29k_context_save_sup(void); -extern void a29k_sigdfl_sup(void); - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( A29K_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - */ - -/* #warning "Check these definitions!!!" */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - unsigned32 signal; - unsigned32 gr1; - unsigned32 rab; - unsigned32 PC0; - unsigned32 PC1; - unsigned32 PC2; - unsigned32 CHA; - unsigned32 CHD; - unsigned32 CHC; - unsigned32 ALU; - unsigned32 OPS; - unsigned32 tav; - unsigned32 lr1; - unsigned32 rfb; - unsigned32 msp; - - unsigned32 FPStat0; - unsigned32 FPStat1; - unsigned32 FPStat2; - unsigned32 IPA; - unsigned32 IPB; - unsigned32 IPC; - unsigned32 Q; - - unsigned32 gr96; - unsigned32 gr97; - unsigned32 gr98; - unsigned32 gr99; - unsigned32 gr100; - unsigned32 gr101; - unsigned32 gr102; - unsigned32 gr103; - unsigned32 gr104; - unsigned32 gr105; - unsigned32 gr106; - unsigned32 gr107; - unsigned32 gr108; - unsigned32 gr109; - unsigned32 gr110; - unsigned32 gr111; - - unsigned32 gr112; - unsigned32 gr113; - unsigned32 gr114; - unsigned32 gr115; - - unsigned32 gr116; - unsigned32 gr117; - unsigned32 gr118; - unsigned32 gr119; - unsigned32 gr120; - unsigned32 gr121; - unsigned32 gr122; - unsigned32 gr123; - unsigned32 gr124; - - unsigned32 local_count; - - unsigned32 locals[128]; -} Context_Control; - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef struct { - unsigned32 special_interrupt_register; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the a29K processor specific parameters. - * - * NOTE: The interrupt_stack_size field is required if - * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE. - * - * The pretasking_hook, predriver_hook, and postdriver_hook, - * and the do_zero_of_workspace fields are required on ALL CPUs. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access AMD A29K specific additions to the CPU Table - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (8192) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do{ _isr_cookie = a29k_disable(); }while(0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - do{ a29k_enable(_isr_cookie) ; }while(0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - do{ \ - _CPU_ISR_Enable( _isr_cookie ); \ - _CPU_ISR_Disable( _isr_cookie ); \ - }while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( new_level ) \ - do{ \ - if ( new_level ) a29k_disable_all(); \ - else a29k_enable_all(); \ - }while(0); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -extern void _CPU_Context_save( - Context_Control *new_context -); - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - do{ /* allocate 1/4 of stack for memory stack, 3/4 of stack for register stack */ \ - unsigned32 _mem_stack_tmp = (unsigned32)(_stack_base) + (_size); \ - unsigned32 _reg_stack_tmp = (unsigned32)(_stack_base) + (((_size)*3)/4); \ - _mem_stack_tmp &= ~(CPU_ALIGNMENT-1); \ - _reg_stack_tmp &= ~(CPU_ALIGNMENT-1); \ - _CPU_Context_save(_the_context); \ - (_the_context)->msp = _mem_stack_tmp; /* gr125 */ \ - (_the_context)->lr1 = \ - (_the_context)->locals[1] = \ - (_the_context)->rfb = _reg_stack_tmp; /* gr127 */ \ - (_the_context)->gr1 = _reg_stack_tmp - 4 * 4; \ - (_the_context)->rab = _reg_stack_tmp - 128 * 4; /* gr126 */ \ - (_the_context)->local_count = 1-1; \ - (_the_context)->PC1 = _entry_point; \ - (_the_context)->PC0 = (unsigned32)((char *)_entry_point + 4); \ - if (_isr) { (_the_context)->OPS |= (TD | DI); } \ - else \ - { (_the_context)->OPS &= ~(TD | DI); } \ - }while(0) - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ) - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (char *) (_base) + (_offset) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } while(0) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - a29k_fatal_error(_error) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch)() -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -#define CPU_swap_u32( value ) \ - ((value&0xff) << 24) | (((value >> 8)&0xff) << 16) | \ - (((value >> 16)&0xff) << 8) | ((value>>24)&0xff) - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/a29k/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/a29k/rtems/score/cpu_asm.h deleted file mode 100644 index d2c09fa103..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/cpu_asm.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * cpu_asm.h - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ -/* @(#)cpu_asm.h 06/08/96 1.2 */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -/* #include <rtems/score/offsets.h> */ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/a29k/rtems/score/types.h b/c/src/exec/score/cpu/a29k/rtems/score/types.h deleted file mode 100644 index 130fd30dd4..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* no_cputypes.h - * - * This include file contains type definitions pertaining to the Intel - * no_cpu processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __NO_CPU_TYPES_h -#define __NO_CPU_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void no_cpu_isr; -typedef void ( *no_cpu_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/a29k/sig.S b/c/src/exec/score/cpu/a29k/sig.S deleted file mode 100644 index 9caddf1382..0000000000 --- a/c/src/exec/score/cpu/a29k/sig.S +++ /dev/null @@ -1,213 +0,0 @@ -;/* -; * $Id$ -; */ - -; .include "register.ah" -#include <amd.ah> -#include <pswmacro.ah> - .comm WindowSize,4 - .text - .reg it0,gr64 - .reg it1,gr65 - .reg it2,gr66 - .reg it3,gr67 - .reg v0,gr96 - .reg v1,gr97 - .reg v2,gr98 - .reg v3,gr99 - .reg trapreg,it0 - .reg FPStat0,gr79 - .reg FPStat1,gr79 - .reg FPStat2,gr79 - .reg FPStat3,gr79 - - .global _intr14 -_intr14: -#if 0 - const it3,14 - sup_sv - jmp interrupt - nop -#endif - - .global _intr18 -_intr18: -#if 0 - const it3,18 - sup_sv - jmp interrupt - nop -#endif - - .global _intr19 -_intr19: -#if 0 - const it3,19 - sup_sv - jmp interrupt - nop -#endif - -interrupt: -#if 0 - push msp,it3 - push msp,gr1 - push msp,rab - const it0,512 - sub rab,rfb,it0 ;set rab = rfb-512 - pushsr msp,it0,pc0 - pushsr msp,it0,pc1 - pushsr msp,it0,pc2 - pushsr msp,it0,cha - pushsr msp,it0,chd - pushsr msp,it0,chc - pushsr msp,it0,alu - pushsr msp,it0,ops - push msp,tav -; -;now come off freeze, and go to user-mode code. -;ensure load/store does not restart -; - mtsrim chc,0 - - mfsr it0, cps - const it1, FZ - consth it1, FZ - andn it0, it0, it1 - const it1,(DI|TD) - consth it1,(DI|TD) - or it0,it1,it0 - mtsr cps, it0 -; fall through to _sigcode -#endif - - .extern _a29k_ISR_Handler - .global _sigcode -_sigcode: -#if 0 - - push msp, lr1 ; R stack support - push msp, rfb ; support - push msp, msp ; M stack support - -; push msp, FPStat0 ; Floating point 0 -; push msp, FPStat1 ; Floating point 1 -; push msp, FPStat2 ; Floating point 2 -; push msp, FPStat3 ; Floating point 3 - sub msp,msp,4*4 - - pushsr msp, tav, IPA ; save user mode special - pushsr msp, tav, IPB ; save user mode special - pushsr msp, tav, IPC ; save user mode special - pushsr msp, tav, Q ; save user mode special - - sub msp, msp, 29*4 ; gr96-gr124 - mtsrim cr, 29-1 ; - storem 0, 0, gr96, msp ; - - - const v0, WindowSize ; Window Size value - consth v0, WindowSize ; Window Size value - load 0, 0, v0, v0 ; load Window size - add v2, msp, SIGCTX_RAB ; intr RAB value - - load 0, 0, v2, v2 ; rab value - - sub v1, rfb, v2 ; - cpgeu v1, v1, v0 ; - jmpt v1, nfill ; jmp if spill - add v1, gr1, 8 ; - - cpgtu v1, v1, rfb ; longjump test - jmpt v1, nfill ; - nop ; - -ifill: - add v0, msp, SIGCTX_RAB+4 ; - push v0, rab ; - const v2, fill+4 ; - consth v2, fill+4 ; - - push v0, v2 ; resave PC0 - sub v2, v2, 4 ; - push v0, v2 ; resave PC1 - const v2, 0 ; - - sub v0, v0, 3*4 ; - push v0, v2 ; - -nfill: - cpgtu v0, gr1, rfb ; if gr1>rfb -> gr1=rfb - jmpt v0, lower ; - cpltu v0, gr1, rab ; - jmpt v0, raise ; gr1<rab then gr1=rab - nop ; - -sendsig: - sub gr1, gr1, RALLOC ; - asgeu V_SPILL, gr1, rab ; - add lr1, rfb, 0 ; - add v1, msp, SIGCTX_SIG ; - -cont: - add lr2,it3,0 ; signal # - call lr0, _a29k_ISR_Handler ; call the handler - nop - - nop ; WASTE - jmp _a29k_sigdfl ; return code - nop ; WASTE - nop ; ALIGN - -lower: - jmp sendsig ; - add gr1, rfb, 0 ; -raise: - jmp sendsig ; - add gr1, rab, 0 ; -#endif - - - .global _a29k_sigdfl_sup -_a29k_sigdfl_sup: -#if 0 - repair_R_stack ; - repair_regs ; - sig_return ; return - halt ; never executes -#endif - - - .global _sigret -_sigret: -#if 0 -;assume msp points to tav - mfsr it0,cps - const it1,FZ - or it1,it0,it1 - mtsr cps,it1 - nop - nop -_sigret1: - pop tav,msp - popsr ops,it0,msp - popsr alu,it0,msp - popsr chc,it0,msp - popsr chd,it0,msp - popsr cha,it0,msp - popsr pc2,it0,msp - popsr pc1,it0,msp - popsr pc0,it0,msp - pop rab,msp - pop it0,msp - add gr1,it0,0 - add msp,msp,4 ;discount signal - iret -#endif - -_a29k_sigdfl: -#if 0 - asneq SIGDFL,gr1,gr1 - jmpi lr0 - nop -#endif diff --git a/c/src/exec/score/cpu/arm/.cvsignore b/c/src/exec/score/cpu/arm/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/arm/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/arm/ChangeLog b/c/src/exec/score/cpu/arm/ChangeLog deleted file mode 100644 index 8b946f1ad2..0000000000 --- a/c/src/exec/score/cpu/arm/ChangeLog +++ /dev/null @@ -1,153 +0,0 @@ -2002-07-17 Jay Monkman <jtm@smoothsmoothie.com> - - * rtems/score/cpu_asm.h: Enhanced to include register offsets. - * Makefile.am: Install rtems/score/cpu_asm.h. - * cpu.c: Significantly enhanced including the implementation of - _CPU_ISR_Get_level. - * cpu_asm.S: Improved behavior of context switch and interrupt - dispatching. - * rtems/score/arm.h: Improved the CPU model name determination. - * rtems/score/cpu.h: Improved interrupt disable/enable functions. - -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Filled in something that was marked XXX. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-18 Jay Monkman <jtm@smoothsmoothie.com> - - * rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them - where they correctly inform the compiler about the register they - are modifying. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/a29ktypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2001-02-04 Joel Sherrill <joel@OARcorp.com> - - * configure.ac: Removed references to rtems/Makefile and - rtems/score/Makefile. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2002-02-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP. - -2002-01-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Include rtems/bspIo.h instead of bspIo.h. - -2001-12-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use RTEMS_ENV_RTEMSCPU. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-12-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: include cpuopts.h instead of targopts.h - * rtems/score/arm.h: Use __arm__. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am, formatting. - * rtems/Makefile.am: Formatting. - * rtems/score/Makefile.am: Formatting. - -2000-08-29 Joel Sherrill <joel.sherrill@OARcorp.com> - - * cpu.c: Spacing issues. - * rtems/score/cpu.h: Removed warning by setting _level. - -2000-08-29 Joel Sherrill <joel.sherrill@OARcorp.com> - - * Makefile.am: Added S_O_FILES to list of objects. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/arm/Makefile.am b/c/src/exec/score/cpu/arm/Makefile.am deleted file mode 100644 index 03e6e36ebf..0000000000 --- a/c/src/exec/score/cpu/arm/Makefile.am +++ /dev/null @@ -1,55 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/cpu_asm.h \ - rtems/score/arm.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/arm/asm.h b/c/src/exec/score/cpu/arm/asm.h deleted file mode 100644 index b974287b45..0000000000 --- a/c/src/exec/score/cpu/arm/asm.h +++ /dev/null @@ -1,125 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#ifndef __ARM_ASM_h -#define __ARM_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/arm.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) -#define r8 REG(r8) -#define r9 REG(r9) -#define r10 REG(r10) -#define r11 REG(r11) -#define r12 REG(r12) -#define r13 REG(r13) -#define r14 REG(r14) -#define r15 REG(r15) - -#define CPSR REG(CPSR) - -#define SPSR REG(SPSR) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/arm/configure.ac b/c/src/exec/score/cpu/arm/configure.ac deleted file mode 100644 index d7094bae11..0000000000 --- a/c/src/exec/score/cpu/arm/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-arm],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/arm/cpu.c b/c/src/exec/score/cpu/arm/cpu.c deleted file mode 100644 index 3ae3f5828a..0000000000 --- a/c/src/exec/score/cpu/arm/cpu.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * ARM CPU Dependent Source - * - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * Copyright (c) 2002 Advent Networks, Inc - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#include <rtems/system.h> -#include <rtems.h> -#include <rtems/bspIo.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/thread.h> -#include <rtems/score/cpu.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of ISR disptaching routine (unused) - * - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - _CPU_Table = *cpu_table; -} - -/* - * - * _CPU_ISR_Get_level - returns the current interrupt level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 reg; - - asm volatile ("mrs %0, cpsr \n" \ - "and %0, %0, #0xc0 \n" \ - : "=r" (reg)); - - return reg; -} - -/* - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * new_handler - replacement ISR for this vector number - * old_handler - pointer to store former ISR for this vector number - * - * FIXME: This vector scheme should be changed to allow FIQ to be - * handled better. I'd like to be able to put VectorTable - * elsewhere - JTM - * - * - * Output parameters: NONE - * - */ -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* pointer on the redirection table in RAM */ - long *VectorTable = (long *)(MAX_EXCEPTIONS * 4); - - if (old_handler != NULL) { - old_handler = *(proc_ptr *)(VectorTable + vector); - } - - *(VectorTable + vector) = (long)new_handler ; - -} - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -) -{ - the_context->register_sp = ((unsigned32)(stack_base)) + (size) ; - the_context->register_pc = (entry_point); - the_context->register_cpsr = (new_level | 0x13); -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -/* FIXME: do something here */ -#if 0 - extern unsigned long _fiq_stack; - extern unsigned long _fiq_stack_size; - extern unsigned long _irq_stack; - extern unsigned long _irq_stack_size; - extern unsigned long _abt_stack; - extern unsigned long _abt_stack_size; - unsigned long *ptr; - int i; - - ptr = &_fiq_stack; - for (i = 0; i < ((int)&_fiq_stack_size/4); i++) { - ptr[i] = 0x13131313; - } - - ptr = &_irq_stack; - for (i = 0; i < ((int)&_irq_stack_size/4); i++) { - ptr[i] = 0xf0f0f0f0; - } - - ptr = &_abt_stack; - for (i = 0; i < ((int)&_abt_stack_size/4); i++) { - ptr[i] = 0x55555555; - } -#endif -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -void _CPU_Thread_Idle_body( void ) -{ - - while(1); /* FIXME: finish this */ - /* insert your "halt" instruction here */ ; -} - -void _defaultExcHandler (CPU_Exception_frame *ctx) -{ - printk("\n\r"); - printk("----------------------------------------------------------\n\r"); - printk("Exception 0x%x caught at PC 0x%x by thread %d\n", - ctx->register_pc, ctx->register_lr - 4, - _Thread_Executing->Object.id); - printk("----------------------------------------------------------\n\r"); - printk("Processor execution context at time of the fault was :\n\r"); - printk("----------------------------------------------------------\n\r"); - printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r", - ctx->register_r0, ctx->register_r1, - ctx->register_r2, ctx->register_r3); - printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r", - ctx->register_r4, ctx->register_r5, - ctx->register_r6, ctx->register_r7); - printk(" r8 = %8x r9 = %8x r10 = %8x\n\r", - ctx->register_r8, ctx->register_r9, ctx->register_r10); - printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r", - ctx->register_fp, ctx->register_ip, - ctx->register_sp, ctx->register_lr - 4); - printk("----------------------------------------------------------\n\r"); - - if (_ISR_Nest_level > 0) { - /* - * In this case we shall not delete the task interrupted as - * it has nothing to do with the fault. We cannot return either - * because the eip points to the faulty instruction so... - */ - printk("Exception while executing ISR!!!. System locked\n\r"); - while(1); - } - else { - printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r"); - rtems_task_delete(_Thread_Executing->Object.id); - } -} - -cpuExcHandlerType _currentExcHandler = _defaultExcHandler; - -extern void _Exception_Handler_Undef_Swi(); -extern void _Exception_Handler_Abort(); -/* FIXME: put comments here */ -void rtems_exception_init_mngt() -{ - ISR_Level level; - - _CPU_ISR_Disable(level); - _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, - _Exception_Handler_Undef_Swi, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_SWI, - _Exception_Handler_Undef_Swi, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_Enable(level); -} - - diff --git a/c/src/exec/score/cpu/arm/cpu_asm.S b/c/src/exec/score/cpu/arm/cpu_asm.S deleted file mode 100644 index 60c638d80a..0000000000 --- a/c/src/exec/score/cpu/arm/cpu_asm.S +++ /dev/null @@ -1,216 +0,0 @@ -/* - * $Id$ - * - * This file contains all assembly code for the ARM implementation - * of RTEMS. - * - * Copyright (c) 2002 by Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#include <asm.h> -#include <rtems/score/cpu_asm.h> - - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * void _CPU_Context_restore( run_context, heir_context ) - * - * This routine performs a normal non-FP context. - * - * R0 = run_context R1 = heir_context - * - * This function copies the current registers to where r0 points, then - * restores the ones from where r1 points. - * - * - * NOTE: The function should be able to only save/restore the registers - * that would be saved by a C function since the others have already - * been saved. - * - * It should also be able to use the stm/ldm instructions. - * - */ - - .globl _CPU_Context_switch -_CPU_Context_switch: -/* FIXME: This should use load and store multiple instructions */ -/* Start saving context */ - str r2, [r0, #REG_R2] - str r3, [r0, #REG_R3] - str r4, [r0, #REG_R4] - str r5, [r0, #REG_R5] - str r6, [r0, #REG_R6] - str r7, [r0, #REG_R7] - str r8, [r0, #REG_R8] - str r9, [r0, #REG_R9] - str r10, [r0, #REG_R10] - - str r11, [r0, #REG_R11] - str r12, [r0, #REG_R12] - - str sp, [r0, #REG_SP] - str lr, [r0, #REG_PC] /* save LR at PC's location */ - - mrs r2, cpsr - str r2, [r0, #REG_CPSR] - -/* Start restoring context */ - - ldr r2, [r1, #REG_CPSR] - msr cpsr, r2 - - ldr r2, [r1, #REG_R2] - ldr r3, [r1, #REG_R3] - ldr r4, [r1, #REG_R4] - ldr r5, [r1, #REG_R5] - ldr r6, [r1, #REG_R6] - ldr r7, [r1, #REG_R7] - ldr r8, [r1, #REG_R8] - ldr r9, [r1, #REG_R9] - ldr r10, [r1, #REG_R10] - ldr r11, [r1, #REG_R11] - ldr r12, [r1, #REG_R12] - - ldr sp, [r1, #REG_SP] - ldr lr, [r1, #REG_PC] - mov pc, lr - -/* - * void _CPU_Context_restore( new_context ) - * - * This function copies the restores the registers from where r0 points. - * It must match _CPU_Context_switch() - * - * NOTE: The function should be able to only save/restore the registers - * that would be saved by a C function since the others have already - * been saved. - * - * It should also be able to use the stm/ldm instructions. - * - */ - .globl _CPU_Context_restore -_CPU_Context_restore: -/* FIXME: This should use load and store multiple instructions */ - ldr r2, [r0, #REG_CPSR] - msr cpsr, r2 - - ldr r2, [r0, #REG_R2] - ldr r3, [r0, #REG_R3] - ldr r4, [r0, #REG_R4] - ldr r5, [r0, #REG_R5] - ldr r6, [r0, #REG_R6] - ldr r7, [r0, #REG_R7] - ldr r8, [r0, #REG_R8] - ldr r9, [r0, #REG_R9] - ldr r10, [r0, #REG_R10] - ldr r11, [r1, #REG_R11] - ldr r12, [r1, #REG_R12] - - ldr sp, [r0, #REG_SP] - ldr lr, [r0, #REG_PC] - mov pc, lr - - -/* FIXME: _Exception_Handler_Undef_Swi is untested */ - .globl _Exception_Handler_Undef_Swi -_Exception_Handler_Undef_Swi: -/* FIXME: This should use load and store multiple instructions */ - sub r13,r13,#SIZE_REGS - str r0, [r13, #REG_R0] - str r1, [r13, #REG_R1] - str r2, [r13, #REG_R2] - str r3, [r13, #REG_R3] - str r4, [r13, #REG_R4] - str r5, [r13, #REG_R5] - str r6, [r13, #REG_R6] - str r7, [r13, #REG_R7] - str r8, [r13, #REG_R8] - str r9, [r13, #REG_R9] - str r10, [r13, #REG_R10] - str r11, [r13, #REG_R11] - str r12, [r13, #REG_R12] - str sp, [r13, #REG_SP] - str lr, [r13, #REG_LR] - mrs r0, cpsr /* read the status */ - and r0, r0,#0x1f /* we keep the mode as exception number */ - str r0, [r13, #REG_PC] /* we store it in a free place */ - mov r0, r13 /* put frame address in r0 (C arg 1) */ - - ldr r1, =SWI_Handler - ldr lr, =_go_back_1 - ldr pc,[r1] /* call handler */ -_go_back_1: - ldr r0, [r13, #REG_R0] - ldr r1, [r13, #REG_R1] - ldr r2, [r13, #REG_R2] - ldr r3, [r13, #REG_R3] - ldr r4, [r13, #REG_R4] - ldr r5, [r13, #REG_R5] - ldr r6, [r13, #REG_R6] - ldr r7, [r13, #REG_R7] - ldr r8, [r13, #REG_R8] - ldr r9, [r13, #REG_R9] - ldr r10, [r13, #REG_R10] - ldr r11, [r13, #REG_R11] - ldr r12, [r13, #REG_R12] - ldr sp, [r13, #REG_SP] - ldr lr, [r13, #REG_LR] - add r13,r13,#SIZE_REGS - movs pc,r14 /* return */ - -/* FIXME: _Exception_Handler_Abort is untested */ - .globl _Exception_Handler_Abort -_Exception_Handler_Abort: -/* FIXME: This should use load and store multiple instructions */ - sub r13,r13,#SIZE_REGS - str r0, [r13, #REG_R0] - str r1, [r13, #REG_R1] - str r2, [r13, #REG_R2] - str r3, [r13, #REG_R3] - str r4, [r13, #REG_R4] - str r5, [r13, #REG_R5] - str r6, [r13, #REG_R6] - str r7, [r13, #REG_R7] - str r8, [r13, #REG_R8] - str r9, [r13, #REG_R9] - str r10, [r13, #REG_R10] - str sp, [r13, #REG_R11] - str lr, [r13, #REG_R12] - str lr, [r13, #REG_SP] - str lr, [r13, #REG_LR] - mrs r0, cpsr /* read the status */ - and r0, r0,#0x1f /* we keep the mode as exception number */ - str r0, [r13, #REG_PC] /* we store it in a free place */ - mov r0, r13 /* put frame address in ro (C arg 1) */ - - ldr r1, =_currentExcHandler - ldr lr, =_go_back_2 - ldr pc,[r1] /* call handler */ -_go_back_2: - ldr r0, [r13, #REG_R0] - ldr r1, [r13, #REG_R1] - ldr r2, [r13, #REG_R2] - ldr r3, [r13, #REG_R3] - ldr r4, [r13, #REG_R4] - ldr r5, [r13, #REG_R5] - ldr r6, [r13, #REG_R6] - ldr r7, [r13, #REG_R7] - ldr r8, [r13, #REG_R8] - ldr r9, [r13, #REG_R9] - ldr r10, [r13, #REG_R10] - ldr sp, [r13, #REG_R11] - ldr lr, [r13, #REG_R12] - ldr lr, [r13, #REG_SP] - ldr lr, [r13, #REG_LR] - add r13,r13,#SIZE_REGS - subs pc,r14,#4 /* return */ - diff --git a/c/src/exec/score/cpu/arm/rtems/.cvsignore b/c/src/exec/score/cpu/arm/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/arm/rtems/score/.cvsignore b/c/src/exec/score/cpu/arm/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/arm/rtems/score/arm.h b/c/src/exec/score/cpu/arm/rtems/score/arm.h deleted file mode 100644 index 05aed89892..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/arm.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * $Id$ - * - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * Copyright (c) 2002 Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#ifndef _INCLUDE_ARM_h -#define _INCLUDE_ARM_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "arm" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ -#if defined(__arm9__) -# define CPU_MODEL_NAME "arm9" -# define ARM_HAS_FPU 0 -#elif defined(__arm9tdmi__) -# define CPU_MODEL_NAME "arm9tdmi" -# define ARM_HAS_FPU 0 -#elif defined(__arm7__) -# define CPU_MODEL_NAME "arm7" -# define ARM_HAS_FPU 0 -#elif defined(__arm7tdmi__) -# define CPU_MODEL_NAME "arm7tdmi" -# define ARM_HAS_FPU 0 -#elif defined(__arm__) -# define CPU_MODEL_NAME "unknown ARM" -# define ARM_HAS_FPU 0 -#else -# error "Unsupported CPU Model" -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "ARM" - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_ARM_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/arm/rtems/score/cpu.h b/c/src/exec/score/cpu/arm/rtems/score/cpu.h deleted file mode 100644 index 7074d0022e..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/cpu.h +++ /dev/null @@ -1,962 +0,0 @@ -/* - * This include file contains information pertaining to the ARM - * processor. - * - * COPYRIGHT (c) 2002 Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* FIXME: finish commenting/cleaning up this file */ -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/arm.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRU - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( ARM_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000c0 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - unsigned32 register_r0; - unsigned32 register_r1; - unsigned32 register_r2; - unsigned32 register_r3; - unsigned32 register_r4; - unsigned32 register_r5; - unsigned32 register_r6; - unsigned32 register_r7; - unsigned32 register_r8; - unsigned32 register_r9; - unsigned32 register_r10; - unsigned32 register_fp; - unsigned32 register_ip; - unsigned32 register_sp; - unsigned32 register_lr; - unsigned32 register_pc; - unsigned32 register_cpsr; -} Context_Control; - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Exception_frame; - -typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); -extern cpuExcHandlerType _currentExcHandler; -extern void rtems_exception_init_mngt(); - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt - * that will lead to re-enter the kernel to signal the thread. - */ - -typedef CPU_Exception_frame CPU_Interrupt_frame; - -/* - * The following table contains the information required to configure - * the ARM processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access NO_CPU specific additions to the CPU Table - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*16) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT 4 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - do { \ - int reg; \ - asm volatile ("MRS %0, cpsr \n" \ - "ORR %1, %0, #0xc0 \n" \ - "MSR cpsr, %1 \n" \ - "AND %0, %0, #0xc0 \n" \ - : "=r" (_level), "=r" (reg) \ - : "0" (_level), "1" (reg)); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - do { \ - int reg; \ - asm volatile ("MRS %0, cpsr \n" \ - "BIC %0, %0, #0xc0 \n" \ - "ORR %0, %0, %2 \n" \ - "MSR cpsr, %0 \n" \ - : "=r" (reg) \ - : "0" (reg), "r" (_level)); \ - } while (0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - { \ - int reg1; \ - int reg2; \ - asm volatile ("MRS %0, cpsr \n" \ - "BIC %1, %0, #0xc0 \n" \ - "ORR %1, %1, %4 \n" \ - "MSR cpsr, %1 \n" \ - "MSR cpsr, %0 \n" \ - : "=r" (reg1), "=r" (reg2) \ - : "0" (reg1), "1" (reg2), "r" (_level)); \ - } - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - */ - -#define _CPU_ISR_Set_level( new_level ) \ - { \ - int reg; \ - asm volatile ("MRS %0, cpsr \n" \ - "BIC %0, %0, #0xc0 \n" \ - "ORR %0, %0, %2 \n" \ - "MSR cpsr_c, %0 \n" \ - : "=r" (reg) \ - : "0" (reg), "r" (new_level)); \ - } - - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -typedef enum { - ARM_EXCEPTION_RESET = 0, - ARM_EXCEPTION_UNDEF = 1, - ARM_EXCEPTION_SWI = 2, - ARM_EXCEPTION_PREF_ABORT = 3, - ARM_EXCEPTION_DATA_ABORT = 4, - ARM_EXCEPTION_RESERVED = 5, - ARM_EXCEPTION_IRQ = 6, - ARM_EXCEPTION_FIQ = 7, - MAX_EXCEPTIONS = 8 -} Arm_symbolic_exception_name; - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h deleted file mode 100644 index 2c13347578..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * $Id$ - * - * Copyright (c) 2002 by Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * This file is the include file for cpu_asm.S - * - * - */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - - -/* Registers saved in context switch: */ -.set REG_R0, 0 -.set REG_R1, 4 -.set REG_R2, 8 -.set REG_R3, 12 -.set REG_R4, 16 -.set REG_R5, 20 -.set REG_R6, 24 -.set REG_R7, 28 -.set REG_R8, 32 -.set REG_R9, 36 -.set REG_R10, 40 -.set REG_R11, 44 -.set REG_R12, 48 -.set REG_SP, 52 -.set REG_LR, 56 -.set REG_PC, 60 -.set REG_CPSR, 64 -.set SIZE_REGS, REG_CPSR + 4 - - -#endif diff --git a/c/src/exec/score/cpu/arm/rtems/score/types.h b/c/src/exec/score/cpu/arm/rtems/score/types.h deleted file mode 100644 index 4408046d4e..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/types.h +++ /dev/null @@ -1,55 +0,0 @@ -/* armtypes.h - * - * This include file contains type definitions pertaining to the - * arm processor family. - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#ifndef __ARM_TYPES_h -#define __ARM_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void no_cpu_isr; -typedef void ( *no_cpu_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/c4x/.cvsignore b/c/src/exec/score/cpu/c4x/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/c4x/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/c4x/ChangeLog b/c/src/exec/score/cpu/c4x/ChangeLog deleted file mode 100644 index 9682f57b5b..0000000000 --- a/c/src/exec/score/cpu/c4x/ChangeLog +++ /dev/null @@ -1,126 +0,0 @@ -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * cpu.c, irq.c, rtems/score/cpu.h: Filled in something that was - marked XXX. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/c4xtypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2002-02-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: Remove #include <rtems/score/targopts.h>. - Add #include <rtems/score/cpuopts.h>. - - - -2002-02-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP. - -2001-12-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use RTEMS_ENV_RTEMSCPU. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-10-18 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/c4x.h: Modified to properly multilib. This required - using only macros predefined by gcc. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am, formatting. - * rtems/Makefile.am: formatting. - * rtems/score/Makefile.am: formatting. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/c4x/Makefile.am b/c/src/exec/score/cpu/c4x/Makefile.am deleted file mode 100644 index 2c35fe7137..0000000000 --- a/c/src/exec/score/cpu/c4x/Makefile.am +++ /dev/null @@ -1,55 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h c4xio.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/c4x.h \ - rtems/score/types.h \ - rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c irq.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c irq.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/c4x/asm.h b/c/src/exec/score/cpu/c4x/asm.h deleted file mode 100644 index 24f9c5e391..0000000000 --- a/c/src/exec/score/cpu/c4x/asm.h +++ /dev/null @@ -1,101 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __C4X_ASM_h -#define __C4X_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/c4x.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/c4x/c4xio.h b/c/src/exec/score/cpu/c4x/c4xio.h deleted file mode 100644 index f85f461ebc..0000000000 --- a/c/src/exec/score/cpu/c4x/c4xio.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * C4X IO Information - * - * $Id$ - */ - -#ifndef __C4XIO_h -#define __C4XIO_h - -/* - * Address defines - */ - -#ifdef _TMS320C40 -#define C4X_TIMER_0 ((struct c4x_timer*)0x100020) -#else -#define C4X_TIMER_0 ((struct c4x_timer*)0x808020) -#define C4X_TIMER_1 ((struct c4x_timer*)0x808030) -#endif - -/* XXX how portable */ - -/* C32 Internal Control Registers */ -#define C4X_STRB0_REG 0x808064 -#define C4X_STRB1_REG 0x808068 -#define C4X_IOSTRB_REG 0x808060 - -/* C32 Internal RAM Locations */ -/* XXX how long */ -#define C4X_RAM_BLK_0 0x87fe00 -#define C4X_RAM_BLK_1 0x87ff00 - -/* - * Data Structures to Overlay the Peripherals on the CPU - */ - -struct c4x_timer { - volatile int tcontrol; - volatile int r1[3]; - volatile int tcounter; - volatile int r2[3]; - volatile int tperiod; -}; - - - - -/* - * Timer Support Routines - * - * The following section of C4x timer code is based on C40 specific - * timer code from Ran Cabell <rcabell@norfolk.infi.net>. The - * only C3x/C4x difference spotted was the address of the timer. - * The names have been changed to be more RTEMS like. - */ - -#define c4x_timer_get_control( _timer ) (volatile int)(_timer->tcontrol) - -#define c4x_timer_set_control( _timer, _value ) \ - do { \ - (volatile int)(_timer->tcontrol) = _value; \ - } while (0); - -#define c4x_timer_start( _timer ) \ - c4x_timer_set_control(_timer, 0x02c1 ) - -#define c4x_timer_stop( _timer ) _timer->tcontrol = 0 - -#define c4x_timer_get_counter( _timer ) (volatile int)(_timer->tcounter) - -#define c4x_timer_set_counter( _timer, _value ) \ - do { \ - (volatile int)(_timer->tcounter) = _value; \ - } while (0); - -#define c4x_timer_get_period( _timer ) (volatile int)(_timer->tperiod) - -#define c4x_timer_set_period( _timer, _value ) \ - do { \ - (volatile int)(_timer->tperiod) = _value; \ - } while (0); - -/* - * IO Flags - * - * NOTE: iof on c3x, iiof on c4x - */ - -#ifdef _TMS320C40 - -#else - -static inline unsigned32 c3x_get_iof( void ) -{ - register unsigned32 iof_value; - - __asm__ volatile ("ldi iof, %0" : "=r" (iof_value)); - return iof_value; -} - -static inline void c3x_set_iof( unsigned32 value ) -{ - __asm__ volatile ("ldi %0,iof" : : "g" (value) : "iof", "cc"); -} - -#endif - - -#endif -/* end if include file */ diff --git a/c/src/exec/score/cpu/c4x/configure.ac b/c/src/exec/score/cpu/c4x/configure.ac deleted file mode 100644 index c181e52669..0000000000 --- a/c/src/exec/score/cpu/c4x/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-c4x],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/c4x/cpu.c b/c/src/exec/score/cpu/c4x/cpu.c deleted file mode 100644 index 44d43f837a..0000000000 --- a/c/src/exec/score/cpu/c4x/cpu.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * C4x CPU Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - * C4x Specific Information: - * - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ -#if 0 - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; -#endif - -#if (CPU_HARDWARE_FP == TRUE) - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ -#endif - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * C4x Specific Information: - * - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - void **ittp; - - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - - ittp = c4x_get_ittp(); - *old_handler = ittp[ vector ]; - ittp[ vector ] = new_handler; -} - -/*XXX */ - -#define C4X_CACHE 1 -#define C4X_BASE_ST (C4X_CACHE==1) ? 0x4800 : 0x4000 - -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - unsigned32 _size, - unsigned32 _isr, - void (*_entry_point)(void), - int _is_fp -) -{ - unsigned int *_stack; - _stack = (unsigned int *)_stack_base; - - *_stack = (unsigned int) _entry_point; - _the_context->sp = (unsigned int) _stack; - _the_context->st = C4X_BASE_ST; - if ( _isr == 0 ) - _the_context->st |= C4X_ST_GIE; -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * C4x Specific Information: - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr ignored; - extern void rtems_irq_prologue_0(void); - extern void rtems_irq_prologue_1(void); - void *entry; - - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - entry = (void *)rtems_irq_prologue_0 + - ((rtems_irq_prologue_1 - rtems_irq_prologue_0) * vector); - _CPU_ISR_install_raw_handler( vector, entry, &ignored ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * C4x Specific Information: - * - * - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1) -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) { - __asm__( "idle" ); - __asm__( "nop" ); - __asm__( "nop" ); - __asm__( "nop" ); - /* insert your "halt" instruction here */ ; - } -} -#endif diff --git a/c/src/exec/score/cpu/c4x/cpu_asm.S b/c/src/exec/score/cpu/c4x/cpu_asm.S deleted file mode 100644 index 9dbc227563..0000000000 --- a/c/src/exec/score/cpu/c4x/cpu_asm.S +++ /dev/null @@ -1,770 +0,0 @@ -/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This is supposed to be a .S or .s file NOT a C file. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <asm.h> - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * void _CPU_Context_save_fp( - * void **fp_context_ptr - * - * C4x Specific Information: - * - * There is no distiniction between FP and integer context in this port. - */ - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * void _CPU_Context_restore_fp( - * void **fp_context_ptr - * ) - * - * C4x Specific Information: - * - * There is no distiniction between FP and integer context in this port. - */ - - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - * - * void _CPU_Context_switch( - * Context_Control *run, - * Context_Control *heir - * ) - * - * TMS320C3x General-Purpose Applications User's Guide, section 2.4 - * (p 2-11 and following), Context Switching in Interrupts and - * Subroutines states that "If the program is in a subroutine, it - * must preserve the dedicated C registers as follows:" - * - * Save as Integers Save as Floating-Point - * ================ ====================== - * R4 R8 R6 R7 - * AR4 AR5 - * AR6 AR7 - * FP DP (small model only) - * SP - */ - - .global SYM(_CPU_Context_switch) -SYM(_CPU_Context_switch): - .if .REGPARM == 0 - ldi sp, ar0 - ldi *ar0, ar2 ; get the location of running context - .endif - sti st,*ar2++ ; store status word - sti ar3,*ar2++ ; store ar3 - sti ar4,*ar2++ ; store ar4 - sti ar5,*ar2++ ; store ar5 - sti ar6,*ar2++ ; store ar6 - sti ar7,*ar2++ ; store ar7 - sti r4,*ar2++ ; store integer portion of r4 - sti r5,*ar2++ ; store integer portion of r5 - stf r6,*ar2++ ; store float portion of r6 - stf r7,*ar2++ ; store float portion of r7 - .if .TMS320C40 - sti r8,*ar2++ ; store integer portion of r8 - .endif - sti sp,*ar2++ ; store sp - - ; end of save - - .if .REGPARM == 0 - ldi *-ar0(2), ar2 ; get the location of heir context - .else - ldi r2,ar2 - .endif -_local_restore: - ldi *ar2++,ar0 ; load status word into register - ldi *ar2++,ar3 ; load ar3 - ldi *ar2++,ar4 ; load ar4 - ldi *ar2++,ar5 ; load ar5 - ldi *ar2++,ar6 ; load ar6 - ldi *ar2++,ar7 ; load ar7 - ldi *ar2++,r4 ; load integer portion of r4 - ldi *ar2++,r5 ; load integer portion of r5 - ldf *ar2++,r6 ; load float portion of r6 - ldf *ar2++,r7 ; load float portion of r7 - .if .TMS320C40 - ldi *ar2++,r8 ; load integer portion of r8 - .endif - ldi *ar2++,sp ; load sp - ldi ar0,st ; restore status word and interrupts - rets - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * void _CPU_Context_restore( - * Context_Control *new_context - * ) - */ - - .global SYM(_CPU_Context_restore) -SYM(_CPU_Context_restore): - .if .REGPARM == 0 - ldi sp, ar0 - ldi *ar0, ar2 ; get the location of context to restore - .endif - br _local_restore - -/* void _ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * void _ISR_Handler() - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - */ - - /* - * save some or all context on stack - * may need to save some special interrupt information for exit - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - * - * _ISR_Nest_level++; - * - * _Thread_Dispatch_disable_level++; - * - * (*_ISR_Vector_table[ vector ])( vector ); - * - * --_ISR_Nest_level; - * - * if ( _ISR_Nest_level ) - * goto the label "exit interrupt (simple case)" - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - * - * if ( !_Context_Switch_necessary ) - * goto the label "exit interrupt (simple case)" - * - * if ( !_ISR_Signals_to_thread_executing ) - * _ISR_Signals_to_thread_executing = FALSE; - * goto the label "exit interrupt (simple case)" - * - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch - * - * prepare to get out of interrupt - * return from interrupt (maybe to _ISR_Dispatch) - * - * LABEL "exit interrupt (simple case): - * prepare to get out of interrupt - * return from interrupt - */ - - .global SYM(_ISR_Handler_save_registers) -SYM(_ISR_Handler_save_registers): - ; no push st because it is already pushed - ; no push ar2 because it is already pushed and vector number loaded - push ar0 - push ar1 - push dp - push ir0 - push ir1 - push rs - push re - push rc - push bk - - push r0 - pushf r0 - push r1 - pushf r1 - push r2 - pushf r2 - push r3 - pushf r3 - ; no push r4 because other part of register is in basic context - push r4 - pushf r4 - ; no push r5 because other part of register is in basic context - push r5 - pushf r5 - push r6 - pushf r6 - ; no pushf r6 because other part of register is in basic context - push r7 - pushf r7 - ; no pushf r7 because other part of register is in basic context - .if .TMS320C40 - push r8 - ; no pushf r8 because other part of register is in basic context - push r9 - pushf r9 - push r10 - pushf r10 - push r11 - pushf r11 - .endif - - ldi sp,r2 - call SYM(__ISR_Handler) - - .if .TMS320C40 - popf r11 - pop r11 - popf r10 - pop r10 - popf r9 - pop r9 - ; no popf r8 because other part of register is in basic context - pop r8 - .endif - ; no popf r7 because other part of register is in basic context - popf r7 - pop r7 - ; no popf r6 because other part of register is in basic context - popf r6 - pop r6 - ; no popf r5 because other part of register is in basic context - popf r5 - pop r5 - ; no pop r4 because other part of register is in basic context - popf r4 - pop r4 - popf r3 - pop r3 - popf r2 - pop r2 - popf r1 - pop r1 - popf r0 - pop r0 - - pop bk - pop rc - pop re - pop rs - pop ir1 - pop ir0 - pop dp - pop ar1 - pop ar0 - pop ar2 ; because the vector numbers goes here - pop st - reti - -/* - * Prologues so we can know the vector number. Generated by this script: - * - * i=0 - * while test $i -lt 64 - * do - * - * printf "\t.global\tSYM(rtems_irq_prologue_%X)\n" $i - * printf "SYM(rtems_irq_prologue_%X):\n" $i - * printf "\tpush\tst\n" - * printf "\tpush\tar2\n" - * printf "\tldi\t0x%x,ar2\n" $i - * printf "\tbr\tSYM(_ISR_Handler_save_registers)\n" - * printf "\n" - * i=`expr $i + 1` - * - * done - */ - - .global SYM(rtems_irq_prologue_0) -SYM(rtems_irq_prologue_0): - push st - push ar2 - ldi 0x0,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1) -SYM(rtems_irq_prologue_1): - push st - push ar2 - ldi 0x1,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2) -SYM(rtems_irq_prologue_2): - push st - push ar2 - ldi 0x2,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3) -SYM(rtems_irq_prologue_3): - push st - push ar2 - ldi 0x3,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_4) -SYM(rtems_irq_prologue_4): - push st - push ar2 - ldi 0x4,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_5) -SYM(rtems_irq_prologue_5): - push st - push ar2 - ldi 0x5,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_6) -SYM(rtems_irq_prologue_6): - push st - push ar2 - ldi 0x6,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_7) -SYM(rtems_irq_prologue_7): - push st - push ar2 - ldi 0x7,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_8) -SYM(rtems_irq_prologue_8): - push st - push ar2 - ldi 0x8,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_9) -SYM(rtems_irq_prologue_9): - push st - push ar2 - ldi 0x9,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_A) -SYM(rtems_irq_prologue_A): - push st - push ar2 - ldi 0xa,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_B) -SYM(rtems_irq_prologue_B): - push st - push ar2 - ldi 0xb,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_C) -SYM(rtems_irq_prologue_C): - push st - push ar2 - ldi 0xc,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_D) -SYM(rtems_irq_prologue_D): - push st - push ar2 - ldi 0xd,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_E) -SYM(rtems_irq_prologue_E): - push st - push ar2 - ldi 0xe,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_F) -SYM(rtems_irq_prologue_F): - push st - push ar2 - ldi 0xf,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_10) -SYM(rtems_irq_prologue_10): - push st - push ar2 - ldi 0x10,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_11) -SYM(rtems_irq_prologue_11): - push st - push ar2 - ldi 0x11,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_12) -SYM(rtems_irq_prologue_12): - push st - push ar2 - ldi 0x12,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_13) -SYM(rtems_irq_prologue_13): - push st - push ar2 - ldi 0x13,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_14) -SYM(rtems_irq_prologue_14): - push st - push ar2 - ldi 0x14,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_15) -SYM(rtems_irq_prologue_15): - push st - push ar2 - ldi 0x15,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_16) -SYM(rtems_irq_prologue_16): - push st - push ar2 - ldi 0x16,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_17) -SYM(rtems_irq_prologue_17): - push st - push ar2 - ldi 0x17,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_18) -SYM(rtems_irq_prologue_18): - push st - push ar2 - ldi 0x18,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_19) -SYM(rtems_irq_prologue_19): - push st - push ar2 - ldi 0x19,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1A) -SYM(rtems_irq_prologue_1A): - push st - push ar2 - ldi 0x1a,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1B) -SYM(rtems_irq_prologue_1B): - push st - push ar2 - ldi 0x1b,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1C) -SYM(rtems_irq_prologue_1C): - push st - push ar2 - ldi 0x1c,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1D) -SYM(rtems_irq_prologue_1D): - push st - push ar2 - ldi 0x1d,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1E) -SYM(rtems_irq_prologue_1E): - push st - push ar2 - ldi 0x1e,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1F) -SYM(rtems_irq_prologue_1F): - push st - push ar2 - ldi 0x1f,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_20) -SYM(rtems_irq_prologue_20): - push st - push ar2 - ldi 0x20,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_21) -SYM(rtems_irq_prologue_21): - push st - push ar2 - ldi 0x21,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_22) -SYM(rtems_irq_prologue_22): - push st - push ar2 - ldi 0x22,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_23) -SYM(rtems_irq_prologue_23): - push st - push ar2 - ldi 0x23,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_24) -SYM(rtems_irq_prologue_24): - push st - push ar2 - ldi 0x24,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_25) -SYM(rtems_irq_prologue_25): - push st - push ar2 - ldi 0x25,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_26) -SYM(rtems_irq_prologue_26): - push st - push ar2 - ldi 0x26,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_27) -SYM(rtems_irq_prologue_27): - push st - push ar2 - ldi 0x27,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_28) -SYM(rtems_irq_prologue_28): - push st - push ar2 - ldi 0x28,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_29) -SYM(rtems_irq_prologue_29): - push st - push ar2 - ldi 0x29,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2A) -SYM(rtems_irq_prologue_2A): - push st - push ar2 - ldi 0x2a,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2B) -SYM(rtems_irq_prologue_2B): - push st - push ar2 - ldi 0x2b,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2C) -SYM(rtems_irq_prologue_2C): - push st - push ar2 - ldi 0x2c,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2D) -SYM(rtems_irq_prologue_2D): - push st - push ar2 - ldi 0x2d,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2E) -SYM(rtems_irq_prologue_2E): - push st - push ar2 - ldi 0x2e,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2F) -SYM(rtems_irq_prologue_2F): - push st - push ar2 - ldi 0x2f,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_30) -SYM(rtems_irq_prologue_30): - push st - push ar2 - ldi 0x30,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_31) -SYM(rtems_irq_prologue_31): - push st - push ar2 - ldi 0x31,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_32) -SYM(rtems_irq_prologue_32): - push st - push ar2 - ldi 0x32,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_33) -SYM(rtems_irq_prologue_33): - push st - push ar2 - ldi 0x33,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_34) -SYM(rtems_irq_prologue_34): - push st - push ar2 - ldi 0x34,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_35) -SYM(rtems_irq_prologue_35): - push st - push ar2 - ldi 0x35,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_36) -SYM(rtems_irq_prologue_36): - push st - push ar2 - ldi 0x36,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_37) -SYM(rtems_irq_prologue_37): - push st - push ar2 - ldi 0x37,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_38) -SYM(rtems_irq_prologue_38): - push st - push ar2 - ldi 0x38,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_39) -SYM(rtems_irq_prologue_39): - push st - push ar2 - ldi 0x39,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3A) -SYM(rtems_irq_prologue_3A): - push st - push ar2 - ldi 0x3a,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3B) -SYM(rtems_irq_prologue_3B): - push st - push ar2 - ldi 0x3b,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3C) -SYM(rtems_irq_prologue_3C): - push st - push ar2 - ldi 0x3c,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3D) -SYM(rtems_irq_prologue_3D): - push st - push ar2 - ldi 0x3d,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3E) -SYM(rtems_irq_prologue_3E): - push st - push ar2 - ldi 0x3e,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3F) -SYM(rtems_irq_prologue_3F): - push st - push ar2 - ldi 0x3f,ar2 - br SYM(_ISR_Handler_save_registers) - diff --git a/c/src/exec/score/cpu/c4x/irq.c b/c/src/exec/score/cpu/c4x/irq.c deleted file mode 100644 index 055bae40c4..0000000000 --- a/c/src/exec/score/cpu/c4x/irq.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * C4x CPU Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/cpu.h> -#include <rtems/score/isr.h> -#include <rtems/score/thread.h> - -/* - * This routine provides the RTEMS interrupt management. - */ - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - unsigned long *_old_stack_ptr; -#endif - -register unsigned long *stack_ptr asm("sp"); - -void __ISR_Handler(unsigned32 vector, void *isr_sp) -{ - register unsigned32 level; - - /* already disabled when we get here */ - /* _CPU_ISR_Disable( level ); */ - - _Thread_Dispatch_disable_level++; - -#if 0 - if ( stack_ptr > (_Thread_Executing->Start.stack + - _Thread_Executing->Start.Initial_stack.size) ) { - printk( "Blown interrupt stack at 0x%x\n", stack_ptr ); - } -#endif - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if ( _ISR_Nest_level == 0 ) { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_low; - } -#endif - - _ISR_Nest_level++; - - /* leave it to the ISR to decide if they get reenabled */ - /* _CPU_ISR_Enable( level ); */ - - /* call isp */ - if ( _ISR_Vector_table[ vector] ) - (*_ISR_Vector_table[ vector ])( - vector, isr_sp - sizeof(CPU_Interrupt_frame) + 1 ); - - _CPU_ISR_Disable( level ); - - _ISR_Nest_level--; - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if ( _ISR_Nest_level == 0 ) /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; -#endif - - _Thread_Dispatch_disable_level--; - - _CPU_ISR_Enable( level ); - if ( _Thread_Dispatch_disable_level == 0 ) { - if ( _Context_Switch_necessary || !_ISR_Signals_to_thread_executing ) { - _ISR_Signals_to_thread_executing = FALSE; - _Thread_Dispatch(); - } - } -} diff --git a/c/src/exec/score/cpu/c4x/rtems/.cvsignore b/c/src/exec/score/cpu/c4x/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/c4x/rtems/score/.cvsignore b/c/src/exec/score/cpu/c4x/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/c4x/rtems/score/c4x.h b/c/src/exec/score/cpu/c4x/rtems/score/c4x.h deleted file mode 100644 index 757b8ea012..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/c4x.h +++ /dev/null @@ -1,365 +0,0 @@ -/* c4x.h - * - * This file is an example (i.e. "no CPU") of the file which is - * created for each CPU family port of RTEMS. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef _INCLUDE_C4X_h -#define _INCLUDE_C4X_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#if defined(_C30) -#define CPU_MODEL_NAME "C30" - -#elif defined(_C31) -#define CPU_MODEL_NAME "C31" - -#elif defined(_C32) -#define CPU_MODEL_NAME "C32" - -#elif defined(_C33) -#define CPU_MODEL_NAME "C33" - -#elif defined(_C40) -#define CPU_MODEL_NAME "C40" - -#elif defined(_C44) -#define CPU_MODEL_NAME "C44" - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Texas Instruments C3x/C4x" - -/* - * This port is a little unusual in that even though there are "floating - * point registers", the notion of floating point is very inherent to - * applications. In addition, the calling conventions require that - * only a few extended registers be preserved across subroutine calls. - * The overhead of including these few registers in the basic - * context is small compared to the overhead of managing the notion - * of separate floating point contexts. So we decided to pretend that - * there is no FPU on the C3x or C4x. - */ - -#define C4X_HAS_FPU 0 - -/* - * Routines to manipulate the bits in the Status Word (ST). - */ - -#define C4X_ST_C 0x0001 -#define C4X_ST_V 0x0002 -#define C4X_ST_Z 0x0004 -#define C4X_ST_N 0x0008 -#define C4X_ST_UF 0x0010 -#define C4X_ST_LV 0x0020 -#define C4X_ST_LUF 0x0040 -#define C4X_ST_OVM 0x0080 -#define C4X_ST_RM 0x0100 -#define C4X_ST_CF 0x0400 -#define C4X_ST_CE 0x0800 -#define C4X_ST_CC 0x1000 -#define C4X_ST_GIE 0x2000 - -#ifndef _TMS320C40 -#define C3X_IE_INTERRUPT_MASK_BITS 0xffff -#define C3x_IE_INTERRUPTS_ALL_ENABLED 0x0000 -#define C3x_IE_INTERRUPTS_ALL_DISABLED 0xffff -#endif - -#ifndef ASM - -/* - * A nop macro. - */ - -#define c4x_nop() \ - __asm__("nop"); - -/* - * Routines to set and clear individual bits in the ST (status word). - * - * cpu_st_bit_clear - clear bit in ST - * cpu_st_bit_set - set bit in ST - * cpu_st_get - obtain entire ST - */ - -#ifdef _TMS320C40 -#define c4x_gie_nop() -#else -#define c4x_gie_nop() { c4x_nop(); c4x_nop(); } -#endif - -#define cpu_st_bit_clear(_st_bit) \ - do { \ - __asm__("andn %0,st" : : "g" (_st_bit) : "cc"); \ - c4x_gie_nop(); \ - } while (0) - -#define cpu_st_bit_set(_st_bit) \ - do { \ - __asm__("or %0,st" : : "g" (_st_bit) : "cc"); \ - c4x_gie_nop(); \ - } while (0) - -static inline unsigned int cpu_st_get(void) -{ - register unsigned int st_value; - __asm__("ldi st, %0" : "=r" (st_value)); - return st_value; -} - -/* - * Routines to manipulate the Global Interrupt Enable (GIE) bit in - * the Status Word (ST). - * - * c4x_global_interrupts_get - returns current GIE setting - * c4x_global_interrupts_disable - disables global interrupts - * c4x_global_interrupts_enable - enables global interrupts - * c4x_global_interrupts_restore - restores GIE to pre-disable state - * c4x_global_interrupts_flash - temporarily enable global interrupts - */ - -#define c4x_global_interrupts_get() \ - (cpu_st_get() & C4X_ST_GIE) - -#define c4x_global_interrupts_disable() \ - cpu_st_bit_clear(C4X_ST_GIE) - -#define c4x_global_interrupts_enable() \ - cpu_st_bit_set(C4X_ST_GIE) - -#define c4x_global_interrupts_restore(_old_level) \ - cpu_st_bit_set(_old_level) - -#define c4x_global_interrupts_flash(_old_level) \ - do { \ - cpu_st_bit_set(_old_level); \ - cpu_st_bit_clear(C4X_ST_GIE); \ - } while (0) - -#ifndef _TMS320C40 - -/* - * Routines to set and get the IF register - * - * c3x_get_if - obtains IF register - * c3x_set_if - sets IF register - */ - -static inline unsigned int c3x_get_if(void) -{ - register unsigned int _if_value; - - __asm__( "ldi if, %0" : "=r" (_if_value) ); - return _if_value; -} - -static inline void c3x_set_if(unsigned int _if_value) -{ - __asm__( "ldi %0, if" : : "g" (_if_value) : "if", "cc"); -} - -/* - * Routines to set and get the IE register - * - * c3x_get_ie - obtains IE register - * c3x_set_ie - sets IE register - */ - -static inline unsigned int c3x_get_ie(void) -{ - register unsigned int _ie_value; - - __asm__ volatile ( "ldi ie, %0" : "=r" (_ie_value) ); - return _ie_value; -} - -static inline void c3x_set_ie(unsigned int _ie_value) -{ - __asm__ volatile ( "ldi %0, ie" : : "g" (_ie_value) : "ie", "cc"); -} - -/* - * Routines to manipulates the mask portion of the IE register. - * - * c3x_ie_mask_all - returns previous IE mask - * c3x_ie_mask_restore - restores previous IE mask - * c3x_ie_mask_flash - temporarily restores previous IE mask - * c3x_ie_mask_set - sets a specific set of the IE mask - */ - -#define c3x_ie_mask_all( _isr_cookie ) \ - do { \ - __asm__("ldi ie,%0\n" \ - "\tandn 0ffffh, ie" \ - : "=r" (_isr_cookie): : "ie", "cc" ); \ - } while (0) - -#define c3x_ie_mask_restore( _isr_cookie ) \ - do { \ - __asm__("or %0, ie" \ - : : "g" (_isr_cookie) : "ie", "cc" ); \ - } while (0) - -#define c3x_ie_mask_flash( _isr_cookie ) \ - do { \ - __asm__("or %0, ie\n" \ - "\tandn 0ffffh, ie" \ - : : "g" (_isr_cookie) : "ie", "cc" ); \ - } while (0) - -#define c3x_ie_mask_set( _new_mask ) \ - do { unsigned int _ie_mask; \ - unsigned int _ie_value; \ - \ - if ( _new_mask == 0 ) _ie_mask = 0; \ - else _ie_mask = 0xffff; \ - _ie_value = c3x_get_ie(); \ - _ie_value &= C4X_IE_INTERRUPT_MASK_BITS; \ - _ie_value |= _ie_mask; \ - c3x_set_ie(_ie_value); \ - } while (0) -#endif -/* end of C3x specific interrupt flag routines */ - -/* - * This is a section of C4x specific interrupt flag management routines. - */ - -#ifdef _TMS320C40 - -/* - * Routines to set and get the IIF register - * - * c4x_get_iif - obtains IIF register - * c4x_set_iif - sets IIF register - */ - -static inline unsigned int c4x_get_iif(void) -{ - register unsigned int _iif_value; - - __asm__( "ldi iif, %0" : "=r" (_iif_value) ); - return _iif_value; -} - -static inline void c4x_set_iif(unsigned int _iif_value) -{ - __asm__( "ldi %0, iif" : : "g" (_iif_value) : "iif", "cc"); -} - -/* - * Routines to set and get the IIE register - * - * c4x_get_iie - obtains IIE register - * c4x_set_iie - sets IIE register - */ - -static inline unsigned int c4x_get_iie(void) -{ - register unsigned int _iie_value; - - __asm__( "ldi iie, %0" : "=r" (_iie_value) ); - return _iie_value; -} - -static inline void c4x_set_iie(unsigned int _iie_value) -{ - __asm__( "ldi %0, iie" : : "g" (_iie_value) : "iie", "cc"); -} - -/* - * Routines to manipulates the mask portion of the IIE register. - * - * c4x_ie_mask_all - returns previous IIE mask - * c4x_ie_mask_restore - restores previous IIE mask - * c4x_ie_mask_flash - temporarily restores previous IIE mask - * c4x_ie_mask_set - sets a specific set of the IIE mask - */ - -#if 0 -#warning "C4x IIE masking routines not implemented." -#define c4x_iie_mask_all( _isr_cookie ) -#define c4x_iie_mask_restore( _isr_cookie ) -#define c4x_iie_mask_flash( _isr_cookie ) -#define c4x_iie_mask_set( _new_mask ) -#endif - -#endif -/* end of C4x specific interrupt flag routines */ - -/* - * Routines to access the Interrupt Trap Table Pointer - * - * c4x_get_ittp - get ITTP - * c4x_set_ittp - set ITTP - */ - -static inline void * c4x_get_ittp(void) -{ - register unsigned int _if_value; - - __asm__( "ldi if, %0" : "=r" (_if_value) ); - return (void *)((_if_value & 0xffff0000) >> 8); -} - -static inline void c4x_set_ittp(void *_ittp_value) -{ - unsigned int _if_value; - unsigned int _ittp_field; - -#ifdef _TMS320C40 - _if_value = c4x_get_iif(); -#else - _if_value = c3x_get_if(); -#endif - _if_value &= 0xffff; - _ittp_field = (((unsigned int) _ittp_value) >> 8); - _if_value |= _ittp_field << 16 ; -#ifdef _TMS320C40 - c4x_set_iif( _if_value ); -#else - c3x_set_if( _if_value ); -#endif -} - -#endif /* ifndef ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_C4X_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/c4x/rtems/score/cpu.h b/c/src/exec/score/cpu/c4x/rtems/score/cpu.h deleted file mode 100644 index f42895c4f1..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/cpu.h +++ /dev/null @@ -1,1268 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the C4x - * processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/c4x.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * C4x Specific Information: - * - * We might as well try to inline this code until there is a - * code space problem. - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * C4x Specific Information: - * - * We might as well unroll this loop until there is a reason not to do so. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * C4x Specific Information: - * - * Initial investigation indicates a software managed stack will be needed. - * But the implementation does not currently include support for one. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * C4x Specific Information: - * - * XXXanswer - * - * Initial investigation indicates a software managed stack will be needed. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - * C4x Specific Information: - * - * XXXanswer - * - * Until we know what to do with the memory, we should not allocated it. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * C4x Specific Information: - * - * XXXanswer - * - * The interrupt code will have to be written before this is answered - * but the answer should be yes. - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "C4X_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * C4x Specific Information: - * - * See c4x.h for more details but the bottom line is that the - * few extended registers required to be preserved across subroutines - * calls are considered part of the integer context. This eliminates - * overhead. - * - * The C4X_HAS_FPU refers to the extended precision registers R0-R7 - * (plus R8-R11 on some models). - * - * XXX check that we even need to have the context area pointer in - * the TCB in this case. - */ - -#if ( C4X_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * C4x Specific Information: - * - * There is no known reason to make all tasks include the extended - * precision registers (i.e. floating point context). - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * C4x Specific Information: - * - * There is no known reason to make the IDLE task floating point and - * no point in wasting the memory or increasing the context switch - * time for the IDLE task. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * C4x Specific Information: - * - * There is no reason to avoid the deferred FP switch logic on this - * CPU family. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * C4x Specific Information: - * - * There is currently no reason to avoid using the generic implementation. - * In the future, a C4x specific IDLE thread body may be added to take - * advantage of low power modes. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * C4x Specific Information: - * - * The system stack grows from low to high memory. - * - * C4x Specific Information: - * - * This setting was derived from the discussion of stack management - * in section 6.1 (p. 6-29) System and User Stack Management of the - * TMS32C3x User's Guide (rev L, July 1997) which states: "A push - * performs a preincrement, and a pop performs a postdecrement of the - * system-stack pointer." There are instructions for making "a stack" - * run from high to low memory but this appears to be the exception. - */ - -#define CPU_STACK_GROWS_UP TRUE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * C4x Specific Information: - * - * The C4x is word oriented and there should be no alignment issues. - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * C4x Specific Information: - * - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * C4x Specific Information: - * - * Currently we are only supporting interrupt levels 0 (all on) and - * 1 (all off). Levels 2-255 COULD be looked up in a user provided - * table that gives GIE and IE Mask settings. But this is not the - * case today. - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000FF - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - * - * C4x Specific Information: - * - * XXXanswer - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * C4x Specific Information: - * - * From email with Michael Hayes: - * > > But what are the rules for what is passed in what registers? - * - * Args are passed in the following registers (in order): - * - * AR2, R2, R3, RC, RS, RE - * - * However, the first and second floating point values are always in R2 - * and R3 (and all other floats are on the stack). Structs are always - * passed on the stack. If the last argument is an ellipsis, the - * previous argument is passed on the stack so that its address can be - * taken for the stdargs macros. - * - * > > What is assumed to be preserved across calls? - * - * AR3, AR4, AR5, AR6, AR7 - * R4, R5, R8 (using STI/LDI) - * R6, R7 (using STF/LDF) - * - * > > What is assumed to be scratch registers? - * - * R0, R1, R2, R3, AR0, AR1, AR2, IR0, IR1, BK, RS, RE, RC, R9, R10, R11 - * - * Based on this information, the task specific context is quite small - * but the interrupt context is much larger. In fact, it could - * easily be argued that there is no point in distinguishing between - * integer and floating point contexts on the Cxx since there is - * so little context involved. So that is the decision made. - * - * Not Mentioned in list: DP - * - * Assumed to be global resources: - * - * C3X: IE, IF, and IOF - * C4X: DIE, IIF, and IIF - */ - - -typedef struct { - unsigned int st; - unsigned int ar3; - unsigned int ar4; - unsigned int ar5; - unsigned int ar6; - unsigned int ar7; - unsigned int r4_sti; /* other part of register is in interrupt context */ - unsigned int r5_sti; /* other part of register is in interrupt context */ - unsigned int r6_stf; /* other part of register is in interrupt context */ - unsigned int r7_stf; /* other part of register is in interrupt context */ -#ifdef _TMS320C40 - unsigned int r8_sti; /* other part of register is in interrupt context */ -#endif - unsigned int sp; -} Context_Control; - -typedef struct { -} Context_Control_fp; - -/* - * This is the order the interrupt entry code pushes the registers. - */ - -typedef struct { - void *interrupted; - unsigned int st; - unsigned int ar2; /* because the vector numbers goes here */ - unsigned int ar0; - unsigned int ar1; - unsigned int dp; - unsigned int ir0; - unsigned int ir1; - unsigned int rs; - unsigned int re; - unsigned int rc; - unsigned int bk; - unsigned int r0_sti; - unsigned int r0_stf; - unsigned int r1_sti; - unsigned int r1_stf; - unsigned int r2_sti; - unsigned int r2_stf; - unsigned int r3_sti; - unsigned int r3_stf; - unsigned int r4_stf; /* other part of register is in basic context */ - unsigned int r5_stf; /* other part of register is in basic context */ - unsigned int r6_sti; /* other part of register is in basic context */ - unsigned int r7_sti; /* other part of register is in basic context */ - -#ifdef _TMS320C40 - unsigned int r8_sti; /* other part of register is in basic context */ - unsigned int r9_sti; - unsigned int r9_stf; - unsigned int r10_sti; - unsigned int r10_stf; - unsigned int r11_sti; - unsigned int r11_stf; -#endif - -} CPU_Interrupt_frame; - -/* - * The following table contains the information required to configure - * the C4x processor specific parameters. - * - * C4x Specific Information: - * - * XXXanswer - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access C4X specific additions to the CPU Table - * - * C4x Specific Information: - * - * XXXanswer - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -#if 0 -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * C4x Specific Information: - * - * Unused - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -#endif - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * C4x Specific Information: - * - * XXXanswer - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - * - * C4x Specific Information: - * - * This port should not require this. - */ - -#if 0 -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); -#endif - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * C4x Specific Information: - * - * XXXanswer - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * C4x Specific Information: - * - * If we decide to have a separate floating point context, then - * the answer is the size of the data structure. Otherwise, we - * need to define it as 0 to let upper level configuration work. - */ - -#if ( C4X_HAS_FPU == 1 ) -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) -#else -#define CPU_CONTEXT_FP_SIZE 0 -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * C4x Specific Information: - * - * Based on the information provided in section 7.6.1 (p. 7-26) - * titled "TMS320C30 and TMS320C31 Interrupt Vector Table" and section - * 7.6.2 "TMS320C32 Interrupt Vector Table" of the TMS32C3x User's - * Guide (rev L, July 1997), vectors are numbered 0x00 - 0x3F. Thus - * there are 0x40 or 64 vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 0x40 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define CPU_STACK_MINIMUM_SIZE (1024) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * C4x Specific Information: - * - * XXXanswer - * As best I can tell, there are no restrictions since this is a word - * -- not byte -- oriented archtiecture. - */ - -#define CPU_ALIGNMENT 0 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * C4x Specific Information: - * - * XXXanswer - * - * A CPU_HEAP_ALIGNMENT of 2 comes close to disabling all the rounding - * while still ensuring that the least significant bit of the front - * and back flags can be used as the used bit -- not part of the size. - */ - -#define CPU_HEAP_ALIGNMENT 2 - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * C4x Specific Information: - * - * XXXanswer - * I think a CPU_PARTITION_ALIGNMENT of 1 will effectively disable all - * the rounding. - */ - -#define CPU_PARTITION_ALIGNMENT 1 - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - * - * C4x Specific Information: - * - * These macros disable interrupts using the GIE (global interrupts enable) - * bit in the status word. - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _isr_cookie. - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = c4x_global_interrupts_get(); \ - c4x_global_interrupts_disable(); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _isr_cookie is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - c4x_global_interrupts_restore( _isr_cookie ) - -/* - * This temporarily restores the interrupt to _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _isr_cookie is not - * modified. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - c4x_global_interrupts_flash( _isr_cookie ) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - * C4x Specific Information: - * - * The C4x port probably needs to allow the BSP to define - * a mask table for all values 0-255. For now, 0 is global - * interrupts enabled and and non-zero is global interrupts - * disabled. In the future, values 1-254 could be defined as - * specific combinations of the global interrupt enabled and the IE mask. - * - * The logic for setting the mask field is something like this: - * _ie_value = c4x_get_ie(); - * _ie_value &= C4X_IE_INTERRUPT_MASK_BITS; - * _ie_value |= _ie_mask; - * c4x_set_ie(_ie_value); - * - * NOTE: If this is implemented, then the context of each task - * must be extended to include the IE register. - */ - -#define _CPU_ISR_Set_level( _new_level ) \ - do { \ - if ( _new_level == 0 ) c4x_global_interrupts_enable(); \ - else c4x_global_interrupts_disable(); \ - } while (0) - -/* if GIE = 1, then logical level is 0. */ -#define _CPU_ISR_Get_level() \ - (c4x_global_interrupts_get() ? 0 : 1) - - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - unsigned32 _size, - unsigned32 _isr, - void (*_entry_point)(void), - int _is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#if ( C4X_HAS_FPU == 1 ) -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) -#endif - -#if ( C4X_HAS_FPU == 1 ) -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } while (0) -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define _CPU_Fatal_halt( _error ) \ - do { \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * C4x Specific Information: - * - * There does not appear to be a simple way to do this on this - * processor family that is better than the generic algorithm. - * Almost certainly, a hand-optimized assembly version of the - * generic algorithm could be written although it is not - * worth the development effort at this time. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - do { \ - (_output) = 0; /* do something to prevent warnings */ \ - } while (0) - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * - * C4x Specific Information: - * - * XXXanswer - * is TRUE. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1) -void _CPU_Thread_Idle_body( void ); -#endif - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#if ( C4X_HAS_FPU == 1 ) -void _CPU_Context_save_fp( - void **fp_context_ptr -); -#endif - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#if ( C4X_HAS_FPU == 1 ) -void _CPU_Context_restore_fp( - void **fp_context_ptr -); -#endif - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * C4x Specific Information: - * - * XXXanswer - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/c4x/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/c4x/rtems/score/cpu_asm.h deleted file mode 100644 index b5f3673d61..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/cpu_asm.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * cpu_asm.h - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/c4x/rtems/score/types.h b/c/src/exec/score/cpu/c4x/rtems/score/types.h deleted file mode 100644 index 89d7bc3c35..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* c4xtypes.h - * - * This include file contains type definitions pertaining to the Intel - * C4x processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __C4X_TYPES_h -#define __C4X_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void c4x_isr; -typedef void ( *c4x_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/h8300/.cvsignore b/c/src/exec/score/cpu/h8300/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/h8300/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/h8300/ChangeLog b/c/src/exec/score/cpu/h8300/ChangeLog deleted file mode 100644 index 6d9bc588a0..0000000000 --- a/c/src/exec/score/cpu/h8300/ChangeLog +++ /dev/null @@ -1,126 +0,0 @@ -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Filled in something that was marked XXX. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-04 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am: Remove reference to deprecated rtems.c. - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Fixed comments and renamed - CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK to - CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK to be consistent with other code. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/h8300types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2002-01-07 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/cpu.h: #include <rtems/bspIo.h>. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-10-18 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.S, rtems/score/cpu.h: Modified to better support - multilibing. These changes result in the code being able to - compile with the default gcc settings. It is not functional - in this configuration but does compile. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/h8300/Makefile.am b/c/src/exec/score/cpu/h8300/Makefile.am deleted file mode 100644 index e910a63f3c..0000000000 --- a/c/src/exec/score/cpu/h8300/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/h8300.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/h8300/README b/c/src/exec/score/cpu/h8300/README deleted file mode 100644 index a55c61c662..0000000000 --- a/c/src/exec/score/cpu/h8300/README +++ /dev/null @@ -1,31 +0,0 @@ -# -# $Id$ -# - - -This port was done by Philip Quaife <philip@qs.co.nz> of Q Solutions -using RTEMS 3.5.1 under DOS and Hiview. Philip used an H8300H -to develop and test this port. - -It was updated to 4.5 and merged into the main development trunk -by Joel Sherrill <joel@OARcorp.com>. As part of the merger, the -port was made to conditionally compile for the H8, H8300H, and H8300S -series. - -The status of each CPU subfamily is as follows. - -H8 - Although RTEMS compiles with for these CPUs, it does not - truly support them. All code that will not work on these - CPUs is conditionally disabled. These CPUs have a 16-bit - address space. Thus although a port is technically - feasible, some work will to be performed on RTEMS to - further minimize its footprint and address pointer - manipulation issues. - -H8H - Port was developed on this class of H8 so there should be - no problems. - -H8S - Port should work on this class of H8 but it is untested. - ---joel -28 June 2000 diff --git a/c/src/exec/score/cpu/h8300/asm.h b/c/src/exec/score/cpu/h8300/asm.h deleted file mode 100644 index ecd858f968..0000000000 --- a/c/src/exec/score/cpu/h8300/asm.h +++ /dev/null @@ -1,123 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __H8300_CPU_ASM_h -#define __H8300_CPU_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#define ASM -#include <rtems/score/h8300.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) - -#define er0 REG(er0) -#define er1 REG(er1) -#define er2 REG(er2) -#define er3 REG(er3) -#define er4 REG(er4) -#define er5 REG(er5) -#define er6 REG(er6) -#define er7 REG(er7) - -#define sp REG(sp) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE asm ( ".text -#define END_CODE "); -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - asm( \".h8300h\" ); - diff --git a/c/src/exec/score/cpu/h8300/configure.ac b/c/src/exec/score/cpu/h8300/configure.ac deleted file mode 100644 index 6cfb01fd98..0000000000 --- a/c/src/exec/score/cpu/h8300/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-h8300],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/h8300/cpu.c b/c/src/exec/score/cpu/h8300/cpu.c deleted file mode 100644 index f01c39d969..0000000000 --- a/c/src/exec/score/cpu/h8300/cpu.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Hitachi H8300 CPU Dependent Source - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * This routine returns the current interrupt level. - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned int _ccr; - -#if defined(__H8300__) -#warning "How do we get ccr on base CPU models" -#else - asm volatile ( "stc ccr, %0" : "=m" (_ccr) : ); -#endif - - if ( _ccr & 0x80 ) - return 1; - return 0; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - * Use Debug level IRQ Handlers - */ - H8BD_Install_IRQ(vector,new_handler,old_handler); -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -#if 0 -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - IDLE_Monitor(); - /*asm(" sleep \n"); */ - /* insert your "halt" instruction here */ ; -} -#endif diff --git a/c/src/exec/score/cpu/h8300/cpu_asm.S b/c/src/exec/score/cpu/h8300/cpu_asm.S deleted file mode 100644 index 1cef5abf67..0000000000 --- a/c/src/exec/score/cpu/h8300/cpu_asm.S +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Hitachi H8 Score CPU functions - * Copyright Comnet Technologies Ltd 1999 - * - * Based on example code and other ports with this copyright: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -;.equ RUNCONTEXT_ARG, er0 -;.equ HEIRCONTEXT_ARG, er1 - -/* - * Make sure we tell the assembler what type of CPU model we are - * being compiled for. - */ - -#if defined(__H8300H__) - .h8300h -#endif -#if defined(__H8300S__) - .h8300s -#endif - .text - - .text -/* - GCC Compiled with optimisations and Wimplicit decs to ensure - that stack from doesn't change - - Supposedly R2 and R3 do not need to be saved but who knows - - Arg1 = er0 (not on stack) - Arg2 = er1 (not on stack) -*/ - - .align 2 - - .global __CPU_Context_switch - -__CPU_Context_switch: - /* Save Context */ -#if defined(__H8300H__) || defined(__H8300S__) - stc.w ccr,@(0:16,er0) - mov.l er7,@(2:16,er0) - mov.l er6,@(6:16,er0) - mov.l er5,@(10:16,er0) - mov.l er4,@(14:16,er0) - mov.l er3,@(18:16,er0) - mov.l er2,@(22:16,er0) - - /* Install New context */ - -restore: - mov.l @(22:16,er1),er2 - mov.l @(18:16,er1),er3 - mov.l @(14:16,er1),er4 - mov.l @(10:16,er1),er5 - mov.l @(6:16,er1),er6 - mov.l @(2:16,er1),er7 - ldc.w @(0:16,er1),ccr -#endif - - rts - - .align 2 - - .global __CPU_Context_restore - -__CPU_Context_restore: - -#if defined(__H8300H__) || defined(__H8300S__) - mov.l er0,er1 - jmp @restore:24 -#endif - - - -/* - VHandler for Vectored Interrupts - - All IRQ's are vectored to routine _ISR_#vector_number - This routine stacks er0 and loads er0 with vector number - before transferring to here - -*/ - .align 2 - .global __ISR_Handler - .extern __ISR_Nest_level - .extern __Vector_table - .extern __Context_switch_necessary - - -__ISR_Handler: -#if defined(__H8300H__) || defined(__H8300S__) - mov.l er1,@-er7 - mov.l er2,@-er7 - mov.l er3,@-er7 - mov.l er4,@-er7 - mov.l er5,@-er7 - mov.l er6,@-er7 - -/* Set IRQ Stack */ - orc #0xc0,ccr - mov.l er7,er6 ; save stack pointer - mov.l @__ISR_Nest_level,er1 - bne nested - mov.l @__CPU_Interrupt_stack_high,er7 - -nested: - mov.l er6,@-er7 ; save sp so pop regardless of nest level - -;; Inc system counters - mov.l @__ISR_Nest_level,er1 - inc.l #1,er1 - mov.l er1,@__ISR_Nest_level - mov.l @__Thread_Dispatch_disable_level,er1 - inc.l #1,er1 - mov.l er1,@__Thread_Dispatch_disable_level - -/* Vector to ISR */ - - mov.l @__ISR_Vector_table,er1 - mov er0,er2 ; copy vector - shll.l er2 - shll.l er2 ; vector = vector * 4 (sizeof(int)) - add.l er2,er1 - mov.l @er1,er1 - jsr @er1 ; er0 = arg1 =vector - - orc #0xc0,ccr - mov.l @__ISR_Nest_level,er1 - dec.l #1,er1 - mov.l er1,@__ISR_Nest_level - mov.l @__Thread_Dispatch_disable_level,er1 - dec.l #1,er1 - mov.l er1,@__Thread_Dispatch_disable_level - bne exit - - mov.l @__Context_Switch_necessary,er1 - bne bframe ; If yes then dispatch next task - - mov.l @__ISR_Signals_to_thread_executing,er1 - beq exit ; If no signals waiting - - /* Context switch here through ISR_Dispatch */ - -bframe: - orc #0xc0,ccr -/* Pop Stack */ - mov @er7+,er6 - mov er6,er7 - mov.l #0,er2 - mov.l er2,@__ISR_Signals_to_thread_executing - - /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */ - - mov.l #0xc0000000,er2 /* Disable IRQ */ - or.l #_ISR_Dispatch,er2 - mov.l er2,@-er7 - rte - -/* Inner IRQ Return, pop flags and return */ -exit: -/* Pop Stack */ - orc #0x80,ccr - mov @er7+,er6 - mov er6,er7 - mov @er7+,er6 - mov @er7+,er5 - mov @er7+,er4 - mov @er7+,er3 - mov @er7+,er2 - mov @er7+,er1 - mov @er7+,er0 -#endif - rte - -/* - Called from ISR_Handler as a way of ending IRQ - but allowing dispatch to another task. - Must use RTE as CCR is still on stack but IRQ has been serviced. - CCR and PC occupy same word so rte can be used. - now using task stack -*/ - - .align 2 - .global _ISR_Dispatch - -_ISR_Dispatch: - -#if defined(__H8300H__) || defined(__H8300S__) - jsr @__Thread_Dispatch - mov @er7+,er6 - mov @er7+,er5 - mov @er7+,er4 - mov @er7+,er3 - mov @er7+,er2 - mov @er7+,er1 - mov @er7+,er0 -#endif - rte - - - .align 2 - .global __CPU_Context_save_fp - -__CPU_Context_save_fp: - rts - - - .align 2 - .global __CPU_Context_restore_fp - -__CPU_Context_restore_fp: - rts - diff --git a/c/src/exec/score/cpu/h8300/rtems/.cvsignore b/c/src/exec/score/cpu/h8300/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/h8300/rtems/score/.cvsignore b/c/src/exec/score/cpu/h8300/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/h8300/rtems/score/cpu.h b/c/src/exec/score/cpu/h8300/rtems/score/cpu.h deleted file mode 100644 index fc3a4011f3..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/score/cpu.h +++ /dev/null @@ -1,1187 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the H8300 - * processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/h8300.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -#include <rtems/bspIo.h> /* printk */ - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HARDWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * H8300 Specific Information: - * - * XXX - * The port initially called a BSP dependent routine called - * IDLE_Monitor. The idle task body can be overridden by - * the BSP in newer versions of RTEMS. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - * - * H8300 Specific Information: - * - * XXX - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * H8300 Specific Information: - * - * XXX - */ - - - -#define nogap __attribute__ ((packed)) - -typedef struct { - unsigned16 ccr nogap; - void *er7 nogap; - void *er6 nogap; - unsigned32 er5 nogap; - unsigned32 er4 nogap; - unsigned32 er3 nogap; - unsigned32 er2 nogap; - unsigned32 er1 nogap; - unsigned32 er0 nogap; - unsigned32 xxx nogap; -} Context_Control; - -typedef struct { - double some_float_register[2]; -} Context_Control_fp; - -typedef struct { - unsigned32 special_interrupt_register; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the XXX processor specific parameters. - * - * NOTE: The interrupt_stack_size field is required if - * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE. - * - * The pretasking_hook, predriver_hook, and postdriver_hook, - * and the do_zero_of_workspace fields are required on ALL CPUs. - * - * H8300 Specific Information: - * - * XXX - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); -} rtems_cpu_table; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * H8300 Specific Information: - * - * XXX - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - * - * H8300 Specific Information: - * - * XXX - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * H8300 Specific Information: - * - * XXX - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - * - * H8300 Specific Information: - * - * It is highly unlikely the H8300 will get used in a multiprocessor system. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_MINIMUM_SIZE (1536) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_ALIGNMENT 2 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools. - Note requires ISR_Level be unsigned16 or assembler croaks. -*/ - -#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 ) - - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - asm volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \ - } while (0) - - -/* - * Enable interrupts to the previois level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - - -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \ - } while (0) - - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - - -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \ - } while (0) - -/* end of ISR handler macros */ - -#else /* modern gcc version */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * H8300 Specific Information: - * - * XXX - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - unsigned char __ccr; \ - asm volatile( "stc ccr, %0 ; orc #0x80,ccr " \ - : "=m" (__ccr) : "0" (__ccr) ); \ - (_isr_cookie) = __ccr; \ - } while (0) -#else -#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0 -#endif - - -/* - * Enable interrupts to the previois level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * H8300 Specific Information: - * - * XXX - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - unsigned char __ccr = (unsigned char) (_isr_cookie); \ - asm volatile( "ldc %0, ccr" : : "m" (__ccr) ); \ - } while (0) -#else -#define _CPU_ISR_Enable( _isr_cookie ) -#endif - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * H8300 Specific Information: - * - * XXX - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - unsigned char __ccr = (unsigned char) (_isr_cookie); \ - asm volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \ - } while (0) -#else -#define _CPU_ISR_Flash( _isr_cookie ) -#endif - -#endif /* end of old gcc */ - - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if ( _new_level ) asm volatile ( "orc #0x80,ccr\n" ); \ - else asm volatile ( "andc #0x7f,ccr\n" ); \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * H8300 Specific Information: - * - * XXX - */ - - -#define CPU_CCR_INTERRUPTS_ON 0x80 -#define CPU_CCR_INTERRUPTS_OFF 0x00 - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - /* Locate Me */ \ - do { \ - unsigned32 _stack; \ - \ - if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \ - else (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \ - \ - _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - (_the_context)->er7 = (void *) _stack; \ - (_the_context)->er6 = (void *) _stack; \ - (_the_context)->er5 = 0; \ - (_the_context)->er4 = 1; \ - (_the_context)->er3 = 2; \ - } while (0) - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) (_base) + (_offset) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Fatal_halt( _error ) \ - printk("Fatal Error %d Halted\n",_error); \ - for(;;) - - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * H8300 Specific Information: - * - * XXX - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * H8300 Specific Information: - * - * XXX - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * H8300 Specific Information: - * - * XXX - */ - -static inline unsigned32 CPU_swap_u32( - unsigned32 value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/h8300/rtems/score/h8300.h b/c/src/exec/score/cpu/h8300/rtems/score/h8300.h deleted file mode 100644 index becaed362f..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/score/h8300.h +++ /dev/null @@ -1,57 +0,0 @@ -/* h8300.h - * - * This file contains information pertaining to the Hitachi H8/300 - * processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef _INCLUDE_H8300_h -#define _INCLUDE_H8300_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "h8300" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -/* - * RTEMS compiles for the base H8 with numerous warnings but has never - * been tested on a CPU with 16 bit address space. - * - * FIXME: - * This macro is defined to handle a couple of places where - * addresses are cast to pointers. There really should be - * a "int-pointer" type that pointers are cast to before being - * mathematcically manipulated. When that is added, search - * for all references to this macro and remove them. - */ - -#if defined(__H8300__) -#define RTEMS_CPU_HAS_16_BIT_ADDRESSES 1 -#endif - -#define CPU_NAME "Hitachi H8300" -#define CPU_MODEL_NAME "h8300" -#define H8300_HAS_FPU 0 - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/h8300/rtems/score/types.h b/c/src/exec/score/cpu/h8300/rtems/score/types.h deleted file mode 100644 index d1fec2699e..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* h8300types.h - * - * This include file contains type definitions pertaining to the Hitachi - * h8300 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __H8300_TYPES_h -#define __H8300_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned long unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed long signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void h8300_isr; -typedef void ( *h8300_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/hppa1.1/.cvsignore b/c/src/exec/score/cpu/hppa1.1/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/hppa1.1/ChangeLog b/c/src/exec/score/cpu/hppa1.1/ChangeLog deleted file mode 100644 index c634275fa4..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/ChangeLog +++ /dev/null @@ -1,121 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am, cpu.c, cpu_asm.S, rtems.S: Modified to make - this all compile again. It has been a while since we have - had a semi-working hppa1.1-rtems cross compiler. :) - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/hppa.h: Remove rtems/score/targopts.h. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/hppa1.1types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'CLEANFILES ='. - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Remove references to PROJECT_INCLUDE. - * rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-25 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/hppa.h: Switched to using cpuopts.h not - targopts.h to reduce dependency on BSP. - -2000-09-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use PROJECT_TOPdir in path to genoffsets. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/hppa1.1/Makefile.am b/c/src/exec/score/cpu/hppa1.1/Makefile.am deleted file mode 100644 index 6563d63282..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/Makefile.am +++ /dev/null @@ -1,66 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS= -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/cpu_asm.h \ - rtems/score/hppa.h \ - rtems/score/types.h \ - rtems/score/offsets.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) rtems/score/offsets.h $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -# FIXME: We should get rid of genoffsets -GENOFFSETS = $(PROJECT_TOPdir)/tools/cpu/hppa1.1/genoffsets - -GENERIC_H_FILES = rtems/score/offsets.h -rtems/score/offsets.h: $(GENOFFSETS) rtems/score/cpu.h - $(mkinstalldirs) rtems/score - $(RM) $@ - $(GENOFFSETS) > $@ -CLEANFILES = rtems/score/offsets.h - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/hppa1.1/configure.ac b/c/src/exec/score/cpu/hppa1.1/configure.ac deleted file mode 100644 index 0d8764cdc0..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-hppa1.1],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.c b/c/src/exec/score/cpu/hppa1.1/cpu.c deleted file mode 100644 index 19a5476a79..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/cpu.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * HP PA-RISC Dependent Source - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -void hppa_cpu_halt(unsigned32 the_error); - - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is unsupported. For HPPA this function is handled by BSP - */ - - _CPU_Fatal_halt( 0xdeaddead ); -} - - - -/* - * This is the default handler which is called if - * _CPU_ISR_install_vector() has not been called for the - * specified vector. It simply forwards onto the spurious - * handler defined in the cpu-table. - */ - -static ISR_Handler -hppa_interrupt_report_spurious(ISR_Vector_number vector, - void* rtems_isr_frame) /* HPPA extension */ -{ - - /* - * If the CPU table defines a spurious_handler, then - * call it. If the handler returns halt. - */ - if ( _CPU_Table.spurious_handler ) - _CPU_Table.spurious_handler(vector, rtems_isr_frame); - - hppa_cpu_halt(vector); -} - - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level(void) -{ - int level; - HPPA_ASM_SSM(0, level); /* change no bits; just get copy */ - if (level & HPPA_PSW_I) - return 0; - return 1; -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. The handler is a C callable routine. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[vector]; - - _ISR_Vector_table[vector] = new_handler; -} - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - register unsigned8 *fp_context; - unsigned32 i; - proc_ptr old_handler; - - /* - * This is the default fp context for all tasks - * Set it up so that denormalized results go to zero. - */ - - fp_context = (unsigned8*) &_CPU_Null_fp_context; - for (i=0 ; i<sizeof(Context_Control_fp); i++) - *fp_context++ = 0; - *((unsigned32 *) &_CPU_Null_fp_context) = HPPA_FPSTATUS_D; - - /* - * Save r27 into _CPU_Default_gr27 so it will hopefully be the correct - * global data pointer for the entire system. - */ - - asm volatile( "stw %%r27,%0" : "=m" (_CPU_Default_gr27): ); - - /* - * Init the 2nd level interrupt handlers - */ - - for (i=0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++) - _CPU_ISR_install_vector(i, - hppa_interrupt_report_spurious, - &old_handler); - - _CPU_Table = *cpu_table; - -} - - -/* - * Halt the system. - * Called by the _CPU_Fatal_halt macro - * - * XXX - * Later on, this will allow us to return to the prom. - * For now, we just ignore 'type_of_halt' - * - * XXX - * NOTE: for gcc, this function must be at the bottom - * of the file, that is because if it is at the top - * of the file, gcc will inline it's calls. Since - * the function uses the HPPA_ASM_LABEL() macro, when - * gcc inlines it, you get two definitions of the same - * label name, which is an assembly error. - */ - - -void -hppa_cpu_halt(unsigned32 the_error) -{ - unsigned32 isrlevel; - - _CPU_ISR_Disable(isrlevel); - - /* - * XXXXX NOTE: This label is only needed that that when - * the simulator stops, it shows the label name specified - */ - /* HPPA_ASM_LABEL("_asm_hppa_cpu_halt");*/ - HPPA_ASM_BREAK(0, 0); -} - diff --git a/c/src/exec/score/cpu/hppa1.1/cpu_asm.S b/c/src/exec/score/cpu/hppa1.1/cpu_asm.S deleted file mode 100644 index 7ad9b39810..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/cpu_asm.S +++ /dev/null @@ -1,805 +0,0 @@ -/* - * TODO: - * Context_switch needs to only save callee save registers - * I think this means can skip: r1, r2, r19-29, r31 - * Ref: p 3-2 of Procedure Calling Conventions Manual - * This should be #ifndef DEBUG so that debugger has - * accurate visibility into all registers - * - * This file contains the assembly code for the HPPA implementation - * of RTEMS. - * - * COPYRIGHT (c) 1994,95 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/score/hppa.h> -#include <rtems/score/cpu_asm.h> -#include <rtems/score/cpu.h> -#include <rtems/score/offsets.h> - -#if 0 -#define TEXT_SEGMENT \ - .SPACE $TEXT$ !\ - .SUBSPA $CODE$ -#define RO_SEGMENT \ - .SPACE $TEXT$ !\ - .SUBSPA $lit$ -#define DATA_SEGMENT \ - .SPACE $PRIVATE$ !\ - .SUBSPA $data$ -#define BSS_SEGMENT \ - .SPACE $PRIVATE$ !\ - .SUBSPA $bss$ -#else -#define TEXT_SEGMENT .text -#define RO_SEGMENT .rodata -#define DATA_SEGMENT .data -#define BSS_SEGMENT .bss -#endif - - - -#if 0 - .SPACE $PRIVATE$ - .SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31 - .SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82 - .SPACE $TEXT$ - .SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44 - .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY - .SPACE $TEXT$ - .SUBSPA $CODE$ - -#endif - TEXT_SEGMENT - -/* - * Special register usage for context switch and interrupts - * Stay away from %cr28 which is used for TLB misses on 72000 - */ - -isr_arg0 .reg %cr24 -isr_r9 .reg %cr25 -isr_r8 .reg %cr26 - -/* - * Interrupt stack frame looks like this - * - * offset item - * ----------------------------------------------------------------- - * INTEGER_CONTEXT_OFFSET Context_Control - * FP_CONTEXT_OFFSET Context_Control_fp - * - * It is padded out to a multiple of 64 - */ - - -/*PAGE^L - * void _Generic_ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * We jump here from the interrupt vector. - * The HPPA hardware has done some stuff for us: - * PSW saved in IPSW - * PSW set to 0 - * PSW[E] set to default (0) - * PSW[M] set to 1 iff this is HPMC - * - * IIA queue is frozen (since PSW[Q] is now 0) - * privilege level promoted to 0 - * IIR, ISR, IOR potentially updated if PSW[Q] was 1 at trap - * registers GR 1,8,9,16,17,24,25 copied to shadow regs - * SHR 0 1 2 3 4 5 6 - * - * Our vector stub (in the BSP) MUST have done the following: - * - * a) Saved the original %r9 into %isr_r9 (%cr25) - * b) Placed the vector number in %r9 - * c) Was allowed to also destroy $isr_r8 (%cr26), - * but the stub was NOT allowed to destroy any other registers. - * - * The typical stub sequence (in the BSP) should look like this: - * - * a) mtctl %r9,isr_r9 ; (save r9 in cr25) - * b) ldi vector,%r9 ; (load constant vector number in r9) - * c) mtctl %r8,isr_r8 ; (save r8 in cr26) - * d) ldil L%MY_BSP_first_level_interrupt_handler,%r8 - * e) ldo R%MY_BSP_first_level_interrupt_handler(%r8),%r8 - * ; (point to BSP raw handler table) - * f) ldwx,s %r9(%r8),%r8 ; (load value from raw handler table) - * g) bv 0(%r8) ; (call raw handler: _Generic_ISR_Handler) - * h) mfctl isr_r8,%r8 ; (restore r8 from cr26 in delay slot) - * - * Optionally, steps (c) thru (h) _could_ be replaced with a single - * bl,n _Generic_ISR_Handler,%r0 - * - * - */ - .EXPORT _Generic_ISR_Handler,ENTRY,PRIV_LEV=0 -_Generic_ISR_Handler: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - - mtctl arg0, isr_arg0 - -/* - * save interrupt state - */ - mfctl ipsw, arg0 - stw arg0, IPSW_OFFSET(sp) - - mfctl iir, arg0 - stw arg0, IIR_OFFSET(sp) - - mfctl ior, arg0 - stw arg0, IOR_OFFSET(sp) - - mfctl pcoq, arg0 - stw arg0, PCOQFRONT_OFFSET(sp) - - mtctl %r0, pcoq - mfctl pcoq, arg0 - stw arg0, PCOQBACK_OFFSET(sp) - - mfctl %sar, arg0 - stw arg0, SAR_OFFSET(sp) - -/* - * Build an interrupt frame to hold the contexts we will need. - * We have already saved the interrupt items on the stack - * - * At this point the following registers are damaged wrt the interrupt - * reg current value saved value - * ------------------------------------------------ - * arg0 scratch isr_arg0 (cr24) - * r9 vector number isr_r9 (cr25) - * - * Point to beginning of integer context and - * save the integer context - */ - stw %r1,R1_OFFSET(sp) - stw %r2,R2_OFFSET(sp) - stw %r3,R3_OFFSET(sp) - stw %r4,R4_OFFSET(sp) - stw %r5,R5_OFFSET(sp) - stw %r6,R6_OFFSET(sp) - stw %r7,R7_OFFSET(sp) - stw %r8,R8_OFFSET(sp) -/* - * skip r9 - */ - stw %r10,R10_OFFSET(sp) - stw %r11,R11_OFFSET(sp) - stw %r12,R12_OFFSET(sp) - stw %r13,R13_OFFSET(sp) - stw %r14,R14_OFFSET(sp) - stw %r15,R15_OFFSET(sp) - stw %r16,R16_OFFSET(sp) - stw %r17,R17_OFFSET(sp) - stw %r18,R18_OFFSET(sp) - stw %r19,R19_OFFSET(sp) - stw %r20,R20_OFFSET(sp) - stw %r21,R21_OFFSET(sp) - stw %r22,R22_OFFSET(sp) - stw %r23,R23_OFFSET(sp) - stw %r24,R24_OFFSET(sp) - stw %r25,R25_OFFSET(sp) -/* - * skip arg0 - */ - stw %r27,R27_OFFSET(sp) - stw %r28,R28_OFFSET(sp) - stw %r29,R29_OFFSET(sp) - stw %r30,R30_OFFSET(sp) - stw %r31,R31_OFFSET(sp) - -/* Now most registers are available since they have been saved - * - * The following items are currently wrong in the integer context - * reg current value saved value - * ------------------------------------------------ - * arg0 scratch isr_arg0 (cr24) - * r9 vector number isr_r9 (cr25) - * - * Fix them - */ - - mfctl isr_arg0,%r3 - stw %r3,ARG0_OFFSET(sp) - - mfctl isr_r9,%r3 - stw %r3,R9_OFFSET(sp) - -/* - * At this point we are done with isr_arg0, and isr_r9 control registers - * - * Prepare to re-enter virtual mode - * We need Q in case the interrupt handler enables interrupts - */ - - ldil L%CPU_PSW_DEFAULT, arg0 - ldo R%CPU_PSW_DEFAULT(arg0), arg0 - mtctl arg0, ipsw - -/* - * Now jump to "rest_of_isr_handler" with the rfi - * We are assuming the space queues are all correct already - */ - - ldil L%rest_of_isr_handler, arg0 - ldo R%rest_of_isr_handler(arg0), arg0 - mtctl arg0, pcoq - ldo 4(arg0), arg0 - mtctl arg0, pcoq - - rfi - nop - -/* - * At this point we are back in virtual mode and all our - * normal addressing is once again ok. - * - * It is now ok to take an exception or trap - */ - -rest_of_isr_handler: - -/* - * Point to beginning of float context and - * save the floating point context -- doing whatever patches are necessary - */ - - .call ARGW0=GR - bl _CPU_Save_float_context,%r2 - ldo FP_CONTEXT_OFFSET(sp),arg0 - -/* - * save the ptr to interrupt frame as an argument for the interrupt handler - */ - - copy sp, arg1 - -/* - * Advance the frame to point beyond all interrupt contexts (integer & float) - * this also includes the pad to align to 64byte stack boundary - */ - ldo CPU_INTERRUPT_FRAME_SIZE(sp), sp - -/* - * r3 -- &_ISR_Nest_level - * r5 -- value _ISR_Nest_level - * r4 -- &_Thread_Dispatch_disable_level - * r6 -- value _Thread_Dispatch_disable_level - * r9 -- vector number - */ - - .import _ISR_Nest_level,data - ldil L%_ISR_Nest_level,%r3 - ldo R%_ISR_Nest_level(%r3),%r3 - ldw 0(%r3),%r5 - - .import _Thread_Dispatch_disable_level,data - ldil L%_Thread_Dispatch_disable_level,%r4 - ldo R%_Thread_Dispatch_disable_level(%r4),%r4 - ldw 0(%r4),%r6 - -/* - * increment interrupt nest level counter. If outermost interrupt - * switch the stack and squirrel away the previous sp. - */ - addi 1,%r5,%r5 - stw %r5, 0(%r3) - -/* - * compute and save new stack (with frame) - * just in case we are nested -- simpler this way - */ - comibf,= 1,%r5,stack_done - ldo 128(sp),%r7 - -/* - * Switch to interrupt stack allocated by the interrupt manager (intr.c) - */ - .import _CPU_Interrupt_stack_low,data - ldil L%_CPU_Interrupt_stack_low,%r7 - ldw R%_CPU_Interrupt_stack_low(%r7),%r7 - ldo 128(%r7),%r7 - -stack_done: -/* - * save our current stack pointer where the "old sp" is supposed to be - */ - stw sp, -4(%r7) -/* - * and switch stacks (or advance old stack in nested case) - */ - copy %r7, sp - -/* - * increment the dispatch disable level counter. - */ - addi 1,%r6,%r6 - stw %r6, 0(%r4) - -/* - * load address of user handler - * Note: No error checking is done, it is assumed that the - * vector table contains a valid address or a stub - * spurious handler. - */ - .import _ISR_Vector_table,data - ldil L%_ISR_Vector_table,%r8 - ldo R%_ISR_Vector_table(%r8),%r8 - ldw 0(%r8),%r8 - ldwx,s %r9(%r8),%r8 - -/* - * invoke user interrupt handler - * Interrupts are currently disabled, as per RTEMS convention - * The handler has the option of re-enabling interrupts - * NOTE: can not use 'bl' since it uses "pc-relative" addressing - * and we are using a hard coded address from a table - * So... we fudge r2 ourselves (ala dynacall) - * arg0 = vector number, arg1 = ptr to rtems_interrupt_frame - */ - copy %r9, %r26 - .call ARGW0=GR, ARGW1=GR - blr %r0, rp - bv,n 0(%r8) - -post_user_interrupt_handler: - -/* - * Back from user handler(s) - * Disable external interrupts (since the interrupt handler could - * have turned them on) and return to the interrupted task stack (assuming - * (_ISR_Nest_level == 0) - */ - - rsm HPPA_PSW_I + HPPA_PSW_R, %r0 - ldw -4(sp), sp - -/* - * r3 -- (most of) &_ISR_Nest_level - * r5 -- value _ISR_Nest_level - * r4 -- (most of) &_Thread_Dispatch_disable_level - * r6 -- value _Thread_Dispatch_disable_level - * r7 -- (most of) &_ISR_Signals_to_thread_executing - * r8 -- value _ISR_Signals_to_thread_executing - */ - - .import _ISR_Nest_level,data - ldil L%_ISR_Nest_level,%r3 - ldw R%_ISR_Nest_level(%r3),%r5 - - .import _Thread_Dispatch_disable_level,data - ldil L%_Thread_Dispatch_disable_level,%r4 - ldw R%_Thread_Dispatch_disable_level(%r4),%r6 - - .import _ISR_Signals_to_thread_executing,data - ldil L%_ISR_Signals_to_thread_executing,%r7 - -/* - * decrement isr nest level - */ - addi -1, %r5, %r5 - stw %r5, R%_ISR_Nest_level(%r3) - -/* - * decrement dispatch disable level counter and, if not 0, go on - */ - addi -1,%r6,%r6 - comibf,= 0,%r6,isr_restore - stw %r6, R%_Thread_Dispatch_disable_level(%r4) - -/* - * check whether or not a context switch is necessary - */ - .import _Context_Switch_necessary,data - ldil L%_Context_Switch_necessary,%r8 - ldw R%_Context_Switch_necessary(%r8),%r8 - comibf,=,n 0,%r8,ISR_dispatch - -/* - * check whether or not a context switch is necessary because an ISR - * sent signals to the interrupted task - */ - ldw R%_ISR_Signals_to_thread_executing(%r7),%r8 - comibt,=,n 0,%r8,isr_restore - - -/* - * OK, something happened while in ISR and we need to switch to a task - * other than the one which was interrupted or the - * ISR_Signals_to_thread_executing case - * We also turn on interrupts, since the interrupted task had them - * on (obviously :-) and Thread_Dispatch is happy to leave ints on. - */ - -ISR_dispatch: - stw %r0, R%_ISR_Signals_to_thread_executing(%r7) - - ssm HPPA_PSW_I, %r0 - - .import _Thread_Dispatch,code - .call - bl _Thread_Dispatch,%r2 - ldo 128(sp),sp - - ldo -128(sp),sp - -isr_restore: - -/* - * enable interrupts during most of restore - */ - ssm HPPA_PSW_I, %r0 - -/* - * Get a pointer to beginning of our stack frame - */ - ldo -CPU_INTERRUPT_FRAME_SIZE(sp), %arg1 - -/* - * restore float - */ - .call ARGW0=GR - bl _CPU_Restore_float_context,%r2 - ldo FP_CONTEXT_OFFSET(%arg1), arg0 - - copy %arg1, %arg0 - -/* - * ********** FALL THRU ********** - */ - -/* - * Jump here from bottom of Context_Switch - * Also called directly by _CPU_Context_Restart_self via _Thread_Restart_self - * restore interrupt state - */ - - .EXPORT _CPU_Context_restore -_CPU_Context_restore: - -/* - * restore integer state - */ - ldw R1_OFFSET(arg0),%r1 - ldw R2_OFFSET(arg0),%r2 - ldw R3_OFFSET(arg0),%r3 - ldw R4_OFFSET(arg0),%r4 - ldw R5_OFFSET(arg0),%r5 - ldw R6_OFFSET(arg0),%r6 - ldw R7_OFFSET(arg0),%r7 - ldw R8_OFFSET(arg0),%r8 - ldw R9_OFFSET(arg0),%r9 - ldw R10_OFFSET(arg0),%r10 - ldw R11_OFFSET(arg0),%r11 - ldw R12_OFFSET(arg0),%r12 - ldw R13_OFFSET(arg0),%r13 - ldw R14_OFFSET(arg0),%r14 - ldw R15_OFFSET(arg0),%r15 - ldw R16_OFFSET(arg0),%r16 - ldw R17_OFFSET(arg0),%r17 - ldw R18_OFFSET(arg0),%r18 - ldw R19_OFFSET(arg0),%r19 - ldw R20_OFFSET(arg0),%r20 - ldw R21_OFFSET(arg0),%r21 - ldw R22_OFFSET(arg0),%r22 - ldw R23_OFFSET(arg0),%r23 - ldw R24_OFFSET(arg0),%r24 -/* - * skipping r25; used as scratch register below - * skipping r26 (arg0) until we are done with it - */ - ldw R27_OFFSET(arg0),%r27 - ldw R28_OFFSET(arg0),%r28 - ldw R29_OFFSET(arg0),%r29 -/* - * skipping r30 (sp) until we turn off interrupts - */ - ldw R31_OFFSET(arg0),%r31 - -/* - * Turn off Q & R & I so we can write r30 and interrupt control registers - */ - rsm HPPA_PSW_Q + HPPA_PSW_R + HPPA_PSW_I, %r0 - -/* - * now safe to restore r30 - */ - ldw R30_OFFSET(arg0),%r30 - - ldw IPSW_OFFSET(arg0), %r25 - mtctl %r25, ipsw - - ldw SAR_OFFSET(arg0), %r25 - mtctl %r25, sar - - ldw PCOQFRONT_OFFSET(arg0), %r25 - mtctl %r25, pcoq - - ldw PCOQBACK_OFFSET(arg0), %r25 - mtctl %r25, pcoq - -/* - * Load r25 with interrupts off - */ - ldw R25_OFFSET(arg0),%r25 -/* - * Must load r26 (arg0) last - */ - ldw R26_OFFSET(arg0),%r26 - -isr_exit: - rfi - .EXIT - .PROCEND - -/* - * This section is used to context switch floating point registers. - * Ref: 6-35 of Architecture 1.1 - * - * NOTE: since integer multiply uses the floating point unit, - * we have to save/restore fp on every trap. We cannot - * just try to keep track of fp usage. - */ - - .align 32 - .EXPORT _CPU_Save_float_context,ENTRY,PRIV_LEV=0 -_CPU_Save_float_context: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - fstds,ma %fr0,8(%arg0) - fstds,ma %fr1,8(%arg0) - fstds,ma %fr2,8(%arg0) - fstds,ma %fr3,8(%arg0) - fstds,ma %fr4,8(%arg0) - fstds,ma %fr5,8(%arg0) - fstds,ma %fr6,8(%arg0) - fstds,ma %fr7,8(%arg0) - fstds,ma %fr8,8(%arg0) - fstds,ma %fr9,8(%arg0) - fstds,ma %fr10,8(%arg0) - fstds,ma %fr11,8(%arg0) - fstds,ma %fr12,8(%arg0) - fstds,ma %fr13,8(%arg0) - fstds,ma %fr14,8(%arg0) - fstds,ma %fr15,8(%arg0) - fstds,ma %fr16,8(%arg0) - fstds,ma %fr17,8(%arg0) - fstds,ma %fr18,8(%arg0) - fstds,ma %fr19,8(%arg0) - fstds,ma %fr20,8(%arg0) - fstds,ma %fr21,8(%arg0) - fstds,ma %fr22,8(%arg0) - fstds,ma %fr23,8(%arg0) - fstds,ma %fr24,8(%arg0) - fstds,ma %fr25,8(%arg0) - fstds,ma %fr26,8(%arg0) - fstds,ma %fr27,8(%arg0) - fstds,ma %fr28,8(%arg0) - fstds,ma %fr29,8(%arg0) - fstds,ma %fr30,8(%arg0) - fstds %fr31,0(%arg0) - bv 0(%r2) - addi -(31*8), %arg0, %arg0 ; restore arg0 just for fun - .EXIT - .PROCEND - - .align 32 - .EXPORT _CPU_Restore_float_context,ENTRY,PRIV_LEV=0 -_CPU_Restore_float_context: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - addi (31*8), %arg0, %arg0 ; point at last double - fldds 0(%arg0),%fr31 - fldds,mb -8(%arg0),%fr30 - fldds,mb -8(%arg0),%fr29 - fldds,mb -8(%arg0),%fr28 - fldds,mb -8(%arg0),%fr27 - fldds,mb -8(%arg0),%fr26 - fldds,mb -8(%arg0),%fr25 - fldds,mb -8(%arg0),%fr24 - fldds,mb -8(%arg0),%fr23 - fldds,mb -8(%arg0),%fr22 - fldds,mb -8(%arg0),%fr21 - fldds,mb -8(%arg0),%fr20 - fldds,mb -8(%arg0),%fr19 - fldds,mb -8(%arg0),%fr18 - fldds,mb -8(%arg0),%fr17 - fldds,mb -8(%arg0),%fr16 - fldds,mb -8(%arg0),%fr15 - fldds,mb -8(%arg0),%fr14 - fldds,mb -8(%arg0),%fr13 - fldds,mb -8(%arg0),%fr12 - fldds,mb -8(%arg0),%fr11 - fldds,mb -8(%arg0),%fr10 - fldds,mb -8(%arg0),%fr9 - fldds,mb -8(%arg0),%fr8 - fldds,mb -8(%arg0),%fr7 - fldds,mb -8(%arg0),%fr6 - fldds,mb -8(%arg0),%fr5 - fldds,mb -8(%arg0),%fr4 - fldds,mb -8(%arg0),%fr3 - fldds,mb -8(%arg0),%fr2 - fldds,mb -8(%arg0),%fr1 - bv 0(%r2) - fldds,mb -8(%arg0),%fr0 - .EXIT - .PROCEND - -/* - * These 2 small routines are unused right now. - * Normally we just go thru _CPU_Save_float_context (and Restore) - * - * Here we just deref the ptr and jump up, letting _CPU_Save_float_context - * do the return for us. - */ - - .EXPORT _CPU_Context_save_fp,ENTRY,PRIV_LEV=0 -_CPU_Context_save_fp: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - bl _CPU_Save_float_context, %r0 - ldw 0(%arg0), %arg0 - .EXIT - .PROCEND - - .EXPORT _CPU_Context_restore_fp,ENTRY,PRIV_LEV=0 -_CPU_Context_restore_fp: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - bl _CPU_Restore_float_context, %r0 - ldw 0(%arg0), %arg0 - .EXIT - .PROCEND - - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * - * This routine performs a normal non-FP context switch. - */ - - .align 32 - .EXPORT _CPU_Context_switch,ENTRY,PRIV_LEV=0,ARGW0=GR,ARGW1=GR -_CPU_Context_switch: - .PROC - .CALLINFO FRAME=64 - .ENTRY - -/* - * Save the integer context - */ - stw %r1,R1_OFFSET(arg0) - stw %r2,R2_OFFSET(arg0) - stw %r3,R3_OFFSET(arg0) - stw %r4,R4_OFFSET(arg0) - stw %r5,R5_OFFSET(arg0) - stw %r6,R6_OFFSET(arg0) - stw %r7,R7_OFFSET(arg0) - stw %r8,R8_OFFSET(arg0) - stw %r9,R9_OFFSET(arg0) - stw %r10,R10_OFFSET(arg0) - stw %r11,R11_OFFSET(arg0) - stw %r12,R12_OFFSET(arg0) - stw %r13,R13_OFFSET(arg0) - stw %r14,R14_OFFSET(arg0) - stw %r15,R15_OFFSET(arg0) - stw %r16,R16_OFFSET(arg0) - stw %r17,R17_OFFSET(arg0) - stw %r18,R18_OFFSET(arg0) - stw %r19,R19_OFFSET(arg0) - stw %r20,R20_OFFSET(arg0) - stw %r21,R21_OFFSET(arg0) - stw %r22,R22_OFFSET(arg0) - stw %r23,R23_OFFSET(arg0) - stw %r24,R24_OFFSET(arg0) - stw %r25,R25_OFFSET(arg0) - stw %r26,R26_OFFSET(arg0) - stw %r27,R27_OFFSET(arg0) - stw %r28,R28_OFFSET(arg0) - stw %r29,R29_OFFSET(arg0) - stw %r30,R30_OFFSET(arg0) - stw %r31,R31_OFFSET(arg0) - -/* - * fill in interrupt context section - */ - stw %r2, PCOQFRONT_OFFSET(%arg0) - ldo 4(%r2), %r2 - stw %r2, PCOQBACK_OFFSET(%arg0) - -/* - * Generate a suitable IPSW by using the system default psw - * with the current low bits added in. - */ - - ldil L%CPU_PSW_DEFAULT, %r2 - ldo R%CPU_PSW_DEFAULT(%r2), %r2 - ssm 0, %arg2 - dep %arg2, 31, 8, %r2 - stw %r2, IPSW_OFFSET(%arg0) - -/* - * at this point, the running task context is completely saved - * Now jump to the bottom of the interrupt handler to load the - * heirs context - */ - - b _CPU_Context_restore - copy %arg1, %arg0 - - .EXIT - .PROCEND - - -/* - * Find first bit - * NOTE: - * This is used (and written) only for the ready chain code and - * priority bit maps. - * Any other use constitutes fraud. - * Returns first bit from the least significant side. - * Eg: if input is 0x8001 - * output will indicate the '1' bit and return 0. - * This is counter to HPPA bit numbering which calls this - * bit 31. This way simplifies the macros _CPU_Priority_Mask - * and _CPU_Priority_Bits_index. - * - * NOTE: - * We just use 16 bit version - * does not handle zero case - * - * Based on the UTAH Mach libc version of ffs. - */ - - .align 32 - .EXPORT hppa_rtems_ffs,ENTRY,PRIV_LEV=0,ARGW0=GR -hppa_rtems_ffs: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - -#ifdef RETURN_ERROR_ON_ZERO - comb,= %arg0,%r0,ffsdone ; If arg0 is 0 - ldi -1,%ret0 ; return -1 -#endif - -#if BITFIELD_SIZE == 32 - ldi 31,%ret0 ; Set return to high bit - extru,= %arg0,31,16,%r0 ; If low 16 bits are non-zero - addi,tr -16,%ret0,%ret0 ; subtract 16 from bitpos - shd %r0,%arg0,16,%arg0 ; else shift right 16 bits -#else - ldi 15,%ret0 ; Set return to high bit -#endif - extru,= %arg0,31,8,%r0 ; If low 8 bits are non-zero - addi,tr -8,%ret0,%ret0 ; subtract 8 from bitpos - shd %r0,%arg0,8,%arg0 ; else shift right 8 bits - extru,= %arg0,31,4,%r0 ; If low 4 bits are non-zero - addi,tr -4,%ret0,%ret0 ; subtract 4 from bitpos - shd %r0,%arg0,4,%arg0 ; else shift right 4 bits - extru,= %arg0,31,2,%r0 ; If low 2 bits are non-zero - addi,tr -2,%ret0,%ret0 ; subtract 2 from bitpos - shd %r0,%arg0,2,%arg0 ; else shift right 2 bits - extru,= %arg0,31,1,%r0 ; If low bit is non-zero - addi -1,%ret0,%ret0 ; subtract 1 from bitpos -ffsdone: - bv,n 0(%r2) - nop - .EXIT - .PROCEND diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/.cvsignore b/c/src/exec/score/cpu/hppa1.1/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/.cvsignore b/c/src/exec/score/cpu/hppa1.1/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h b/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h deleted file mode 100644 index fe4182c342..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h +++ /dev/null @@ -1,653 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the HP - * PA-RISC processor (Level 1.1). - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/hppa.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * RTEMS manages an interrupt stack in software for the HPPA. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * HPPA has hardware FP, it is assumed to exist by GCC so all tasks - * may implicitly use it (especially for integer multiplies). Because - * the FP context is technically part of the basic integer context - * on this CPU, we cannot use the deferred FP context switch algorithm. - */ - -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#define CPU_ALL_TASKS_ARE_FP TRUE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE -#define CPU_STACK_GROWS_UP TRUE -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((__aligned__ (32))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* constants */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * PSW contstants - */ - -#define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D) -#define CPU_PSW_INTERRUPTS_ON (CPU_PSW_BASE | HPPA_PSW_I) -#define CPU_PSW_INTERRUPTS_OFF (CPU_PSW_BASE) - -#define CPU_PSW_DEFAULT CPU_PSW_BASE - - -#ifndef ASM - -/* - * Contexts - * - * This means we have the following context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * - * The PA-RISC is very fast so the expense of saving an extra register - * or two is not of great concern at the present. So we are not making - * a distinction between what is saved during a task switch and what is - * saved at each interrupt. Plus saving the entire context should make - * it easier to make gdb aware of RTEMS tasks. - */ - -typedef struct { - unsigned32 flags; /* whatever */ - unsigned32 gr1; /* scratch -- caller saves */ - unsigned32 gr2; /* RP -- return pointer */ - unsigned32 gr3; /* scratch -- callee saves */ - unsigned32 gr4; /* scratch -- callee saves */ - unsigned32 gr5; /* scratch -- callee saves */ - unsigned32 gr6; /* scratch -- callee saves */ - unsigned32 gr7; /* scratch -- callee saves */ - unsigned32 gr8; /* scratch -- callee saves */ - unsigned32 gr9; /* scratch -- callee saves */ - unsigned32 gr10; /* scratch -- callee saves */ - unsigned32 gr11; /* scratch -- callee saves */ - unsigned32 gr12; /* scratch -- callee saves */ - unsigned32 gr13; /* scratch -- callee saves */ - unsigned32 gr14; /* scratch -- callee saves */ - unsigned32 gr15; /* scratch -- callee saves */ - unsigned32 gr16; /* scratch -- callee saves */ - unsigned32 gr17; /* scratch -- callee saves */ - unsigned32 gr18; /* scratch -- callee saves */ - unsigned32 gr19; /* scratch -- caller saves */ - unsigned32 gr20; /* scratch -- caller saves */ - unsigned32 gr21; /* scratch -- caller saves */ - unsigned32 gr22; /* scratch -- caller saves */ - unsigned32 gr23; /* argument 3 */ - unsigned32 gr24; /* argument 2 */ - unsigned32 gr25; /* argument 1 */ - unsigned32 gr26; /* argument 0 */ - unsigned32 gr27; /* DP -- global data pointer */ - unsigned32 gr28; /* return values -- caller saves */ - unsigned32 gr29; /* return values -- caller saves */ - unsigned32 sp; /* gr30 */ - unsigned32 gr31; - - /* Various control registers */ - - unsigned32 sar; /* cr11 */ - unsigned32 ipsw; /* cr22; full 32 bits of psw */ - unsigned32 iir; /* cr19; interrupt instruction register */ - unsigned32 ior; /* cr21; interrupt offset register */ - unsigned32 isr; /* cr20; interrupt space register (not used) */ - unsigned32 pcoqfront; /* cr18; front que offset */ - unsigned32 pcoqback; /* cr18; back que offset */ - unsigned32 pcsqfront; /* cr17; front que space (not used) */ - unsigned32 pcsqback; /* cr17; back que space (not used) */ - unsigned32 itimer; /* cr16; itimer value */ - -} Context_Control; - - -/* Must be double word aligned. - * This will be ok since our allocator returns 8 byte aligned chunks - */ - -typedef struct { - double fr0; /* status */ - double fr1; /* exception information */ - double fr2; /* exception information */ - double fr3; /* exception information */ - double fr4; /* argument */ - double fr5; /* argument */ - double fr6; /* argument */ - double fr7; /* argument */ - double fr8; /* scratch -- caller saves */ - double fr9; /* scratch -- caller saves */ - double fr10; /* scratch -- caller saves */ - double fr11; /* scratch -- caller saves */ - double fr12; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr13; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr14; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr15; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr16; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr17; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr18; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr19; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr20; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr21; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr22; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr23; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr24; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr25; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr26; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr27; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr28; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr29; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr30; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr31; /* caller saves -- (PA-RISC 1.1 CPUs) */ -} Context_Control_fp; - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt. - */ - -typedef struct { - Context_Control Integer; - Context_Control_fp Floating_Point; -} CPU_Interrupt_frame; - -/* - * Our interrupt handlers take a 2nd argument: - * a pointer to a CPU_Interrupt_frame - * So we use our own prototype instead of rtems_isr_entry - */ - -typedef void ( *hppa_rtems_isr_entry )( - unsigned32, - CPU_Interrupt_frame * - ); - -/* - * The following table contains the information required to configure - * the HPPA specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void * ); - /* end of fields required on all CPUs */ - - hppa_rtems_isr_entry spurious_handler; - - unsigned32 itimer_clicks_per_microsecond; /* for use by Clock driver */ -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access HPPA specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_spurious_handler() \ - (_CPU_Table.spurious_handler) - -#define rtems_cpu_configuration_get_itimer_clicks_per_microsecond() \ - (_CPU_Table.itimer_clicks_per_microsecond) - -/* variables */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -SCORE_EXTERN unsigned32 _CPU_Default_gr27; -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -#endif /* ! ASM */ - -/* - * context sizes - */ - -#ifndef ASM -#define CPU_CONTEXT_SIZE sizeof( Context_Control ) -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) -#endif - -/* - * size of a frame on the stack - */ - -#define CPU_FRAME_SIZE (16 * 4) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_SIZE (CPU_FRAME_SIZE * 2) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * HPPA has 32 traps, then 32 external interrupts - * Rtems (_ISR_Vector_Table) is aware ONLY of the first 32 - * The BSP is aware of the external interrupts and possibly more. - * - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS (HPPA_INTERNAL_TRAPS) -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Don't be chintzy here; we don't want to debug these problems - * Some of the tests eat almost 4k. - * Plus, the HPPA always allocates chunks of 64 bytes for stack - * growth. - */ - -#define CPU_STACK_MINIMUM_SIZE (8 * 1024) - -/* - * HPPA double's must be on 8 byte boundary - */ - -#define CPU_ALIGNMENT 8 - -/* - * just follow the basic HPPA alignment for the heap and partition - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * HPPA stack is best when 64 byte aligned. - */ - -#define CPU_STACK_ALIGNMENT 64 - -#ifndef ASM - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* Disable interrupts; returning previous psw bits in _isr_level */ - -#define _CPU_ISR_Disable( _isr_level ) \ - do { \ - HPPA_ASM_RSM(HPPA_PSW_I, _isr_level); \ - if (_isr_level & HPPA_PSW_I) _isr_level = 0; \ - else _isr_level = 1; \ - } while(0) - -/* Enable interrupts to previous level from _CPU_ISR_Disable - * does not change 'level' - */ - -#define _CPU_ISR_Enable( _isr_level ) \ - { \ - register int _ignore; \ - if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \ - else HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \ - } - -/* restore, then disable interrupts; does not change level */ -#define _CPU_ISR_Flash( _isr_level ) \ - { \ - if (_isr_level == 0) \ - { \ - register int _ignore; \ - HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \ - HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \ - } \ - } - -/* - * Interrupt task levels - * - * Future scheme proposal - * level will be an index into a array. - * Each entry of array will be the interrupt bits - * enabled for that level. There will be 32 bits of external - * interrupts (to be placed in EIEM) and some (optional) bsp - * specific bits - * - * For pixel flow this *may* mean something like: - * level 0: all interrupts enabled (external + rhino) - * level 1: rhino disabled - * level 2: all io interrupts disabled (timer still enabled) - * level 7: *ALL* disabled (timer disabled) - */ - -/* set interrupts on or off; does not return new level */ -#define _CPU_ISR_Set_level( new_level ) \ - { \ - volatile int ignore; \ - if ( new_level ) HPPA_ASM_RSM(HPPA_PSW_I, ignore); \ - else HPPA_ASM_SSM(HPPA_PSW_I, ignore); \ - } - -/* return current level */ -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - * - * HPPA port adds two macros which hide the "indirectness" of the - * pointer passed the save/restore FP context assembly routines. - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _new_level, _entry_point, _is_fp ) \ - do { \ - unsigned32 _stack; \ - \ - (_the_context)->flags = 0xfeedf00d; \ - (_the_context)->pcoqfront = (unsigned32)(_entry_point); \ - (_the_context)->pcoqback = (unsigned32)(_entry_point) + 4; \ - (_the_context)->pcsqfront = 0; \ - (_the_context)->pcsqback = 0; \ - if ( (_new_level) ) \ - (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \ - else \ - (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \ - \ - _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \ - _stack &= ~(CPU_STACK_ALIGNMENT - 1); \ - if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \ - _stack += CPU_FRAME_SIZE; \ - \ - (_the_context)->sp = (_stack); \ - (_the_context)->gr27 = _CPU_Default_gr27; \ - } while (0) - -#define _CPU_Context_Restart_self( _the_context ) \ - do { \ - _CPU_Context_restore( (_the_context) ); \ - } while (0) - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\ - } while(0) - -#define _CPU_Context_save_fp( _fp_context ) \ - _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) ) - -#define _CPU_Context_restore_fp( _fp_context ) \ - _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) ) - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -void hppa_cpu_halt(unsigned32 the_error); -#define _CPU_Fatal_halt( _error ) \ - hppa_cpu_halt(_error) - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - * - * NOTE: - * - * The HPPA does not have a scan instruction. This functionality - * is implemented in software. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -int hppa_rtems_ffs(unsigned int value); -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - _output = hppa_rtems_ffs(_value) - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - * - * Note: 255 is the lowest priority - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Save_float_context - * - * This routine saves the floating point context passed to it. - * - * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA - * which dereferences the pointer before calling this. - */ - -void _CPU_Save_float_context( - Context_Control_fp *fp_context -); - -/* - * _CPU_Restore_float_context - * - * This routine restores the floating point context passed to it. - * - * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA - * which dereferences the pointer before calling this. - */ - -void _CPU_Restore_float_context( - Context_Control_fp *fp_context -); - - -/* - * The raw interrupt handler for external interrupts - */ - -extern void _Generic_ISR_Handler( - void -); - - -/* The following routine swaps the endian format of an unsigned int. - * It must be static so it can be referenced indirectly. - */ - -static inline unsigned int -CPU_swap_u32(unsigned32 value) -{ - unsigned32 swapped; - - HPPA_ASM_SWAPBYTES(value, swapped); - - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#endif /* ! ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* ! __CPU_h */ diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu_asm.h deleted file mode 100644 index 951f80dcf0..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu_asm.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 1990,1991 The University of Utah and - * the Center for Software Science (CSS). All rights reserved. - * - * Permission to use, copy, modify and distribute this software is hereby - * granted provided that (1) source code retains these copyright, permission, - * and disclaimer notices, and (2) redistributions including binaries - * reproduce the notices in supporting documentation, and (3) all advertising - * materials mentioning features or use of this software display the following - * acknowledgement: ``This product includes software developed by the Center - * for Software Science at the University of Utah.'' - * - * THE UNIVERSITY OF UTAH AND CSS ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS - * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSS DISCLAIM ANY LIABILITY OF - * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * - * CSS requests users of this software to return to css-dist@cs.utah.edu any - * improvements that they make and grant CSS redistribution rights. - * - * Utah $Hdr: asm.h 1.6 91/12/03$ - * - * $Id$ - */ - -/* - * Hardware Space Registers - */ -sr0 .reg %sr0 -sr1 .reg %sr1 -sr2 .reg %sr2 -sr3 .reg %sr3 -sr4 .reg %sr4 -sr5 .reg %sr5 -sr6 .reg %sr6 -sr7 .reg %sr7 - -/* - * Control register aliases - */ - -rctr .reg %cr0 -pidr1 .reg %cr8 -pidr2 .reg %cr9 -ccr .reg %cr10 -sar .reg %cr11 -pidr3 .reg %cr12 -pidr4 .reg %cr13 -iva .reg %cr14 -eiem .reg %cr15 -itmr .reg %cr16 -pcsq .reg %cr17 -pcoq .reg %cr18 -iir .reg %cr19 -isr .reg %cr20 -ior .reg %cr21 -ipsw .reg %cr22 -eirr .reg %cr23 - -/* - * Calling Convention - */ -rp .reg %r2 -arg3 .reg %r23 -arg2 .reg %r24 -arg1 .reg %r25 -arg0 .reg %r26 -dp .reg %r27 -ret0 .reg %r28 -ret1 .reg %r29 -sl .reg %r29 -sp .reg %r30 - - diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/hppa.h b/c/src/exec/score/cpu/hppa1.1/rtems/score/hppa.h deleted file mode 100644 index ceaf2fcce2..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/hppa.h +++ /dev/null @@ -1,727 +0,0 @@ -/* - * Description: - * - * Definitions for HP PA Risc - * ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - * - * $Id$ - */ - -#ifndef _INCLUDE_HPPA_H -#define _INCLUDE_HPPA_H - -#if defined(__cplusplus) -extern "C" { -#endif - -/* - * This section contains the information required to build - * RTEMS for a particular member of the Hewlett Packard - * PA-RISC family. It does this by setting variables to - * indicate which implementation dependent features are - * present in a particular member of the family. - */ - -/* - * Hack to allow multlib effort to continue -- known to build. - */ - -#define CPU_MODEL_NAME "hppa 7xxx" -#if 0 -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" - -#elif defined(hppa7100) - -#define CPU_MODEL_NAME "hppa 7100" - -#elif defined(hppa7200) - -#define CPU_MODEL_NAME "hppa 7200" - -#else - -#error "Unsupported CPU Model" - -#endif -#endif - -/* - * Define the name of the CPU family. - */ - -#if !defined(CPU_NAME) -#define CPU_NAME "HP PA-RISC 1.1" -#endif - -/* - * Processor Status Word (PSW) Masks - */ - - -#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */ -#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */ -#define HPPA_PSW_r2 0x20000000 /* reserved */ -#define HPPA_PSW_r3 0x10000000 /* reserved */ -#define HPPA_PSW_r4 0x08000000 /* reserved */ -#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */ -#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */ -#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */ -#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/ -#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */ -#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */ -#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */ -#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */ -#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */ -#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */ -#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */ -#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */ -#define HPPA_PSW_r24 0x00000080 /* reserved */ -#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */ -#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */ -#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */ -#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */ -#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */ -#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */ -#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */ - /* Low-Priority Machine Check */ - /* Interruption Enable */ - -/* - * HPPA traps and interrupts - * basic layout. Note numbers do not denote priority - * - * 0-31 basic traps and interrupts defined by HPPA architecture - * 0-31 32 external interrupts - * 32-... bsp defined - */ - -#define HPPA_TRAP_NON_EXISTENT 0 -/* group 1 */ -#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1 -/* group 2 */ -#define HPPA_TRAP_POWER_FAIL 2 -#define HPPA_TRAP_RECOVERY_COUNTER 3 -#define HPPA_TRAP_EXTERNAL_INTERRUPT 4 -#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5 -#define HPPA_TRAP_PERFORMANCE_MONITOR 29 -/* group 3 */ -#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6 -#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7 -#define HPPA_TRAP_INSTRUCTION_DEBUG 30 -#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8 -#define HPPA_TRAP_BREAK_INSTRUCTION 9 -#define HPPA_TRAP_PRIVILEGED_OPERATION 10 -#define HPPA_TRAP_PRIVILEGED_REGISTER 11 -#define HPPA_TRAP_OVERFLOW 12 -#define HPPA_TRAP_CONDITIONAL 13 -#define HPPA_TRAP_ASSIST_EXCEPTION 14 -#define HPPA_TRAP_DATA_TLB_MISS 15 -#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16 -#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17 -#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26 -#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27 -#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28 -#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18 -#define HPPA_TRAP_DATA_MEMORY_BREAK 19 -#define HPPA_TRAP_TLB_DIRTY_BIT 20 -#define HPPA_TRAP_PAGE_REFERENCE 21 -#define HPPA_TRAP_DATA_DEBUG 31 -#define HPPA_TRAP_ASSIST_EMULATION 22 -/* group 4 */ -#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23 -#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24 -#define HPPA_TRAP_TAKEN_BRANCH 25 - -#define HPPA_INTERNAL_TRAPS 32 - -/* External Interrupts via interrupt 4 */ - -#define HPPA_INTERRUPT_EXTERNAL_0 0 -#define HPPA_INTERRUPT_EXTERNAL_1 1 -#define HPPA_INTERRUPT_EXTERNAL_2 2 -#define HPPA_INTERRUPT_EXTERNAL_3 3 -#define HPPA_INTERRUPT_EXTERNAL_4 4 -#define HPPA_INTERRUPT_EXTERNAL_5 5 -#define HPPA_INTERRUPT_EXTERNAL_6 6 -#define HPPA_INTERRUPT_EXTERNAL_7 7 -#define HPPA_INTERRUPT_EXTERNAL_8 8 -#define HPPA_INTERRUPT_EXTERNAL_9 9 -#define HPPA_INTERRUPT_EXTERNAL_10 10 -#define HPPA_INTERRUPT_EXTERNAL_11 11 -#define HPPA_INTERRUPT_EXTERNAL_12 12 -#define HPPA_INTERRUPT_EXTERNAL_13 13 -#define HPPA_INTERRUPT_EXTERNAL_14 14 -#define HPPA_INTERRUPT_EXTERNAL_15 15 -#define HPPA_INTERRUPT_EXTERNAL_16 16 -#define HPPA_INTERRUPT_EXTERNAL_17 17 -#define HPPA_INTERRUPT_EXTERNAL_18 18 -#define HPPA_INTERRUPT_EXTERNAL_19 19 -#define HPPA_INTERRUPT_EXTERNAL_20 20 -#define HPPA_INTERRUPT_EXTERNAL_21 21 -#define HPPA_INTERRUPT_EXTERNAL_22 22 -#define HPPA_INTERRUPT_EXTERNAL_23 23 -#define HPPA_INTERRUPT_EXTERNAL_24 24 -#define HPPA_INTERRUPT_EXTERNAL_25 25 -#define HPPA_INTERRUPT_EXTERNAL_26 26 -#define HPPA_INTERRUPT_EXTERNAL_27 27 -#define HPPA_INTERRUPT_EXTERNAL_28 28 -#define HPPA_INTERRUPT_EXTERNAL_29 29 -#define HPPA_INTERRUPT_EXTERNAL_30 30 -#define HPPA_INTERRUPT_EXTERNAL_31 31 - -#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0 -#define HPPA_EXTERNAL_INTERRUPTS 32 - -/* BSP defined interrupts begin here */ - -#define HPPA_INTERRUPT_MAX 32 - -/* - * Cache characteristics - */ - -#define HPPA_CACHELINE_SIZE 32 -#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1) - -/* - * page size characteristics - */ - -#define HPPA_PAGE_SIZE 4096 -#define HPPA_PAGE_MASK (0xfffff000) - - -/* - * TLB characteristics - * - * Flags and Access Control layout for using TLB protection insertion - * - * 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 - * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |?|?|T|D|B|type |PL1|Pl2|U| access id |?| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - */ - -/* - * Access rights (type + PL1 + PL2) - */ -#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */ -#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */ -#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */ -#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */ -#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */ -#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */ -#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */ -#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */ - -/* - * Floating point status register definitions - */ - -#define HPPA_FPSTATUS_ENABLE_I 0x00000001 /* inexact operation */ -#define HPPA_FPSTATUS_ENABLE_U 0x00000002 /* underflow */ -#define HPPA_FPSTATUS_ENABLE_O 0x00000004 /* overflow */ -#define HPPA_FPSTATUS_ENABLE_Z 0x00000008 /* division by zero */ -#define HPPA_FPSTATUS_ENABLE_V 0x00000010 /* invalid operation */ -#define HPPA_FPSTATUS_D 0x00000020 /* denormalize as zero */ -#define HPPA_FPSTATUS_T 0x00000040 /* delayed trap */ -#define HPPA_FPSTATUS_RM_MASK 0x00000600 /* rounding mode */ -#define HPPA_FPSTATUS_RM_SHIFT 9 -#define HPPA_FPSTATUS_CQ_MASK 0x001FFC00 /* compare queue */ -#define HPPA_FPSTATUS_CQ_SHIFT 13 -#define HPPA_FPSTATUS_C 0x04000000 /* most recent ompare bit */ -#define HPPA_FPSTATUS_FLAG_I 0x08000000 /* inexact */ -#define HPPA_FPSTATUS_FLAG_U 0x10000000 /* underflow */ -#define HPPA_FPSTATUS_FLAG_O 0x20000000 /* overflow */ -#define HPPA_FPSTATUS_FLAG_Z 0x40000000 /* division by zero */ -#define HPPA_FPSTATUS_FLAG_V 0x80000000 /* invalid operation */ - - -/* - * Inline macros for misc. interesting opcodes - */ - -/* generate a global label */ -#define HPPA_ASM_LABEL(label) \ - asm(".export " label ", ! .label " label); - -/* Return From Interrupt RFI */ -#define HPPA_ASM_RFI() asm volatile ("rfi") - -/* Set System Mask SSM i,t */ -#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \ - : "=r" (gr) \ - : "i" (i)) -/* Reset System Mask RSM i,t */ -#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \ - : "=r" (gr) \ - : "i" (i)) -/* Move To System Mask MTSM r */ -#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \ - : : "r" (gr)) - -/* Load Space Identifier LDSID (s,b),t */ -#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (grb)) - -/* - * Gcc extended asm doesn't really allow for treatment of space registers - * as "registers", so we have to use "i" format. - * Unfortunately this means that the "=" constraint is not available. - */ - -/* Move To Space Register MTSP r,sr */ -#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \ - : : "i" (sr), \ - "r" (gr)) - -/* Move From Space Register MFSP sr,t */ -#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \ - : "=r" (gr) \ - : "i" (sr)) - -/* Move To Control register MTCTL r,t */ -#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \ - : : "i" (cr), \ - "r" (gr)) - -/* Move From Control register MFCTL r,t */ -#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \ - : "=r" (gr) \ - : "i" (cr)) - -/* Synchronize caches SYNC */ -#define HPPA_ASM_SYNC() asm volatile ("sync") - -/* Probe Read Access PROBER (s,b),r,t */ -#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \ - asm volatile ("prober (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "r" (gracc)) - -/* Probe Read Access Immediate PROBERI (s,b),i,t*/ -#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \ - asm volatile ("proberi (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "i" (iacc)) - -/* Probe Write Access PROBEW (s,b),r,t */ -#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \ - asm volatile ("probew (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "r" (gracc)) - -/* Probe Write Access Immediate PROBEWI (s,b),i,t */ -#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \ - asm volatile ("probewi (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "i" (iacc)) - -/* Load Physical Address LPA x(s,b),t */ -#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (grb)) - -/* Load Coherence Index LCI x(s,b),t */ -/* AKA: Load Hash Address LHA x(s,b),t */ -#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \ - : "=r" (grt) \ - : "r" (grx),\ - "i" (sr), \ - "r" (grb)) -#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt) - -/* Purge Data Tlb PDTLB x(s,b) */ -#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Instruction Tlb PITLB x(s,b) */ -#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Data Tlb Entry PDTLBE x(s,b) */ -#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Instruction Tlb Entry PITLBE x(s,b) */ -#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - - -/* Insert Data TLB Address IDTLBA r,(s,b) */ -#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Insert Instruction TLB Address IITLBA r,(s,b) */ -#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Insert Data TLB Protection IDTLBP r,(s,b) */ -#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Insert Instruction TLB Protection IITLBP r,(s,b) */ -#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Data Cache PDC x(s,b) */ -#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Data Cache FDC x(s,b) */ -#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Instruction Cache FDC x(s,b) */ -#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Data Cache Entry FDCE x(s,b) */ -#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Instruction Cache Entry FICE x(s,b) */ -#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Break BREAK i5,i13 */ -#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \ - : : "i" (i5), \ - "i" (i13)) - -/* Load and Clear Word Short LDCWS d(s,b),t */ -#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \ - : "=r" (grt) \ - : "i" (i), \ - "i" (sr), \ - "r" (grb)) - -/* Load and Clear Word Indexed LDCWX x(s,b),t */ -#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \ - : "=r" (grt) \ - : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Load Word Absolute Short LDWAS d(b),t */ -/* NOTE: "short" here means "short displacement" */ -#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \ - : "=r" (gr) \ - : "i" (disp), \ - "r" (grbase)) - -/* Store Word Absolute Short STWAS r,d(b) */ -/* NOTE: "short" here means "short displacement" */ -#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \ - : : "r" (gr), \ - "i" (disp), \ - "r" (grbase)) - -/* - * Swap bytes - * REFERENCE: PA72000 TRM -- Appendix C - */ -#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \ - " shd %1,%1,16,%0 \n\ - dep %0,15,8,%0 \n\ - shd %1,%0,8,%0" \ - : "=r" (swapped) \ - : "r" (value) \ - ) - - -/* 72000 Diagnose instructions follow - * These macros assume gas knows about these instructions. - * gas2.2.u1 did not. - * I added them to my copy and installed it locally. - * - * There are *very* special requirements for these guys - * ref: TRM 6.1.3 Programming Constraints - * - * The macros below handle the following rules - * - * Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled. - * Must never be nullified (hence the leading nop) - * NOP must preced every RDD,RDT,WDD,WDT,RDTLB - * Instruction preceeding GR_SHDW must not set any of the GR's saved - * - * The macros do *NOT* deal with the following problems - * doubled DIAGNOSE instructions must not straddle a page boundary - * if code translation enabled. (since 2nd could trap on ITLB) - * If you care about DHIT and DPE bits of DR0, then - * No store instruction in the 2 insn window before RDD - */ - - -/* Move To CPU/DIAG register MTCPU r,t */ -#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \ - " mtcpu %1,%0 \n" \ - " mtcpu %1,%0" \ - : : "i" (dr), \ - "r" (gr)) - -/* Move From CPU/DIAG register MFCPU r,t */ -#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \ - " mfcpu %1,%0\n" \ - " mfcpu %1,%0" \ - : "=r" (gr) \ - : "i" (dr)) - -/* Transfer of Control Enable TOC_EN */ -#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \ - " tocen") - -/* Transfer of Control Disable TOC_DIS */ -#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \ - " tocdis") - -/* Shadow Registers to General Register SHDW_GR */ -#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \ - " shdwgr" \ - ::: "r1" "r8" "r9" "r16" \ - "r17" "r24" "r25") - -/* General Registers to Shadow Register GR_SHDW */ -#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \ - " grshdw \n" \ - " grshdw") - -/* - * Definitions of special registers for use by the above macros. - */ - -/* Hardware Space Registers */ -#define HPPA_SR0 0 -#define HPPA_SR1 1 -#define HPPA_SR2 2 -#define HPPA_SR3 3 -#define HPPA_SR4 4 -#define HPPA_SR5 5 -#define HPPA_SR6 6 -#define HPPA_SR7 7 - -/* Hardware Control Registers */ -#define HPPA_CR0 0 -#define HPPA_RCTR 0 /* Recovery Counter Register */ - -#define HPPA_CR8 8 /* Protection ID 1 */ -#define HPPA_PIDR1 8 - -#define HPPA_CR9 9 /* Protection ID 2 */ -#define HPPA_PIDR2 9 - -#define HPPA_CR10 10 -#define HPPA_CCR 10 /* Coprocessor Confiquration Register */ - -#define HPPA_CR11 11 -#define HPPA_SAR 11 /* Shift Amount Register */ - -#define HPPA_CR12 12 -#define HPPA_PIDR3 12 /* Protection ID 3 */ - -#define HPPA_CR13 13 -#define HPPA_PIDR4 13 /* Protection ID 4 */ - -#define HPPA_CR14 14 -#define HPPA_IVA 14 /* Interrupt Vector Address */ - -#define HPPA_CR15 15 -#define HPPA_EIEM 15 /* External Interrupt Enable Mask */ - -#define HPPA_CR16 16 -#define HPPA_ITMR 16 /* Interval Timer */ - -#define HPPA_CR17 17 -#define HPPA_PCSQ 17 /* Program Counter Space queue */ - -#define HPPA_CR18 18 -#define HPPA_PCOQ 18 /* Program Counter Offset queue */ - -#define HPPA_CR19 19 -#define HPPA_IIR 19 /* Interruption Instruction Register */ - -#define HPPA_CR20 20 -#define HPPA_ISR 20 /* Interruption Space Register */ - -#define HPPA_CR21 21 -#define HPPA_IOR 21 /* Interruption Offset Register */ - -#define HPPA_CR22 22 -#define HPPA_IPSW 22 /* Interrpution Processor Status Word */ - -#define HPPA_CR23 23 -#define HPPA_EIRR 23 /* External Interrupt Request */ - -#define HPPA_CR24 24 -#define HPPA_PPDA 24 /* Physcial Page Directory Address */ -#define HPPA_TR0 24 /* Temporary register 0 */ - -#define HPPA_CR25 25 -#define HPPA_HTA 25 /* Hash Table Address */ -#define HPPA_TR1 25 /* Temporary register 1 */ - -#define HPPA_CR26 26 -#define HPPA_TR2 26 /* Temporary register 2 */ - -#define HPPA_CR27 27 -#define HPPA_TR3 27 /* Temporary register 3 */ - -#define HPPA_CR28 28 -#define HPPA_TR4 28 /* Temporary register 4 */ - -#define HPPA_CR29 29 -#define HPPA_TR5 29 /* Temporary register 5 */ - -#define HPPA_CR30 30 -#define HPPA_TR6 30 /* Temporary register 6 */ - -#define HPPA_CR31 31 -#define HPPA_CPUID 31 /* MP identifier */ - -/* - * Diagnose registers - */ - -#define HPPA_DR0 0 -#define HPPA_DR1 1 -#define HPPA_DR8 8 -#define HPPA_DR24 24 -#define HPPA_DR25 25 - -/* - * Tear apart a break instruction to find its type. - */ -#define HPPA_BREAK5(x) ((x) & 0x1F) -#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF) - -/* assemble a break instruction */ -#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) | (((i13) & 0x1FFF) << 13)) - - -/* - * this won't work in ASM or non-GNU compilers - */ - -#if !defined(ASM) && defined(__GNUC__) - -/* - * static inline utility functions to get at control registers - */ - -#define EMIT_GET_CONTROL(name, reg) \ -static __inline__ unsigned int \ -get_ ## name (void) \ -{ \ - unsigned int value; \ - HPPA_ASM_MFCTL(reg, value); \ - return value; \ -} - -#define EMIT_SET_CONTROL(name, reg) \ -static __inline__ void \ -set_ ## name (unsigned int new_value) \ -{ \ - HPPA_ASM_MTCTL(new_value, reg); \ -} - -#define EMIT_CONTROLS(name, reg) \ - EMIT_GET_CONTROL(name, reg) \ - EMIT_SET_CONTROL(name, reg) - -EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */ -EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */ -EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */ -EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */ -EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */ -EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */ -EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */ -EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */ -EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */ -EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */ -EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */ -EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */ -EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */ -EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */ -EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */ -EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */ -EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */ -EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */ -EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */ -EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */ -EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */ -EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */ -EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */ -EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */ -EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */ -EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */ - -#endif /* ASM and GNU */ - -/* - * If and How to invoke the debugger (a ROM debugger generally) - */ -#define CPU_INVOKE_DEBUGGER \ - do { \ - HPPA_ASM_BREAK(1,1); \ - } while (0) - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_HPPA_H */ - diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/types.h b/c/src/exec/score/cpu/hppa1.1/rtems/score/types.h deleted file mode 100644 index 512323819b..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/types.h +++ /dev/null @@ -1,46 +0,0 @@ -/* hppatypes.h - * - * This include file contains type definitions pertaining to the Hewlett - * Packard PA-RISC processor family. - * - * $Id$ - */ - -#ifndef _INCLUDE_HPPATYPES_H -#define _INCLUDE_HPPATYPES_H - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* 8-bit unsigned integer */ -typedef unsigned short unsigned16; /* 16-bit unsigned integer */ -typedef unsigned int unsigned32; /* 32-bit unsigned integer */ -typedef unsigned long long unsigned64; /* 64-bit unsigned integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif /* _INCLUDE_HPPATYPES_H */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/i386/.cvsignore b/c/src/exec/score/cpu/i386/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/i386/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/i386/ChangeLog b/c/src/exec/score/cpu/i386/ChangeLog deleted file mode 100644 index 5ba423533b..0000000000 --- a/c/src/exec/score/cpu/i386/ChangeLog +++ /dev/null @@ -1,135 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-03-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/idtr.h: New file, extracted from libcpu/cpu.h. - * rtems/score/interrupts.h: New file, extracted from libcpu/cpu.h. - * rtems/score/registers.h: New file, moved from libcpu. - * Makefile.am: Reflect changes above. - * cpu.c: Don't include cpuModel.h, - #include <rtems.h>, - #include <rtems/score/i386types.h>, - #include <rtems/score/idtr.h>. - * rtems/score/cpu.h: Don't include libcpu/cpu.h. - #include <rtems/score/interrupts.h>, - #include <rtems/score/registers.h>. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/i386types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2001-02-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/Makefile.am, rtems/score/Makefile.am: Removed again. - -2002-01-31 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-01-30 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am: Corrected so .h files from rtems/score/ are installed. - -2002-01-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Include rtems/bspIo.h instead of bspIo.h. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-12 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/i386.h: Corrected "#elsif" to be "#elif". - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/i386.h: cpu-variant define handling - Rewrite due to introduction of multilib defines. - * asm.h: include cpuopts.h instead of targopts.h - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/i386/Makefile.am b/c/src/exec/score/cpu/i386/Makefile.am deleted file mode 100644 index efcc908a16..0000000000 --- a/c/src/exec/score/cpu/i386/Makefile.am +++ /dev/null @@ -1,58 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS= asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/i386.h \ - rtems/score/types.h \ - rtems/score/interrupts.h \ - rtems/score/registers.h \ - rtems/score/idtr.h - -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -REL = $(ARCH)/rtems-cpu.rel - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/i386/asm.h b/c/src/exec/score/cpu/i386/asm.h deleted file mode 100644 index f1981791a3..0000000000 --- a/c/src/exec/score/cpu/i386/asm.h +++ /dev/null @@ -1,138 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __i386_ASM_h -#define __i386_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/i386.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* - * Looks like there is a bug in gcc 2.6.2 where this is not - * defined correctly when configured as i386-coff and - * i386-aout. - */ - -#undef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ % - -/* -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif -*/ - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -#define eax REG (eax) -#define ebx REG (ebx) -#define ecx REG (ecx) -#define edx REG (edx) -#define esi REG (esi) -#define edi REG (edi) -#define esp REG (esp) -#define ebp REG (ebp) -#define cr0 REG (cr0) - -#define ax REG (ax) -#define bx REG (bx) -#define cx REG (cx) -#define dx REG (dx) -#define si REG (si) -#define di REG (di) -#define sp REG (sp) -#define bp REG (bp) - -#define ah REG (ah) -#define bh REG (bh) -#define ch REG (ch) -#define dh REG (dh) - -#define al REG (al) -#define bl REG (bl) -#define cl REG (cl) -#define dl REG (dl) - -#define cs REG (cs) -#define ds REG (ds) -#define es REG (es) -#define fs REG (fs) -#define gs REG (gs) -#define ss REG (ss) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/i386/configure.ac b/c/src/exec/score/cpu/i386/configure.ac deleted file mode 100644 index ce9ddef33e..0000000000 --- a/c/src/exec/score/cpu/i386/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-i386],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/i386/cpu.c b/c/src/exec/score/cpu/i386/cpu.c deleted file mode 100644 index b55be879ab..0000000000 --- a/c/src/exec/score/cpu/i386/cpu.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Intel i386 Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems.h> -#include <rtems/system.h> -#include <rtems/score/types.h> -#include <rtems/score/isr.h> -#include <rtems/score/idtr.h> - -#include <rtems/bspIo.h> -#include <rtems/score/thread.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ -#if CPU_HARDWARE_FP - register unsigned16 fp_status asm ("ax"); - register void *fp_context; -#endif - - _CPU_Table = *cpu_table; - - /* - * The following code saves a NULL i387 context which is given - * to each task at start and restart time. The following code - * is based upon that provided in the i386 Programmer's - * Manual and should work on any coprocessor greater than - * the i80287. - * - * NOTE: The NO WAIT form of the coprocessor instructions - * MUST be used in case there is not a coprocessor - * to wait for. - */ - -#if CPU_HARDWARE_FP - fp_status = 0xa5a5; - asm volatile( "fninit" ); - asm volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) ); - - if ( fp_status == 0 ) { - - fp_context = &_CPU_Null_fp_context; - - asm volatile( "fsave (%0)" : "=r" (fp_context) - : "0" (fp_context) - ); - } -#endif - -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level; - - i386_get_interrupt_level( level ); - - return level; -} - -void _CPU_Thread_Idle_body () -{ - while(1){ - asm volatile ("hlt"); - } -} - -void _defaultExcHandler (CPU_Exception_frame *ctx) -{ - unsigned int faultAddr = 0; - printk("----------------------------------------------------------\n"); - printk("Exception %d caught at PC %x by thread %d\n", - ctx->idtIndex, - ctx->eip, - _Thread_Executing->Object.id); - printk("----------------------------------------------------------\n"); - printk("Processor execution context at time of the fault was :\n"); - printk("----------------------------------------------------------\n"); - printk(" EAX = %x EBX = %x ECX = %x EDX = %x\n", - ctx->eax, ctx->ebx, ctx->ecx, ctx->edx); - printk(" ESI = %x EDI = %x EBP = %x ESP = %x\n", - ctx->esi, ctx->edi, ctx->ebp, ctx->esp0); - printk("----------------------------------------------------------\n"); - printk("Error code pushed by processor itself (if not 0) = %x\n", - ctx->faultCode); - printk("----------------------------------------------------------\n"); - if (ctx->idtIndex == I386_EXCEPTION_PAGE_FAULT){ - faultAddr = i386_get_cr2(); - printk("Page fault linear address (CR2) = %x\n", faultAddr); - printk("----------------------------------------------------------\n\n"); - } - if (_ISR_Nest_level > 0) { - /* - * In this case we shall not delete the task interrupted as - * it has nothing to do with the fault. We cannot return either - * because the eip points to the faulty instruction so... - */ - printk("Exception while executing ISR!!!. System locked\n"); - _CPU_Fatal_halt(faultAddr); - } - else { - /* - * OK I could probably use a simplified version but at least this - * should work. - */ - printk(" ************ FAULTY THREAD WILL BE DELETED **************\n"); - rtems_task_delete(_Thread_Executing->Object.id); - } -} - -cpuExcHandlerType _currentExcHandler = _defaultExcHandler; - -extern void rtems_exception_prologue_0(); -extern void rtems_exception_prologue_1(); -extern void rtems_exception_prologue_2(); -extern void rtems_exception_prologue_3(); -extern void rtems_exception_prologue_4(); -extern void rtems_exception_prologue_5(); -extern void rtems_exception_prologue_6(); -extern void rtems_exception_prologue_7(); -extern void rtems_exception_prologue_8(); -extern void rtems_exception_prologue_9(); -extern void rtems_exception_prologue_10(); -extern void rtems_exception_prologue_11(); -extern void rtems_exception_prologue_12(); -extern void rtems_exception_prologue_13(); -extern void rtems_exception_prologue_14(); -extern void rtems_exception_prologue_16(); -extern void rtems_exception_prologue_17(); -extern void rtems_exception_prologue_18(); - -static rtems_raw_irq_hdl tbl[] = { - rtems_exception_prologue_0, - rtems_exception_prologue_1, - rtems_exception_prologue_2, - rtems_exception_prologue_3, - rtems_exception_prologue_4, - rtems_exception_prologue_5, - rtems_exception_prologue_6, - rtems_exception_prologue_7, - rtems_exception_prologue_8, - rtems_exception_prologue_9, - rtems_exception_prologue_10, - rtems_exception_prologue_11, - rtems_exception_prologue_12, - rtems_exception_prologue_13, - rtems_exception_prologue_14, - rtems_exception_prologue_16, - rtems_exception_prologue_17, - rtems_exception_prologue_18, -}; - -void rtems_exception_init_mngt() -{ - unsigned int i,j; - interrupt_gate_descriptor *currentIdtEntry; - unsigned limit; - unsigned level; - - i = sizeof(tbl) / sizeof (rtems_raw_irq_hdl); - - i386_get_info_from_IDTR (¤tIdtEntry, &limit); - - _CPU_ISR_Disable(level); - for (j = 0; j < i; j++) { - create_interrupt_gate_descriptor (¤tIdtEntry[j], tbl[j]); - } - _CPU_ISR_Enable(level); -} - diff --git a/c/src/exec/score/cpu/i386/cpu_asm.S b/c/src/exec/score/cpu/i386/cpu_asm.S deleted file mode 100644 index 85316e357a..0000000000 --- a/c/src/exec/score/cpu/i386/cpu_asm.S +++ /dev/null @@ -1,274 +0,0 @@ -/* cpu_asm.s - * - * This file contains all assembly code for the Intel i386 implementation - * of RTEMS. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <asm.h> - -/* - * Format of i386 Register structure - */ - -.set REG_EFLAGS, 0 -.set REG_ESP, REG_EFLAGS + 4 -.set REG_EBP, REG_ESP + 4 -.set REG_EBX, REG_EBP + 4 -.set REG_ESI, REG_EBX + 4 -.set REG_EDI, REG_ESI + 4 -.set SIZE_REGS, REG_EDI + 4 - - BEGIN_CODE - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * - * This routine performs a normal non-FP context. - */ - - .p2align 1 - PUBLIC (_CPU_Context_switch) - -.set RUNCONTEXT_ARG, 4 # save context argument -.set HEIRCONTEXT_ARG, 8 # restore context argument - -SYM (_CPU_Context_switch): - movl RUNCONTEXT_ARG(esp),eax # eax = running threads context - pushf # push eflags - popl REG_EFLAGS(eax) # save eflags - movl esp,REG_ESP(eax) # save stack pointer - movl ebp,REG_EBP(eax) # save base pointer - movl ebx,REG_EBX(eax) # save ebx - movl esi,REG_ESI(eax) # save source register - movl edi,REG_EDI(eax) # save destination register - - movl HEIRCONTEXT_ARG(esp),eax # eax = heir threads context - -restore: - pushl REG_EFLAGS(eax) # push eflags - popf # restore eflags - movl REG_ESP(eax),esp # restore stack pointer - movl REG_EBP(eax),ebp # restore base pointer - movl REG_EBX(eax),ebx # restore ebx - movl REG_ESI(eax),esi # restore source register - movl REG_EDI(eax),edi # restore destination register - ret - -/* - * NOTE: May be unnecessary to reload some registers. - */ - -/* - * void _CPU_Context_restore( new_context ) - * - * This routine performs a normal non-FP context. - */ - - PUBLIC (_CPU_Context_restore) - -.set NEWCONTEXT_ARG, 4 # context to restore argument - -SYM (_CPU_Context_restore): - - movl NEWCONTEXT_ARG(esp),eax # eax = running threads context - jmp restore - -/*PAGE - * void _CPU_Context_save_fp_context( &fp_context_ptr ) - * void _CPU_Context_restore_fp_context( &fp_context_ptr ) - * - * This section is used to context switch an i80287, i80387, - * the built-in coprocessor or the i80486 or compatible. - */ - -.set FPCONTEXT_ARG, 4 # FP context argument - - .p2align 1 - PUBLIC (_CPU_Context_save_fp) -SYM (_CPU_Context_save_fp): - movl FPCONTEXT_ARG(esp),eax # eax = &ptr to FP context area - movl (eax),eax # eax = FP context area - fsave (eax) # save FP context - ret - - .p2align 1 - PUBLIC (_CPU_Context_restore_fp) -SYM (_CPU_Context_restore_fp): - movl FPCONTEXT_ARG(esp),eax # eax = &ptr to FP context area - movl (eax),eax # eax = FP context area - frstor (eax) # restore FP context - ret - - PUBLIC (_Exception_Handler) -SYM (_Exception_Handler): - pusha # Push general purpose registers - pushl esp # Push exception frame address - movl _currentExcHandler, eax # Call function storead in _currentExcHandler - call * eax - addl $4, esp - popa # restore general purpose registers - addl $8, esp # skill vector number and faultCode - iret - -#define DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY(_vector) \ - .p2align 4 ; \ - PUBLIC (rtems_exception_prologue_ ## _vector ) ; \ -SYM (rtems_exception_prologue_ ## _vector ): \ - pushl $ _vector ; \ - jmp SYM (_Exception_Handler) ; - -#define DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY(_vector) \ - .p2align 4 ; \ - PUBLIC (rtems_exception_prologue_ ## _vector ) ; \ -SYM (rtems_exception_prologue_ ## _vector ): \ - pushl $ 0 ; \ - pushl $ _vector ; \ - jmp SYM (_Exception_Handler) ; - -/* - * Divide Error - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (0) -/* - * Debug Exception - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (1) -/* - * NMI - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (2) -/* - * Breakpoint - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (3) -/* - * Overflow - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (4) -/* - * Bound Range Exceeded - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (5) -/* - * Invalid Opcode - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (6) -/* - * No Math Coproc - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (7) -/* - * Double Fault - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (8) -/* - * Coprocessor segment overrun - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (9) -/* - * Invalid TSS - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (10) -/* - * Segment Not Present - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (11) -/* - * Stack segment Fault - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (12) -/* - * General Protection Fault - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (13) -/* - * Page Fault - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (14) -/* - * Floating point error (NB 15 is reserved it is therefor skipped) - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (16) -/* - * Aligment Check - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (17) -/* - * Machine Check - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (18) - - -/* - * void *i386_Logical_to_physical( - * rtems_unsigned16 segment, - * void *address - * ); - * - * Returns thirty-two bit physical address for segment:address. - */ - -.set SEGMENT_ARG, 4 -.set ADDRESS_ARG, 8 - - PUBLIC (i386_Logical_to_physical) - -SYM (i386_Logical_to_physical): - - xorl eax,eax # clear eax - movzwl SEGMENT_ARG(esp),ecx # ecx = segment value - movl $ SYM (_Global_descriptor_table),edx - # edx = address of our GDT - addl ecx,edx # edx = address of desired entry - movb 7(edx),ah # ah = base 31:24 - movb 4(edx),al # al = base 23:16 - shll $16,eax # move ax into correct bits - movw 2(edx),ax # ax = base 0:15 - movl ADDRESS_ARG(esp),ecx # ecx = address to convert - addl eax,ecx # ecx = physical address equivalent - movl ecx,eax # eax = ecx - ret - -/* - * void *i386_Physical_to_logical( - * rtems_unsigned16 segment, - * void *address - * ); - * - * Returns thirty-two bit physical address for segment:address. - */ - -/* - *.set SEGMENT_ARG, 4 - *.set ADDRESS_ARG, 8 -- use sets from above - */ - - PUBLIC (i386_Physical_to_logical) - -SYM (i386_Physical_to_logical): - xorl eax,eax # clear eax - movzwl SEGMENT_ARG(esp),ecx # ecx = segment value - movl $ SYM (_Global_descriptor_table),edx - # edx = address of our GDT - addl ecx,edx # edx = address of desired entry - movb 7(edx),ah # ah = base 31:24 - movb 4(edx),al # al = base 23:16 - shll $16,eax # move ax into correct bits - movw 2(edx),ax # ax = base 0:15 - movl ADDRESS_ARG(esp),ecx # ecx = address to convert - subl eax,ecx # ecx = logical address equivalent - movl ecx,eax # eax = ecx - ret - -END_CODE - -END diff --git a/c/src/exec/score/cpu/i386/rtems/.cvsignore b/c/src/exec/score/cpu/i386/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/i386/rtems/score/.cvsignore b/c/src/exec/score/cpu/i386/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/i386/rtems/score/cpu.h b/c/src/exec/score/cpu/i386/rtems/score/cpu.h deleted file mode 100644 index a6ea2c7628..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/cpu.h +++ /dev/null @@ -1,513 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the Intel - * i386 processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/i386.h> /* pick up machine definitions */ - -#ifndef ASM -#include <rtems/score/types.h> -#include <rtems/score/interrupts.h> /* formerly in libcpu/cpu.h> */ -#include <rtems/score/registers.h> /* formerly part of libcpu */ -#endif - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE -#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE - -/* - * i386 has an RTEMS allocated and managed interrupt stack. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Some family members have no FP, some have an FPU such as the i387 - * for the i386, others have it built in (i486DX, Pentium). - */ - -#if ( I386_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE /* i387 for i386 */ -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_STACK_GROWS_UP FALSE -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE - -/* structures */ - -/* - * Basic integer context for the i386 family. - */ - -typedef struct { - unsigned32 eflags; /* extended flags register */ - void *esp; /* extended stack pointer register */ - void *ebp; /* extended base pointer register */ - unsigned32 ebx; /* extended bx register */ - unsigned32 esi; /* extended source index register */ - unsigned32 edi; /* extended destination index flags register */ -} Context_Control; - -/* - * FP context save area for the i387 numeric coprocessors. - */ - -typedef struct { - unsigned8 fp_save_area[108]; /* context size area for I80387 */ - /* 28 bytes for environment */ -} Context_Control_fp; - - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of execptions. - * - * idtIndex is either the interrupt number or the trap/exception number. - * faultCode is the code pushed by the processor on some exceptions. - */ - -typedef struct { - unsigned32 edi; - unsigned32 esi; - unsigned32 ebp; - unsigned32 esp0; - unsigned32 ebx; - unsigned32 edx; - unsigned32 ecx; - unsigned32 eax; - unsigned32 idtIndex; - unsigned32 faultCode; - unsigned32 eip; - unsigned32 cs; - unsigned32 eflags; -} CPU_Exception_frame; - -typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); -extern cpuExcHandlerType _currentExcHandler; -extern void rtems_exception_init_mngt(); - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt - * that will lead to re-enter the kernel to signal the thread. - */ - -typedef CPU_Exception_frame CPU_Interrupt_frame; - -typedef enum { - I386_EXCEPTION_DIVIDE_BY_ZERO = 0, - I386_EXCEPTION_DEBUG = 1, - I386_EXCEPTION_NMI = 2, - I386_EXCEPTION_BREAKPOINT = 3, - I386_EXCEPTION_OVERFLOW = 4, - I386_EXCEPTION_BOUND = 5, - I386_EXCEPTION_ILLEGAL_INSTR = 6, - I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, - I386_EXCEPTION_DOUBLE_FAULT = 8, - I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, - I386_EXCEPTION_INVALID_TSS = 10, - I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, - I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, - I386_EXCEPTION_GENERAL_PROT_ERR = 13, - I386_EXCEPTION_PAGE_FAULT = 14, - I386_EXCEPTION_INTEL_RES15 = 15, - I386_EXCEPTION_FLOAT_ERROR = 16, - I386_EXCEPTION_ALIGN_CHECK = 17, - I386_EXCEPTION_MACHINE_CHECK = 18, - I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ - -} Intel_symbolic_exception_name; - - -/* - * The following table contains the information required to configure - * the i386 specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - - unsigned32 interrupt_table_segment; - void *interrupt_table_offset; -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access i386 specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_interrupt_table_segment() \ - (_CPU_Table.interrupt_table_segment) - -#define rtems_cpu_configuration_get_interrupt_table_offset() \ - (_CPU_Table.interrupt_table_offset) - -/* - * context size area for floating point - * - * NOTE: This is out of place on the i386 to avoid a forward reference. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* variables */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * i386 family supports 256 distinct vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - */ - -#define CPU_STACK_MINIMUM_SIZE 1024 - -/* - * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. - */ - -#define CPU_ALIGNMENT 4 -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * On i386 thread stacks require no further alignment after allocation - * from the Workspace. - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_Initialize_vectors() - -#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) - -#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) - -#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if ( _new_level ) asm volatile ( "cli" ); \ - else asm volatile ( "sti" ); \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 -#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - do { \ - unsigned32 _stack; \ - \ - if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \ - else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \ - \ - _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \ - \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - (_the_context)->ebp = (void *) _stack; \ - (_the_context)->esp = (void *) _stack; \ - } while (0) - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - unsigned32 *_source = (unsigned32 *) &_CPU_Null_fp_context; \ - unsigned32 *_destination = *(_fp_area); \ - unsigned32 _index; \ - \ - for ( _index=0 ; _index < CPU_CONTEXT_FP_SIZE/4 ; _index++ ) \ - *_destination++ = *_source++; \ - } - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#define _CPU_Fatal_halt( _error ) \ - { \ - asm volatile ( "cli ; \ - movl %0,%%eax ; \ - hlt" \ - : "=r" ((_error)) : "0" ((_error)) \ - ); \ - } - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register unsigned16 __value_in_register = (_value); \ - \ - _output = 0; \ - \ - asm volatile ( "bsfw %0,%1 " \ - : "=r" (__value_in_register), "=r" (_output) \ - : "0" (__value_in_register), "1" (_output) \ - ); \ - } - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Thread_Idle_body - * - * Use the halt instruction of low power mode of a particular i386 model. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -void _CPU_Thread_Idle_body( void ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i386/rtems/score/i386.h b/c/src/exec/score/cpu/i386/rtems/score/i386.h deleted file mode 100644 index 9d317f7843..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/i386.h +++ /dev/null @@ -1,244 +0,0 @@ -/* i386.h - * - * This include file contains information pertaining to the Intel - * i386 processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __i386_h -#define __i386_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section contains the information required to build - * RTEMS for a particular member of the Intel i386 - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * Currently recognized: - * i386_fp (i386 DX or SX w/i387) - * i386_nofp (i386 DX or SX w/o i387) - * i486dx - * i486sx - * pentium - * pentiumpro - * - * CPU Model Feature Flags: - * - * I386_HAS_BSWAP: Defined to "1" if the instruction for endian swapping - * (bswap) should be used. This instruction appears to - * be present in all i486's and above. - * - * I386_HAS_FPU: Defined to "1" if the CPU has an FPU. - * - */ - -#if defined(_SOFT_FLOAT) -#define I386_HAS_FPU 0 -#else -#define I386_HAS_FPU 1 -#endif - -#if defined(__pentiumpro__) - -#define CPU_MODEL_NAME "Pentium Pro" - -#elif defined(__i586__) - -# if defined(__pentium__) -# define CPU_MODEL_NAME "Pentium" -# elif defined(__k6__) -# define CPU_MODEL_NAME "K6" -# else -# define CPU_MODEL_NAME "i586" -# endif - -#elif defined(__i486__) - -# if !defined(_SOFT_FLOAT) -# define CPU_MODEL_NAME "i486dx" -# else -# define CPU_MODEL_NAME "i486sx" -# endif - -#elif defined(__i386__) - -#define I386_HAS_BSWAP 0 - -# if !defined(_SOFT_FLOAT) -# define CPU_MODEL_NAME "i386 with i387" -# else -# define CPU_MODEL_NAME "i386 w/o i387" -# endif - -#else -#error "Unknown CPU Model" -#endif - -/* - * Set default values for CPU model feature flags - * - * NOTE: These settings are chosen to reflect most of the family members. - */ - -#ifndef I386_HAS_FPU -#define I386_HAS_FPU 1 -#endif - -#ifndef I386_HAS_BSWAP -#define I386_HAS_BSWAP 1 -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Intel i386" - -#ifndef ASM - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static so it can be referenced indirectly. - */ - -static inline unsigned int i386_swap_U32( - unsigned int value -) -{ - unsigned long lout; - -#if (I386_HAS_BSWAP == 0) - asm volatile( "rorw $8,%%ax;" - "rorl $16,%0;" - "rorw $8,%%ax" : "=a" (lout) : "0" (value) ); -#else - __asm__ volatile( "bswap %0" : "=r" (lout) : "0" (value)); -#endif - return( lout ); -} - -static inline unsigned int i386_swap_U16( - unsigned int value -) -{ - unsigned short sout; - - __asm__ volatile( "rorw $8,%0" : "=r" (sout) : "0" (value)); - return (sout); -} - - -/* - * Added for pagination management - */ - -static inline unsigned int i386_get_cr0() -{ - register unsigned int segment = 0; - - asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline void i386_set_cr0(unsigned int segment) -{ - asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) ); -} - -static inline unsigned int i386_get_cr2() -{ - register unsigned int segment = 0; - - asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline unsigned int i386_get_cr3() -{ - register unsigned int segment = 0; - - asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline void i386_set_cr3(unsigned int segment) -{ - asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) ); -} - -/* routines */ - -/* - * i386_Logical_to_physical - * - * Converts logical address to physical address. - */ - -void *i386_Logical_to_physical( - unsigned short segment, - void *address -); - -/* - * i386_Physical_to_logical - * - * Converts physical address to logical address. - */ - -void *i386_Physical_to_logical( - unsigned short segment, - void *address -); - - -/* - * "Simpler" names for a lot of the things defined in this file - */ - -/* segment access routines */ - -#define get_cs() i386_get_cs() -#define get_ds() i386_get_ds() -#define get_es() i386_get_es() -#define get_ss() i386_get_ss() -#define get_fs() i386_get_fs() -#define get_gs() i386_get_gs() - -#define CPU_swap_u32( _value ) i386_swap_U32( _value ) -#define CPU_swap_u16( _value ) i386_swap_U16( _value ) - -/* i80x86 I/O instructions */ - -#define outport_byte( _port, _value ) i386_outport_byte( _port, _value ) -#define outport_word( _port, _value ) i386_outport_word( _port, _value ) -#define outport_long( _port, _value ) i386_outport_long( _port, _value ) -#define inport_byte( _port, _value ) i386_inport_byte( _port, _value ) -#define inport_word( _port, _value ) i386_inport_word( _port, _value ) -#define inport_long( _port, _value ) i386_inport_long( _port, _value ) - - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i386/rtems/score/idtr.h b/c/src/exec/score/cpu/i386/rtems/score/idtr.h deleted file mode 100644 index 7c4f95214f..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/idtr.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file contains definitions for data structure related - * to Intel system programming. More information can be found - * on Intel site and more precisely in the following book : - * - * Pentium Processor familly - * Developper's Manual - * - * Volume 3 : Architecture and Programming Manual - * - * Formerly contained in and extracted from libcpu/i386/cpu.h. - * - * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - * Applications must not include this file directly. - */ - -#ifndef _rtems_score_idtr_h -#define _rtems_score_idtr_h - -/* - * See page 14.9 Figure 14-2. - * - */ -typedef struct -{ - unsigned int low_offsets_bits:16; - unsigned int segment_selector:16; - unsigned int fixed_value_bits:8; - unsigned int gate_type:5; - unsigned int privilege:2; - unsigned int present:1; - unsigned int high_offsets_bits:16; -} interrupt_gate_descriptor; - -/* - * C callable function enabling to create a interrupt_gate_descriptor - */ -extern void create_interrupt_gate_descriptor (interrupt_gate_descriptor*, rtems_raw_irq_hdl); - -/* - * C callable function enabling to get easily usable info from - * the actual value of IDT register. - */ -extern void i386_get_info_from_IDTR (interrupt_gate_descriptor** table, - unsigned* limit); - -/* - * C callable function enabling to change the value of IDT register. Must be called - * with interrupts masked at processor level!!!. - */ -extern void i386_set_IDTR (interrupt_gate_descriptor* table, - unsigned limit); - -#endif diff --git a/c/src/exec/score/cpu/i386/rtems/score/interrupts.h b/c/src/exec/score/cpu/i386/rtems/score/interrupts.h deleted file mode 100644 index bcc1dfb85a..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/interrupts.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * i386 interrupt macros. - * - * Formerly contained in and extracted from libcpu/i386/cpu.h - * - * COPYRIGHT (c) 1998 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - * Applications must not include this file directly. - */ - -#ifndef _rtems_score_interrupts_h -#define _rtems_score_interrupts_h - -#ifndef ASM - -struct __rtems_raw_irq_connect_data__; - -typedef void (*rtems_raw_irq_hdl) (void); -typedef void (*rtems_raw_irq_enable) (const struct __rtems_raw_irq_connect_data__*); -typedef void (*rtems_raw_irq_disable) (const struct __rtems_raw_irq_connect_data__*); -typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_data__*); - -/* - * Interrupt Level Macros - */ - -#define i386_disable_interrupts( _level ) \ - { \ - asm volatile ( "pushf ; \ - cli ; \ - pop %0" \ - : "=rm" ((_level)) \ - ); \ - } - -#define i386_enable_interrupts( _level ) \ - { \ - asm volatile ( "push %0 ; \ - popf" \ - : : "rm" ((_level)) : "cc" \ - ); \ - } - -#define i386_flash_interrupts( _level ) \ - { \ - asm volatile ( "push %0 ; \ - popf ; \ - cli" \ - : : "rm" ((_level)) : "cc" \ - ); \ - } - -#define i386_get_interrupt_level( _level ) \ - do { \ - register unsigned32 _eflags; \ - \ - asm volatile ( "pushf ; \ - pop %0" \ - : "=rm" ((_eflags)) \ - ); \ - \ - _level = (_eflags & EFLAGS_INTR_ENABLE) ? 0 : 1; \ - } while (0) - -#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) -#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) - -#endif -#endif diff --git a/c/src/exec/score/cpu/i386/rtems/score/registers.h b/c/src/exec/score/cpu/i386/rtems/score/registers.h deleted file mode 100644 index 993b7fb834..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/registers.h +++ /dev/null @@ -1,184 +0,0 @@ -/* registers.h - * - * This file contains definition and constants related to Intel Cpu - * - * COPYRIGHT (c) 1998 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef _rtems_score_registers_h -#define _rtems_score_registers_h - -/* - * definition related to EFLAGS - */ -#define EFLAGS_CARRY 0x1 -#define EFLAGS_PARITY 0x4 - -#define EFLAGS_AUX_CARRY 0x10 -#define EFLAGS_ZERO 0x40 -#define EFLAGS_SIGN 0x80 - -#define EFLAGS_TRAP 0x100 -#define EFLAGS_INTR_ENABLE 0x200 -#define EFLAGS_DIRECTION 0x400 -#define EFLAGS_OVERFLOW 0x800 - -#define EFLAGS_IOPL_MASK 0x3000 -#define EFLAGS_NESTED_TASK 0x8000 - -#define EFLAGS_RESUME 0x10000 -#define EFLAGS_VIRTUAL_MODE 0x20000 -#define EFLAGS_ALIGN_CHECK 0x40000 -#define EFLAGS_VIRTUAL_INTR 0x80000 - -#define EFLAGS_VIRTUAL_INTR_PEND 0x100000 -#define EFLAGS_ID 0x200000 - -/* - * definitions related to CR0 - */ -#define CR0_PROTECTION_ENABLE 0x1 -#define CR0_MONITOR_COPROC 0x2 -#define CR0_COPROC_SOFT_EMUL 0x4 -#define CR0_FLOATING_INSTR_EXCEPTION 0x8 - -#define CR0_EXTENSION_TYPE 0x10 -#define CR0_NUMERIC_ERROR 0x20 - -#define CR0_WRITE_PROTECT 0x10000 -#define CR0_ALIGMENT_MASK 0x40000 - -#define CR0_NO_WRITE_THROUGH 0x20000000 -#define CR0_PAGE_LEVEL_CACHE_DISABLE 0x40000000 -#define CR0_PAGING 0x80000000 - -/* - * definitions related to CR3 - */ - -#define CR3_PAGE_CACHE_DISABLE 0x10 -#define CR3_PAGE_WRITE_THROUGH 0x8 - - -#ifndef ASM - -/* - * definition of eflags registers has a bit field structure - */ -typedef struct { - /* - * fist byte : bits 0->7 - */ - unsigned int carry : 1; - unsigned int : 1; - unsigned int parity : 1; - unsigned int : 1; - - unsigned int auxiliary_carry : 1; - unsigned int : 1; - unsigned int zero : 1; /* result is zero */ - unsigned int sign : 1; /* result is less than zero */ - /* - * Second byte : bits 7->15 - */ - unsigned int trap : 1; - unsigned int intr_enable : 1; /* set => intr on */ - unsigned int direction : 1; /* set => autodecrement */ - unsigned int overflow : 1; - - unsigned int IO_privilege : 2; - unsigned int nested_task : 1; - unsigned int : 1; - /* - * Third byte : bits 15->23 - */ - unsigned int resume : 1; - unsigned int virtual_mode : 1; - unsigned int aligment_check : 1; - unsigned int virtual_intr : 1; - - unsigned int virtual_intr_pending : 1; - unsigned int id : 1; - unsigned int : 2; - - /* - * fourth byte : bits 24->31 : UNUSED - */ - unsigned int : 8; -}eflags_bits; - -typedef union { - eflags_bits eflags; - unsigned int i; -}eflags; -/* - * definition of eflags registers has a bit field structure - */ -typedef struct { - /* - * fist byte : bits 0->7 - */ - unsigned int protection_enable : 1; - unsigned int monitor_coproc : 1; - unsigned int coproc_soft_emul : 1; - unsigned int floating_instr_except : 1; - - unsigned int extension_type : 1; - unsigned int numeric_error : 1; - unsigned int : 2; - /* - * second byte 8->15 : UNUSED - */ - unsigned int : 8; - /* - * third byte 16->23 - */ - unsigned int write_protect : 1; - unsigned int : 1; - unsigned int aligment_mask : 1; - unsigned int : 1; - - unsigned int : 4; - /* - * fourth byte 24->31 - */ - unsigned int : 4; - - unsigned int : 1; - unsigned int no_write_through : 1; - unsigned int page_level_cache_disable : 1; - unsigned int paging : 1; -}cr0_bits; - -typedef union { - cr0_bits cr0; - unsigned int i; -}cr0; - -/* - * definition of cr3 registers has a bit field structure - */ -typedef struct { - - unsigned int : 3; - unsigned int page_write_transparent : 1; - unsigned int page_cache_disable : 1; - unsigned int : 7; - unsigned int page_directory_base :20; -}cr3_bits; - -typedef union { - cr3_bits cr3; - unsigned int i; -}cr3; - -#endif - -#endif - diff --git a/c/src/exec/score/cpu/i386/rtems/score/types.h b/c/src/exec/score/cpu/i386/rtems/score/types.h deleted file mode 100644 index 1b9091f501..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/* i386types.h - * - * This include file contains type definitions pertaining to the Intel - * i386 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __i386_TYPES_h -#define __i386_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void i386_isr; - -typedef i386_isr ( *i386_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i960/.cvsignore b/c/src/exec/score/cpu/i960/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/i960/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/i960/ChangeLog b/c/src/exec/score/cpu/i960/ChangeLog deleted file mode 100644 index 61e394c060..0000000000 --- a/c/src/exec/score/cpu/i960/ChangeLog +++ /dev/null @@ -1,113 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/m68ktypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/i960types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/i960/Makefile.am b/c/src/exec/score/cpu/i960/Makefile.am deleted file mode 100644 index 4a60795a5e..0000000000 --- a/c/src/exec/score/cpu/i960/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/i960.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S i960RP.h - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/i960/asm.h b/c/src/exec/score/cpu/i960/asm.h deleted file mode 100644 index e98f900f59..0000000000 --- a/c/src/exec/score/cpu/i960/asm.h +++ /dev/null @@ -1,110 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __i960_ASM_h -#define __i960_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/i960.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -#define g0 REG (g0) -#define g1 REG (g1) -#define g2 REG (g2) -#define g3 REG (g3) -#define g4 REG (g4) -#define g5 REG (g5) -#define g6 REG (g6) -#define g7 REG (g7) -#define g8 REG (g8) -#define g9 REG (g9) -#define g10 REG (g10) -#define g11 REG (g11) -#define g12 REG (g12) -#define g13 REG (g13) -#define g14 REG (g14) -#define g15 REG (g15) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i960/configure.ac b/c/src/exec/score/cpu/i960/configure.ac deleted file mode 100644 index 90beb7ec0d..0000000000 --- a/c/src/exec/score/cpu/i960/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-i960],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/i960/cpu.c b/c/src/exec/score/cpu/i960/cpu.c deleted file mode 100644 index 78eeb3c5f2..0000000000 --- a/c/src/exec/score/cpu/i960/cpu.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Intel i960CA Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - * OUTPUT PARAMETERS: NONE - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - - _CPU_Table = *cpu_table; - -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level; - - i960_get_interrupt_level( level ); - - return level; -} - -/*PAGE - * - * _CPU__ISR_install_vector - * - * Install the RTEMS vector wrapper in the CPU's interrupt table. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr ignored; - - *old_handler = _ISR_Vector_table[ vector ]; - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); - - _ISR_Vector_table[ vector ] = new_handler; -} diff --git a/c/src/exec/score/cpu/i960/cpu_asm.S b/c/src/exec/score/cpu/i960/cpu_asm.S deleted file mode 100644 index 82906ad4ff..0000000000 --- a/c/src/exec/score/cpu/i960/cpu_asm.S +++ /dev/null @@ -1,214 +0,0 @@ -/* - * This file contains all assembly code for the i960 port of RTEMS. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - .data -_ISR_reg_save: - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - - .text -/* - * Format of i960ca Register structure - */ - -.set REG_R0_PFP , 0 # (r0) Previous Frame Pointer -.set REG_R1_SP , REG_R0_PFP+4 # (r1) Stack Pointer -.set REG_PC , REG_R1_SP+4 # (pc) Processor Controls -.set REG_G8 , REG_PC+4 # (g8) Global Register 8 -.set REG_G9 , REG_G8+4 # (g9) Global Register 9 -.set REG_G10 , REG_G9+4 # (g10) Global Register 10 -.set REG_G11 , REG_G10+4 # (g11) Global Register 11 -.set REG_G12 , REG_G11+4 # (g12) Global Register 12 -.set REG_G13 , REG_G12+4 # (g13) Global Register 13 -.set REG_G14 , REG_G13+4 # (g14) Global Register 14 -.set REG_G15_FP , REG_G14+4 # (g15) Global Register 15 -.set SIZE_REGS , REG_G15_FP+4 # size of cpu_context_registers - # structure - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * - * This routine performs a normal non-FP context. - */ - .align 4 - .globl __CPU_Context_switch - -__CPU_Context_switch: - modpc 0,0,g2 # get old intr level (PC) - st g2,REG_PC(g0) # save pc - stq g8,REG_G8(g0) # save g8-g11 - stq g12,REG_G12(g0) # save g12-g15 - stl pfp,REG_R0_PFP(g0) # save pfp, sp - -restore: flushreg # flush register cache - ldconst 0x001f0000,g2 # g2 = PC mask - ld REG_PC(g1),g3 # thread->Regs.pc = pc; - ldq REG_G12(g1),g12 # restore g12-g15 - ldl REG_R0_PFP(g1),pfp # restore pfp, sp - ldq REG_G8(g1),g8 # restore g8-g11 - modpc 0,g2,g3 # restore PC register - ret - -/* - * void _CPU_Context_restore( new_context ) - * - * This routine performs a normal non-FP context. - */ - - .globl __CPU_Context_restore -__CPU_Context_restore: - mov g0,g1 # g0 = _Thread_executing - b restore - -/*PAGE - * void _CPU_Context_save_fp_context( &fp_context_ptr ) - * void _CPU_Context_restore_fp_context( &fp_context_ptr ) - * - * There is currently no hardware floating point for the i960. - */ - - .globl __CPU_Context_save_fp - .globl __CPU_Context_restore_fp -__CPU_Context_save_fp: -__CPU_Context_restore_fp: -#if ( I960_HAS_FPU == 1 ) -#error "Floating point support for i960 family has been implemented!!!" -#endif - ret - -/*PAGE - * void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * NOTE: - * Upon entry, the supervisor stack will contain a stack frame - * back to the interrupted thread and the interrupt stack will contain - * an interrupt stack frame. If dispatching is enabled, this - * is the outer most interrupt, and (a context switch is necessary or - * the current thread has signals), then set up the supervisor stack to - * transfer control to the interrupt dispatcher. - */ - - .globl __ISR_Handler -__ISR_Handler: - #ldconst 1,r8 - #modpc 0,r8,r8 # enable tracing - - # r4 = &_Thread_Dispatch_disable_level - ld __Thread_Dispatch_disable_level,r4 - movl g0,r8 # save g0-g1 - - ld -16+8(fp),g0 # g0 = vector number - movl g2,r10 # save g2-g3 - - ld __ISR_Nest_level,r5 # r5 = &_Isr_nest_level - mov g14,r7 # save g14 - - lda 0,g14 # NOT Branch and Link - movl g4,r12 # save g4-g5 - - lda 1(r4),r4 # increment dispatch disable level - movl g6,r14 # save g6-g7 - - ld __ISR_Vector_table,g1 # g1 = base of vector table - - stq g8, _ISR_reg_save # save g8-g11 - stl g12, _ISR_reg_save+16 # save g12-g13 - - ld (g1)[g0*4],g1 # g1 = Users handler - addo 1,r5,r5 # increment ISR level - - st r4,__Thread_Dispatch_disable_level - # one ISR nest level deeper - subo 1,r4,r4 # decrement dispatch disable level - - st r5,__ISR_Nest_level # disable multitasking - subo 1,r5,r5 # decrement ISR nest level - - callx (g1) # invoke user ISR - - # unnest multitasking - st r5,__ISR_Nest_level # one less ISR nest level - cmpobne.f 0,r4,exit # If dispatch disabled, exit - ldl -16(fp),g0 # g0 = threads PC reg - # g1 = threads AC reg - ld __Context_Switch_necessary,r6 - # r6 = Is thread switch necessary? - bbs.f 13,g0,exit # not outer level, then exit - cmpobne.f 0,r6,bframe # Switch necessary? - - ld __ISR_Signals_to_thread_executing,g2 - # signals sent to Run_thread - # while in interrupt handler? - cmpobe.f 0,g2,exit # No, then exit - -bframe: mov 0,g2 - st g2,__ISR_Signals_to_thread_executing - - ldconst 0x1f0000,g2 # g2 = intr disable mask - mov g2,g3 # g3 = new intr level - modpc 0,g2,g3 # set new level - - andnot 7,pfp,r4 # r4 = pfp without ret type - flushreg # flush registers - # push _Isr_dispatch ret frame - # build ISF in r4-r6 - ldconst 64,g2 # g2 = size of stack frame - ld 4(r4),g3 # g3 = previous sp - addo g2,g3,r5 # r5 = _Isr_dispatch SP - lda __ISR_Dispatch,r6 # r6 = _Isr_dispatch entry - stt r4,(g3) # set _Isr_dispatch ret info - st g1,16(g3) # set r4 = AC for ISR disp - or 7,g3,pfp # pfp to _Isr_dispatch - flushreg - b exit1 -exit: st r4,__Thread_Dispatch_disable_level -exit1: mov r7,g14 # restore g14 - movq r8,g0 # restore g0-g3 - movq r12,g4 # restore g4-g7 - ldq _ISR_reg_save, g8 # restore g8-g11 - ldl _ISR_reg_save+16, g12 # restore g12-g13 - ret - - -/*PAGE - * - * void __ISR_Dispatch() - * - * Entry point from the outermost interrupt service routine exit. - * The current stack is the supervisor mode stack. - */ - - .globl __ISR_Dispatch -__ISR_Dispatch: - mov g14,r7 - mov 0,g14 - movq g0,r8 - movq g4,r12 - call __Thread_Dispatch - - ldconst -1,r5 # r5 = reload mask - modac r5,r4,r4 # restore threads AC register - mov r7,g14 - movq r8,g0 - movq r12,g4 - ret - diff --git a/c/src/exec/score/cpu/i960/rtems/.cvsignore b/c/src/exec/score/cpu/i960/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/i960/rtems/score/.cvsignore b/c/src/exec/score/cpu/i960/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/i960/rtems/score/cpu.h b/c/src/exec/score/cpu/i960/rtems/score/cpu.h deleted file mode 100644 index a3251dae3c..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/score/cpu.h +++ /dev/null @@ -1,485 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the Intel - * i960 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/i960.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -#define CPU_INLINE_ENABLE_DISPATCH FALSE -#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE - -/* - * Use the i960's hardware interrupt stack support and have the - * interrupt manager allocate the memory for it. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Some family members have no FP (SA/KA/CA/CF), others have it built in - * (KB/MC/MX). There does not appear to be an external coprocessor - * for this family. - */ - -#if ( I960_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#error "Floating point support for i960 family has been implemented!!!" -#else -#define CPU_HARDWARE_FP FALSE -#endif - -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE -#define CPU_STACK_GROWS_UP TRUE -#define CPU_STRUCTURE_ALIGNMENT /* __attribute__ ((aligned (16))) */ - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - - -/* structures */ - -/* - * Basic integer context for the i960 family. - */ - -typedef struct { - void *r0_pfp; /* (r0) Previous Frame Pointer */ - void *r1_sp; /* (r1) Stack Pointer */ - unsigned32 pc; /* (pc) Processor Control */ - void *g8; /* (g8) Global Register 8 */ - void *g9; /* (g9) Global Register 9 */ - void *g10; /* (g10) Global Register 10 */ - void *g11; /* (g11) Global Register 11 */ - void *g12; /* (g12) Global Register 12 */ - void *g13; /* (g13) Global Register 13 */ - unsigned32 g14; /* (g14) Global Register 14 */ - void *g15_fp; /* (g15) Frame Pointer */ -} Context_Control; - -/* - * FP context save area for the i960 Numeric Extension - */ - -typedef struct { - unsigned32 fp0_1; /* (fp0) first word */ - unsigned32 fp0_2; /* (fp0) second word */ - unsigned32 fp0_3; /* (fp0) third word */ - unsigned32 fp1_1; /* (fp1) first word */ - unsigned32 fp1_2; /* (fp1) second word */ - unsigned32 fp1_3; /* (fp1) third word */ - unsigned32 fp2_1; /* (fp2) first word */ - unsigned32 fp2_2; /* (fp2) second word */ - unsigned32 fp2_3; /* (fp2) third word */ - unsigned32 fp3_1; /* (fp3) first word */ - unsigned32 fp3_2; /* (fp3) second word */ - unsigned32 fp3_3; /* (fp3) third word */ -} Context_Control_fp; - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt. - */ - -typedef struct { - unsigned32 TBD; /* XXX Fix for this CPU */ -} CPU_Interrupt_frame; - -/* - * Call frame for the i960 family. - */ - -typedef struct { - void *r0_pfp; /* (r0) Previous Frame Pointer */ - void *r1_sp; /* (r1) Stack Pointer */ - void *r2_rip; /* (r2) Return Instruction Pointer */ - void *r3; /* (r3) Local Register 3 */ - void *r4; /* (r4) Local Register 4 */ - void *r5; /* (r5) Local Register 5 */ - void *r6; /* (r6) Local Register 6 */ - void *r7; /* (r7) Local Register 7 */ - void *r8; /* (r8) Local Register 8 */ - void *r9; /* (r9) Local Register 9 */ - void *r10; /* (r10) Local Register 10 */ - void *r11; /* (r11) Local Register 11 */ - void *r12; /* (r12) Local Register 12 */ - void *r13; /* (r13) Local Register 13 */ - void *r14; /* (r14) Local Register 14 */ - void *r15; /* (r15) Local Register 15 */ - /* XXX Looks like sometimes there is FP stuff here (MC manual)? */ -} CPU_Call_frame; - -/* - * The following table contains the information required to configure - * the i960 specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access i960 specific additions to the CPU Table - * - * NONE - */ - -/* variables */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x0000001f /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x0000001f /* interrupt level in mode */ - -/* - * context size area for floating point - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE) - -/* - * i960 family supports 256 distinct vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - * - * NOTE: See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK - */ - -#define CPU_STACK_MINIMUM_SIZE 2048 - -/* - * i960 is pretty tolerant of alignment but some CPU models do - * better with different default aligments so we use what the - * CPU model selected in rtems/score/i960.h. - */ - -#define CPU_ALIGNMENT I960_CPU_ALIGNMENT -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * i960ca stack requires 16 byte alignment - * - * NOTE: This factor may need to be family member dependent. - */ - -#define CPU_STACK_ALIGNMENT 16 - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_Initialize_vectors() -#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level ) -#define _CPU_ISR_Enable( _level ) i960_enable_interrupts( _level ) -#define _CPU_ISR_Flash( _level ) i960_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( newlevel ) \ - { \ - unsigned32 _mask = 0; \ - unsigned32 _level = (newlevel); \ - \ - __asm__ volatile ( "ldconst 0x1f0000,%0; \ - modpc 0,%0,%1" : "=d" (_mask), "=d" (_level) \ - : "0" (_mask), "1" (_level) \ - ); \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* ISR handler section macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry, _is_fp ) \ - { CPU_Call_frame *_texit_frame; \ - unsigned32 _mask; \ - unsigned32 _base_pc; \ - unsigned32 _stack_tmp; \ - void *_stack; \ - \ - _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \ - _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ - _stack = (void *) _stack_tmp; \ - \ - __asm__ volatile ( "flushreg" : : ); /* flush register cache */ \ - \ - (_the_context)->r0_pfp = _stack; \ - (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \ - (_the_context)->r1_sp = _stack + (2 * sizeof(CPU_Call_frame)); \ - __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \ - "modpc 0,0,%1 ; " \ - "andnot %0,%1,%1 ; " \ - : "=d" (_mask), "=d" (_base_pc) : ); \ - (_the_context)->pc = _base_pc | ((_isr) << 16); \ - (_the_context)->g14 = 0; \ - \ - _texit_frame = (CPU_Call_frame *)_stack; \ - _texit_frame->r0_pfp = NULL; \ - _texit_frame->r1_sp = (_the_context)->g15_fp; \ - _texit_frame->r2_rip = (_entry); \ - } - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#define _CPU_Context_Fp_start( _base, _offset ) NULL - -#define _CPU_Context_Initialize_fp( _fp_area ) - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#define _CPU_Fatal_halt( _errorcode ) \ - { unsigned32 _mask, _level; \ - unsigned32 _error = (_errorcode); \ - \ - __asm__ volatile ( "ldconst 0x1f0000,%0 ; \ - mov %0,%1 ; \ - modpc 0,%0,%1 ; \ - mov %2,g0 ; \ - self: b self " \ - : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \ - } - -/* end of Fatal Error Manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { unsigned32 _search = (_value); \ - \ - (_output) = 0; /* to prevent warnings */ \ - __asm__ volatile ( "scanbit %0,%1 " \ - : "=d" (_search), "=d" (_output) \ - : "0" (_search), "1" (_output) ); \ - } - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x8000 >> (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - ( 15 - (_priority) ) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i960/rtems/score/i960.h b/c/src/exec/score/cpu/i960/rtems/score/i960.h deleted file mode 100644 index 6cc60af8c9..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/score/i960.h +++ /dev/null @@ -1,194 +0,0 @@ -/* i960.h - * - * This include file contains information pertaining to the Intel - * i960 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __i960_h -#define __i960_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the Intel i960 - * family. It does this by setting variables to indicate - * which implementation dependent features are present - * in a particular member of the family. - * - * NOTE: For now i960 support is for models without an FPU. - * The stubs for FP routines are in place so only need to be filled in. - * - * NOTE: RTEMS defines a canonical name for each cpu model. - */ - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Intel i960" - -/* - * This should work since most i960 models do not have FPUs. The logic is: - * - * + If the user specifically asks for soft-float, give it to them - * regardless of hardware availability. - * + If the CPU has hardware FPU, then use it. - * + Otherwise, we have to use soft float. - */ - -#if defined(_SOFT_FLOAT) -#define I960_HAS_FPU 0 -#elif defined(_i960_KB__) || defined(_i960_SB__) || defined(_i960_SB__) || \ - defined(_i960_JF__) || defined(_i960_MC__) || defined(_i960_CC__) -#define I960_HAS_FPU 1 -#else -#define I960_HAS_FPU 0 -#endif - -/* - * Some of the CPU models may have better performance with - * alignment of 8 or 16 but we don't know what model we are - * being compiled for based solely on the information provided - * when multilibbing. - */ - -#define I960_CPU_ALIGNMENT 4 - -/* - * This is not the perfect CPU model name but it is adequate and - * reflects what we know from multilib. - */ - -#if I960_HAS_FPU -#define CPU_MODEL_NAME "w/FPU" -#else -#define CPU_MODEL_NAME "w/soft-float" -#endif -#ifndef ASM - - -/* - * Miscellaneous Support Routines - */ - -#define i960_reload_ctl_group( group ) \ - { register int _cmd = ((group)|0x400) ; \ - asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \ - } - -#define i960_atomic_modify( mask, addr, prev ) \ - { register unsigned int _mask = (mask); \ - register unsigned int *_addr = (unsigned int *)(addr); \ - asm volatile( "atmod %0,%1,%1" \ - : "=d" (_addr), "=d" (_mask) \ - : "0" (_addr), "1" (_mask) ); \ - (prev) = _mask; \ - } - -#define atomic_modify( _mask, _address, _previous ) \ - i960_atomic_modify( _mask, _address, _previous ) - -#define i960_enable_tracing() \ - { register unsigned int _pc = 0x1; \ - asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \ - } - -/* - * Interrupt Level Routines - */ - -#define i960_disable_interrupts( oldlevel ) \ - { (oldlevel) = 0x1f0000; \ - asm volatile ( "modpc 0,%1,%1" \ - : "=d" ((oldlevel)) \ - : "0" ((oldlevel)) ); \ - } - -#define i960_enable_interrupts( oldlevel ) \ - { unsigned int _mask = 0x1f0000; \ - asm volatile ( "modpc 0,%0,%1" \ - : "=d" (_mask), "=d" ((oldlevel)) \ - : "0" (_mask), "1" ((oldlevel)) ); \ - } - -#define i960_flash_interrupts( oldlevel ) \ - { unsigned int _mask = 0x1f0000; \ - asm volatile ( "modpc 0,%0,%1 ; \ - mov %0,%1 ; \ - modpc 0,%0,%1" \ - : "=d" (_mask), "=d" ((oldlevel)) \ - : "0" (_mask), "1" ((oldlevel)) ); \ - } - -#define i960_get_interrupt_level( _level ) \ - { \ - i960_disable_interrupts( _level ); \ - i960_enable_interrupts( _level ); \ - (_level) = ((_level) & 0x1f0000) >> 16; \ - } while ( 0 ) - -#define i960_cause_intr( intr ) \ - { register int _intr = (intr); \ - asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \ - } - -/* - * Interrupt Masking Routines - */ - -static inline unsigned int i960_get_fp() -{ register unsigned int _fp=0; - asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) ); - return ( _fp ); -} - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version is based on code presented in Vol. 4, No. 4 of - * Insight 960. It is certainly something you wouldn't think - * of on your own. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - register unsigned int to_swap = value; - register unsigned int temp = 0xFF00FF00; - register unsigned int swapped = 0; - - /* to_swap swapped */ - asm volatile ( "rotate 16,%0,%2 ;" /* 0x12345678 0x56781234 */ - "modify %1,%0,%2 ;" /* 0x12345678 0x12785634 */ - "rotate 8,%2,%2" /* 0x12345678 0x78563412 */ - : "=r" (to_swap), "=r" (temp), "=r" (swapped) - : "0" (to_swap), "1" (temp), "2" (swapped) - ); - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i960/rtems/score/types.h b/c/src/exec/score/cpu/i960/rtems/score/types.h deleted file mode 100644 index 81deddaa1f..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/* i960types.h - * - * This include file contains type definitions pertaining to the Intel - * i960 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __i960_TYPES_h -#define __i960_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned32 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void i960_isr; - -typedef void ( *i960_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/m68k/.cvsignore b/c/src/exec/score/cpu/m68k/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/m68k/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/m68k/ChangeLog b/c/src/exec/score/cpu/m68k/ChangeLog deleted file mode 100644 index 6cf037728b..0000000000 --- a/c/src/exec/score/cpu/m68k/ChangeLog +++ /dev/null @@ -1,145 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-05-28 Chris Johns <ccj@acm.org> - - * rtems/score/m68k.h: Per PR227, mc68060 does not require FPSP - since it is now multilib'ed. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * include/rtems/score/ispsh7750.h, score/ispsh7750.c: Account for - name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-03-15 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/m68k.h: m68k_swap_u32 fix typo. - -2002-03-06 Victor V. Vengerov <vvv@oktet.ru> - - * rtems/score/m68k.h [M68K_COLDFIRE_ARCH] (CPU_swap_u16, CPU_swap_u32): - Generic implementation of endian swap primitives added for Coldfire - family. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-08-09 Chris Johns <ccj@acm.org> - - * cpu_asm.S: This patch was co-developed with Eric Norum - <eric.norum@usask.ca>. It closes a one instruction window - on some m68k CPU cores. It fixes symptoms seen as: - 1) No more `interrupt handler invoked twice for - a single interrupt'. - 2) No more `lockup when mc68360 CPM and PIT interrupts - are at different levels'. - It does insert a little more overhead on machines without hardware - interrupt stacks but correctness has a price. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-12-19 Joel Sherrill <joel@OARcorp.com> - - * cpu.c: Do not read or write raw interrupt vector table if - we are on a CPU that does not have a %vbr register and the - BSP is configured as having the table in ROM. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-10-19 Antti P Miettinen <anmietti@trshp.ntc.nokia.com> - - * rtems/score/cpu.h: define CPU_Exception_frame for rdbg. - * m68302.h: Make buffer pointer in m302_SCC_bd volatile. - -2000-10-12 John S Gwynne <jgwynne@mrcday.com> - - * sim.h: These changes enable RTEMS to automatically generate - the ram_init file used by gdb with the BDM patches. The 332 has - on-board chip select lines (for RAM and FLASH) that must be - configured before use of these peripherals. These patches parse - data from start.c where the chip select lines are configured in - the runtime executable and automatically generates the gdb - initialization file using the same settings. A great time saver. - A similar file, ram_init_FW (flash writable), is also generated - that the flash programming tool uses. - * BSP/start/start.c: Must be modified to support above. - * BSP/start/ram_init.ld, BSP/start/ram_init.sed: New files. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/m68k/Makefile.am b/c/src/exec/score/cpu/m68k/Makefile.am deleted file mode 100644 index 147cbfae7d..0000000000 --- a/c/src/exec/score/cpu/m68k/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h m68302.h m68360.h qsm.h sim.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/m68k.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c memcpy.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S memcpy.c - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/m68k/asm.h b/c/src/exec/score/cpu/m68k/asm.h deleted file mode 100644 index 6c388fb396..0000000000 --- a/c/src/exec/score/cpu/m68k/asm.h +++ /dev/null @@ -1,144 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __M68k_ASM_h -#define __M68k_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -#define d0 REG (d0) -#define d1 REG (d1) -#define d2 REG (d2) -#define d3 REG (d3) -#define d4 REG (d4) -#define d5 REG (d5) -#define d6 REG (d6) -#define d7 REG (d7) -#define a0 REG (a0) -#define a1 REG (a1) -#define a2 REG (a2) -#define a3 REG (a3) -#define a4 REG (a4) -#define a5 REG (a5) -#define a6 REG (a6) -#define a7 REG (a7) -#define sp REG (sp) - -#define msp REG (msp) -#define usp REG (usp) -#define isp REG (isp) -#define sr REG (sr) -#define vbr REG (vbr) -#define dfc REG (dfc) -#define sfc REG (sfc) - -/* mcf52xx special regs */ -#define cacr REG (cacr) -#define acr0 REG (acr0) -#define acr1 REG (acr1) -#define rambar0 REG (rambar0) -#define mbar REG (mbar) - - -#define fp0 REG (fp0) -#define fp1 REG (fp1) -#define fp2 REG (fp2) -#define fp3 REG (fp3) -#define fp4 REG (fp4) -#define fp5 REG (fp5) -#define fp6 REG (fp6) -#define fp7 REG (fp7) - -#define fpc REG (fpc) -#define fpi REG (fpi) -#define fps REG (fps) -#define fpsr REG (fpsr) - - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/m68k/configure.ac b/c/src/exec/score/cpu/m68k/configure.ac deleted file mode 100644 index b812d9897a..0000000000 --- a/c/src/exec/score/cpu/m68k/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-m68k],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/m68k/cpu.c b/c/src/exec/score/cpu/m68k/cpu.c deleted file mode 100644 index c7337c378e..0000000000 --- a/c/src/exec/score/cpu/m68k/cpu.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Motorola MC68xxx Dependent Source - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - entry pointer to thread dispatcher - * - * OUTPUT PARAMETERS: NONE - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ -#if ( M68K_HAS_VBR == 0 ) - /* fill the isr redirect table with the code to place the format/id - onto the stack */ - - unsigned32 slot; - - for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++) - { - _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7; - _CPU_ISR_jump_table[slot].format_id = slot << 2; - _CPU_ISR_jump_table[slot].jmp = M68K_JMP; - _CPU_ISR_jump_table[slot].isr_handler = (unsigned32) 0xDEADDEAD; - } -#endif /* M68K_HAS_VBR */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level; - - m68k_get_interrupt_level( level ); - - return level; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr *interrupt_table = NULL; - -#if (M68K_HAS_FPSP_PACKAGE == 1) - /* - * If this vector being installed is one related to FP, then the - * FPSP will install the handler itself and handle it completely - * with no intervention from RTEMS. - */ - - if (*_FPSP_install_raw_handler && - (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler)) - return; -#endif - - - /* - * On CPU models without a VBR, it is necessary for there to be some - * header code for each ISR which saves a register, loads the vector - * number, and jumps to _ISR_Handler. - */ - - m68k_get_vbr( interrupt_table ); -#if ( M68K_HAS_VBR == 1 ) - *old_handler = interrupt_table[ vector ]; - interrupt_table[ vector ] = new_handler; -#else - - /* - * Install handler into RTEMS jump table and if VBR table is in - * RAM, install the pointer to the appropriate jump table slot. - * If the VBR table is in ROM, it is the BSP's responsibility to - * load it appropriately to vector to the RTEMS jump table. - */ - - *old_handler = _CPU_ISR_jump_table[vector].isr_handler; - _CPU_ISR_jump_table[vector].isr_handler = (unsigned32) new_handler; - if ( (unsigned32) interrupt_table != 0xFFFFFFFF ) - interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector]; -#endif /* M68K_HAS_VBR */ -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * new_handler - replacement ISR for this vector number - * old_handler - former ISR for this vector number - * - * Output parameters: NONE - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr ignored; - - *old_handler = _ISR_Vector_table[ vector ]; - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); - - _ISR_Vector_table[ vector ] = new_handler; -} - - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - void *isp = _CPU_Interrupt_stack_high; - - asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) ); -#endif -} - -#if ( M68K_HAS_BFFFO != 1 ) -/* - * Returns table for duplication of the BFFFO instruction (16 bits only) - */ -const unsigned char __BFFFOtable[256] = { - 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; -#endif - -/*PAGE - * - * The following code context switches the software FPU emulation - * code provided with GCC. - */ - -#if (CPU_SOFTWARE_FP == TRUE) -extern Context_Control_fp _fpCCR; - -void CPU_Context_save_fp (void **fp_context_ptr) -{ - Context_Control_fp *fp; - - fp = (Context_Control_fp *) *fp_context_ptr; - - *fp = _fpCCR; -} - -void CPU_Context_restore_fp (void **fp_context_ptr) -{ - Context_Control_fp *fp; - - fp = (Context_Control_fp *) *fp_context_ptr; - - _fpCCR = *fp; -} -#endif - diff --git a/c/src/exec/score/cpu/m68k/cpu_asm.S b/c/src/exec/score/cpu/m68k/cpu_asm.S deleted file mode 100644 index 0d14c16401..0000000000 --- a/c/src/exec/score/cpu/m68k/cpu_asm.S +++ /dev/null @@ -1,263 +0,0 @@ -/* cpu_asm.s - * - * This file contains all assembly code for the MC68020 implementation - * of RTEMS. - * - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include <asm.h> - - .text - -/* void _CPU_Context_switch( run_context, heir_context ) - * - * This routine performs a normal non-FP context. - */ - - .align 4 - .global SYM (_CPU_Context_switch) - -.set RUNCONTEXT_ARG, 4 | save context argument -.set HEIRCONTEXT_ARG, 8 | restore context argument - -SYM (_CPU_Context_switch): - moval a7@(RUNCONTEXT_ARG),a0| a0 = running thread context - movw sr,d1 | d1 = status register - movml d1-d7/a2-a7,a0@ | save context - - moval a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context -restore: movml a0@,d1-d7/a2-a7 | restore context - movw d1,sr | restore status register - rts - -/*PAGE - * void __CPU_Context_save_fp_context( &fp_context_ptr ) - * void __CPU_Context_restore_fp_context( &fp_context_ptr ) - * - * These routines are used to context switch a MC68881 or MC68882. - * - * NOTE: Context save and restore code is based upon the code shown - * on page 6-38 of the MC68881/68882 Users Manual (rev 1). - * - * CPU_FP_CONTEXT_SIZE is higher than expected to account for the - * -1 pushed at end of this sequence. - * - * Neither of these entries is required if we have software FPU - * emulation. But if we don't have an FPU or emulation, then - * we need the stub versions of these routines. - */ - -#if (CPU_SOFTWARE_FP == FALSE) - -.set FPCONTEXT_ARG, 4 | save FP context argument - - .align 4 - .global SYM (_CPU_Context_save_fp) -SYM (_CPU_Context_save_fp): -#if ( M68K_HAS_FPU == 1 ) - moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area - moval a1@,a0 | a0 = Save context area - fsave a0@- | save 68881/68882 state frame - tstb a0@ | check for a null frame - beq.b nosv | Yes, skip save of user model - fmovem fp0-fp7,a0@- | save data registers (fp0-fp7) - fmovem fpc/fps/fpi,a0@- | and save control registers - movl #-1,a0@- | place not-null flag on stack -nosv: movl a0,a1@ | save pointer to saved context -#endif - rts - - .align 4 - .global SYM (_CPU_Context_restore_fp) -SYM (_CPU_Context_restore_fp): -#if ( M68K_HAS_FPU == 1 ) - moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area - moval a1@,a0 | a0 = address of saved context - tstb a0@ | Null context frame? - beq.b norst | Yes, skip fp restore - addql #4,a0 | throwaway non-null flag - fmovem a0@+,fpc/fps/fpi | restore control registers - fmovem a0@+,fp0-fp7 | restore data regs (fp0-fp7) -norst: frestore a0@+ | restore the fp state frame - movl a0,a1@ | save pointer to saved context -#endif - rts -#endif - -/*PAGE - * void _ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * NOTE: - * Upon entry, the master stack will contain an interrupt stack frame - * back to the interrupted thread and the interrupt stack will contain - * a throwaway interrupt stack frame. If dispatching is enabled, and this - * is the outer most interrupt, and a context switch is necessary or - * the current thread has pending signals, then set up the master stack to - * transfer control to the interrupt dispatcher. - */ - -#if ( M68K_COLDFIRE_ARCH == 1 ) -.set SR_OFFSET, 2 | Status register offset -.set PC_OFFSET, 4 | Program Counter offset -.set FVO_OFFSET, 0 | Format/vector offset -#elif ( M68K_HAS_VBR == 1) -.set SR_OFFSET, 0 | Status register offset -.set PC_OFFSET, 2 | Program Counter offset -.set FVO_OFFSET, 6 | Format/vector offset -#else -.set SR_OFFSET, 2 | Status register offset -.set PC_OFFSET, 4 | Program Counter offset -.set FVO_OFFSET, 0 | Format/vector offset placed in the stack -#endif /* M68K_HAS_VBR */ - -.set SAVED, 16 | space for saved registers - - .align 4 - .global SYM (_ISR_Handler) - -SYM (_ISR_Handler): - addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking -#if ( M68K_COLDFIRE_ARCH == 0 ) - moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 -#else - lea a7@(-SAVED),a7 - movm.l d0-d1/a0-a1,a7@ | save d0-d1,a0-a1 -#endif - movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO - andl #0x0ffc,d0 | d0 = vector offset in vbr - - -#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) - movel _CPU_Interrupt_stack_high,a0 | a0 now point just above interrupt stack - cmpl _CPU_Interrupt_stack_low,a7 | stack below interrupt stack? - bcs.b 1f | yes, switch to interrupt stack - cmpl a0,a7 | stack above interrupt stack? - bcs.b 2f | no, do not switch stacks -1: - movel a7,a1 | copy task stack pointer - movel a0,a7 | switch to interrupt stack - movel a1,a7@- | store task stack pointer on interrupt stack -2: -#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ - - movel SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table -# |