diff options
Diffstat (limited to 'c/src/exec/score/cpu/powerpc/cpu.h')
-rw-r--r-- | c/src/exec/score/cpu/powerpc/cpu.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/c/src/exec/score/cpu/powerpc/cpu.h b/c/src/exec/score/cpu/powerpc/cpu.h index 5360b21770..b966f5895b 100644 --- a/c/src/exec/score/cpu/powerpc/cpu.h +++ b/c/src/exec/score/cpu/powerpc/cpu.h @@ -147,6 +147,14 @@ struct CPU_Interrupt_frame; #define CPU_ALLOCATE_INTERRUPT_STACK TRUE /* + * Does the RTEMS invoke the user's ISR with the vector number and + * a pointer to the saved interrupt frame (1) or just the vector + * number (0)? + */ + +#define CPU_ISR_PASSES_FRAME_POINTER 1 + +/* * Does the CPU have hardware floating point? * * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. @@ -1094,6 +1102,38 @@ static inline unsigned int CPU_swap_u32( #define CPU_swap_u16( value ) \ (((value&0xff) << 8) | ((value >> 8)&0xff)) +/* + * Routines to access the decrementer register + */ + +#define PPC_Set_decrementer( _clicks ) \ + do { \ + asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +/* + * Routines to access the time base register + */ + +static inline unsigned64 PPC_Get_timebase_register( void ) +{ + unsigned32 tbr_low; + unsigned32 tbr_high; + unsigned32 tbr_high_old; + unsigned64 tbr; + + do { + asm volatile( "mftbu %0" : "=r" (tbr_high_old)); + asm volatile( "mftb %0" : "=r" (tbr_low)); + asm volatile( "mftbu %0" : "=r" (tbr_high)); + } while ( tbr_high_old != tbr_high ); + + tbr = tbr_high; + tbr <<= 32; + tbr |= tbr_low; + return tbr; +} + #ifdef __cplusplus } #endif |