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-rw-r--r--c/src/exec/score/cpu/a29k/cpu.h8
-rw-r--r--c/src/exec/score/cpu/hppa1.1/cpu.h8
-rw-r--r--c/src/exec/score/cpu/i386/cpu.h8
-rw-r--r--c/src/exec/score/cpu/i960/cpu.h8
-rw-r--r--c/src/exec/score/cpu/m68k/cpu.h8
-rw-r--r--c/src/exec/score/cpu/mips64orion/cpu.h8
-rw-r--r--c/src/exec/score/cpu/no_cpu/cpu.h8
-rw-r--r--c/src/exec/score/cpu/powerpc/cpu.h40
-rw-r--r--c/src/exec/score/cpu/sh/cpu.h7
-rw-r--r--c/src/exec/score/cpu/sparc/cpu.h8
-rw-r--r--c/src/exec/score/cpu/unix/cpu.h8
-rw-r--r--c/src/exec/score/headers/isr.h7
-rw-r--r--c/src/exec/score/include/rtems/score/isr.h7
-rw-r--r--cpukit/score/include/rtems/score/isr.h7
14 files changed, 140 insertions, 0 deletions
diff --git a/c/src/exec/score/cpu/a29k/cpu.h b/c/src/exec/score/cpu/a29k/cpu.h
index bf7f5230b9..6578621f79 100644
--- a/c/src/exec/score/cpu/a29k/cpu.h
+++ b/c/src/exec/score/cpu/a29k/cpu.h
@@ -160,6 +160,14 @@ extern void a29k_sigdfl_sup(void);
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.h b/c/src/exec/score/cpu/hppa1.1/cpu.h
index 91dbdc8cad..84fcd39d57 100644
--- a/c/src/exec/score/cpu/hppa1.1/cpu.h
+++ b/c/src/exec/score/cpu/hppa1.1/cpu.h
@@ -41,6 +41,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
* HPPA has hardware FP, it is assumed to exist by GCC so all tasks
* may implicitly use it (especially for integer multiplies). Because
* the FP context is technically part of the basic integer context
diff --git a/c/src/exec/score/cpu/i386/cpu.h b/c/src/exec/score/cpu/i386/cpu.h
index 621571b917..42ec7db6f5 100644
--- a/c/src/exec/score/cpu/i386/cpu.h
+++ b/c/src/exec/score/cpu/i386/cpu.h
@@ -40,6 +40,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
* Some family members have no FP, some have an FPU such as the i387
* for the i386, others have it built in (i486DX, Pentium).
*/
diff --git a/c/src/exec/score/cpu/i960/cpu.h b/c/src/exec/score/cpu/i960/cpu.h
index 915b0bf242..2a0882149b 100644
--- a/c/src/exec/score/cpu/i960/cpu.h
+++ b/c/src/exec/score/cpu/i960/cpu.h
@@ -41,6 +41,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
* Some family members have no FP (SA/KA/CA/CF), others have it built in
* (KB/MC/MX). There does not appear to be an external coprocessor
* for this family.
diff --git a/c/src/exec/score/cpu/m68k/cpu.h b/c/src/exec/score/cpu/m68k/cpu.h
index a5c3672c26..21cc5493ca 100644
--- a/c/src/exec/score/cpu/m68k/cpu.h
+++ b/c/src/exec/score/cpu/m68k/cpu.h
@@ -47,6 +47,14 @@ extern "C" {
#endif
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
* Some family members have no FP, some have an FPU such as the
* MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
*
diff --git a/c/src/exec/score/cpu/mips64orion/cpu.h b/c/src/exec/score/cpu/mips64orion/cpu.h
index 75809b3384..684d9d590e 100644
--- a/c/src/exec/score/cpu/mips64orion/cpu.h
+++ b/c/src/exec/score/cpu/mips64orion/cpu.h
@@ -147,6 +147,14 @@ extern void mips_fatal_error ( int error );
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
diff --git a/c/src/exec/score/cpu/no_cpu/cpu.h b/c/src/exec/score/cpu/no_cpu/cpu.h
index 0373e43fc7..77c06f4a55 100644
--- a/c/src/exec/score/cpu/no_cpu/cpu.h
+++ b/c/src/exec/score/cpu/no_cpu/cpu.h
@@ -123,6 +123,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
diff --git a/c/src/exec/score/cpu/powerpc/cpu.h b/c/src/exec/score/cpu/powerpc/cpu.h
index 5360b21770..b966f5895b 100644
--- a/c/src/exec/score/cpu/powerpc/cpu.h
+++ b/c/src/exec/score/cpu/powerpc/cpu.h
@@ -147,6 +147,14 @@ struct CPU_Interrupt_frame;
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 1
+
+/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
@@ -1094,6 +1102,38 @@ static inline unsigned int CPU_swap_u32(
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
+/*
+ * Routines to access the decrementer register
+ */
+
+#define PPC_Set_decrementer( _clicks ) \
+ do { \
+ asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
+ } while (0)
+
+/*
+ * Routines to access the time base register
+ */
+
+static inline unsigned64 PPC_Get_timebase_register( void )
+{
+ unsigned32 tbr_low;
+ unsigned32 tbr_high;
+ unsigned32 tbr_high_old;
+ unsigned64 tbr;
+
+ do {
+ asm volatile( "mftbu %0" : "=r" (tbr_high_old));
+ asm volatile( "mftb %0" : "=r" (tbr_low));
+ asm volatile( "mftbu %0" : "=r" (tbr_high));
+ } while ( tbr_high_old != tbr_high );
+
+ tbr = tbr_high;
+ tbr <<= 32;
+ tbr |= tbr_low;
+ return tbr;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/c/src/exec/score/cpu/sh/cpu.h b/c/src/exec/score/cpu/sh/cpu.h
index 310e3271f6..9ff5319aa3 100644
--- a/c/src/exec/score/cpu/sh/cpu.h
+++ b/c/src/exec/score/cpu/sh/cpu.h
@@ -108,6 +108,13 @@ extern "C" {
*/
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
+/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
diff --git a/c/src/exec/score/cpu/sparc/cpu.h b/c/src/exec/score/cpu/sparc/cpu.h
index 21b24a0ba7..3f09e24a5b 100644
--- a/c/src/exec/score/cpu/sparc/cpu.h
+++ b/c/src/exec/score/cpu/sparc/cpu.h
@@ -94,6 +94,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the FLOATING_POINT task attribute is supported.
diff --git a/c/src/exec/score/cpu/unix/cpu.h b/c/src/exec/score/cpu/unix/cpu.h
index 1667438f92..5eb4147df6 100644
--- a/c/src/exec/score/cpu/unix/cpu.h
+++ b/c/src/exec/score/cpu/unix/cpu.h
@@ -134,6 +134,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
diff --git a/c/src/exec/score/headers/isr.h b/c/src/exec/score/headers/isr.h
index 8016e2116b..97ffe7f2ec 100644
--- a/c/src/exec/score/headers/isr.h
+++ b/c/src/exec/score/headers/isr.h
@@ -46,9 +46,16 @@ typedef void ISR_Handler;
* Pointer to an ISR Handler
*/
+#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
+typedef ISR_Handler ( *ISR_Handler_entry )(
+ ISR_Vector_number,
+ CPU_Interrupt_frame *
+ );
+#else
typedef ISR_Handler ( *ISR_Handler_entry )(
ISR_Vector_number
);
+#endif
/*
* This constant promotes out the number of vectors truly supported by
* the current CPU being used. This is usually the number of distinct vectors
diff --git a/c/src/exec/score/include/rtems/score/isr.h b/c/src/exec/score/include/rtems/score/isr.h
index 8016e2116b..97ffe7f2ec 100644
--- a/c/src/exec/score/include/rtems/score/isr.h
+++ b/c/src/exec/score/include/rtems/score/isr.h
@@ -46,9 +46,16 @@ typedef void ISR_Handler;
* Pointer to an ISR Handler
*/
+#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
+typedef ISR_Handler ( *ISR_Handler_entry )(
+ ISR_Vector_number,
+ CPU_Interrupt_frame *
+ );
+#else
typedef ISR_Handler ( *ISR_Handler_entry )(
ISR_Vector_number
);
+#endif
/*
* This constant promotes out the number of vectors truly supported by
* the current CPU being used. This is usually the number of distinct vectors
diff --git a/cpukit/score/include/rtems/score/isr.h b/cpukit/score/include/rtems/score/isr.h
index 8016e2116b..97ffe7f2ec 100644
--- a/cpukit/score/include/rtems/score/isr.h
+++ b/cpukit/score/include/rtems/score/isr.h
@@ -46,9 +46,16 @@ typedef void ISR_Handler;
* Pointer to an ISR Handler
*/
+#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
+typedef ISR_Handler ( *ISR_Handler_entry )(
+ ISR_Vector_number,
+ CPU_Interrupt_frame *
+ );
+#else
typedef ISR_Handler ( *ISR_Handler_entry )(
ISR_Vector_number
);
+#endif
/*
* This constant promotes out the number of vectors truly supported by
* the current CPU being used. This is usually the number of distinct vectors
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-24 15:40:16 +0000