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-rw-r--r--bsps/sparc/shared/start/bsp_fatal_exit.c25
-rw-r--r--bsps/sparc/shared/start/bsp_fatal_halt.c33
-rw-r--r--bsps/sparc/shared/start/bspgetworkarea.c2
-rw-r--r--bsps/sparc/shared/start/linkcmds.base2
-rw-r--r--bsps/sparc/shared/start/sparc-counter-asm.S151
-rw-r--r--bsps/sparc/shared/start/start.S60
6 files changed, 221 insertions, 52 deletions
diff --git a/bsps/sparc/shared/start/bsp_fatal_exit.c b/bsps/sparc/shared/start/bsp_fatal_exit.c
index 2ad11846e5..d2ecfb1b7a 100644
--- a/bsps/sparc/shared/start/bsp_fatal_exit.c
+++ b/bsps/sparc/shared/start/bsp_fatal_exit.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
* @ingroup RTEMSBSPsSPARCShared
@@ -8,9 +10,26 @@
* COPYRIGHT (c) 2014.
* Aeroflex Gaisler AB.
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp.h>
diff --git a/bsps/sparc/shared/start/bsp_fatal_halt.c b/bsps/sparc/shared/start/bsp_fatal_halt.c
deleted file mode 100644
index f53275a073..0000000000
--- a/bsps/sparc/shared/start/bsp_fatal_halt.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/**
- * @file
- * @ingroup RTEMSBSPsSPARCShared
- * @brief ERC32/LEON2 BSP Fatal_halt handler.
- *
- * COPYRIGHT (c) 2014.
- * Aeroflex Gaisler AB.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include <bsp.h>
-#include <rtems/score/cpuimpl.h>
-
-void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
-{
-#ifdef BSP_POWER_DOWN_AT_FATAL_HALT
- /* Spin CPU on fatal error exit */
- uint32_t level = sparc_disable_interrupts();
-
- __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) );
-
- while (1) ; /* loop forever */
-#else
- /*
- * Return to debugger, simulator, hypervisor or similar by exiting
- * with an error code. g1=1, g2=FATAL_SOURCE, G3=error-code.
- */
- sparc_syscall_exit(source, error);
-#endif
-}
diff --git a/bsps/sparc/shared/start/bspgetworkarea.c b/bsps/sparc/shared/start/bspgetworkarea.c
index 6ceda38c07..f30d6e186c 100644
--- a/bsps/sparc/shared/start/bspgetworkarea.c
+++ b/bsps/sparc/shared/start/bspgetworkarea.c
@@ -9,7 +9,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2019, 2021 embedded brains GmbH
+ * Copyright (C) 2019, 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/bsps/sparc/shared/start/linkcmds.base b/bsps/sparc/shared/start/linkcmds.base
index ed7ab38b37..b278c78a46 100644
--- a/bsps/sparc/shared/start/linkcmds.base
+++ b/bsps/sparc/shared/start/linkcmds.base
@@ -155,7 +155,7 @@ SECTIONS
*(.rela.rtemsrwset*)
} >ram
.noinit (NOLOAD) : {
- *(.noinit*)
+ *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*)))
} > ram
.rtemsstack (NOLOAD) : {
*(SORT(.rtemsstack.*))
diff --git a/bsps/sparc/shared/start/sparc-counter-asm.S b/bsps/sparc/shared/start/sparc-counter-asm.S
new file mode 100644
index 0000000000..590d77050d
--- /dev/null
+++ b/bsps/sparc/shared/start/sparc-counter-asm.S
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2016, 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/asm.h>
+
+ /*
+ * All functions except _SPARC_Counter_read_clock() in this module are
+ * sometimes called with traps disabled.
+ */
+
+ .section ".text"
+ .align 4
+
+ /*
+ * This is a workaround for:
+ * https://gcc.gnu.org/bugzilla//show_bug.cgi?id=69027
+ */
+ PUBLIC(_CPU_Counter_read)
+SYM(_CPU_Counter_read):
+ sethi %hi(_SPARC_Counter + 4), %o1
+ ld [%o1 + %lo(_SPARC_Counter + 4)], %o1
+ or %o7, %g0, %g1
+ call %o1, 0
+ or %g1, %g0, %o7
+
+#if defined(RTEMS_PROFILING)
+ /*
+ * This is a workaround for:
+ * https://gcc.gnu.org/bugzilla//show_bug.cgi?id=69027
+ */
+ PUBLIC(_SPARC_Counter_read_ISR_disabled)
+SYM(_SPARC_Counter_read_ISR_disabled):
+ sethi %hi(_SPARC_Counter), %o1
+ ld [%o1 + %lo(_SPARC_Counter)], %o1
+ or %o7, %g0, %g1
+ call %o1, 0
+ or %g1, %g0, %o7
+#endif
+
+ PUBLIC(_SPARC_Counter_read_default)
+SYM(_SPARC_Counter_read_default):
+ sethi %hi(_SPARC_Counter + 12), %o1
+ ld [%o1 + %lo(_SPARC_Counter + 12)], %o0
+ add %o0, 1, %o0
+ st %o0, [%o1 + %lo(_SPARC_Counter + 12)]
+ jmp %o7 + 8
+ nop
+
+ /*
+ * For the corresponding C code is something like this:
+ *
+ * CPU_Counter_ticks _SPARC_Counter_read_clock_isr_disabled( void )
+ * {
+ * const SPARC_Counter *ctr;
+ * CPU_Counter_ticks ticks;
+ * CPU_Counter_ticks accumulated;
+ *
+ * ctr = &_SPARC_Counter;
+ * ticks = *ctr->counter_register;
+ * accumulated = ctr->accumulated;
+ *
+ * if ( ( *ctr->pending_register & ctr->pending_mask ) != 0 ) {
+ * ticks = *ctr->counter_register;
+ * accumulated += ctr->interval;
+ * }
+ *
+ * return accumulated - ticks;
+ * }
+ */
+ PUBLIC(_SPARC_Counter_read_clock_isr_disabled)
+SYM(_SPARC_Counter_read_clock_isr_disabled):
+ sethi %hi(_SPARC_Counter), %o5
+ or %o5, %lo(_SPARC_Counter), %o5
+ ld [%o5 + 8], %o3
+ ld [%o5 + 12], %o4
+ ld [%o5 + 16], %o2
+ ld [%o3], %o0
+ ld [%o4], %o1
+ btst %o1, %o2
+ bne .Lpending_isr_disabled
+ ld [%o5 + 20], %o4
+ jmp %o7 + 8
+ sub %o4, %o0, %o0
+.Lpending_isr_disabled:
+ ld [%o5 + 24], %o5
+ ld [%o3], %o0
+ add %o4, %o5, %o4
+ jmp %o7 + 8
+ sub %o4, %o0, %o0
+
+ /*
+ * For the corresponding C code see
+ * _SPARC_Counter_read_clock_isr_disabled() above.
+ */
+ PUBLIC(_SPARC_Counter_read_clock)
+ PUBLIC(_SPARC_Get_timecount_clock)
+SYM(_SPARC_Counter_read_clock):
+SYM(_SPARC_Get_timecount_clock):
+ sethi %hi(_SPARC_Counter), %o5
+ or %o5, %lo(_SPARC_Counter), %o5
+ ta SPARC_SWTRAP_IRQDIS
+ ld [%o5 + 8], %o3
+ ld [%o5 + 12], %o4
+ ld [%o5 + 16], %o2
+ ld [%o3], %o0
+ ld [%o4], %o1
+ btst %o1, %o2
+ bne .Lpending
+ ld [%o5 + 20], %o4
+ ta SPARC_SWTRAP_IRQEN
+#ifdef __FIX_LEON3FT_TN0018
+ /* A nop is added to work around the GRLIB-TN-0018 errata */
+ nop
+#endif
+ jmp %o7 + 8
+ sub %o4, %o0, %o0
+.Lpending:
+ ld [%o5 + 24], %o5
+ ld [%o3], %o0
+ ta SPARC_SWTRAP_IRQEN
+ add %o4, %o5, %o4
+ jmp %o7 + 8
+ sub %o4, %o0, %o0
diff --git a/bsps/sparc/shared/start/start.S b/bsps/sparc/shared/start/start.S
index 45bd145d4a..8a22f8ff74 100644
--- a/bsps/sparc/shared/start/start.S
+++ b/bsps/sparc/shared/start/start.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* Common start code for SPARC.
*
@@ -10,9 +12,26 @@
* COPYRIGHT (c) 1989-2011.
* On-Line Applications Research Corporation (OAR).
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#include <rtems/asm.h>
@@ -474,17 +493,13 @@ SYM(hard_reset):
mov %sp, %fp ! set frame pointer
#if defined(START_LEON3_ENABLE_SMP)
- /* If LEON3_Boot_Cpu < 0 then assign us as boot CPU and continue. */
- set SYM(LEON3_Boot_Cpu), %l0
- ld [%l0], %l1
- tst %l1
- bneg .Lbootcpu
- nop
-
- call SYM(bsp_start_on_secondary_processor) ! does not return
- mov %g6, %o0
-.Lbootcpu:
- st %l7, [%l0]
+ /* If .Lbootcpuindex < 0 then assign us as boot CPU and continue. */
+ set SYM(.Lbootcpuindex), %l0
+ mov -1, %l1
+ casa [%l0] (10), %l1, %l7
+ cmp %l1, %l7
+ bne .Lbootsecondarycpu
+ nop
#endif
/* clear the bss */
@@ -508,4 +523,21 @@ SYM(hard_reset):
call SYM(boot_card) ! does not return
mov %g0, %o0 ! command line
+#if defined(START_LEON3_ENABLE_SMP)
+.Lbootsecondarycpu:
+ call SYM(bsp_start_on_secondary_processor) ! does not return
+ mov %g6, %o0
+
+ /*
+ * This is the index of the boot CPU. Set by the first CPU at boot to
+ * its CPU index.
+ */
+ .section .data, "aw"
+ .align 4
+ .type .Lbootcpuindex, #object
+ .size .Lbootcpuindex, 4
+.Lbootcpuindex:
+ .long -1
+#endif
+
/* end of file */
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-27 09:54:12 +0000