diff options
Diffstat (limited to 'bsps/sparc')
70 files changed, 3915 insertions, 871 deletions
diff --git a/bsps/sparc/erc32/clock/ckinit.c b/bsps/sparc/erc32/clock/ckinit.c index 83cafb73c3..c0101c5839 100644 --- a/bsps/sparc/erc32/clock/ckinit.c +++ b/bsps/sparc/erc32/clock/ckinit.c @@ -26,7 +26,7 @@ #include <rtems/irq-extension.h> #include <rtems/sysinit.h> #include <rtems/timecounter.h> -#include <rtems/score/sparcimpl.h> +#include <bsp/sparc-counter.h> extern int CLOCK_SPEED; @@ -46,17 +46,15 @@ static void erc32_clock_init( void ) rtems_timecounter_install(tc); } -uint32_t _CPU_Counter_frequency(void) +uint32_t _CPU_Counter_frequency( void ) { return ERC32_REAL_TIME_CLOCK_FREQUENCY; } -static void erc32_clock_at_tick( void ) +static void erc32_clock_at_tick( SPARC_Counter *counter ) { - SPARC_Counter *counter; rtems_interrupt_level level; - counter = &_SPARC_Counter_mutable; rtems_interrupt_local_disable(level); ERC32_Clear_interrupt( ERC32_INTERRUPT_REAL_TIME_CLOCK ); @@ -83,7 +81,7 @@ static void erc32_clock_initialize_early( void ) ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO ); - counter = &_SPARC_Counter_mutable; + counter = &_SPARC_Counter; counter->read_isr_disabled = _SPARC_Counter_read_clock_isr_disabled; counter->read = _SPARC_Counter_read_clock; counter->counter_register = &ERC32_MEC.Real_Time_Clock_Counter, @@ -110,7 +108,7 @@ RTEMS_SYSINIT_ITEM( "Clock", \ RTEMS_INTERRUPT_SHARED, \ _new, \ - NULL \ + &_SPARC_Counter \ ) #define Clock_driver_support_set_interrupt_affinity( _online_processors ) \ @@ -118,7 +116,7 @@ RTEMS_SYSINIT_ITEM( (void) _online_processors; \ } while (0) -#define Clock_driver_support_at_tick() erc32_clock_at_tick() +#define Clock_driver_support_at_tick(arg) erc32_clock_at_tick(arg) #define Clock_driver_support_initialize_hardware() erc32_clock_init() diff --git a/bsps/sparc/erc32/console/erc32_console.c b/bsps/sparc/erc32/console/erc32_console.c index 81dfe026fb..f50b8b4073 100644 --- a/bsps/sparc/erc32/console/erc32_console.c +++ b/bsps/sparc/erc32/console/erc32_console.c @@ -66,7 +66,7 @@ static void erc32_console_initialize(int minor); erc32_console_initialize, /* deviceInitialize */ NULL, /* deviceWritePolled */ NULL, /* deviceSetAttributes */ - TERMIOS_IRQ_DRIVEN /* deviceOutputUsesInterrupts */ + true /* deviceOutputUsesInterrupts */ }; #else const console_fns erc32_fns = { @@ -78,7 +78,7 @@ static void erc32_console_initialize(int minor); erc32_console_initialize, /* deviceInitialize */ NULL, /* deviceWritePolled */ NULL, /* deviceSetAttributes */ - TERMIOS_POLLED /* deviceOutputUsesInterrupts */ + false /* deviceOutputUsesInterrupts */ }; #endif diff --git a/bsps/sparc/erc32/include/bsp.h b/bsps/sparc/erc32/include/bsp.h index fd453fb6c2..1e8bddad33 100644 --- a/bsps/sparc/erc32/include/bsp.h +++ b/bsps/sparc/erc32/include/bsp.h @@ -105,7 +105,7 @@ typedef void (*bsp_shared_isr)(void *arg); * isr Function pointer to the ISR * arg Second argument to function isr */ -static __inline__ int BSP_shared_interrupt_register +RTEMS_DEPRECATED static inline int BSP_shared_interrupt_register ( int irq, const char *info, @@ -124,7 +124,7 @@ static __inline__ int BSP_shared_interrupt_register * isr Function pointer to the ISR * arg Second argument to function isr */ -static __inline__ int BSP_shared_interrupt_unregister +RTEMS_DEPRECATED static inline int BSP_shared_interrupt_unregister ( int irq, bsp_shared_isr isr, @@ -142,7 +142,10 @@ static __inline__ int BSP_shared_interrupt_unregister * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_clear(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_clear( int irq ) +{ + (void) rtems_interrupt_clear( (rtems_vector_number) irq ); +} /* Enable Interrupt. This function will unmask the IRQ at the interrupt * controller. This is normally done by _register(). Note that this will @@ -151,7 +154,10 @@ extern void BSP_shared_interrupt_clear(int irq); * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_unmask(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_unmask( int irq ) +{ + (void) rtems_interrupt_vector_enable( (rtems_vector_number) irq ); +} /* Disable Interrupt. This function will mask one IRQ at the interrupt * controller. This is normally done by _unregister(). Note that this will @@ -160,7 +166,10 @@ extern void BSP_shared_interrupt_unmask(int irq); * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_mask(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_mask( int irq ) +{ + (void) rtems_interrupt_vector_disable( (rtems_vector_number) irq ); +} /* * Delay for the specified number of microseconds. diff --git a/bsps/sparc/erc32/include/bsp/irq.h b/bsps/sparc/erc32/include/bsp/irq.h index 83b383ba7a..210883ad05 100644 --- a/bsps/sparc/erc32/include/bsp/irq.h +++ b/bsps/sparc/erc32/include/bsp/irq.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup sparc_erc32 @@ -10,39 +12,36 @@ * Copyright (c) 2012. * Aeroflex Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_ERC32_IRQ_CONFIG_H #define LIBBSP_ERC32_IRQ_CONFIG_H -#include <rtems/score/processormask.h> +#include <rtems.h> #define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ #define BSP_INTERRUPT_VECTOR_COUNT (BSP_INTERRUPT_VECTOR_MAX_STD + 1) #define BSP_INTERRUPT_CUSTOM_VALID_VECTOR -RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -) -{ - (void) vector; - (void) affinity; - return RTEMS_SUCCESSFUL; -} - -RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -) -{ - (void) vector; - _Processor_mask_From_index( affinity, 0 ); - return RTEMS_SUCCESSFUL; -} - #endif /* LIBBSP_ERC32_IRQ_CONFIG_H */ diff --git a/bsps/sparc/erc32/include/bsp/irqimpl.h b/bsps/sparc/erc32/include/bsp/irqimpl.h new file mode 100644 index 0000000000..6a8b17f188 --- /dev/null +++ b/bsps/sparc/erc32/include/bsp/irqimpl.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCERC32 + * + * @brief This header file provides interfaces used by the interrupt support + * implementation. + */ + +/* + * Copyright (C) 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SPARC_ERC32_BSP_IRQIMPL_H +#define LIBBSP_SPARC_ERC32_BSP_IRQIMPL_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup RTEMSBSPsSPARCERC32 + * + * @{ + */ + +static inline uint32_t bsp_irq_fixup( uint32_t irq ) +{ + return irq; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_SPARC_ERC32_BSP_IRQIMPL_H */ diff --git a/bsps/sparc/erc32/include/erc32.h b/bsps/sparc/erc32/include/erc32.h index f9cdbc960a..3967f4c918 100644 --- a/bsps/sparc/erc32/include/erc32.h +++ b/bsps/sparc/erc32/include/erc32.h @@ -326,11 +326,6 @@ typedef struct { extern ERC32_Register_Map ERC32_MEC; -static __inline__ int bsp_irq_fixup(int irq) -{ - return irq; -} - /* * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, * and the Interrupt Pending Registers. diff --git a/bsps/sparc/erc32/include/tm27.h b/bsps/sparc/erc32/include/tm27.h index 2ed4f2b78c..90b885d876 100644 --- a/bsps/sparc/erc32/include/tm27.h +++ b/bsps/sparc/erc32/include/tm27.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup sparc_erc32 @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2006. * Aeroflex Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_TMTEST27 @@ -40,6 +59,8 @@ #define MUST_WAIT_FOR_INTERRUPT 1 +#define TM27_USE_VECTOR_HANDLER + #define Install_tm27_vector( handler ) \ set_vector( (handler), TEST_VECTOR, 1 ); @@ -61,22 +82,20 @@ #define MUST_WAIT_FOR_INTERRUPT 1 -static inline void Install_tm27_vector( - void ( *handler )( rtems_vector_number ) -) +static inline void Install_tm27_vector( rtems_interrupt_handler handler ) { (void) rtems_interrupt_handler_install( TEST_INTERRUPT_SOURCE, "tm27 low", RTEMS_INTERRUPT_SHARED, - (rtems_interrupt_handler) handler, + handler, NULL ); (void) rtems_interrupt_handler_install( TEST_INTERRUPT_SOURCE2, "tm27 high", RTEMS_INTERRUPT_SHARED, - (rtems_interrupt_handler) handler, + handler, NULL ); } diff --git a/bsps/sparc/erc32/start/bspsmp.c b/bsps/sparc/erc32/start/bspsmp.c index fd63fc02e1..f66e9c306f 100644 --- a/bsps/sparc/erc32/start/bspsmp.c +++ b/bsps/sparc/erc32/start/bspsmp.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2019 embedded brains GmbH + * Copyright (C) 2019 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/sparc/erc32/start/bspstart.c b/bsps/sparc/erc32/start/bspstart.c index 1979c68308..f4a90aebd0 100644 --- a/bsps/sparc/erc32/start/bspstart.c +++ b/bsps/sparc/erc32/start/bspstart.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* Installs the BSP pre-driver hook */ @@ -5,9 +7,26 @@ * COPYRIGHT (c) 2011 * Aeroflex Gaisler * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> diff --git a/bsps/sparc/include/bsp/gnatcommon.h b/bsps/sparc/include/bsp/gnatcommon.h index 1a04449293..40e8829bb9 100644 --- a/bsps/sparc/include/bsp/gnatcommon.h +++ b/bsps/sparc/include/bsp/gnatcommon.h @@ -1,3 +1,18 @@ +/** + * @file + * + * @ingroup RTEMSImplGnat + * + * @brief This header file provides interfaces of the + * gnat/rtems interrupts and exception handling. + */ + +/** + * @defgroup RTEMSImplGnat GNAT/RTEMS interrupts and exception handling + * + * @ingroup RTEMSImpl + */ + #ifndef __GNATCOMMON_H #define __GNATCOMMON_H diff --git a/bsps/sparc/include/bsp/gr_leon4_n2x.h b/bsps/sparc/include/bsp/gr_leon4_n2x.h index 9a8041202a..97ca6d5dfb 100644 --- a/bsps/sparc/include/bsp/gr_leon4_n2x.h +++ b/bsps/sparc/include/bsp/gr_leon4_n2x.h @@ -1,11 +1,38 @@ -/* GR-CPCI-LEON4-N2X (NGFP) PCI Peripheral driver +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 * + * @brief This header file provides interfaces of the + * GR-CPCI-LEON4-N2X (NGFP) PCI Peripheral driver. + */ + +/* * COPYRIGHT (c) 2013. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * Configures the GR-CPIC-LEON4-N2X interface PCI board in peripheral * mode. This driver provides a AMBA PnP bus by using the general part diff --git a/bsps/sparc/include/bsp/sparc-counter.h b/bsps/sparc/include/bsp/sparc-counter.h new file mode 100644 index 0000000000..bc4f2220e7 --- /dev/null +++ b/bsps/sparc/include/bsp/sparc-counter.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCShared + * + * @brief This header file provides interfaces of a CPU counter implementation + * for SPARC BSPs. + */ + +/* + * Copyright (C) 2016, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _BSP_SPARC_COUNTER_H +#define _BSP_SPARC_COUNTER_H + +#include <rtems/score/cpu.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct timecounter; + +void _SPARC_Counter_at_tick_clock( void ); + +CPU_Counter_ticks _SPARC_Counter_read_default( void ); + +CPU_Counter_ticks _SPARC_Counter_read_clock_isr_disabled( void ); + +CPU_Counter_ticks _SPARC_Counter_read_clock( void ); + +uint32_t _SPARC_Get_timecount_clock( struct timecounter * ); + +typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void ); + +/* + * The SPARC processors supported by RTEMS have no built-in CPU counter + * support. We have to use some hardware counter module for this purpose, for + * example the GPTIMER instance used by the clock driver. The BSP must provide + * an implementation of the CPU counter read function. This allows the use of + * dynamic hardware enumeration. + */ +typedef struct { + SPARC_Counter_read read_isr_disabled; + SPARC_Counter_read read; + volatile const CPU_Counter_ticks *counter_register; + volatile const uint32_t *pending_register; + uint32_t pending_mask; + CPU_Counter_ticks accumulated; + CPU_Counter_ticks interval; +} SPARC_Counter; + +extern SPARC_Counter _SPARC_Counter; + +#define SPARC_COUNTER_DEFINITION \ + SPARC_Counter _SPARC_Counter = { \ + .read_isr_disabled = _SPARC_Counter_read_default, \ + .read = _SPARC_Counter_read_default \ + } + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _BSP_SPARC_COUNTER_H */ diff --git a/bsps/sparc/include/drvmgr/leon2_amba_bus.h b/bsps/sparc/include/drvmgr/leon2_amba_bus.h index 1b35413c30..0dea2a9426 100644 --- a/bsps/sparc/include/drvmgr/leon2_amba_bus.h +++ b/bsps/sparc/include/drvmgr/leon2_amba_bus.h @@ -1,5 +1,15 @@ -/* LEON2 Hardcoded bus driver interface. +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON2 * + * @brief This header file provides interfaces of the + * LEON2 Hardcoded bus driver. + */ + +/* * COPYRIGHT (c) 2008. * Cobham Gaisler AB. * @@ -11,9 +21,26 @@ * A Core is described by assigning a base register and * IRQ0..IRQ15 using the leon2_core structure. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __LEON2_AMBA_BUS_H__ diff --git a/bsps/sparc/include/grlib/io.h b/bsps/sparc/include/grlib/io.h new file mode 100644 index 0000000000..3035859d11 --- /dev/null +++ b/bsps/sparc/include/grlib/io.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief This header file defines the register load/store interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/sparc/if/grlib-io-header */ + +#ifndef _GRLIB_IO_H +#define _GRLIB_IO_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/sparc/if/grlib-io-group */ + +/** + * @defgroup RTEMSDeviceGRLIBIO Register Load/Store + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRLIB register load/store API. + */ + +/* Generated from spec:/bsp/sparc/if/grlib-load-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint8_t grlib_load_8( const volatile uint8_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-load-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint16_t grlib_load_16( const volatile uint16_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-load-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint32_t grlib_load_32( const volatile uint32_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-load-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint64_t grlib_load_64( const volatile uint64_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_8( volatile uint8_t *address, uint8_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_16( volatile uint16_t *address, uint16_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_32( volatile uint32_t *address, uint32_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_64( volatile uint64_t *address, uint64_t value ) +{ + *address = value; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_IO_H */ diff --git a/bsps/sparc/leon2/clock/ckinit.c b/bsps/sparc/leon2/clock/ckinit.c index 8b6ce9a00b..3aad931218 100644 --- a/bsps/sparc/leon2/clock/ckinit.c +++ b/bsps/sparc/leon2/clock/ckinit.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup RTEMSBSPsSPARCLEON2 @@ -17,16 +19,33 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> #include <bspopts.h> #include <rtems/sysinit.h> #include <rtems/timecounter.h> -#include <rtems/score/sparcimpl.h> +#include <bsp/sparc-counter.h> extern int CLOCK_SPEED; @@ -51,7 +70,7 @@ static void leon2_clock_at_tick( void ) SPARC_Counter *counter; rtems_interrupt_level level; - counter = &_SPARC_Counter_mutable; + counter = &_SPARC_Counter; rtems_interrupt_local_disable(level); LEON_Clear_interrupt( LEON_INTERRUPT_TIMER1 ); @@ -72,7 +91,7 @@ static void leon2_clock_initialize_early( void ) LEON_REG_TIMER_COUNTER_LOAD_COUNTER ); - counter = &_SPARC_Counter_mutable; + counter = &_SPARC_Counter; counter->read_isr_disabled = _SPARC_Counter_read_clock_isr_disabled; counter->read = _SPARC_Counter_read_clock; counter->counter_register = &LEON_REG.Timer_Counter_1; @@ -88,7 +107,7 @@ RTEMS_SYSINIT_ITEM( RTEMS_SYSINIT_ORDER_FIRST ); -uint32_t _CPU_Counter_frequency(void) +uint32_t _CPU_Counter_frequency( void ) { return LEON2_TIMER_1_FREQUENCY; } @@ -102,7 +121,7 @@ uint32_t _CPU_Counter_frequency(void) NULL \ ) -#define Clock_driver_support_at_tick() leon2_clock_at_tick() +#define Clock_driver_support_at_tick(arg) leon2_clock_at_tick() #define Clock_driver_support_initialize_hardware() leon2_clock_init() diff --git a/bsps/sparc/leon2/console/console.c b/bsps/sparc/leon2/console/console.c index 579792a06a..063afac178 100644 --- a/bsps/sparc/leon2/console/console.c +++ b/bsps/sparc/leon2/console/console.c @@ -327,7 +327,7 @@ rtems_device_driver console_open( NULL, /* setAttributes */ NULL, /* stopRemoteTx */ NULL, /* startRemoteTx */ - 0 /* outputUsesInterrupts */ + TERMIOS_POLLED /* outputUsesInterrupts */ }; #else static const rtems_termios_callbacks pollCallbacks = { @@ -338,7 +338,7 @@ rtems_device_driver console_open( NULL, /* setAttributes */ NULL, /* stopRemoteTx */ NULL, /* startRemoteTx */ - 0 /* outputUsesInterrupts */ + TERMIOS_POLLED /* outputUsesInterrupts */ }; #endif diff --git a/bsps/sparc/leon2/include/bsp.h b/bsps/sparc/leon2/include/bsp.h index 510262206b..67601d2351 100644 --- a/bsps/sparc/leon2/include/bsp.h +++ b/bsps/sparc/leon2/include/bsp.h @@ -129,7 +129,7 @@ typedef void (*bsp_shared_isr)(void *arg); * isr Function pointer to the ISR * arg Second argument to function isr */ -static __inline__ int BSP_shared_interrupt_register +RTEMS_DEPRECATED static inline int BSP_shared_interrupt_register ( int irq, const char *info, @@ -148,7 +148,7 @@ static __inline__ int BSP_shared_interrupt_register * isr Function pointer to the ISR * arg Second argument to function isr */ -static __inline__ int BSP_shared_interrupt_unregister +RTEMS_DEPRECATED static inline int BSP_shared_interrupt_unregister ( int irq, bsp_shared_isr isr, @@ -166,7 +166,10 @@ static __inline__ int BSP_shared_interrupt_unregister * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_clear(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_clear( int irq ) +{ + (void) rtems_interrupt_clear( (rtems_vector_number) irq ); +} /* Enable Interrupt. This function will unmask the IRQ at the interrupt * controller. This is normally done by _register(). Note that this will @@ -175,7 +178,10 @@ extern void BSP_shared_interrupt_clear(int irq); * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_unmask(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_unmask( int irq ) +{ + (void) rtems_interrupt_vector_enable( (rtems_vector_number) irq ); +} /* Disable Interrupt. This function will mask one IRQ at the interrupt * controller. This is normally done by _unregister(). Note that this will @@ -184,7 +190,10 @@ extern void BSP_shared_interrupt_unmask(int irq); * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_mask(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_mask( int irq ) +{ + (void) rtems_interrupt_vector_disable( (rtems_vector_number) irq ); +} /* * Delay method diff --git a/bsps/sparc/leon2/include/bsp/at697_pci.h b/bsps/sparc/leon2/include/bsp/at697_pci.h index 9a511ec6f9..6a3e0d0a60 100644 --- a/bsps/sparc/leon2/include/bsp/at697_pci.h +++ b/bsps/sparc/leon2/include/bsp/at697_pci.h @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* AT697 PCI host bridge driver * * COPYRIGHT (c) 2015. * Cobham Gaisler. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * */ diff --git a/bsps/sparc/leon2/include/bsp/irq.h b/bsps/sparc/leon2/include/bsp/irq.h index a4ce3c55ff..8fd264e360 100644 --- a/bsps/sparc/leon2/include/bsp/irq.h +++ b/bsps/sparc/leon2/include/bsp/irq.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup RTEMSBSPsSPARCLEON2 @@ -10,9 +12,26 @@ * Copyright (c) 2012. * Aeroflex Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_LEON2_IRQ_CONFIG_H diff --git a/bsps/sparc/leon2/include/bsp/irqimpl.h b/bsps/sparc/leon2/include/bsp/irqimpl.h new file mode 100644 index 0000000000..868822f3aa --- /dev/null +++ b/bsps/sparc/leon2/include/bsp/irqimpl.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON2 + * + * @brief This header file provides interfaces used by the interrupt support + * implementation. + */ + +/* + * Copyright (C) 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H +#define LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup RTEMSBSPsSPARCLEON2 + * + * @{ + */ + +static inline uint32_t bsp_irq_fixup( uint32_t irq ) +{ + return irq; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H */ diff --git a/bsps/sparc/leon2/include/leon.h b/bsps/sparc/leon2/include/leon.h index 11196aee6d..8f2d807eb4 100644 --- a/bsps/sparc/leon2/include/leon.h +++ b/bsps/sparc/leon2/include/leon.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -24,9 +26,26 @@ * COPYRIGHT (c) 1989-1998. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * Ported to LEON implementation of the SPARC by On-Line Applications * Research Corporation (OAR) under contract to the European Space @@ -273,11 +292,6 @@ typedef struct { extern LEON_Register_Map LEON_REG; -static __inline__ int bsp_irq_fixup(int irq) -{ - return irq; -} - /* * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, * and the Interrupt Pending Registers. diff --git a/bsps/sparc/leon2/include/tm27.h b/bsps/sparc/leon2/include/tm27.h index 8d29607c86..06e5151e73 100644 --- a/bsps/sparc/leon2/include/tm27.h +++ b/bsps/sparc/leon2/include/tm27.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup RTEMSBSPsSPARCLEON2 @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2006. * Aeroflex Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_TMTEST27 @@ -40,6 +59,8 @@ #define MUST_WAIT_FOR_INTERRUPT 1 +#define TM27_USE_VECTOR_HANDLER + #define Install_tm27_vector( handler ) \ set_vector( (handler), TEST_VECTOR, 1 ); @@ -60,22 +81,20 @@ #define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1 #define MUST_WAIT_FOR_INTERRUPT 1 -static inline void Install_tm27_vector( - void ( *handler )( rtems_vector_number ) -) +static inline void Install_tm27_vector( rtems_interrupt_handler handler ) { (void) rtems_interrupt_handler_install( TEST_INTERRUPT_SOURCE, "tm27 low", RTEMS_INTERRUPT_SHARED, - (rtems_interrupt_handler) handler, + handler, NULL ); (void) rtems_interrupt_handler_install( TEST_INTERRUPT_SOURCE2, "tm27 high", RTEMS_INTERRUPT_SHARED, - (rtems_interrupt_handler) handler, + handler, NULL ); } diff --git a/bsps/sparc/leon2/pci/at697_pci.c b/bsps/sparc/leon2/pci/at697_pci.c index 40ba93d0f7..12cb79b38e 100644 --- a/bsps/sparc/leon2/pci/at697_pci.c +++ b/bsps/sparc/leon2/pci/at697_pci.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* LEON2 AT697 PCI Host Driver. * * COPYRIGHT (c) 2008. @@ -11,9 +13,26 @@ * default taken from Plug and Play, but may be overridden by the * driver resources INTA#..INTD#. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ /* Configurable parameters diff --git a/bsps/sparc/leon2/start/bspstart.c b/bsps/sparc/leon2/start/bspstart.c index e90cfad5a8..56491ff2fd 100644 --- a/bsps/sparc/leon2/start/bspstart.c +++ b/bsps/sparc/leon2/start/bspstart.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup RTEMSBSPsSPARCLEON2 @@ -13,9 +15,26 @@ * COPYRIGHT (c) 1989-2009. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * Ported to ERC32 implementation of the SPARC by On-Line Applications * Research Corporation (OAR) under contract to the European Space @@ -27,6 +46,7 @@ #include <bsp.h> #include <bsp/bootcard.h> +#include <bsp/irq-generic.h> #include <rtems/sysinit.h> /* diff --git a/bsps/sparc/leon3/btimer/btimer.c b/bsps/sparc/leon3/btimer/btimer.c index 9e9f2b02fc..9f2a7ede74 100644 --- a/bsps/sparc/leon3/btimer/btimer.c +++ b/bsps/sparc/leon3/btimer/btimer.c @@ -33,23 +33,21 @@ bool benchmark_timer_find_average_overhead; bool benchmark_timer_is_initialized = false; -extern volatile struct gptimer_regs *LEON3_Timer_Regs; - void benchmark_timer_initialize(void) { /* * Timer runs long and accurate enough not to require an interrupt. */ if (LEON3_Timer_Regs) { + gptimer_timer *timer = &LEON3_Timer_Regs->timer[LEON3_TIMER_INDEX]; if ( benchmark_timer_is_initialized == false ) { /* approximately 1 us per countdown */ - LEON3_Timer_Regs->timer[LEON3_TIMER_INDEX].reload = 0xffffff; - LEON3_Timer_Regs->timer[LEON3_TIMER_INDEX].value = 0xffffff; + grlib_store_32( &timer->trldval, 0xffffff ); + grlib_store_32( &timer->tcntval, 0xffffff ); } else { benchmark_timer_is_initialized = true; } - LEON3_Timer_Regs->timer[LEON3_TIMER_INDEX].ctrl = - GPTIMER_TIMER_CTRL_EN | GPTIMER_TIMER_CTRL_LD; + grlib_store_32( &timer->tctrl, GPTIMER_TCTRL_EN | GPTIMER_TCTRL_LD ); } } @@ -62,7 +60,8 @@ benchmark_timer_t benchmark_timer_read(void) uint32_t total; if (LEON3_Timer_Regs) { - total = LEON3_Timer_Regs->timer[LEON3_TIMER_INDEX].value; + total = + grlib_load_32( &LEON3_Timer_Regs->timer[LEON3_TIMER_INDEX].tcntval ); total = 0xffffff - total; diff --git a/bsps/sparc/leon3/btimer/watchdog.c b/bsps/sparc/leon3/btimer/watchdog.c index 4e8f428f78..919744496f 100644 --- a/bsps/sparc/leon3/btimer/watchdog.c +++ b/bsps/sparc/leon3/btimer/watchdog.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GPTIMER Watchdog timer routines. On some systems the first GPTIMER * core's last Timer instance underflow signal is connected to system * reset. @@ -5,20 +7,35 @@ * COPYRIGHT (c) 2012. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> +#include <bsp/leon3.h> #include <bsp/watchdog.h> -#include <grlib/grlib.h> - -extern volatile struct gptimer_regs *LEON3_Timer_Regs; struct gptimer_watchdog_priv { - struct gptimer_regs *regs; - struct gptimer_timer_regs *timer; + gptimer *regs; + gptimer_timer *timer; int timerno; }; @@ -41,10 +58,10 @@ int bsp_watchdog_init(void) * functionality is available or not, we assume that it is if we * reached this function. */ - bsp_watchdogs[0].regs = (struct gptimer_regs *)LEON3_Timer_Regs; + bsp_watchdogs[0].regs = LEON3_Timer_Regs; /* Find Timer that has watchdog functionality */ - timercnt = bsp_watchdogs[0].regs->cfg & 0x7; + timercnt = grlib_load_32(&bsp_watchdogs[0].regs->config) & 0x7; if (timercnt < 2) /* First timer system clock timer */ return 0; @@ -57,6 +74,9 @@ int bsp_watchdog_init(void) void bsp_watchdog_reload(int watchdog, unsigned int reload_value) { + gptimer_timer *timer; + uint32_t tctrl; + if (bsp_watchdog_count == 0) bsp_watchdog_init(); @@ -64,10 +84,12 @@ void bsp_watchdog_reload(int watchdog, unsigned int reload_value) return; /* Kick watchdog, and clear interrupt pending bit */ - bsp_watchdogs[watchdog].timer->reload = reload_value; - bsp_watchdogs[watchdog].timer->ctrl = - (GPTIMER_TIMER_CTRL_LD | GPTIMER_TIMER_CTRL_EN) | - (bsp_watchdogs[watchdog].timer->ctrl & ~(1<<4)); + timer = bsp_watchdogs[watchdog].timer; + grlib_store_32(&timer->trldval, reload_value); + tctrl = grlib_load_32(&timer->tctrl); + tctrl |= GPTIMER_TCTRL_LD | GPTIMER_TCTRL_EN; + tctrl &= ~GPTIMER_TCTRL_IP; + grlib_store_32(&timer->tctrl, tctrl); } void bsp_watchdog_stop(int watchdog) @@ -79,7 +101,7 @@ void bsp_watchdog_stop(int watchdog) return; /* Stop watchdog timer */ - bsp_watchdogs[watchdog].timer->ctrl = 0; + grlib_store_32(&bsp_watchdogs[watchdog].timer->tctrl, 0); } /* Use watchdog timer to reset system */ diff --git a/bsps/sparc/leon3/clock/ckinit.c b/bsps/sparc/leon3/clock/ckinit.c index 69afb25f3c..503cb28bab 100644 --- a/bsps/sparc/leon3/clock/ckinit.c +++ b/bsps/sparc/leon3/clock/ckinit.c @@ -1,11 +1,14 @@ -/* - * Clock Tick Device Driver - * - * This routine initializes LEON timer 1 which used for the clock tick. +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file * - * The tick frequency is directly programmed to the configured number of - * microseconds per tick. + * @ingroup RTEMSBSPsSPARCLEON3 * + * @brief This source file contains the Clock Driver implementation. + */ + +/* * COPYRIGHT (c) 1989-2006. * On-Line Applications Research Corporation (OAR). * @@ -13,21 +16,36 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * Copyright (c) 2014, 2018 embedded brains GmbH + * Copyright (C) 2014, 2023 embedded brains GmbH & Co. KG * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> -#include <bsp/irq.h> -#include <bspopts.h> #include <bsp/fatal.h> -#include <rtems/rtems/intr.h> -#include <grlib/ambapp.h> +#include <bsp/irq-generic.h> +#include <bsp/leon3.h> +#include <grlib/irqamp.h> #include <rtems/score/profiling.h> -#include <rtems/score/sparcimpl.h> #include <rtems/timecounter.h> /* The LEON3 BSP Timer driver can rely on the Driver Manager if the @@ -41,31 +59,45 @@ /* LEON3 Timer system interrupt number */ static int clkirq; -static void (*leon3_tc_tick)(void); +#if defined(RTEMS_PROFILING) && \ + (defined(LEON3_HAS_ASR_22_23_UP_COUNTER) || \ + defined(LEON3_PROBE_ASR_22_23_UP_COUNTER) || \ + defined(LEON3_IRQAMP_PROBE_TIMESTAMP)) -static struct timecounter leon3_tc; +#define LEON3_CLOCK_PROBE_IRQAMP_TIMESTAMP -#ifdef RTEMS_PROFILING #define IRQMP_TIMESTAMP_S1_S2 ((1U << 25) | (1U << 26)) +static void leon3_tc_tick_default(void) +{ + rtems_timecounter_tick(); +} + +static void (*leon3_tc_tick)(void) = leon3_tc_tick_default; + +static void leon3_tc_do_tick(void) +{ + (*leon3_tc_tick)(); +} + static void leon3_tc_tick_irqmp_timestamp(void) { - volatile struct irqmp_timestamp_regs *irqmp_ts = - &LEON3_IrqCtrl_Regs->timestamp[0]; - unsigned int first = irqmp_ts->assertion; - unsigned int second = irqmp_ts->counter; + irqamp_timestamp *irqmp_ts = + irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs); + uint32_t first = grlib_load_32(&irqmp_ts->itstmpas); + uint32_t second = grlib_load_32(&irqmp_ts->itcnt); + uint32_t control = grlib_load_32(&irqmp_ts->itstmpc); - irqmp_ts->control |= IRQMP_TIMESTAMP_S1_S2; + control |= IRQMP_TIMESTAMP_S1_S2; + grlib_store_32(&irqmp_ts->itstmpc, control); _Profiling_Update_max_interrupt_delay(_Per_CPU_Get(), second - first); rtems_timecounter_tick(); } -#endif static void leon3_tc_tick_irqmp_timestamp_init(void) { -#ifdef RTEMS_PROFILING /* * Ignore the first clock interrupt, since it contains the sequential system * initialization time. Do the timestamp initialization on the fly. @@ -81,42 +113,26 @@ static void leon3_tc_tick_irqmp_timestamp_init(void) bool done = true; #endif - volatile struct irqmp_timestamp_regs *irqmp_ts = - &LEON3_IrqCtrl_Regs->timestamp[0]; - unsigned int ks = 1U << 5; + irqamp_timestamp *irqmp_ts = + irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs); + uint32_t ks = 1U << 5; + uint32_t control = grlib_load_32(&irqmp_ts->itstmpc); - irqmp_ts->control = ks | IRQMP_TIMESTAMP_S1_S2 | (unsigned int) clkirq; + control = ks | IRQMP_TIMESTAMP_S1_S2 | (unsigned int) clkirq; + grlib_store_32(&irqmp_ts->itstmpc, control); if (done) { leon3_tc_tick = leon3_tc_tick_irqmp_timestamp; } -#endif rtems_timecounter_tick(); } - -static void leon3_tc_tick_default(void) -{ -#ifndef RTEMS_SMP - SPARC_Counter *counter; - rtems_interrupt_level level; - - counter = &_SPARC_Counter_mutable; - rtems_interrupt_local_disable(level); - - LEON3_IrqCtrl_Regs->iclear = counter->pending_mask; - counter->accumulated += counter->interval; - - rtems_interrupt_local_enable(level); -#endif - - rtems_timecounter_tick(); -} - +#else static void leon3_tc_do_tick(void) { - (*leon3_tc_tick)(); + rtems_timecounter_tick(); } +#endif #define Adjust_clkirq_for_node() do { clkirq += LEON3_CLOCK_INDEX; } while(0) @@ -124,7 +140,7 @@ static void leon3_tc_do_tick(void) do { \ /* Assume timer found during BSP initialization */ \ if (LEON3_Timer_Regs) { \ - clkirq = (LEON3_Timer_Regs->cfg & 0xf8) >> 3; \ + clkirq = (grlib_load_32(&LEON3_Timer_Regs->config) & 0xf8) >> 3; \ \ Adjust_clkirq_for_node(); \ } \ @@ -160,88 +176,35 @@ static void bsp_clock_handler_install(rtems_interrupt_handler isr) static void leon3_clock_initialize(void) { - volatile struct irqmp_timestamp_regs *irqmp_ts; - volatile struct gptimer_regs *gpt; - struct timecounter *tc; - - irqmp_ts = &LEON3_IrqCtrl_Regs->timestamp[0]; - gpt = LEON3_Timer_Regs; - tc = &leon3_tc; - - gpt->timer[LEON3_CLOCK_INDEX].reload = - rtems_configuration_get_microseconds_per_tick() - 1; - gpt->timer[LEON3_CLOCK_INDEX].ctrl = - GPTIMER_TIMER_CTRL_EN | GPTIMER_TIMER_CTRL_RS | - GPTIMER_TIMER_CTRL_LD | GPTIMER_TIMER_CTRL_IE; - - leon3_up_counter_enable(); - - if (leon3_up_counter_is_available()) { - /* Use the LEON4 up-counter if available */ - tc->tc_get_timecount = _SPARC_Get_timecount_asr23; - tc->tc_frequency = leon3_up_counter_frequency(); - -#ifdef RTEMS_PROFILING - if (!irqmp_has_timestamp(irqmp_ts)) { - bsp_fatal(LEON3_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT); - } -#endif + gptimer_timer *timer; - leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init; - } else if (irqmp_has_timestamp(irqmp_ts)) { - /* Use the interrupt controller timestamp counter if available */ - tc->tc_get_timecount = _SPARC_Get_timecount_up; - tc->tc_frequency = ambapp_freq_get(ambapp_plb(), LEON3_Timer_Adev); - - leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init; + timer = &LEON3_Timer_Regs->timer[LEON3_CLOCK_INDEX]; - /* - * At least one TSISEL field must be non-zero to enable the timestamp - * counter. Use an arbitrary interrupt source. - */ - irqmp_ts->control = 0x1; - } else { -#ifdef RTEMS_SMP - /* - * The GR712RC for example has no timestamp unit in the interrupt - * controller. At least on SMP configurations we must use a second timer - * in free running mode for the timecounter. - */ - gpt->timer[LEON3_COUNTER_GPTIMER_INDEX].ctrl = - GPTIMER_TIMER_CTRL_EN | GPTIMER_TIMER_CTRL_IE; - - tc->tc_get_timecount = _SPARC_Get_timecount_down; -#else - SPARC_Counter *counter; - - counter = &_SPARC_Counter_mutable; - counter->read_isr_disabled = _SPARC_Counter_read_clock_isr_disabled; - counter->read = _SPARC_Counter_read_clock; - counter->counter_register = &gpt->timer[LEON3_CLOCK_INDEX].value; - counter->pending_register = &LEON3_IrqCtrl_Regs->ipend; - counter->pending_mask = UINT32_C(1) << clkirq; - counter->accumulated = rtems_configuration_get_microseconds_per_tick(); - counter->interval = rtems_configuration_get_microseconds_per_tick(); - - tc->tc_get_timecount = _SPARC_Get_timecount_clock; -#endif + grlib_store_32( + &timer->trldval, + rtems_configuration_get_microseconds_per_tick() - 1 + ); + grlib_store_32( + &timer->tctrl, + GPTIMER_TCTRL_EN | GPTIMER_TCTRL_RS | GPTIMER_TCTRL_LD | GPTIMER_TCTRL_IE + ); - tc->tc_frequency = LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER, - leon3_tc_tick = leon3_tc_tick_default; +#if defined(LEON3_CLOCK_PROBE_IRQAMP_TIMESTAMP) + if (irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs) != NULL) { + leon3_tc_tick = leon3_tc_tick_irqmp_timestamp_init; } +#endif - tc->tc_counter_mask = 0xffffffff; - tc->tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; - rtems_timecounter_install(tc); + rtems_timecounter_install(&leon3_timecounter_instance.base); } #define Clock_driver_support_initialize_hardware() \ leon3_clock_initialize() -#define Clock_driver_timecounter_tick() leon3_tc_do_tick() +#define Clock_driver_timecounter_tick(arg) leon3_tc_do_tick() #define BSP_FEATURE_IRQ_EXTENSION #include "../../../shared/dev/clock/clockimpl.h" -#endif +#endif /* RTEMS_DRVMGR_STARTUP */ diff --git a/bsps/sparc/leon3/console/console.c b/bsps/sparc/leon3/console/console.c index 153907840f..891116b2c4 100644 --- a/bsps/sparc/leon3/console/console.c +++ b/bsps/sparc/leon3/console/console.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * This file contains the TTY driver for the serial ports on the LEON. * @@ -10,9 +12,26 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ /* Define CONSOLE_USE_INTERRUPTS to enable APBUART interrupt handling instead @@ -62,7 +81,7 @@ static int find_matching_apbuart(struct ambapp_dev *dev, int index, void *arg) struct ambapp_apb_info *apb = (struct ambapp_apb_info *)dev->devinfo; /* Extract needed information of one APBUART */ - apbuarts[uarts].regs = (struct apbuart_regs *)apb->start; + apbuarts[uarts].regs = (apbuart *)apb->start; apbuarts[uarts].irq = apb->common.irq; /* Get APBUART core frequency, it is assumed that it is the same * as Bus frequency where the UART is situated diff --git a/bsps/sparc/leon3/console/printk_support.c b/bsps/sparc/leon3/console/printk_support.c index f9cf0b7520..fd23a5033f 100644 --- a/bsps/sparc/leon3/console/printk_support.c +++ b/bsps/sparc/leon3/console/printk_support.c @@ -1,8 +1,15 @@ -/* - * This file contains the TTY driver for the serial ports on the LEON. +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file * - * This driver uses the termios pseudo driver. + * @ingroup RTEMSBSPsSPARCLEON3 * + * @brief This source file contains the definition of ::BSP_output_char and + * ::BSP_poll_char. + */ + +/* * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). * @@ -10,26 +17,53 @@ * COPYRIGHT (c) 2011. * Aeroflex Gaisler. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> -#include <leon.h> +#include <bsp/leon3.h> #include <rtems/bspIo.h> #include <rtems/sysinit.h> -#include <rtems/score/thread.h> #include <grlib/apbuart.h> +#include <grlib/io.h> + +#if !defined(LEON3_APBUART_BASE) +#include <grlib/ambapp.h> int leon3_debug_uart_index __attribute__((weak)) = 0; -struct apbuart_regs *leon3_debug_uart = NULL; + +apbuart *leon3_debug_uart = NULL; +#endif static void bsp_debug_uart_init(void); -static void bsp_debug_uart_discard(char c) +static void apbuart_enable_receive_and_transmit(apbuart *regs) { - (void) c; + uint32_t ctrl; + + ctrl = grlib_load_32(®s->ctrl); + ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; + grlib_store_32(®s->ctrl, ctrl); + grlib_store_32(®s->status, 0); } static void bsp_debug_uart_output_char(char c) @@ -49,6 +83,22 @@ static void bsp_debug_uart_pre_init_out(char c) (*BSP_output_char)(c); } +#if defined(LEON3_APBUART_BASE) + +static void bsp_debug_uart_init(void) +{ + apbuart_enable_receive_and_transmit(leon3_debug_uart); + BSP_poll_char = bsp_debug_uart_poll_char; + BSP_output_char = bsp_debug_uart_output_char; +} + +#else /* !LEON3_APBUART_BASE */ + +static void bsp_debug_uart_discard(char c) +{ + (void) c; +} + /* Initialize the BSP system debug console layer. It will scan AMBA Plu&Play * for a debug APBUART and enable RX/TX for that UART. */ @@ -92,15 +142,16 @@ static void bsp_debug_uart_init(void) * printk(). */ apb = (struct ambapp_apb_info *)adev->devinfo; - leon3_debug_uart = (struct apbuart_regs *)apb->start; - leon3_debug_uart->ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; - leon3_debug_uart->status = 0; + leon3_debug_uart = (apbuart *)apb->start; + apbuart_enable_receive_and_transmit(leon3_debug_uart); BSP_poll_char = bsp_debug_uart_poll_char; BSP_output_char = bsp_debug_uart_output_char; } } +#endif /* LEON3_APBUART_BASE */ + RTEMS_SYSINIT_ITEM( bsp_debug_uart_init, RTEMS_SYSINIT_BSP_START, diff --git a/bsps/sparc/leon3/gnatsupp/gnatsupp.c b/bsps/sparc/leon3/gnatsupp/gnatsupp.c index cc5b1027a7..79e68eab7c 100644 --- a/bsps/sparc/leon3/gnatsupp/gnatsupp.c +++ b/bsps/sparc/leon3/gnatsupp/gnatsupp.c @@ -1,7 +1,7 @@ /** * @file * - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * * @brief Support for gnat/rtems interrupts and exception handling */ diff --git a/bsps/sparc/leon3/include/amba.h b/bsps/sparc/leon3/include/amba.h index 1492661fa5..636187bb23 100644 --- a/bsps/sparc/leon3/include/amba.h +++ b/bsps/sparc/leon3/include/amba.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -12,9 +14,26 @@ * COPYRIGHT (c) 2004. * Gaisler Research * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AMBA_H__ diff --git a/bsps/sparc/leon3/include/bsp.h b/bsps/sparc/leon3/include/bsp.h index d47f5d2cdf..ae48d3fd4e 100644 --- a/bsps/sparc/leon3/include/bsp.h +++ b/bsps/sparc/leon3/include/bsp.h @@ -148,7 +148,7 @@ typedef void (*bsp_shared_isr)(void *arg); * isr Function pointer to the ISR * arg Second argument to function isr */ -static __inline__ int BSP_shared_interrupt_register +RTEMS_DEPRECATED static inline int BSP_shared_interrupt_register ( int irq, const char *info, @@ -167,7 +167,7 @@ static __inline__ int BSP_shared_interrupt_register * isr Function pointer to the ISR * arg Second argument to function isr */ -static __inline__ int BSP_shared_interrupt_unregister +RTEMS_DEPRECATED static inline int BSP_shared_interrupt_unregister ( int irq, bsp_shared_isr isr, @@ -185,7 +185,10 @@ static __inline__ int BSP_shared_interrupt_unregister * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_clear(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_clear( int irq ) +{ + (void) rtems_interrupt_clear( (rtems_vector_number) irq ); +} /* Enable Interrupt. This function will unmask the IRQ at the interrupt * controller. This is normally done by _register(). Note that this will @@ -194,7 +197,10 @@ extern void BSP_shared_interrupt_clear(int irq); * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_unmask(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_unmask( int irq ) +{ + (void) rtems_interrupt_vector_enable( (rtems_vector_number) irq ); +} /* Disable Interrupt. This function will mask one IRQ at the interrupt * controller. This is normally done by _unregister(). Note that this will @@ -203,7 +209,10 @@ extern void BSP_shared_interrupt_unmask(int irq); * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_mask(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_mask( int irq ) +{ + (void) rtems_interrupt_vector_disable( (rtems_vector_number) irq ); +} #if defined(RTEMS_SMP) || defined(RTEMS_MULTIPROCESSING) /* Irq used by the shared memory driver and for inter-processor interrupts. diff --git a/bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h b/bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h new file mode 100644 index 0000000000..33fb71aaab --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsGR740Bootstrap + * + * @brief This header file defines the GR740 Boostrap Signals register block + * interface. + */ + +/* + * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-bootstrap-header */ + +#ifndef _BSP_GR740_BOOTSTRAP_REGS_H +#define _BSP_GR740_BOOTSTRAP_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-bootstrap */ + +/** + * @defgroup RTEMSBSPsGR740Bootstrap GR740 Bootstrap Signals + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This group contains the GR740 Bootstrap Signals interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSBSPsGR740BootstrapBOOTSTRAP Bootstrap register (BOOTSTRAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_BOOTSTRAP_BOOTSTRAP_B10 0x2000000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B9 0x1000000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B8 0x800000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B7 0x400000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B6 0x200000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B5 0x100000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B4 0x80000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B3 0x40000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B2 0x20000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B1 0x10000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT 0 +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK 0xffffU +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_GET( _reg ) \ + ( ( ( _reg ) & GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) >> \ + GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT ) +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) | \ + ( ( ( _val ) << GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT ) & \ + GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) ) +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO( _val ) \ + ( ( ( _val ) << GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT ) & \ + GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GR740 Bootstrap Signals register block + * memory map. + */ +typedef struct gr740_bootstrap { + /** + * @brief See @ref RTEMSBSPsGR740BootstrapBOOTSTRAP. + */ + uint32_t bootstrap; +} gr740_bootstrap; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_GR740_BOOTSTRAP_REGS_H */ diff --git a/bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h b/bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h new file mode 100644 index 0000000000..1614ebba8a --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h @@ -0,0 +1,679 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsGR740IOPLL + * + * @brief This header file defines the GR740 I/O and PLL configuration register + * block interface. + */ + +/* + * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll-header */ + +#ifndef _BSP_GR740_IOPLL_REGS_H +#define _BSP_GR740_IOPLL_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll */ + +/** + * @defgroup RTEMSBSPsGR740IOPLL GR740 I/0 and PLL Configuration + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This group contains the GR740 I/0 and PLL Configuration interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLFTMFUNC \ + * FTMCTRL function enable register (FTMFUNC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_FTMFUNC_FTMEN_SHIFT 0 +#define GR740_IOPLL_FTMFUNC_FTMEN_MASK 0x3fffffU +#define GR740_IOPLL_FTMFUNC_FTMEN_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_FTMFUNC_FTMEN_MASK ) >> \ + GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) +#define GR740_IOPLL_FTMFUNC_FTMEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_FTMFUNC_FTMEN_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \ + GR740_IOPLL_FTMFUNC_FTMEN_MASK ) ) +#define GR740_IOPLL_FTMFUNC_FTMEN( _val ) \ + ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \ + GR740_IOPLL_FTMFUNC_FTMEN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLALTFUNC \ + * Alternative function enable register (ALTFUNC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_ALTFUNC_ALTEN_SHIFT 0 +#define GR740_IOPLL_ALTFUNC_ALTEN_MASK 0x3fffffU +#define GR740_IOPLL_ALTFUNC_ALTEN_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_ALTFUNC_ALTEN_MASK ) >> \ + GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) +#define GR740_IOPLL_ALTFUNC_ALTEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_ALTFUNC_ALTEN_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \ + GR740_IOPLL_ALTFUNC_ALTEN_MASK ) ) +#define GR740_IOPLL_ALTFUNC_ALTEN( _val ) \ + ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \ + GR740_IOPLL_ALTFUNC_ALTEN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLLVDSMCLK \ + * LVDS and memory clock pad enable register (LVDSMCLK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_LVDSMCLK_SMEM 0x20000U + +#define GR740_IOPLL_LVDSMCLK_DMEM 0x10000U + +#define GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT 0 +#define GR740_IOPLL_LVDSMCLK_SPWOE_MASK 0xffU +#define GR740_IOPLL_LVDSMCLK_SPWOE_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) >> \ + GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) +#define GR740_IOPLL_LVDSMCLK_SPWOE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \ + GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) ) +#define GR740_IOPLL_LVDSMCLK_SPWOE( _val ) \ + ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \ + GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLPLLNEWCFG \ + * PLL new configuration register (PLLNEWCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT 27 +#define GR740_IOPLL_PLLNEWCFG_SWTAG_MASK 0x18000000U +#define GR740_IOPLL_PLLNEWCFG_SWTAG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) >> \ + GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) +#define GR740_IOPLL_PLLNEWCFG_SWTAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) ) +#define GR740_IOPLL_PLLNEWCFG_SWTAG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) + +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT 18 +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK 0x7fc0000U +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) + +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT 9 +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK 0x3fe00U +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) + +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT 0 +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK 0x1ffU +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLPLLRECFG \ + * PLL reconfigure command register (PLLRECFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_PLLRECFG_RECONF_SHIFT 0 +#define GR740_IOPLL_PLLRECFG_RECONF_MASK 0x7U +#define GR740_IOPLL_PLLRECFG_RECONF_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLRECFG_RECONF_MASK ) >> \ + GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) +#define GR740_IOPLL_PLLRECFG_RECONF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLRECFG_RECONF_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \ + GR740_IOPLL_PLLRECFG_RECONF_MASK ) ) +#define GR740_IOPLL_PLLRECFG_RECONF( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \ + GR740_IOPLL_PLLRECFG_RECONF_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLPLLCURCFG \ + * PLL current configuration register (PLLCURCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT 27 +#define GR740_IOPLL_PLLCURCFG_SWTAG_MASK 0x18000000U +#define GR740_IOPLL_PLLCURCFG_SWTAG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) >> \ + GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) +#define GR740_IOPLL_PLLCURCFG_SWTAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) ) +#define GR740_IOPLL_PLLCURCFG_SWTAG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) + +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT 18 +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK 0x7fc0000U +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) + +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT 9 +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK 0x3fe00U +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) + +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT 0 +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK 0x1ffU +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLDRVSTR1 \ + * Drive strength configuration register 1 (DRVSTR1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_DRVSTR1_S9_SHIFT 18 +#define GR740_IOPLL_DRVSTR1_S9_MASK 0xc0000U +#define GR740_IOPLL_DRVSTR1_S9_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S9_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S9_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S9_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S9_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S9_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S9( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S9_MASK ) + +#define GR740_IOPLL_DRVSTR1_S8_SHIFT 16 +#define GR740_IOPLL_DRVSTR1_S8_MASK 0x30000U +#define GR740_IOPLL_DRVSTR1_S8_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S8_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S8_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S8_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S8_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S8_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S8( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S8_MASK ) + +#define GR740_IOPLL_DRVSTR1_S7_SHIFT 14 +#define GR740_IOPLL_DRVSTR1_S7_MASK 0xc000U +#define GR740_IOPLL_DRVSTR1_S7_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S7_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S7_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S7_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S7_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S7_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S7( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S7_MASK ) + +#define GR740_IOPLL_DRVSTR1_S6_SHIFT 12 +#define GR740_IOPLL_DRVSTR1_S6_MASK 0x3000U +#define GR740_IOPLL_DRVSTR1_S6_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S6_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S6_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S6_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S6_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S6_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S6( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S6_MASK ) + +#define GR740_IOPLL_DRVSTR1_S5_SHIFT 10 +#define GR740_IOPLL_DRVSTR1_S5_MASK 0xc00U +#define GR740_IOPLL_DRVSTR1_S5_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S5_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S5_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S5_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S5_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S5_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S5( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S5_MASK ) + +#define GR740_IOPLL_DRVSTR1_S4_SHIFT 8 +#define GR740_IOPLL_DRVSTR1_S4_MASK 0x300U +#define GR740_IOPLL_DRVSTR1_S4_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S4_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S4_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S4_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S4_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S4( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S4_MASK ) + +#define GR740_IOPLL_DRVSTR1_S3_SHIFT 6 +#define GR740_IOPLL_DRVSTR1_S3_MASK 0xc0U +#define GR740_IOPLL_DRVSTR1_S3_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S3_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S3_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S3_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S3_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S3( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S3_MASK ) + +#define GR740_IOPLL_DRVSTR1_S2_SHIFT 4 +#define GR740_IOPLL_DRVSTR1_S2_MASK 0x30U +#define GR740_IOPLL_DRVSTR1_S2_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S2_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S2_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S2_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S2_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S2( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S2_MASK ) + +#define GR740_IOPLL_DRVSTR1_S1_SHIFT 2 +#define GR740_IOPLL_DRVSTR1_S1_MASK 0xcU +#define GR740_IOPLL_DRVSTR1_S1_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S1_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S1_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S1_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S1_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S1( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S1_MASK ) + +#define GR740_IOPLL_DRVSTR1_S0_SHIFT 0 +#define GR740_IOPLL_DRVSTR1_S0_MASK 0x3U +#define GR740_IOPLL_DRVSTR1_S0_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S0_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S0_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S0_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S0_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S0( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLDRVSTR2 \ + * Drive strength configuration register 2 (DRVSTR2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_DRVSTR2_S19_SHIFT 18 +#define GR740_IOPLL_DRVSTR2_S19_MASK 0xc0000U +#define GR740_IOPLL_DRVSTR2_S19_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S19_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S19_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S19_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S19_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S19_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S19( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S19_MASK ) + +#define GR740_IOPLL_DRVSTR2_S18_SHIFT 16 +#define GR740_IOPLL_DRVSTR2_S18_MASK 0x30000U +#define GR740_IOPLL_DRVSTR2_S18_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S18_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S18_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S18_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S18_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S18_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S18( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S18_MASK ) + +#define GR740_IOPLL_DRVSTR2_S17_SHIFT 14 +#define GR740_IOPLL_DRVSTR2_S17_MASK 0xc000U +#define GR740_IOPLL_DRVSTR2_S17_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S17_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S17_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S17_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S17_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S17_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S17( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S17_MASK ) + +#define GR740_IOPLL_DRVSTR2_S16_SHIFT 12 +#define GR740_IOPLL_DRVSTR2_S16_MASK 0x3000U +#define GR740_IOPLL_DRVSTR2_S16_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S16_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S16_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S16_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S16_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S16_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S16( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S16_MASK ) + +#define GR740_IOPLL_DRVSTR2_S15_SHIFT 10 +#define GR740_IOPLL_DRVSTR2_S15_MASK 0xc00U +#define GR740_IOPLL_DRVSTR2_S15_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S15_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S15_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S15_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S15_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S15_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S15( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S15_MASK ) + +#define GR740_IOPLL_DRVSTR2_S14_SHIFT 8 +#define GR740_IOPLL_DRVSTR2_S14_MASK 0x300U +#define GR740_IOPLL_DRVSTR2_S14_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S14_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S14_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S14_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S14_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S14_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S14( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S14_MASK ) + +#define GR740_IOPLL_DRVSTR2_S13_SHIFT 6 +#define GR740_IOPLL_DRVSTR2_S13_MASK 0xc0U +#define GR740_IOPLL_DRVSTR2_S13_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S13_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S13_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S13_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S13_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S13_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S13( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S13_MASK ) + +#define GR740_IOPLL_DRVSTR2_S12_SHIFT 4 +#define GR740_IOPLL_DRVSTR2_S12_MASK 0x30U +#define GR740_IOPLL_DRVSTR2_S12_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S12_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S12_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S12_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S12_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S12_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S12( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S12_MASK ) + +#define GR740_IOPLL_DRVSTR2_S11_SHIFT 2 +#define GR740_IOPLL_DRVSTR2_S11_MASK 0xcU +#define GR740_IOPLL_DRVSTR2_S11_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S11_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S11_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S11_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S11_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S11_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S11( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S11_MASK ) + +#define GR740_IOPLL_DRVSTR2_S10_SHIFT 0 +#define GR740_IOPLL_DRVSTR2_S10_MASK 0x3U +#define GR740_IOPLL_DRVSTR2_S10_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S10_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S10_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S10_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S10_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S10_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S10( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S10_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLLOCKDOWN \ + * Configuration lockdown register (LOCKDOWN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT 16 +#define GR740_IOPLL_LOCKDOWN_PERMANENT_MASK 0xff0000U +#define GR740_IOPLL_LOCKDOWN_PERMANENT_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) >> \ + GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) +#define GR740_IOPLL_LOCKDOWN_PERMANENT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \ + GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) ) +#define GR740_IOPLL_LOCKDOWN_PERMANENT( _val ) \ + ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \ + GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) + +#define GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT 0 +#define GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK 0xffU +#define GR740_IOPLL_LOCKDOWN_REVOCABLE_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) >> \ + GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) +#define GR740_IOPLL_LOCKDOWN_REVOCABLE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \ + GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) ) +#define GR740_IOPLL_LOCKDOWN_REVOCABLE( _val ) \ + ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \ + GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GR740 I/0 and PLL Configuration register + * block memory map. + */ +typedef struct gr740_iopll { + /** + * @brief See @ref RTEMSBSPsGR740IOPLLFTMFUNC. + */ + uint32_t ftmfunc; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLALTFUNC. + */ + uint32_t altfunc; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLLVDSMCLK. + */ + uint32_t lvdsmclk; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLPLLNEWCFG. + */ + uint32_t pllnewcfg; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLPLLRECFG. + */ + uint32_t pllrecfg; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLPLLCURCFG. + */ + uint32_t pllcurcfg; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLDRVSTR1. + */ + uint32_t drvstr1; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLDRVSTR2. + */ + uint32_t drvstr2; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLLOCKDOWN. + */ + uint32_t lockdown; +} gr740_iopll; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_GR740_IOPLL_REGS_H */ diff --git a/bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h b/bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h new file mode 100644 index 0000000000..54f33adaee --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsGR740ThSens + * + * @brief This header file defines the GR740 Temperatur Sensor Controller + * register block interface. + */ + +/* + * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-thsens-header */ + +#ifndef _BSP_GR740_THSENS_REGS_H +#define _BSP_GR740_THSENS_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-thsens */ + +/** + * @defgroup RTEMSBSPsGR740ThSens GR740 Temperatur Sensor Controller + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This group contains the GR740 Temperatur Sensor Controller + * interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSBSPsGR740ThSensCTRL Control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_THSENS_CTRL_DIV_SHIFT 16 +#define GR740_THSENS_CTRL_DIV_MASK 0x3ff0000U +#define GR740_THSENS_CTRL_DIV_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_CTRL_DIV_MASK ) >> \ + GR740_THSENS_CTRL_DIV_SHIFT ) +#define GR740_THSENS_CTRL_DIV_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_CTRL_DIV_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_CTRL_DIV_SHIFT ) & \ + GR740_THSENS_CTRL_DIV_MASK ) ) +#define GR740_THSENS_CTRL_DIV( _val ) \ + ( ( ( _val ) << GR740_THSENS_CTRL_DIV_SHIFT ) & \ + GR740_THSENS_CTRL_DIV_MASK ) + +#define GR740_THSENS_CTRL_ALEN 0x100U + +#define GR740_THSENS_CTRL_PDN 0x80U + +#define GR740_THSENS_CTRL_DCORRECT_SHIFT 2 +#define GR740_THSENS_CTRL_DCORRECT_MASK 0x7cU +#define GR740_THSENS_CTRL_DCORRECT_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_CTRL_DCORRECT_MASK ) >> \ + GR740_THSENS_CTRL_DCORRECT_SHIFT ) +#define GR740_THSENS_CTRL_DCORRECT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_CTRL_DCORRECT_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_CTRL_DCORRECT_SHIFT ) & \ + GR740_THSENS_CTRL_DCORRECT_MASK ) ) +#define GR740_THSENS_CTRL_DCORRECT( _val ) \ + ( ( ( _val ) << GR740_THSENS_CTRL_DCORRECT_SHIFT ) & \ + GR740_THSENS_CTRL_DCORRECT_MASK ) + +#define GR740_THSENS_CTRL_SRSTN 0x2U + +#define GR740_THSENS_CTRL_CLKEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740ThSensSTATUS Status register (STATUS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_THSENS_STATUS_MAX_SHIFT 24 +#define GR740_THSENS_STATUS_MAX_MASK 0x7f000000U +#define GR740_THSENS_STATUS_MAX_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_STATUS_MAX_MASK ) >> \ + GR740_THSENS_STATUS_MAX_SHIFT ) +#define GR740_THSENS_STATUS_MAX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_STATUS_MAX_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_STATUS_MAX_SHIFT ) & \ + GR740_THSENS_STATUS_MAX_MASK ) ) +#define GR740_THSENS_STATUS_MAX( _val ) \ + ( ( ( _val ) << GR740_THSENS_STATUS_MAX_SHIFT ) & \ + GR740_THSENS_STATUS_MAX_MASK ) + +#define GR740_THSENS_STATUS_MIN_SHIFT 16 +#define GR740_THSENS_STATUS_MIN_MASK 0x7f0000U +#define GR740_THSENS_STATUS_MIN_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_STATUS_MIN_MASK ) >> \ + GR740_THSENS_STATUS_MIN_SHIFT ) +#define GR740_THSENS_STATUS_MIN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_STATUS_MIN_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_STATUS_MIN_SHIFT ) & \ + GR740_THSENS_STATUS_MIN_MASK ) ) +#define GR740_THSENS_STATUS_MIN( _val ) \ + ( ( ( _val ) << GR740_THSENS_STATUS_MIN_SHIFT ) & \ + GR740_THSENS_STATUS_MIN_MASK ) + +#define GR740_THSENS_STATUS_SCLK 0x8000U + +#define GR740_THSENS_STATUS_WE 0x400U + +#define GR740_THSENS_STATUS_UPD 0x200U + +#define GR740_THSENS_STATUS_ALACT 0x100U + +#define GR740_THSENS_STATUS_DATA_SHIFT 0 +#define GR740_THSENS_STATUS_DATA_MASK 0x7fU +#define GR740_THSENS_STATUS_DATA_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_STATUS_DATA_MASK ) >> \ + GR740_THSENS_STATUS_DATA_SHIFT ) +#define GR740_THSENS_STATUS_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_STATUS_DATA_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_STATUS_DATA_SHIFT ) & \ + GR740_THSENS_STATUS_DATA_MASK ) ) +#define GR740_THSENS_STATUS_DATA( _val ) \ + ( ( ( _val ) << GR740_THSENS_STATUS_DATA_SHIFT ) & \ + GR740_THSENS_STATUS_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740ThSensTHRES Threshold register (THRES) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_THSENS_THRES_THRES_SHIFT 0 +#define GR740_THSENS_THRES_THRES_MASK 0x7fU +#define GR740_THSENS_THRES_THRES_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_THRES_THRES_MASK ) >> \ + GR740_THSENS_THRES_THRES_SHIFT ) +#define GR740_THSENS_THRES_THRES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_THRES_THRES_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_THRES_THRES_SHIFT ) & \ + GR740_THSENS_THRES_THRES_MASK ) ) +#define GR740_THSENS_THRES_THRES( _val ) \ + ( ( ( _val ) << GR740_THSENS_THRES_THRES_SHIFT ) & \ + GR740_THSENS_THRES_THRES_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GR740 Temperatur Sensor Controller + * register block memory map. + */ +typedef struct gr740_thsens { + /** + * @brief See @ref RTEMSBSPsGR740ThSensCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSBSPsGR740ThSensSTATUS. + */ + uint32_t status; + + /** + * @brief See @ref RTEMSBSPsGR740ThSensTHRES. + */ + uint32_t thres; +} gr740_thsens; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_GR740_THSENS_REGS_H */ diff --git a/bsps/sparc/leon3/include/bsp/irq.h b/bsps/sparc/leon3/include/bsp/irq.h index 967086f8eb..dd6fd91aa1 100644 --- a/bsps/sparc/leon3/include/bsp/irq.h +++ b/bsps/sparc/leon3/include/bsp/irq.h @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * @brief LEON3 generic shared IRQ setup * * Based on libbsp/shared/include/irq.h. @@ -10,16 +12,32 @@ * Copyright (c) 2012. * Aeroflex Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_LEON3_IRQ_CONFIG_H #define LIBBSP_LEON3_IRQ_CONFIG_H -#include <leon.h> -#include <rtems/score/processormask.h> +#include <rtems.h> #define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ #define BSP_INTERRUPT_VECTOR_MAX_EXT 31 /* Extended IRQ controller */ @@ -29,14 +47,4 @@ /* The check is different depending on IRQ controller, runtime detected */ #define BSP_INTERRUPT_CUSTOM_VALID_VECTOR -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - #endif /* LIBBSP_LEON3_IRQ_CONFIG_H */ diff --git a/bsps/sparc/leon3/include/bsp/irqimpl.h b/bsps/sparc/leon3/include/bsp/irqimpl.h new file mode 100644 index 0000000000..9a9eae51f7 --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/irqimpl.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This header file provides interfaces used by the interrupt support + * implementation. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H +#define LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H + +#include <rtems.h> +#include <grlib/irqamp-regs.h> +#include <grlib/io.h> + +#include <bspopts.h> + +struct ambapp_dev; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup RTEMSBSPsSPARCLEON3 + * + * @{ + */ + +/** + * @brief This object provides the index of the boot processor. + * + * This object should be read-only after initialization. + */ +extern uint32_t LEON3_Cpu_Index; + +/** + * @brief This lock serializes the interrupt controller access. + */ +extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; + +/** + * @brief Acquires the interrupt controller lock. + * + * @param[out] _lock_context is the lock context. + */ +#define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ + rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) + +/** + * @brief Releases the interrupt controller lock. + * + * @param[in, out] _lock_context is the lock context. + */ +#define LEON3_IRQCTRL_RELEASE( _lock_context ) \ + rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) + +/** + * @brief This pointer provides the IRQ(A)MP register block address. + */ +#if defined(LEON3_IRQAMP_BASE) +#define LEON3_IrqCtrl_Regs ((irqamp *) LEON3_IRQAMP_BASE) +#else +extern irqamp *LEON3_IrqCtrl_Regs; + +/** + * @brief This pointer provides the IRQ(A)MP device information block. + */ +extern struct ambapp_dev *LEON3_IrqCtrl_Adev; +#endif + +/** + * @brief This object provides the interrupt number used to multiplex extended + * interrupts or is zero if no extended interrupts are available. + * + * This object should be read-only after initialization. + */ +#if defined(LEON3_IRQAMP_EXTENDED_INTERRUPT) +#define LEON3_IrqCtrl_EIrq LEON3_IRQAMP_EXTENDED_INTERRUPT +#else +extern uint32_t LEON3_IrqCtrl_EIrq; +#endif + +/** + * @brief Initializes the interrupt controller for the boot processor. + * + * @param[in, out] regs is the IRQ(A)MP register block address. + */ +void leon3_ext_irq_init( irqamp *regs ); + +/** + * @brief Acknowledges and maps extended interrupts if this feature is + * available and the interrupt for extended interrupts is present. + * + * @param irq is the standard interrupt number. + */ +static inline uint32_t bsp_irq_fixup( uint32_t irq ) +{ + uint32_t eirq; + uint32_t cpu_self; + + if ( irq != LEON3_IrqCtrl_EIrq ) { + return irq; + } + + cpu_self = _LEON3_Get_current_processor(); + eirq = grlib_load_32( &LEON3_IrqCtrl_Regs->pextack[ cpu_self ] ); + eirq = IRQAMP_PEXTACK_EID_4_0_GET( eirq ); + + if ( eirq < 16 ) { + return irq; + } + + return eirq; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H */ diff --git a/bsps/sparc/leon3/include/bsp/leon3.h b/bsps/sparc/leon3/include/bsp/leon3.h new file mode 100644 index 0000000000..650e2db744 --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/leon3.h @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This header file provides interfaces used by the BSP implementation. + */ + +/* + * Copyright (C) 2014, 2023 embedded brains GmbH & Co. KG + * + * Copyright (C) 2015 Cobham Gaisler AB + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SPARC_LEON3_BSP_LEON3_H +#define LIBBSP_SPARC_LEON3_BSP_LEON3_H + +#include <grlib/apbuart-regs.h> +#include <grlib/gptimer-regs.h> + +#include <bspopts.h> +#include <bsp/irqimpl.h> + +#if !defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER) +#include <grlib/ambapp.h> +#endif + +#include <sys/timetc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup RTEMSBSPsSPARCLEON3 + * + * @{ + */ + +/** + * @brief Sets %asr19 to zero to enter the power-down mode of the processor in + * an infinite loop. + */ +RTEMS_NO_RETURN void leon3_power_down_loop( void ); + +/** + * @brief This constant represents the flush instruction cache flag of the LEON + * cache control register. + */ +#define LEON3_REG_CACHE_CTRL_FI 0x00200000U + +/** + * @brief This constant represents the data cache snooping enable flag of the + * LEON cache control register. + */ +#define LEON3_REG_CACHE_CTRL_DS 0x00800000U + +/** + * @brief Sets the ASI 0x2 system register value. + * + * @param addr is the address of the ASI 0x2 system register. + * + * @param val is the value to set. + */ +static inline void leon3_set_system_register( uint32_t addr, uint32_t val ) +{ + __asm__ volatile( + "sta %1, [%0] 2" + : + : "r" ( addr ), "r" ( val ) + ); +} + +/** + * @brief Gets the ASI 0x2 system register value. + * + * @param addr is the address of the ASI 0x2 system register. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_get_system_register( uint32_t addr ) +{ + uint32_t val; + + __asm__ volatile( + "lda [%1] 2, %0" + : "=r" ( val ) + : "r" ( addr ) + ); + + return val; +} + +/** + * @brief Sets the LEON cache control register value. + * + * @param val is the value to set. + */ +static inline void leon3_set_cache_control_register( uint32_t val ) +{ + leon3_set_system_register( 0x0, val ); +} + +/** + * @brief Gets the LEON cache control register value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_get_cache_control_register( void ) +{ + return leon3_get_system_register( 0x0 ); +} + +/** + * @brief Checks if the data cache snooping is enabled. + * + * @return Returns true, if the data cache snooping is enabled, otherwise + * false. + */ +static inline bool leon3_data_cache_snooping_enabled( void ) +{ + return ( leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS ) != 0; +} + +/** + * @brief Gets the LEON instruction cache configuration register value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_get_inst_cache_config_register( void ) +{ + return leon3_get_system_register( 0x8 ); +} + +/** + * @brief Gets the LEON data cache configuration register value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_get_data_cache_config_register( void ) +{ + return leon3_get_system_register( 0xc ); +} + +/** + * @brief Gets the processor count. + * + * @param[in] regs is the IRQ(A)MP register block address. + * + * @return Returns the processor count. + */ +static inline uint32_t leon3_get_cpu_count( const irqamp *regs ) +{ + return IRQAMP_MPSTAT_NCPU_GET( grlib_load_32( ®s->mpstat ) ) + 1; +} + +#if !defined(LEON3_GPTIMER_BASE) +/** + * @brief This object lets the user override which on-chip GPTIMER core will be + * used for system clock timer. + * + * This controls which timer core will be accociated with LEON3_Timer_Regs + * registers base address. This value will by destroyed during initialization. + * + * * 0 = Default configuration. GPTIMER[0] + * + * * 1 = GPTIMER[1] + * + * * 2 = GPTIMER[2] + * + * * ... + */ +extern int leon3_timer_core_index; + +/** + * @brief This object lets the user override system clock timer prescaler. + * + * This affects all timer instances on the system clock timer core determined + * by ::leon3_timer_core_index. + * + * * 0 = Default configuration. Use bootloader configured value. + * + * * N = Prescaler is set to N. N must not be less that number of timers. + * + * * 8 = Prescaler is set to 8 (the fastest prescaler possible on all HW) + * + * * ... + */ +extern unsigned int leon3_timer_prescaler; +#endif + +/** + * @brief This constant defines the index of the GPTIMER timer used by the + * clock driver. + */ +#if defined(RTEMS_MULTIPROCESSING) +#define LEON3_CLOCK_INDEX \ + ( leon3_timer_core_index != 0 ? 0 : 2 * LEON3_Cpu_Index ) +#else +#define LEON3_CLOCK_INDEX 0 +#endif + +/** + * @brief This constant defines the index of the GPTIMER timer used by the + * CPU counter if the CPU counter uses the GPTIMER. + */ +#define LEON3_COUNTER_GPTIMER_INDEX ( LEON3_CLOCK_INDEX + 1 ) + +/** + * @brief This constant defines the frequency set by the boot loader of the + * first GPTIMER instance. + * + * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to + * run with 1MHz. This is used to determine all clock frequencies of the PnP + * devices. See also ambapp_freq_init() and ambapp_freq_get(). + */ +#define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 + +/** + * @brief This pointer provides the GPTIMER register block address. + */ +#if defined(LEON3_GPTIMER_BASE) +#define LEON3_Timer_Regs ((gptimer *) LEON3_GPTIMER_BASE) +#else +extern gptimer *LEON3_Timer_Regs; + +/** + * @brief This pointer provides the GPTIMER device information block. + */ +extern struct ambapp_dev *LEON3_Timer_Adev; +#endif + +/** + * @brief Gets the processor local bus frequency in Hz. + * + * @return Returns the frequency. + */ +static inline uint32_t leon3_processor_local_bus_frequency( void ) +{ +#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER) + return ( grlib_load_32( &LEON3_Timer_Regs->sreload ) + 1 ) * + LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER; +#else + /* + * For simplicity, assume that the interrupt controller uses the processor + * clock. This is at least true on the GR740. + */ + return ambapp_freq_get( ambapp_plb(), LEON3_IrqCtrl_Adev ); +#endif +} + +/** + * @brief Gets the LEON up-counter low register (%ASR23) value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_up_counter_low( void ) +{ + uint32_t asr23; + + __asm__ volatile ( + "mov %%asr23, %0" + : "=&r" (asr23) + ); + + return asr23; +} + +/** + * @brief Gets the LEON up-counter high register (%ASR22) value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_up_counter_high(void) +{ + uint32_t asr22; + + __asm__ volatile ( + "mov %%asr22, %0" + : "=&r" (asr22) + ); + + return asr22; +} + +/** + * @brief Enables the LEON up-counter. + */ +static inline void leon3_up_counter_enable( void ) +{ + __asm__ volatile ( + "mov %g0, %asr22" + ); +} + +#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER) +/** + * @brief Checks if the LEON up-counter is available. + * + * The LEON up-counter must have been enabled. + * + * @return Returns true, if the LEON up-counter is available, otherwise false. + */ +static inline bool leon3_up_counter_is_available( void ) +{ + return leon3_up_counter_low() != leon3_up_counter_low(); +} +#endif + +/** + * @brief Gets the LEON up-counter frequency in Hz. + * + * @return Returns the frequency. + */ +static inline uint32_t leon3_up_counter_frequency( void ) +{ + return leon3_processor_local_bus_frequency(); +} + +/** + * @brief This pointer provides the debug APBUART register block address. + */ +#if defined(LEON3_APBUART_BASE) +#define leon3_debug_uart ((struct apbuart *) LEON3_APBUART_BASE) +#else +extern apbuart *leon3_debug_uart; +#endif + +/** + * @brief Represents the LEON3-specific timecounter. + */ +typedef struct { + /** + * @brief This member contains the base timecounter. + */ + struct timecounter base; + +#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER) + /** + * @brief This member provides a software fall-back counter. + */ + uint32_t software_counter; + + /** + * @brief This member may reference a hardware counter register. + */ + volatile uint32_t *counter_register; +#endif +} leon3_timecounter; + +/** + * @brief Provides the LEON3-specific timecounter. + * + * It is also used by the CPU counter implementation. + */ +extern leon3_timecounter leon3_timecounter_instance; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_SPARC_LEON3_BSP_LEON3_H */ diff --git a/bsps/sparc/leon3/include/bsp/watchdog.h b/bsps/sparc/leon3/include/bsp/watchdog.h index 3c63be2a8f..8bffd3c95e 100644 --- a/bsps/sparc/leon3/include/bsp/watchdog.h +++ b/bsps/sparc/leon3/include/bsp/watchdog.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* watchdog.h * * The LEON3 BSP timer watch-dog interface @@ -5,9 +7,26 @@ * COPYRIGHT (c) 2012. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __WATCHDOG_H__ diff --git a/bsps/sparc/leon3/include/leon.h b/bsps/sparc/leon3/include/leon.h index 5fadb08052..28ba59ff21 100644 --- a/bsps/sparc/leon3/include/leon.h +++ b/bsps/sparc/leon3/include/leon.h @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * @brief LEON3 BSP data types and macros */ @@ -15,9 +17,26 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _INCLUDE_LEON_h @@ -25,6 +44,8 @@ #include <rtems.h> #include <amba.h> +#include <grlib/io.h> +#include <bsp/leon3.h> #ifdef __cplusplus extern "C" { @@ -121,41 +142,6 @@ extern "C" { #define LEON_REG_UART_CTRL_FA 0x80000000 /* FIFO Available */ #define LEON_REG_UART_CTRL_FA_BIT 31 -/* - * The following defines the bits in the LEON Cache Control Register. - */ -#define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ -#define LEON3_REG_CACHE_CTRL_DS 0x00800000 /* Data cache snooping */ - -/* LEON3 Interrupt Controller */ -extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; -extern struct ambapp_dev *LEON3_IrqCtrl_Adev; - -/* LEON3 GP Timer */ -extern volatile struct gptimer_regs *LEON3_Timer_Regs; -extern struct ambapp_dev *LEON3_Timer_Adev; - -/* LEON3 CPU Index of boot CPU */ -extern uint32_t LEON3_Cpu_Index; - -/* The external IRQ number, -1 if not external interrupts */ -extern int LEON3_IrqCtrl_EIrq; - -static __inline__ int bsp_irq_fixup(int irq) -{ - int eirq, cpu; - - if (LEON3_IrqCtrl_EIrq != 0 && irq == LEON3_IrqCtrl_EIrq) { - /* Get interrupt number from IRQ controller */ - cpu = _LEON3_Get_current_processor(); - eirq = LEON3_IrqCtrl_Regs->intid[cpu] & 0x1f; - if (eirq & 0x10) - irq = eirq; - } - - return irq; -} - /* Macros used for manipulating bits in LEON3 GP Timer Control Register */ #define LEON3_IRQMPSTATUS_CPUNR 28 @@ -174,30 +160,21 @@ static __inline__ int bsp_irq_fixup(int irq) * store the result back are vulnerable. */ -extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; - -#define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ - rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) - -#define LEON3_IRQCTRL_RELEASE( _lock_context ) \ - rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) - #define LEON_Clear_interrupt( _source ) \ - do { \ - LEON3_IrqCtrl_Regs->iclear = (1U << (_source)); \ - } while (0) + grlib_store_32(&LEON3_IrqCtrl_Regs->iclear, 1U << (_source)) #define LEON_Force_interrupt( _source ) \ - do { \ - LEON3_IrqCtrl_Regs->iforce = (1U << (_source)); \ - } while (0) + grlib_store_32(&LEON3_IrqCtrl_Regs->iforce0, 1U << (_source)) #define LEON_Enable_interrupt_broadcast( _source ) \ do { \ rtems_interrupt_lock_context _lock_context; \ uint32_t _mask = 1U << ( _source ); \ + uint32_t _brdcst; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->bcast |= _mask; \ + _brdcst = grlib_load_32(&LEON3_IrqCtrl_Regs->brdcst); \ + _brdcst |= _mask; \ + grlib_store_32(&LEON3_IrqCtrl_Regs->brdcst, _brdcst); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) @@ -205,30 +182,39 @@ extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; do { \ rtems_interrupt_lock_context _lock_context; \ uint32_t _mask = 1U << ( _source ); \ + uint32_t _brdcst; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->bcast &= ~_mask; \ + _brdcst = grlib_load_32(&LEON3_IrqCtrl_Regs->brdcst); \ + _brdcst &= ~_mask; \ + grlib_store_32(&LEON3_IrqCtrl_Regs->brdcst, _brdcst); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) #define LEON_Is_interrupt_pending( _source ) \ - (LEON3_IrqCtrl_Regs->ipend & (1U << (_source))) + (grlib_load_32(&LEON3_IrqCtrl_Regs->ipend) & (1U << (_source))) #define LEON_Cpu_Is_interrupt_masked( _source, _cpu ) \ - (!(LEON3_IrqCtrl_Regs->mask[_cpu] & (1U << (_source)))) + (!(grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu]) & (1U << (_source)))) #define LEON_Cpu_Mask_interrupt( _source, _cpu ) \ do { \ rtems_interrupt_lock_context _lock_context; \ + uint32_t _pimask; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] &= ~(1U << (_source)); \ + _pimask = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \ + _pimask &= ~(1U << (_source)); \ + grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], _pimask); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) #define LEON_Cpu_Unmask_interrupt( _source, _cpu ) \ do { \ rtems_interrupt_lock_context _lock_context; \ + uint32_t _pimask; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] |= (1U << (_source)); \ + _pimask = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \ + _pimask |= 1U << (_source); \ + grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], _pimask); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) @@ -237,8 +223,8 @@ extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; rtems_interrupt_lock_context _lock_context; \ uint32_t _mask = 1U << (_source); \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - (_previous) = LEON3_IrqCtrl_Regs->mask[_cpu]; \ - LEON3_IrqCtrl_Regs->mask[_cpu] = _previous & ~_mask; \ + (_previous) = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \ + grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], (_previous) & ~_mask); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ (_previous) &= _mask; \ } while (0) @@ -246,10 +232,12 @@ extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; #define LEON_Cpu_Restore_interrupt( _source, _previous, _cpu ) \ do { \ rtems_interrupt_lock_context _lock_context; \ - uint32_t _mask = 1U << (_source); \ + uint32_t _pimask; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] = \ - (LEON3_IrqCtrl_Regs->mask[_cpu] & ~_mask) | (_previous); \ + _pimask = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \ + _pimask &= ~(1U << (_source)); \ + _pimask |= _previous; \ + grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], _pimask); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) @@ -324,26 +312,6 @@ extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; #define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 -#if defined(RTEMS_MULTIPROCESSING) - #define LEON3_CLOCK_INDEX \ - (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0) -#else - #define LEON3_CLOCK_INDEX 0 -#endif - -#if defined(RTEMS_SMP) -#define LEON3_COUNTER_GPTIMER_INDEX (LEON3_CLOCK_INDEX + 1) -#else -#define LEON3_COUNTER_GPTIMER_INDEX LEON3_CLOCK_INDEX -#endif - -/* - * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to - * run with 1MHz. This is used to determine all clock frequencies of the PnP - * devices. See also ambapp_freq_init() and ambapp_freq_get(). - */ -#define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 - /* Load 32-bit word by forcing a cache-miss */ static inline unsigned int leon_r32_no_cache(uintptr_t addr) { @@ -361,6 +329,7 @@ static inline unsigned int leon_r32_no_cache(uintptr_t addr) */ extern int syscon_uart_index; +#if !defined(LEON3_APBUART_BASE) /* Let user override which on-chip APBUART will be debug UART * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... * 1 = APBUART[0] @@ -369,133 +338,7 @@ extern int syscon_uart_index; * ... */ extern int leon3_debug_uart_index; - -/* Let user override which on-chip TIMER core will be used for system clock - * timer. This controls which timer core will be accociated with - * LEON3_Timer_Regs registers base address. This value will by destroyed during - * initialization. - * 0 = Default configuration. GPTIMER[0] - * 1 = GPTIMER[1] - * 2 = GPTIMER[2] - * ... - */ -extern int leon3_timer_core_index; - -/* Let user override system clock timer prescaler. This affects all timer - * instances on the system clock timer core determined by - * leon3_timer_core_index. - * 0 = Default configuration. Use bootloader configured value. - * N = Prescaler is set to N. N must not be less that number of timers. - * 8 = Prescaler is set to 8 (the fastest prescaler possible on all HW) - * ... - */ -extern unsigned int leon3_timer_prescaler; - -/* GRLIB extended IRQ controller register */ -void leon3_ext_irq_init(void); - -RTEMS_NO_RETURN void leon3_power_down_loop(void); - -static inline uint32_t leon3_get_cpu_count( - volatile struct irqmp_regs *irqmp -) -{ - uint32_t mpstat = irqmp->mpstat; - - return ((mpstat >> LEON3_IRQMPSTATUS_CPUNR) & 0xf) + 1; -} - -static inline void leon3_set_system_register(uint32_t addr, uint32_t val) -{ - __asm__ volatile( - "sta %1, [%0] 2" - : - : "r" (addr), "r" (val) - ); -} - -static inline uint32_t leon3_get_system_register(uint32_t addr) -{ - uint32_t val; - - __asm__ volatile( - "lda [%1] 2, %0" - : "=r" (val) - : "r" (addr) - ); - - return val; -} - -static inline void leon3_set_cache_control_register(uint32_t val) -{ - leon3_set_system_register(0x0, val); -} - -static inline uint32_t leon3_get_cache_control_register(void) -{ - return leon3_get_system_register(0x0); -} - -static inline bool leon3_data_cache_snooping_enabled(void) -{ - return leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS; -} - -static inline uint32_t leon3_get_inst_cache_config_register(void) -{ - return leon3_get_system_register(0x8); -} - -static inline uint32_t leon3_get_data_cache_config_register(void) -{ - return leon3_get_system_register(0xc); -} - -static inline uint32_t leon3_up_counter_low(void) -{ - uint32_t asr23; - - __asm__ volatile ( - "mov %%asr23, %0" - : "=&r" (asr23) - ); - - return asr23; -} - -static inline uint32_t leon3_up_counter_high(void) -{ - uint32_t asr22; - - __asm__ volatile ( - "mov %%asr22, %0" - : "=&r" (asr22) - ); - - return asr22; -} - -static inline void leon3_up_counter_enable(void) -{ - __asm__ volatile ( - "mov %g0, %asr22" - ); -} - -static inline bool leon3_up_counter_is_available(void) -{ - return leon3_up_counter_low() != leon3_up_counter_low(); -} - -static inline uint32_t leon3_up_counter_frequency(void) -{ - /* - * For simplicity, assume that the interrupt controller uses the processor - * clock. This is at least true on the GR740. - */ - return ambapp_freq_get(ambapp_plb(), LEON3_IrqCtrl_Adev); -} +#endif #endif /* !ASM */ diff --git a/bsps/sparc/leon3/include/tm27.h b/bsps/sparc/leon3/include/tm27.h index 99c79012bd..75004ef5ae 100644 --- a/bsps/sparc/leon3/include/tm27.h +++ b/bsps/sparc/leon3/include/tm27.h @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * @brief Implementations for interrupt mechanisms for Time Test 27 */ @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2006. * Aeroflex Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_TMTEST27 @@ -21,7 +40,7 @@ #define __tm27_h #include <bsp.h> -#include <bsp/irq.h> +#include <bsp/irq-generic.h> #if defined(RTEMS_SMP) #include <rtems/score/smpimpl.h> @@ -47,6 +66,8 @@ #define MUST_WAIT_FOR_INTERRUPT 1 +#define TM27_USE_VECTOR_HANDLER + #define Install_tm27_vector( handler ) \ set_vector( (handler), TEST_VECTOR, 1 ); @@ -68,10 +89,9 @@ extern uint32_t Interrupt_nest; #define TEST_INTERRUPT_SOURCE 5 #define TEST_INTERRUPT_SOURCE2 6 #define MUST_WAIT_FOR_INTERRUPT 1 +#define TM27_INTERRUPT_VECTOR_DEFAULT TEST_INTERRUPT_SOURCE -static inline void Install_tm27_vector( - void ( *handler )( rtems_vector_number ) -) +static inline void Install_tm27_vector( rtems_interrupt_handler handler ) { static rtems_interrupt_entry entry_low; static rtems_interrupt_entry entry_high; @@ -89,7 +109,7 @@ static inline void Install_tm27_vector( rtems_interrupt_entry_initialize( &entry_low, - (rtems_interrupt_handler) handler, + handler, NULL, "tm27 low" ); @@ -100,7 +120,7 @@ static inline void Install_tm27_vector( ); rtems_interrupt_entry_initialize( &entry_high, - (rtems_interrupt_handler) handler, + handler, NULL, "tm27 high" ); diff --git a/bsps/sparc/leon3/mpci/getcfg.c b/bsps/sparc/leon3/mpci/getcfg.c index 8cbc85f3eb..390a38b4a5 100644 --- a/bsps/sparc/leon3/mpci/getcfg.c +++ b/bsps/sparc/leon3/mpci/getcfg.c @@ -60,7 +60,7 @@ void Shm_Get_configuration( BSP_shm_cfgtbl.poll_intr = INTR_MODE; BSP_shm_cfgtbl.Intr.address = - (vol_u32 *) &(LEON3_IrqCtrl_Regs->force[LEON3_Cpu_Index]); + (vol_u32 *) &(LEON3_IrqCtrl_Regs->piforce[LEON3_Cpu_Index]); if (BSP_shm_cfgtbl.Intr.value == 0) BSP_shm_cfgtbl.Intr.value = 1 << LEON3_mp_irq; /* Use default MP-IRQ */ BSP_shm_cfgtbl.Intr.length = 4; diff --git a/bsps/sparc/leon3/start/amba.c b/bsps/sparc/leon3/start/amba.c index 4801916825..05708e06d0 100644 --- a/bsps/sparc/leon3/start/amba.c +++ b/bsps/sparc/leon3/start/amba.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * AMBA Plug & Play Bus Driver * @@ -6,9 +8,26 @@ * COPYRIGHT (c) 2011. * Aeroflex Gaisler * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> @@ -20,8 +39,10 @@ #include <string.h> +#if !defined(LEON3_GPTIMER_BASE) unsigned int leon3_timer_prescaler __attribute__((weak)) = 0; int leon3_timer_core_index __attribute__((weak)) = 0; +#endif /* AMBA Plug&Play information description. * @@ -96,14 +117,15 @@ RTEMS_SYSINIT_ITEM( ); #endif -rtems_interrupt_lock LEON3_IrqCtrl_Lock = - RTEMS_INTERRUPT_LOCK_INITIALIZER("LEON3 IrqCtrl"); - -/* Pointers to Interrupt Controller configuration registers */ -volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; +#if !defined(LEON3_IRQAMP_BASE) +irqamp *LEON3_IrqCtrl_Regs; struct ambapp_dev *LEON3_IrqCtrl_Adev; -volatile struct gptimer_regs *LEON3_Timer_Regs; +#endif + +#if !defined(LEON3_GPTIMER_BASE) +gptimer *LEON3_Timer_Regs; struct ambapp_dev *LEON3_Timer_Adev; +#endif /* * amba_initialize @@ -117,12 +139,16 @@ struct ambapp_dev *LEON3_Timer_Adev; static void amba_initialize(void) { - int icsel; struct ambapp_dev *adev; struct ambapp_bus *plb; plb = ambapp_plb(); +#if defined(LEON3_IRQAMP_BASE) && defined(LEON3_GPTIMER_BASE) + (void) plb; + (void) adev; +#endif +#if !defined(LEON3_IRQAMP_BASE) /* Find LEON3 Interrupt controller */ adev = (void *)ambapp_for_each(plb, (OPTIONS_ALL|OPTIONS_APB_SLVS), VENDOR_GAISLER, GAISLER_IRQMP, @@ -135,38 +161,36 @@ static void amba_initialize(void) bsp_fatal(LEON3_FATAL_NO_IRQMP_CONTROLLER); } - LEON3_IrqCtrl_Regs = (volatile struct irqmp_regs *)DEV_TO_APB(adev)->start; + LEON3_IrqCtrl_Regs = (irqamp *)DEV_TO_APB(adev)->start; LEON3_IrqCtrl_Adev = adev; - if ((LEON3_IrqCtrl_Regs->ampctrl >> 28) > 0) { + if ((grlib_load_32(&LEON3_IrqCtrl_Regs->asmpctrl) >> 28) > 0) { + uint32_t icsel; + /* IRQ Controller has support for multiple IRQ Controllers, each * CPU can be routed to different Controllers, we find out which * controller by looking at the IRQCTRL Select Register for this CPU. * Each Controller is located at a 4KByte offset. */ - icsel = LEON3_IrqCtrl_Regs->icsel[LEON3_Cpu_Index/8]; + icsel = grlib_load_32(&LEON3_IrqCtrl_Regs->icselr[LEON3_Cpu_Index/8]); icsel = (icsel >> ((7 - (LEON3_Cpu_Index & 0x7)) * 4)) & 0xf; LEON3_IrqCtrl_Regs += icsel; } - LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] = 0; - LEON3_IrqCtrl_Regs->force[LEON3_Cpu_Index] = 0; - LEON3_IrqCtrl_Regs->iclear = 0xffffffff; - - /* Init Extended IRQ controller if available */ - leon3_ext_irq_init(); +#endif +#if !defined(LEON3_GPTIMER_BASE) /* find GP Timer */ adev = (void *)ambapp_for_each(plb, (OPTIONS_ALL|OPTIONS_APB_SLVS), VENDOR_GAISLER, GAISLER_GPTIMER, ambapp_find_by_idx, &leon3_timer_core_index); if (adev) { - LEON3_Timer_Regs = (volatile struct gptimer_regs *)DEV_TO_APB(adev)->start; + LEON3_Timer_Regs = (gptimer *)DEV_TO_APB(adev)->start; LEON3_Timer_Adev = adev; /* Register AMBA Bus Frequency */ ambapp_freq_init( plb, LEON3_Timer_Adev, - (LEON3_Timer_Regs->scaler_reload + 1) + (grlib_load_32(&LEON3_Timer_Regs->sreload) + 1) * LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER ); /* Set user prescaler configuration. Use this to increase accuracy of timer @@ -175,8 +199,9 @@ static void amba_initialize(void) * GRTIMER/GPTIMER hardware. See HW manual. */ if (leon3_timer_prescaler) - LEON3_Timer_Regs->scaler_reload = leon3_timer_prescaler; + grlib_store_32(&LEON3_Timer_Regs->sreload, leon3_timer_prescaler); } +#endif } RTEMS_SYSINIT_ITEM( diff --git a/bsps/sparc/leon3/start/bsp_fatal_halt.c b/bsps/sparc/leon3/start/bsp_fatal_halt.c deleted file mode 100644 index 5a6e3f490e..0000000000 --- a/bsps/sparc/leon3/start/bsp_fatal_halt.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file - * @ingroup sparc_leon3 - * @brief LEON3 BSP Fatal_halt handler. - * - * COPYRIGHT (c) 2014. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <bsp.h> -#include <leon.h> -#include <rtems/score/cpuimpl.h> - -void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) -{ -#ifdef BSP_POWER_DOWN_AT_FATAL_HALT - /* Power down LEON CPU on fatal error exit */ - sparc_disable_interrupts(); - leon3_power_down_loop(); -#else - /* - * Return to debugger, simulator, hypervisor or similar by exiting - * with an error code. g1=1, g2=FATAL_SOURCE, G3=error-code. - */ - sparc_syscall_exit(source, error); -#endif -} diff --git a/bsps/sparc/leon3/start/bspclean.c b/bsps/sparc/leon3/start/bspclean.c index 6bdae00237..d624ec74c8 100644 --- a/bsps/sparc/leon3/start/bspclean.c +++ b/bsps/sparc/leon3/start/bspclean.c @@ -1,67 +1,62 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * @brief LEON3 BSP fatal extension * - * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2014 embedded brains GmbH & Co. KG * * COPYRIGHT (c) 2014 * Aeroflex Gaisler * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> #include <bsp/bootcard.h> +#include <bsp/leon3.h> +#include <rtems/score/cpuimpl.h> #include <rtems/score/smpimpl.h> -#include <leon.h> - void bsp_fatal_extension( rtems_fatal_source source, bool always_set_to_false, rtems_fatal_code code ) { + rtems_interrupt_level level; + + (void) always_set_to_false; + rtems_interrupt_local_disable(level); + (void) level; + #if defined(RTEMS_SMP) - /* - * On SMP we must wait for all other CPUs not requesting a fatal halt, they - * are responding to another CPU's fatal request. These CPUs goes into - * power-down. The CPU requesting fatal halt waits for the others and then - * handles the system shutdown via the normal procedure. - */ if ((source == RTEMS_FATAL_SOURCE_SMP) && (code == SMP_FATAL_SHUTDOWN_RESPONSE)) { leon3_power_down_loop(); /* CPU didn't start shutdown sequence .. */ - } else { - volatile struct irqmp_regs *irqmp = LEON3_IrqCtrl_Regs; - - if (irqmp != NULL) { - /* - * Value was chosen to get something in the magnitude of 1ms on a 200MHz - * processor. - */ - uint32_t max_wait = 1234567; - uint32_t self_cpu = rtems_scheduler_get_processor(); - uint32_t cpu_count = rtems_scheduler_get_processor_maximum(); - uint32_t halt_mask = 0; - uint32_t i; - - for (i = 0; i < cpu_count; ++i) { - if ( (i != self_cpu) && _SMP_Should_start_processor( i ) ) { - halt_mask |= UINT32_C(1) << i; - } - } - - /* Wait some time for secondary processors to halt */ - i = 0; - while ((irqmp->mpstat & halt_mask) != halt_mask && i < max_wait) { - ++i; - } - } } + + _SMP_Request_shutdown(); #endif #if BSP_PRINT_EXCEPTION_CONTEXT @@ -71,7 +66,10 @@ void bsp_fatal_extension( #endif #if BSP_RESET_BOARD_AT_EXIT - /* If user wants to implement custom reset/reboot it can be done here */ - bsp_reset(); + /* + * Stop the system termination right now. This skips the dynamically + * installed fatal error extensions and the generics shutdown procedure. + */ + _CPU_Fatal_halt( source, code ); #endif } diff --git a/bsps/sparc/leon3/start/bspdelay.c b/bsps/sparc/leon3/start/bspdelay.c index c4a880be6d..6695f76929 100644 --- a/bsps/sparc/leon3/start/bspdelay.c +++ b/bsps/sparc/leon3/start/bspdelay.c @@ -14,15 +14,17 @@ */ #include <bsp.h> -#include <leon.h> +#include <bsp/leon3.h> void rtems_bsp_delay(int usecs) { uint32_t then; + gptimer_timer *regs; - then =LEON3_Timer_Regs->timer[0].value; + regs = &LEON3_Timer_Regs->timer[0]; + then =grlib_load_32(®s->tcntval); then += usecs; - while (LEON3_Timer_Regs->timer[0].value >= then) + while (grlib_load_32(®s->tcntval) >= then) ; } diff --git a/bsps/sparc/leon3/start/bspidle.S b/bsps/sparc/leon3/start/bspidle.S index 8557ff42a1..82c04a231d 100644 --- a/bsps/sparc/leon3/start/bspidle.S +++ b/bsps/sparc/leon3/start/bspidle.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Idle Thread Body * @@ -6,9 +8,26 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsps/sparc/leon3/start/bspsmp.c b/bsps/sparc/leon3/start/bspsmp.c index acd932843a..82d6e5a163 100644 --- a/bsps/sparc/leon3/start/bspsmp.c +++ b/bsps/sparc/leon3/start/bspsmp.c @@ -1,6 +1,6 @@ /** * @file - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * @brief LEON3 SMP BSP Support */ @@ -16,8 +16,8 @@ #include <bsp.h> #include <bsp/bootcard.h> #include <bsp/fatal.h> -#include <bsp/irq.h> -#include <leon.h> +#include <bsp/irq-generic.h> +#include <bsp/leon3.h> #include <rtems/bspIo.h> #include <rtems/sysinit.h> #include <rtems/score/assert.h> @@ -39,14 +39,9 @@ static void bsp_inter_processor_interrupt( void *arg ) void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self) { - /* - * If data cache snooping is not enabled we terminate using BSP_fatal_exit() - * instead of bsp_fatal(). This is done since the latter function tries to - * acquire a ticket lock, an operation which requires data cache snooping to - * be enabled. - */ - if ( !leon3_data_cache_snooping_enabled() ) - BSP_fatal_exit( LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR ); + if ( !leon3_data_cache_snooping_enabled() ) { + bsp_fatal( LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR ); + } _SMP_Start_multitasking_on_secondary_processor(cpu_self); } @@ -89,7 +84,10 @@ bool _CPU_SMP_Start_processor( uint32_t cpu_index ) printk( "Waking CPU %d\n", cpu_index ); #endif - LEON3_IrqCtrl_Regs->mpstat = 1U << cpu_index; + grlib_store_32( + &LEON3_IrqCtrl_Regs->mpstat, + IRQAMP_MPSTAT_STATUS(1U << cpu_index) + ); return true; } @@ -111,7 +109,10 @@ void _CPU_SMP_Prepare_start_multitasking( void ) void _CPU_SMP_Send_interrupt(uint32_t target_processor_index) { /* send interrupt to destination CPU */ - LEON3_IrqCtrl_Regs->force[target_processor_index] = 1 << LEON3_mp_irq; + grlib_store_32( + &LEON3_IrqCtrl_Regs->piforce[target_processor_index], + 1U << LEON3_mp_irq + ); } #if defined(RTEMS_DRVMGR_STARTUP) diff --git a/bsps/sparc/leon3/start/bspstart.c b/bsps/sparc/leon3/start/bspstart.c index 75042e4c20..2c3844f78d 100644 --- a/bsps/sparc/leon3/start/bspstart.c +++ b/bsps/sparc/leon3/start/bspstart.c @@ -1,9 +1,15 @@ -/* - * This set of routines starts the application. It includes application, - * board, and monitor specific initialization and configuration. - * The generic CPU dependent initialization has been performed - * before any of these are invoked. +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 * + * @brief This source file contains the implementation of bsp_start() and + * definitions of BSP-specific objects. + */ + +/* * COPYRIGHT (c) 2011 * Aeroflex Gaisler * @@ -14,14 +20,31 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> #include <bsp/irq-generic.h> -#include <leon.h> +#include <bsp/leon3.h> #include <bsp/bootcard.h> #include <rtems/sysinit.h> @@ -40,11 +63,6 @@ int CPU_SPARC_HAS_SNOOPING; /* Index of CPU, in an AMP system CPU-index may be non-zero */ uint32_t LEON3_Cpu_Index = 0; -#if defined(RTEMS_SMP) -/* Index of the boot CPU. Set by the first CPU at boot to its CPU ID. */ -int LEON3_Boot_Cpu = -1; -#endif - /* * set_snooping * diff --git a/bsps/sparc/leon3/start/cache.c b/bsps/sparc/leon3/start/cache.c index 922fef59e9..11af2f4d01 100644 --- a/bsps/sparc/leon3/start/cache.c +++ b/bsps/sparc/leon3/start/cache.c @@ -1,13 +1,31 @@ +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This source file contains the implementation of the Cache Manager. + */ + /* - * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2014 embedded brains GmbH & Co. KG * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.org/license/LICENSE. */ -#include <amba.h> -#include <leon.h> +#include <grlib/l2cache-regs.h> +#include <grlib/io.h> + +#include <bsp/leon3.h> + +#if !defined(LEON3_L2CACHE_BASE) +#include <grlib/ambapp.h> +#endif + +#if !defined(LEON3_L2CACHE_BASE) || LEON3_L2CACHE_BASE != 0 +#define LEON3_MAYBE_HAS_L2CACHE +#endif #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS @@ -19,12 +37,12 @@ #define CPU_DATA_CACHE_ALIGNMENT 64 -static inline volatile struct l2c_regs *get_l2c_regs(void) +#if !defined(LEON3_L2CACHE_BASE) +static inline l2cache *get_l2c_regs(void) { - volatile struct l2c_regs *l2c = NULL; struct ambapp_dev *adev; - adev = (void *) ambapp_for_each( + adev = (struct ambapp_dev *) ambapp_for_each( ambapp_plb(), OPTIONS_ALL | OPTIONS_AHB_SLVS, VENDOR_GAISLER, @@ -32,28 +50,14 @@ static inline volatile struct l2c_regs *get_l2c_regs(void) ambapp_find_by_idx, NULL ); - if (adev != NULL) { - l2c = (volatile struct l2c_regs *) DEV_TO_AHB(adev)->start[1]; - } - - return l2c; -} - -static inline size_t get_l2_size(void) -{ - size_t size = 0; - volatile struct l2c_regs *l2c = get_l2c_regs(); - if (l2c != NULL) { - unsigned status = l2c->status; - unsigned ways = (status & 0x3) + 1; - unsigned set_size = ((status & 0x7ff) >> 2) * 1024; - - size = ways * set_size; + if (adev == NULL) { + return NULL; } - return size; + return (l2cache *) DEV_TO_AHB(adev)->start[1]; } +#endif static inline size_t get_l1_size(uint32_t l1_cfg) { @@ -63,10 +67,36 @@ static inline size_t get_l1_size(uint32_t l1_cfg) return ways * wsize; } +#if defined(LEON3_MAYBE_HAS_L2CACHE) +static inline size_t get_l2_size(void) +{ + l2cache *regs; + unsigned status; + unsigned ways; + unsigned set_size; + +#if defined(LEON3_L2CACHE_BASE) + regs = (l2cache *) LEON3_L2CACHE_BASE; +#else + regs = get_l2c_regs(); + + if (regs == NULL) { + return 0; + } +#endif + + status = grlib_load_32(®s->l2cs); + ways = L2CACHE_L2CS_WAY_GET(status) + 1; + set_size = L2CACHE_L2CS_WAY_SIZE_GET(status) * 1024; + + return ways * set_size; +} + static inline size_t get_max_size(size_t a, size_t b) { return a < b ? b : a; } +#endif static inline size_t get_cache_size(uint32_t level, uint32_t l1_cfg) { @@ -74,14 +104,20 @@ static inline size_t get_cache_size(uint32_t level, uint32_t l1_cfg) switch (level) { case 0: +#if defined(LEON3_MAYBE_HAS_L2CACHE) size = get_max_size(get_l1_size(l1_cfg), get_l2_size()); +#else + size = get_l1_size(l1_cfg); +#endif break; case 1: size = get_l1_size(l1_cfg); break; +#if defined(LEON3_MAYBE_HAS_L2CACHE) case 2: size = get_l2_size(); break; +#endif default: size = 0; break; diff --git a/bsps/sparc/leon3/start/cpucounter.c b/bsps/sparc/leon3/start/cpucounter.c index b93aed54bd..8ca1962de9 100644 --- a/bsps/sparc/leon3/start/cpucounter.c +++ b/bsps/sparc/leon3/start/cpucounter.c @@ -1,67 +1,295 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This source file contains the implementation of the CPU Counter. + */ + /* - * Copyright (c) 2014, 2018 embedded brains GmbH. All rights reserved. + * Copyright (C) 2014, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ -#include <leon.h> +#include <bsp/leon3.h> +#include <grlib/irqamp.h> #include <rtems/counter.h> #include <rtems/sysinit.h> -#include <rtems/score/sparcimpl.h> +#include <rtems/timecounter.h> + +#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER) || \ + defined(LEON3_PROBE_ASR_22_23_UP_COUNTER) +static uint32_t leon3_timecounter_get_asr_22_23_up_counter( + struct timecounter *tc +) +{ + return leon3_up_counter_low(); +} + +static void leon3_counter_use_asr_22_23_up_counter(leon3_timecounter *tc) +{ +#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER) + tc->base.tc_get_timecount = leon3_timecounter_get_asr_22_23_up_counter; +#endif + tc->base.tc_frequency = leon3_up_counter_frequency(); +} +#endif + +/* + * The following code blocks provide different CPU counter implementations. + * The implementation used is defined by build configuration options. For a + * particular chip, the best available hardware counter module may be selected + * by build configuration options. The default implementation tries to select + * the best module at runtime. + */ + +#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER) + +CPU_Counter_ticks _CPU_Counter_read(void) +{ + return leon3_up_counter_low(); +} + +RTEMS_ALIAS(_CPU_Counter_read) uint32_t _SPARC_Counter_read_ISR_disabled(void); + +#define LEON3_GET_TIMECOUNT_INIT leon3_timecounter_get_asr_22_23_up_counter + +#elif defined(LEON3_DSU_BASE) + +/* + * In general, using the Debug Support Unit (DSU) is not recommended. Before + * you use it, check that it is available in flight models and that the time + * tag register is implemented in radiation hardened flip-flops. For the + * GR712RC, this is the case. + */ + +/* This value is specific to the GR712RC */ +#define LEON3_DSU_TIME_TAG_ZERO_BITS 2 + +static uint32_t leon3_read_dsu_time_tag(void) +{ + uint32_t value; + volatile uint32_t *reg; + + /* Use a load with a forced cache miss */ + reg = (uint32_t *) (LEON3_DSU_BASE + 8); + __asm__ volatile ( + "\tlda\t[%1]1, %0" + : "=&r"(value) + : "r"(reg) + ); + return value << LEON3_DSU_TIME_TAG_ZERO_BITS; +} + +static uint32_t leon3_timecounter_get_dsu_time_tag( + struct timecounter *tc +) +{ + (void) tc; + return leon3_read_dsu_time_tag(); +} + +CPU_Counter_ticks _CPU_Counter_read(void) +{ + return leon3_read_dsu_time_tag(); +} + +RTEMS_ALIAS(_CPU_Counter_read) uint32_t _SPARC_Counter_read_ISR_disabled(void); + +static void leon3_counter_use_dsu_time_tag(leon3_timecounter *tc) +{ + tc->base.tc_frequency = + leon3_processor_local_bus_frequency() << LEON3_DSU_TIME_TAG_ZERO_BITS; +} + +#define LEON3_GET_TIMECOUNT_INIT leon3_timecounter_get_dsu_time_tag + +#else /* !LEON3_HAS_ASR_22_23_UP_COUNTER && !LEON3_DSU_BASE */ + +/* + * This is a workaround for: + * https://gcc.gnu.org/bugzilla//show_bug.cgi?id=69027 + */ +__asm__ ( + "\t.section\t\".text\"\n" + "\t.align\t4\n" + "\t.globl\t_CPU_Counter_read\n" + "\t.globl\t_SPARC_Counter_read_ISR_disabled\n" + "\t.type\t_CPU_Counter_read, #function\n" + "\t.type\t_SPARC_Counter_read_ISR_disabled, #function\n" + "_CPU_Counter_read:\n" + "_SPARC_Counter_read_ISR_disabled:\n" + "\tsethi\t%hi(leon3_timecounter_instance), %o0\n" + "\tld [%o0 + %lo(leon3_timecounter_instance)], %o1\n" + "\tor\t%o0, %lo(leon3_timecounter_instance), %o0\n" + "\tor\t%o7, %g0, %g1\n" + "\tcall\t%o1, 0\n" + "\t or\t%g1, %g0, %o7\n" + "\t.previous\n" +); + +static uint32_t leon3_timecounter_get_dummy(struct timecounter *base) +{ + leon3_timecounter *tc; + uint32_t counter; + + tc = (leon3_timecounter *) base; + counter = tc->software_counter + 1; + tc->software_counter = counter; + return counter; +} + +#define LEON3_GET_TIMECOUNT_INIT leon3_timecounter_get_dummy + +static uint32_t leon3_timecounter_get_counter_down(struct timecounter *base) +{ + leon3_timecounter *tc; + + tc = (leon3_timecounter *) base; + return -(*tc->counter_register); +} + +static void leon3_counter_use_gptimer( + leon3_timecounter *tc, + gptimer *gpt +) +{ + gptimer_timer *timer; -static uint32_t leon3_counter_frequency = 1000000000; + timer = &gpt->timer[LEON3_COUNTER_GPTIMER_INDEX]; + + /* Make timer free-running */ + grlib_store_32(&timer->trldval, 0xffffffff); + grlib_store_32(&timer->tctrl, GPTIMER_TCTRL_EN | GPTIMER_TCTRL_RS); + + tc->counter_register = &timer->tcntval; + tc->base.tc_get_timecount = leon3_timecounter_get_counter_down; +#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER) + tc->base.tc_frequency = LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER; +#else + tc->base.tc_frequency = ambapp_freq_get(ambapp_plb(), LEON3_Timer_Adev) / + (grlib_load_32(&gpt->sreload) + 1); +#endif +} + +#if defined(LEON3_IRQAMP_PROBE_TIMESTAMP) + +static uint32_t leon3_timecounter_get_counter_up(struct timecounter *base) +{ + leon3_timecounter *tc; + + tc = (leon3_timecounter *) base; + return *tc->counter_register; +} + +static void leon3_counter_use_irqamp_timestamp( + leon3_timecounter *tc, + irqamp_timestamp *irqmp_ts +) +{ + /* Enable interrupt timestamping for an arbitrary interrupt line */ + grlib_store_32(&irqmp_ts->itstmpc, IRQAMP_ITSTMPC_TSISEL(1)); + + tc->counter_register = &irqmp_ts->itcnt; + tc->base.tc_get_timecount = leon3_timecounter_get_counter_up; + tc->base.tc_frequency = leon3_processor_local_bus_frequency(); +} + +#endif /* LEON3_IRQAMP_PROBE_TIMESTAMP */ +#endif /* LEON3_HAS_ASR_22_23_UP_COUNTER || LEON3_DSU_BASE */ + +leon3_timecounter leon3_timecounter_instance = { + .base = { + .tc_get_timecount = LEON3_GET_TIMECOUNT_INIT, + .tc_counter_mask = 0xffffffff, + .tc_frequency = 1000000000, + .tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER + } +}; uint32_t _CPU_Counter_frequency(void) { - return leon3_counter_frequency; + return leon3_timecounter_instance.base.tc_frequency; } static void leon3_counter_initialize(void) { - volatile struct irqmp_timestamp_regs *irqmp_ts; - volatile struct gptimer_regs *gpt; - SPARC_Counter *counter; +#if defined(LEON3_HAS_ASR_22_23_UP_COUNTER) - irqmp_ts = &LEON3_IrqCtrl_Regs->timestamp[0]; - gpt = LEON3_Timer_Regs; - counter = &_SPARC_Counter_mutable; + leon3_up_counter_enable(); + leon3_counter_use_asr_22_23_up_counter(&leon3_timecounter_instance); + +#elif defined(LEON3_DSU_BASE) + + leon3_counter_use_dsu_time_tag(&leon3_timecounter_instance); +#else /* !LEON3_HAS_ASR_22_23_UP_COUNTER && !LEON3_DSU_BASE */ + + /* Try to find the best CPU counter available */ + +#if defined(LEON3_IRQAMP_PROBE_TIMESTAMP) + irqamp_timestamp *irqmp_ts; +#endif + gptimer *gpt; + leon3_timecounter *tc; + + tc = &leon3_timecounter_instance; + +#if defined(LEON3_PROBE_ASR_22_23_UP_COUNTER) leon3_up_counter_enable(); if (leon3_up_counter_is_available()) { /* Use the LEON4 up-counter if available */ - counter->read_isr_disabled = _SPARC_Counter_read_asr23; - counter->read = _SPARC_Counter_read_asr23; + leon3_counter_use_asr_22_23_up_counter(tc); + return; + } +#endif - leon3_counter_frequency = leon3_up_counter_frequency(); - } else if (irqmp_has_timestamp(irqmp_ts)) { +#if defined(LEON3_IRQAMP_PROBE_TIMESTAMP) + irqmp_ts = irqamp_get_timestamp_registers(LEON3_IrqCtrl_Regs); + + if (irqmp_ts != NULL) { /* Use the interrupt controller timestamp counter if available */ - counter->read_isr_disabled = _SPARC_Counter_read_up; - counter->read = _SPARC_Counter_read_up; - counter->counter_register = &LEON3_IrqCtrl_Regs->timestamp[0].counter; + leon3_counter_use_irqamp_timestamp(tc, irqmp_ts); + return; + } +#endif - /* Enable interrupt timestamping for an arbitrary interrupt line */ - irqmp_ts->control = 0x1; + gpt = LEON3_Timer_Regs; - leon3_counter_frequency = ambapp_freq_get(ambapp_plb(), LEON3_IrqCtrl_Adev); - } else if (gpt != NULL) { +#if defined(LEON3_GPTIMER_BASE) + leon3_counter_use_gptimer(tc, gpt); +#else + if (gpt != NULL) { /* Fall back to the first GPTIMER if available */ - counter->read_isr_disabled = _SPARC_Counter_read_down; - counter->read = _SPARC_Counter_read_down; - counter->counter_register = &gpt->timer[LEON3_COUNTER_GPTIMER_INDEX].value; - - /* Enable timer just in case no clock driver is configured */ - gpt->timer[LEON3_COUNTER_GPTIMER_INDEX].reload = 0xffffffff; - gpt->timer[LEON3_COUNTER_GPTIMER_INDEX].ctrl |= GPTIMER_TIMER_CTRL_EN | - GPTIMER_TIMER_CTRL_RS | - GPTIMER_TIMER_CTRL_LD; - - leon3_counter_frequency = ambapp_freq_get(ambapp_plb(), LEON3_Timer_Adev) / - (gpt->scaler_reload + 1); + leon3_counter_use_gptimer(tc, gpt); } +#endif + +#endif /* LEON3_HAS_ASR_22_23_UP_COUNTER || LEON3_DSU_BASE */ } RTEMS_SYSINIT_ITEM( @@ -69,5 +297,3 @@ RTEMS_SYSINIT_ITEM( RTEMS_SYSINIT_CPU_COUNTER, RTEMS_SYSINIT_ORDER_FIRST ); - -SPARC_COUNTER_DEFINITION; diff --git a/bsps/sparc/leon3/start/drvmgr_def_drivers.c b/bsps/sparc/leon3/start/drvmgr_def_drivers.c index 688b37bab9..2eeed6ec46 100644 --- a/bsps/sparc/leon3/start/drvmgr_def_drivers.c +++ b/bsps/sparc/leon3/start/drvmgr_def_drivers.c @@ -1,12 +1,31 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* * Default BSP drivers when Driver Manager enabled * * COPYRIGHT (c) 2019. * Cobham Gaisler * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> diff --git a/bsps/sparc/leon3/start/eirq.c b/bsps/sparc/leon3/start/eirq.c index 2b69b68a13..58ef1828d6 100644 --- a/bsps/sparc/leon3/start/eirq.c +++ b/bsps/sparc/leon3/start/eirq.c @@ -1,31 +1,64 @@ -/* - * GRLIB/LEON3 extended interrupt controller +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 * - * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * @brief This source file contains the implementation of the interrupt + * controller support. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG * * COPYRIGHT (c) 2011 * Aeroflex Gaisler * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * */ -#include <leon.h> -#include <bsp/irq.h> #include <bsp/irq-generic.h> +#include <bsp/irqimpl.h> +#include <rtems/score/processormaskimpl.h> +#if !defined(LEON3_IRQAMP_EXTENDED_INTERRUPT) /* GRLIB extended IRQ controller IRQ number */ -int LEON3_IrqCtrl_EIrq = -1; +uint32_t LEON3_IrqCtrl_EIrq; +#endif + +rtems_interrupt_lock LEON3_IrqCtrl_Lock = + RTEMS_INTERRUPT_LOCK_INITIALIZER("LEON3 IrqCtrl"); /* Initialize Extended Interrupt controller */ -void leon3_ext_irq_init(void) +void leon3_ext_irq_init(irqamp *regs) { - if ( (LEON3_IrqCtrl_Regs->mpstat >> 16) & 0xf ) { - /* Extended IRQ controller available */ - LEON3_IrqCtrl_EIrq = (LEON3_IrqCtrl_Regs->mpstat >> 16) & 0xf; - } + grlib_store_32(®s->pimask[LEON3_Cpu_Index], 0); + grlib_store_32(®s->piforce[LEON3_Cpu_Index], 0); + grlib_store_32(®s->iclear, 0xffffffff); +#if !defined(LEON3_IRQAMP_EXTENDED_INTERRUPT) + LEON3_IrqCtrl_EIrq = IRQAMP_MPSTAT_EIRQ_GET(grlib_load_32(®s->mpstat)); +#endif } bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) @@ -34,11 +67,15 @@ bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) return false; } +#if defined(LEON3_IRQAMP_EXTENDED_INTERRUPT) + return vector <= BSP_INTERRUPT_VECTOR_MAX_EXT; +#else if (LEON3_IrqCtrl_EIrq > 0) { return vector <= BSP_INTERRUPT_VECTOR_MAX_EXT; } return vector <= BSP_INTERRUPT_VECTOR_MAX_STD; +#endif } #if defined(RTEMS_SMP) @@ -57,6 +94,8 @@ void bsp_interrupt_facility_initialize(void) leon3_interrupt_affinities[i] = affinity; } #endif + + leon3_ext_irq_init(LEON3_IrqCtrl_Regs); } rtems_status_code bsp_interrupt_get_attributes( @@ -88,14 +127,16 @@ rtems_status_code bsp_interrupt_is_pending( { rtems_interrupt_level level; uint32_t bit; + irqamp *regs; bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); bsp_interrupt_assert(pending != NULL); bit = 1U << vector; + regs = LEON3_IrqCtrl_Regs; rtems_interrupt_local_disable(level); - *pending = (LEON3_IrqCtrl_Regs->ipend & bit) != 0 || - (LEON3_IrqCtrl_Regs->force[rtems_scheduler_get_processor()] & bit) != 0; + *pending = (grlib_load_32(®s->ipend) & bit) != 0 || + (grlib_load_32(®s->piforce[rtems_scheduler_get_processor()]) & bit) != 0; rtems_interrupt_local_enable(level); return RTEMS_SUCCESSFUL; } @@ -103,9 +144,11 @@ rtems_status_code bsp_interrupt_is_pending( rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) { uint32_t bit; + irqamp *regs; bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); bit = 1U << vector; + regs = LEON3_IrqCtrl_Regs; if ( vector <= BSP_INTERRUPT_VECTOR_MAX_STD ) { uint32_t cpu_count; @@ -114,10 +157,11 @@ rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) cpu_count = rtems_scheduler_get_processor_maximum(); for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) { - LEON3_IrqCtrl_Regs->force[cpu_index] = bit; + grlib_store_32(®s->piforce[cpu_index], bit); } } else { rtems_interrupt_lock_context lock_context; + uint32_t ipend; /* * This is a very dangerous operation and should only be used for test @@ -125,7 +169,9 @@ rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) * peripherals with this read-modify-write operation. */ LEON3_IRQCTRL_ACQUIRE(&lock_context); - LEON3_IrqCtrl_Regs->ipend |= bit; + ipend = grlib_load_32(®s->ipend); + ipend |= bit; + grlib_store_32(®s->ipend, ipend); LEON3_IRQCTRL_RELEASE(&lock_context); } @@ -138,6 +184,8 @@ rtems_status_code bsp_interrupt_raise_on( uint32_t cpu_index ) { + irqamp *regs; + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); bsp_interrupt_assert(cpu_index < rtems_scheduler_get_processor_maximum()); @@ -145,7 +193,8 @@ rtems_status_code bsp_interrupt_raise_on( return RTEMS_UNSATISFIED; } - LEON3_IrqCtrl_Regs->force[cpu_index] = 1U << vector; + regs = LEON3_IrqCtrl_Regs; + grlib_store_32(®s->piforce[cpu_index], 1U << vector); return RTEMS_SUCCESSFUL; } #endif @@ -153,14 +202,16 @@ rtems_status_code bsp_interrupt_raise_on( rtems_status_code bsp_interrupt_clear(rtems_vector_number vector) { uint32_t bit; + irqamp *regs; bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); bit = 1U << vector; + regs = LEON3_IrqCtrl_Regs; - LEON3_IrqCtrl_Regs->iclear = bit; + grlib_store_32(®s->iclear, bit); if (vector <= BSP_INTERRUPT_VECTOR_MAX_STD) { - LEON3_IrqCtrl_Regs->force[rtems_scheduler_get_processor()] = bit << 16; + grlib_store_32(®s->piforce[rtems_scheduler_get_processor()], bit << 16); } return RTEMS_SUCCESSFUL; @@ -171,9 +222,16 @@ rtems_status_code bsp_interrupt_vector_is_enabled( bool *enabled ) { + uint32_t bit; + irqamp *regs; + uint32_t pimask; + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - *enabled = - !BSP_Cpu_Is_interrupt_masked(vector, _LEON3_Get_current_processor()); + + bit = 1U << vector; + regs = LEON3_IrqCtrl_Regs; + pimask = grlib_load_32(®s->pimask[_LEON3_Get_current_processor()]); + *enabled = (pimask & bit) != 0; return RTEMS_SUCCESSFUL; } @@ -185,6 +243,8 @@ static void leon3_interrupt_vector_enable(rtems_vector_number vector) Processor_mask affinity; uint32_t bit; uint32_t unmasked; + uint32_t brdcst; + irqamp *regs; if (vector <= BSP_INTERRUPT_VECTOR_MAX_STD) { affinity = leon3_interrupt_affinities[vector]; @@ -194,72 +254,103 @@ static void leon3_interrupt_vector_enable(rtems_vector_number vector) cpu_count = rtems_scheduler_get_processor_maximum(); bit = 1U << vector; + regs = LEON3_IrqCtrl_Regs; unmasked = 0; for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) { - uint32_t mask; + uint32_t pimask; - mask = LEON3_IrqCtrl_Regs->mask[cpu_index]; + pimask = grlib_load_32(®s->pimask[cpu_index]); if (_Processor_mask_Is_set(&affinity, cpu_index)) { ++unmasked; - mask |= bit; + pimask |= bit; } else { - mask &= ~bit; + pimask &= ~bit; } - LEON3_IrqCtrl_Regs->mask[cpu_index] = mask; + grlib_store_32(®s->pimask[cpu_index], pimask); } + brdcst = grlib_load_32(®s->brdcst); + if (unmasked > 1) { - LEON3_IrqCtrl_Regs->bcast |= bit; + brdcst |= bit; } else { - LEON3_IrqCtrl_Regs->bcast &= ~bit; + brdcst &= ~bit; } + + grlib_store_32(®s->brdcst, brdcst); } #endif rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) { -#if defined(RTEMS_SMP) rtems_interrupt_lock_context lock_context; +#if !defined(RTEMS_SMP) + uint32_t bit; + irqamp *regs; + uint32_t pimask; + uint32_t cpu_index; +#endif bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); +#if !defined(RTEMS_SMP) + bit = 1U << vector; + regs = LEON3_IrqCtrl_Regs; +#endif + LEON3_IRQCTRL_ACQUIRE(&lock_context); +#if defined(RTEMS_SMP) leon3_interrupt_vector_enable(vector); - LEON3_IRQCTRL_RELEASE(&lock_context); #else - bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - BSP_Cpu_Unmask_interrupt(vector, _LEON3_Get_current_processor()); + cpu_index = _LEON3_Get_current_processor(); + pimask = grlib_load_32(®s->pimask[cpu_index]); + pimask |= bit; + grlib_store_32(®s->pimask[cpu_index], pimask); #endif + LEON3_IRQCTRL_RELEASE(&lock_context); return RTEMS_SUCCESSFUL; } rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) { -#if defined(RTEMS_SMP) rtems_interrupt_lock_context lock_context; uint32_t bit; + irqamp *regs; + uint32_t pimask; uint32_t cpu_index; +#if defined(RTEMS_SMP) uint32_t cpu_count; + uint32_t brdcst; +#endif bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); bit = 1U << vector; - cpu_count = rtems_scheduler_get_processor_maximum(); + regs = LEON3_IrqCtrl_Regs; LEON3_IRQCTRL_ACQUIRE(&lock_context); +#if defined(RTEMS_SMP) + cpu_count = rtems_scheduler_get_processor_maximum(); + for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) { - LEON3_IrqCtrl_Regs->mask[cpu_index] &= ~bit; + pimask = grlib_load_32(®s->pimask[cpu_index]); + pimask &= ~bit; + grlib_store_32(®s->pimask[cpu_index], pimask); } - LEON3_IrqCtrl_Regs->bcast &= ~bit; - - LEON3_IRQCTRL_RELEASE(&lock_context); + brdcst = grlib_load_32(®s->brdcst); + brdcst &= ~bit; + grlib_store_32(®s->brdcst, brdcst); #else - bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - BSP_Cpu_Mask_interrupt(vector, _LEON3_Get_current_processor()); + cpu_index = _LEON3_Get_current_processor(); + pimask = grlib_load_32(®s->pimask[cpu_index]); + pimask &= ~bit; + grlib_store_32(®s->pimask[cpu_index], pimask); #endif + + LEON3_IRQCTRL_RELEASE(&lock_context); return RTEMS_SUCCESSFUL; } @@ -273,6 +364,7 @@ rtems_status_code bsp_interrupt_set_affinity( uint32_t cpu_count; uint32_t cpu_index; uint32_t bit; + irqamp *regs; if (vector >= RTEMS_ARRAY_SIZE(leon3_interrupt_affinities)) { return RTEMS_UNSATISFIED; @@ -280,6 +372,7 @@ rtems_status_code bsp_interrupt_set_affinity( cpu_count = rtems_scheduler_get_processor_maximum(); bit = 1U << vector; + regs = LEON3_IrqCtrl_Regs; LEON3_IRQCTRL_ACQUIRE(&lock_context); leon3_interrupt_affinities[vector] = *affinity; @@ -289,7 +382,7 @@ rtems_status_code bsp_interrupt_set_affinity( * using the new affinity. */ for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) { - if ((LEON3_IrqCtrl_Regs->mask[cpu_index] & bit) != 0) { + if ((grlib_load_32(®s->pimask[cpu_index]) & bit) != 0) { leon3_interrupt_vector_enable(vector); break; } diff --git a/bsps/sparc/leon3/start/gettargethash.c b/bsps/sparc/leon3/start/gettargethash.c new file mode 100644 index 0000000000..c51031dc4f --- /dev/null +++ b/bsps/sparc/leon3/start/gettargethash.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This source file contains the sparc/leon3 implementation of + * rtems_get_target_hash(). + */ + +/* + * Copyright (C) 2021, 2022 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems/config.h> +#include <rtems/counter.h> +#include <rtems/sysinit.h> +#include <rtems/score/hash.h> + +#include <bsp/leon3.h> + +static Hash_Control bsp_target_hash; + +static void bsp_target_hash_initialize( void ) +{ + Hash_Context context; + uint32_t frequency; + + _Hash_Initialize( &context ); + + frequency = rtems_counter_frequency(); + _Hash_Add_data( &context, &frequency, sizeof( frequency ) ); + + frequency = leon3_processor_local_bus_frequency(); + _Hash_Add_data( &context, &frequency, sizeof( frequency ) ); + + _Hash_Finalize( &context, &bsp_target_hash ); +} + +const char *rtems_get_target_hash( void ) +{ + return _Hash_Get_string( &bsp_target_hash ); +} + +RTEMS_SYSINIT_ITEM( + bsp_target_hash_initialize, + RTEMS_SYSINIT_TARGET_HASH, + RTEMS_SYSINIT_ORDER_SECOND +); diff --git a/bsps/sparc/leon3/start/setvec.c b/bsps/sparc/leon3/start/setvec.c index 31461893ff..b60796f3c4 100644 --- a/bsps/sparc/leon3/start/setvec.c +++ b/bsps/sparc/leon3/start/setvec.c @@ -1,6 +1,6 @@ /** * @file - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * @brief Install an interrupt vector on SPARC */ diff --git a/bsps/sparc/shared/doxygen.h b/bsps/sparc/shared/doxygen.h index 100a9b6c18..4ed2ae7285 100644 --- a/bsps/sparc/shared/doxygen.h +++ b/bsps/sparc/shared/doxygen.h @@ -1,4 +1,12 @@ /** + * @file + * + * @ingroup RTEMSImplDoxygen + * + * @brief This header file defines sparc-specific groups. + */ + +/** * @defgroup RTEMSBSPsSPARC SPARC * * @ingroup RTEMSBSPs diff --git a/bsps/sparc/shared/drvmgr/ambapp_bus_leon2.c b/bsps/sparc/shared/drvmgr/ambapp_bus_leon2.c index 1a60f23b22..753247d27e 100644 --- a/bsps/sparc/shared/drvmgr/ambapp_bus_leon2.c +++ b/bsps/sparc/shared/drvmgr/ambapp_bus_leon2.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* LEON2 GRLIB AMBA Plug & Play bus driver. * * COPYRIGHT (c) 2008. @@ -10,9 +12,26 @@ * to work. The PnP information is used to extract IRQs and base * register addresses. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> diff --git a/bsps/sparc/shared/drvmgr/leon2_amba_bus.c b/bsps/sparc/shared/drvmgr/leon2_amba_bus.c index aca776c753..9b8de54adc 100644 --- a/bsps/sparc/shared/drvmgr/leon2_amba_bus.c +++ b/bsps/sparc/shared/drvmgr/leon2_amba_bus.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* LEON2 Hardcoded bus driver. * * COPYRIGHT (c) 2008. @@ -11,9 +13,26 @@ * A Core is described by assigning a base register and * IRQ0..IRQ15 using the leon2_core structure. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdio.h> @@ -354,7 +373,7 @@ int leon2_amba_int_register DBG("Registering IRQ %d to func 0x%x arg 0x%x\n", irq, (unsigned int)isr, (unsigned int)arg); - return BSP_shared_interrupt_register(irq, info, isr, arg); + return rtems_interrupt_handler_install(irq, info, RTEMS_INTERRUPT_SHARED, isr, arg); } int leon2_amba_int_unregister @@ -373,7 +392,7 @@ int leon2_amba_int_unregister DBG("Unregistering IRQ %d to func 0x%x arg 0x%x\n", irq, (unsigned int)handler, (unsigned int)arg); - return BSP_shared_interrupt_unregister(irq, isr, arg); + return rtems_interrupt_handler_remove(irq, isr, arg); } int leon2_amba_int_clear @@ -388,7 +407,9 @@ int leon2_amba_int_clear if ( irq < 0 ) return -1; - BSP_shared_interrupt_clear(irq); + if (rtems_interrupt_clear(irq) != RTEMS_SUCCESSFUL) { + return DRVMGR_FAIL; + } return DRVMGR_OK; } @@ -405,7 +426,9 @@ int leon2_amba_int_mask if ( irq < 0 ) return -1; - BSP_shared_interrupt_mask(irq); + if (rtems_interrupt_vector_disable(irq) != RTEMS_SUCCESSFUL) { + return DRVMGR_FAIL; + } return DRVMGR_OK; } @@ -422,7 +445,9 @@ int leon2_amba_int_unmask if ( irq < 0 ) return -1; - BSP_shared_interrupt_unmask(irq); + if (rtems_interrupt_vector_enable(irq) != RTEMS_SUCCESSFUL) { + return DRVMGR_FAIL; + } return DRVMGR_OK; } diff --git a/bsps/sparc/shared/irq/bsp_isr_handler.c b/bsps/sparc/shared/irq/bsp_isr_handler.c index 2616b5caae..4cd5c7be17 100644 --- a/bsps/sparc/shared/irq/bsp_isr_handler.c +++ b/bsps/sparc/shared/irq/bsp_isr_handler.c @@ -1,15 +1,44 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This source file contains the implementation of + * _SPARC_Interrupt_dispatch(). + */ + /* -* COPYRIGHT (c) 2015 -* Cobham Gaisler -* -* The license and distribution terms for this file may be -* found in the file LICENSE in this distribution or at -* http://www.rtems.org/license/LICENSE. -* -*/ + * COPYRIGHT (c) 2015 + * Cobham Gaisler + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ #include <bsp.h> #include <bsp/irq-generic.h> +#include <bsp/irqimpl.h> /* * This function is called directly from _SPARC_Interrupt_trap() for diff --git a/bsps/sparc/shared/irq/irq-shared.c b/bsps/sparc/shared/irq/irq-shared.c index c815e00e40..3d73ad90e7 100644 --- a/bsps/sparc/shared/irq/irq-shared.c +++ b/bsps/sparc/shared/irq/irq-shared.c @@ -1,31 +1,41 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* -* COPYRIGHT (c) 2012-2015 -* Cobham Gaisler -* -* The license and distribution terms for this file may be -* found in the file LICENSE in this distribution or at -* http://www.rtems.org/license/LICENSE. -* -*/ + * COPYRIGHT (c) 2012-2015 + * Cobham Gaisler + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ #include <bsp.h> #include <bsp/irq-generic.h> +#include <rtems/score/processormaskimpl.h> static inline int bsp_irq_cpu(int irq) { -#if defined(RTEMS_SMP) - Processor_mask affinity; - - (void) bsp_interrupt_get_affinity((rtems_vector_number) irq, &affinity); - return (int) _Processor_mask_Find_last_set(&affinity); -#elif defined(LEON3) - return _LEON3_Get_current_processor(); -#else return 0; -#endif } -#if !defined(LEON3) bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) { if (vector == 0) { @@ -131,22 +141,25 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) BSP_Cpu_Mask_interrupt(vector, 0); return RTEMS_SUCCESSFUL; } -#endif - -void BSP_shared_interrupt_mask(int irq) -{ - BSP_Cpu_Mask_interrupt(irq, bsp_irq_cpu(irq)); -} -void BSP_shared_interrupt_unmask(int irq) +#if defined(RTEMS_SMP) +rtems_status_code bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +) { - BSP_Cpu_Unmask_interrupt(irq, bsp_irq_cpu(irq)); + (void) vector; + _Processor_mask_From_index( affinity, 0 ); + return RTEMS_UNSATISFIED; } -void BSP_shared_interrupt_clear(int irq) +rtems_status_code bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +) { - /* We don't have to interrupt lock here, because the register is only - * written and self clearing - */ - BSP_Clear_interrupt(irq); + (void) vector; + (void) affinity; + return RTEMS_UNSATISFIED; } +#endif diff --git a/bsps/sparc/shared/pci/gr_cpci_gr740.c b/bsps/sparc/shared/pci/gr_cpci_gr740.c index 96cb2196bf..bb5bb2db01 100644 --- a/bsps/sparc/shared/pci/gr_cpci_gr740.c +++ b/bsps/sparc/shared/pci/gr_cpci_gr740.c @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* GR-CPCI-GR740 PCI Target driver. * * COPYRIGHT (c) 2017. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * Configures the GR-CPCI-GR740 interface PCI board in peripheral * mode. This driver provides a AMBA PnP bus by using the general part diff --git a/bsps/sparc/shared/pci/gr_leon4_n2x.c b/bsps/sparc/shared/pci/gr_leon4_n2x.c index af7a5d7ec3..26fa8d0d16 100644 --- a/bsps/sparc/shared/pci/gr_leon4_n2x.c +++ b/bsps/sparc/shared/pci/gr_leon4_n2x.c @@ -1,11 +1,32 @@ -/* GR-CPCI-LEON4-N2X (NGFP) PCI Peripheral driver - * +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* * COPYRIGHT (c) 2013. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* @brief GR-CPCI-LEON4-N2X (NGFP) PCI Peripheral driver * * Configures the GR-CPIC-LEON4-N2X interface PCI board in peripheral * mode. This driver provides a AMBA PnP bus by using the general part diff --git a/bsps/sparc/shared/pci/pci_memreg_sparc_be.c b/bsps/sparc/shared/pci/pci_memreg_sparc_be.c index 6dae9c89fe..c2a942c1bb 100644 --- a/bsps/sparc/shared/pci/pci_memreg_sparc_be.c +++ b/bsps/sparc/shared/pci/pci_memreg_sparc_be.c @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* Registers-over-Memory Space - SPARC Big endian PCI bus definitions * * COPYRIGHT (c) 2011. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <pci.h> diff --git a/bsps/sparc/shared/pci/pci_memreg_sparc_le.c b/bsps/sparc/shared/pci/pci_memreg_sparc_le.c index bc95811f24..4f572c9d19 100644 --- a/bsps/sparc/shared/pci/pci_memreg_sparc_le.c +++ b/bsps/sparc/shared/pci/pci_memreg_sparc_le.c @@ -1,11 +1,30 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* Registers-over-Memory Space - SPARC Little endian PCI bus definitions * * COPYRIGHT (c) 2011. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsps/sparc/shared/start/bsp_fatal_exit.c b/bsps/sparc/shared/start/bsp_fatal_exit.c index 2ad11846e5..d2ecfb1b7a 100644 --- a/bsps/sparc/shared/start/bsp_fatal_exit.c +++ b/bsps/sparc/shared/start/bsp_fatal_exit.c @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @ingroup RTEMSBSPsSPARCShared @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2014. * Aeroflex Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp.h> diff --git a/bsps/sparc/shared/start/bsp_fatal_halt.c b/bsps/sparc/shared/start/bsp_fatal_halt.c deleted file mode 100644 index f53275a073..0000000000 --- a/bsps/sparc/shared/start/bsp_fatal_halt.c +++ /dev/null @@ -1,33 +0,0 @@ -/** - * @file - * @ingroup RTEMSBSPsSPARCShared - * @brief ERC32/LEON2 BSP Fatal_halt handler. - * - * COPYRIGHT (c) 2014. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <bsp.h> -#include <rtems/score/cpuimpl.h> - -void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) -{ -#ifdef BSP_POWER_DOWN_AT_FATAL_HALT - /* Spin CPU on fatal error exit */ - uint32_t level = sparc_disable_interrupts(); - - __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); - - while (1) ; /* loop forever */ -#else - /* - * Return to debugger, simulator, hypervisor or similar by exiting - * with an error code. g1=1, g2=FATAL_SOURCE, G3=error-code. - */ - sparc_syscall_exit(source, error); -#endif -} diff --git a/bsps/sparc/shared/start/bspgetworkarea.c b/bsps/sparc/shared/start/bspgetworkarea.c index 6ceda38c07..f30d6e186c 100644 --- a/bsps/sparc/shared/start/bspgetworkarea.c +++ b/bsps/sparc/shared/start/bspgetworkarea.c @@ -9,7 +9,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (C) 2019, 2021 embedded brains GmbH + * Copyright (C) 2019, 2021 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/sparc/shared/start/linkcmds.base b/bsps/sparc/shared/start/linkcmds.base index ed7ab38b37..b278c78a46 100644 --- a/bsps/sparc/shared/start/linkcmds.base +++ b/bsps/sparc/shared/start/linkcmds.base @@ -155,7 +155,7 @@ SECTIONS *(.rela.rtemsrwset*) } >ram .noinit (NOLOAD) : { - *(.noinit*) + *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) } > ram .rtemsstack (NOLOAD) : { *(SORT(.rtemsstack.*)) diff --git a/bsps/sparc/shared/start/sparc-counter-asm.S b/bsps/sparc/shared/start/sparc-counter-asm.S new file mode 100644 index 0000000000..590d77050d --- /dev/null +++ b/bsps/sparc/shared/start/sparc-counter-asm.S @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2016, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/asm.h> + + /* + * All functions except _SPARC_Counter_read_clock() in this module are + * sometimes called with traps disabled. + */ + + .section ".text" + .align 4 + + /* + * This is a workaround for: + * https://gcc.gnu.org/bugzilla//show_bug.cgi?id=69027 + */ + PUBLIC(_CPU_Counter_read) +SYM(_CPU_Counter_read): + sethi %hi(_SPARC_Counter + 4), %o1 + ld [%o1 + %lo(_SPARC_Counter + 4)], %o1 + or %o7, %g0, %g1 + call %o1, 0 + or %g1, %g0, %o7 + +#if defined(RTEMS_PROFILING) + /* + * This is a workaround for: + * https://gcc.gnu.org/bugzilla//show_bug.cgi?id=69027 + */ + PUBLIC(_SPARC_Counter_read_ISR_disabled) +SYM(_SPARC_Counter_read_ISR_disabled): + sethi %hi(_SPARC_Counter), %o1 + ld [%o1 + %lo(_SPARC_Counter)], %o1 + or %o7, %g0, %g1 + call %o1, 0 + or %g1, %g0, %o7 +#endif + + PUBLIC(_SPARC_Counter_read_default) +SYM(_SPARC_Counter_read_default): + sethi %hi(_SPARC_Counter + 12), %o1 + ld [%o1 + %lo(_SPARC_Counter + 12)], %o0 + add %o0, 1, %o0 + st %o0, [%o1 + %lo(_SPARC_Counter + 12)] + jmp %o7 + 8 + nop + + /* + * For the corresponding C code is something like this: + * + * CPU_Counter_ticks _SPARC_Counter_read_clock_isr_disabled( void ) + * { + * const SPARC_Counter *ctr; + * CPU_Counter_ticks ticks; + * CPU_Counter_ticks accumulated; + * + * ctr = &_SPARC_Counter; + * ticks = *ctr->counter_register; + * accumulated = ctr->accumulated; + * + * if ( ( *ctr->pending_register & ctr->pending_mask ) != 0 ) { + * ticks = *ctr->counter_register; + * accumulated += ctr->interval; + * } + * + * return accumulated - ticks; + * } + */ + PUBLIC(_SPARC_Counter_read_clock_isr_disabled) +SYM(_SPARC_Counter_read_clock_isr_disabled): + sethi %hi(_SPARC_Counter), %o5 + or %o5, %lo(_SPARC_Counter), %o5 + ld [%o5 + 8], %o3 + ld [%o5 + 12], %o4 + ld [%o5 + 16], %o2 + ld [%o3], %o0 + ld [%o4], %o1 + btst %o1, %o2 + bne .Lpending_isr_disabled + ld [%o5 + 20], %o4 + jmp %o7 + 8 + sub %o4, %o0, %o0 +.Lpending_isr_disabled: + ld [%o5 + 24], %o5 + ld [%o3], %o0 + add %o4, %o5, %o4 + jmp %o7 + 8 + sub %o4, %o0, %o0 + + /* + * For the corresponding C code see + * _SPARC_Counter_read_clock_isr_disabled() above. + */ + PUBLIC(_SPARC_Counter_read_clock) + PUBLIC(_SPARC_Get_timecount_clock) +SYM(_SPARC_Counter_read_clock): +SYM(_SPARC_Get_timecount_clock): + sethi %hi(_SPARC_Counter), %o5 + or %o5, %lo(_SPARC_Counter), %o5 + ta SPARC_SWTRAP_IRQDIS + ld [%o5 + 8], %o3 + ld [%o5 + 12], %o4 + ld [%o5 + 16], %o2 + ld [%o3], %o0 + ld [%o4], %o1 + btst %o1, %o2 + bne .Lpending + ld [%o5 + 20], %o4 + ta SPARC_SWTRAP_IRQEN +#ifdef __FIX_LEON3FT_TN0018 + /* A nop is added to work around the GRLIB-TN-0018 errata */ + nop +#endif + jmp %o7 + 8 + sub %o4, %o0, %o0 +.Lpending: + ld [%o5 + 24], %o5 + ld [%o3], %o0 + ta SPARC_SWTRAP_IRQEN + add %o4, %o5, %o4 + jmp %o7 + 8 + sub %o4, %o0, %o0 diff --git a/bsps/sparc/shared/start/start.S b/bsps/sparc/shared/start/start.S index 45bd145d4a..8a22f8ff74 100644 --- a/bsps/sparc/shared/start/start.S +++ b/bsps/sparc/shared/start/start.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * Common start code for SPARC. * @@ -10,9 +12,26 @@ * COPYRIGHT (c) 1989-2011. * On-Line Applications Research Corporation (OAR). * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <rtems/asm.h> @@ -474,17 +493,13 @@ SYM(hard_reset): mov %sp, %fp ! set frame pointer #if defined(START_LEON3_ENABLE_SMP) - /* If LEON3_Boot_Cpu < 0 then assign us as boot CPU and continue. */ - set SYM(LEON3_Boot_Cpu), %l0 - ld [%l0], %l1 - tst %l1 - bneg .Lbootcpu - nop - - call SYM(bsp_start_on_secondary_processor) ! does not return - mov %g6, %o0 -.Lbootcpu: - st %l7, [%l0] + /* If .Lbootcpuindex < 0 then assign us as boot CPU and continue. */ + set SYM(.Lbootcpuindex), %l0 + mov -1, %l1 + casa [%l0] (10), %l1, %l7 + cmp %l1, %l7 + bne .Lbootsecondarycpu + nop #endif /* clear the bss */ @@ -508,4 +523,21 @@ SYM(hard_reset): call SYM(boot_card) ! does not return mov %g0, %o0 ! command line +#if defined(START_LEON3_ENABLE_SMP) +.Lbootsecondarycpu: + call SYM(bsp_start_on_secondary_processor) ! does not return + mov %g6, %o0 + + /* + * This is the index of the boot CPU. Set by the first CPU at boot to + * its CPU index. + */ + .section .data, "aw" + .align 4 + .type .Lbootcpuindex, #object + .size .Lbootcpuindex, 4 +.Lbootcpuindex: + .long -1 +#endif + /* end of file */ |