diff options
Diffstat (limited to 'bsps/riscv/riscv/start')
-rw-r--r-- | bsps/riscv/riscv/start/bsp_fatal_halt.c | 17 | ||||
-rw-r--r-- | bsps/riscv/riscv/start/bsp_specs | 0 | ||||
-rw-r--r-- | bsps/riscv/riscv/start/bspsmp.c | 7 | ||||
-rw-r--r-- | bsps/riscv/riscv/start/bspstart.c | 76 | ||||
-rw-r--r-- | bsps/riscv/riscv/start/linkcmds.in | 46 |
5 files changed, 86 insertions, 60 deletions
diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c index d9708661a7..06fffad6df 100644 --- a/bsps/riscv/riscv/start/bsp_fatal_halt.c +++ b/bsps/riscv/riscv/start/bsp_fatal_halt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -38,11 +38,20 @@ void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) int node; volatile uint32_t *sifive_test; -#if RISCV_ENABLE_HTIF_SUPPORT != 0 - htif_poweroff(); + fdt = bsp_fdt_get(); + +#ifdef RISCV_ENABLE_HTIF_SUPPORT + node = fdt_node_offset_by_compatible(fdt, -1, "ucb,htif0"); + + if (node >= 0) { + htif_poweroff(); + } +#endif + +#if RISCV_ENABLE_MPFS_SUPPORT != 0 + for(;;); #endif - fdt = bsp_fdt_get(); node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0"); sifive_test = riscv_fdt_get_address(fdt, node); diff --git a/bsps/riscv/riscv/start/bsp_specs b/bsps/riscv/riscv/start/bsp_specs deleted file mode 100644 index e69de29bb2..0000000000 --- a/bsps/riscv/riscv/start/bsp_specs +++ /dev/null diff --git a/bsps/riscv/riscv/start/bspsmp.c b/bsps/riscv/riscv/start/bspsmp.c index 4f1b3c93cc..a6884299a0 100644 --- a/bsps/riscv/riscv/start/bspsmp.c +++ b/bsps/riscv/riscv/start/bspsmp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,10 +36,7 @@ void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self) cpu_index_self = _Per_CPU_Get_index(cpu_self); - if ( - cpu_index_self < rtems_configuration_get_maximum_processors() - && _SMP_Should_start_processor(cpu_index_self) - ) { + if (_SMP_Should_start_processor(cpu_index_self)) { set_csr(mie, MIP_MSIP | MIP_MEIP); _SMP_Start_multitasking_on_secondary_processor(cpu_self); } else { diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c index d33e9965f8..d65741b13f 100644 --- a/bsps/riscv/riscv/start/bspstart.c +++ b/bsps/riscv/riscv/start/bspstart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -74,6 +74,10 @@ void *riscv_fdt_get_address(const void *fdt, int node) return (void *)(uintptr_t) addr; } +#if RISCV_ENABLE_MPFS_SUPPORT != 0 +uint32_t riscv_hart_count; +static uint32_t riscv_hart_phandles[5]; +#else #ifdef RTEMS_SMP uint32_t riscv_hart_count; @@ -81,6 +85,7 @@ static uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS]; #else static uint32_t riscv_hart_phandles[1]; #endif +#endif static void riscv_find_harts(void) { @@ -106,6 +111,14 @@ static void riscv_find_harts(void) hart_index = fdt32_to_cpu(val[0]); +#if RISCV_BOOT_HARTID != 0 + if (hart_index < RISCV_BOOT_HARTID) { + continue; + } + + hart_index -= RISCV_BOOT_HARTID; +#endif + if (hart_index >= RTEMS_ARRAY_SIZE(riscv_hart_phandles)) { continue; } @@ -146,9 +159,13 @@ static void riscv_find_harts(void) riscv_hart_phandles[hart_index] = phandle; } +#if RISCV_ENABLE_MPFS_SUPPORT != 0 + riscv_hart_count = max_hart_index + 1; +#else #ifdef RTEMS_SMP riscv_hart_count = max_hart_index + 1; #endif +#endif } uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) @@ -157,7 +174,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) for (hart_index = 0; hart_index < riscv_hart_count; ++hart_index) { if (riscv_hart_phandles[hart_index] == phandle) { - return hart_index; + return hart_index + RISCV_BOOT_HARTID; } } @@ -166,7 +183,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) static uint32_t get_core_frequency(void) { -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 +#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 || RISCV_ENABLE_MPFS_SUPPORT != 0 uint32_t node; const char *fdt; const char *tlclk; @@ -177,7 +194,13 @@ static uint32_t get_core_frequency(void) node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock"); tlclk = fdt_getprop(fdt, node, "clock-output-names", &len); - if (strcmp(tlclk,"tlclk") != 0) { +#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 + if (strcmp(tlclk,"tlclk") != 0) +#endif +#if RISCV_ENABLE_MPFS_SUPPORT != 0 + if (strcmp(tlclk,"msspllclk") != 0) +#endif + { bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE); } @@ -186,7 +209,16 @@ static uint32_t get_core_frequency(void) return fdt32_to_cpu(*val); } #endif + +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0 + uint32_t cpu_clock; + + cpu_clock = k210_get_frequency(); + return cpu_clock; +#else return 0; +#endif + } uint32_t riscv_get_core_frequency(void) @@ -197,9 +229,43 @@ uint32_t riscv_get_core_frequency(void) uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells) { (void) icells; - return intr[0]; + return RISCV_INTERRUPT_VECTOR_EXTERNAL(intr[0]); } +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0 +uint32_t k210_get_frequency(void) +{ + k210_sysctl_t *sysctl = (k210_sysctl_t *)K210_SYSCTL_BASE; + uint32_t cpu_clock = 0; + uint32_t clk_freq; + uint32_t pll0, nr, nf, od; + uint32_t node; + const char *fdt; + const fdt32_t *val; + int len; + + fdt = bsp_fdt_get(); + node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock"); + val = fdt_getprop(fdt, node, "clock-frequency", &len); + if (val != NULL && len == 4) { + clk_freq = fdt32_to_cpu(*val); + + if (CLKSEL0_ACLK_SEL(sysctl->clk_sel0) == 1) { + /* PLL0 selected */ + pll0 = sysctl->pll0; + nr = PLL_CLK_R(pll0) + 1; + nf = PLL_CLK_F(pll0) + 1; + od = PLL_CLK_OD(pll0) + 1; + cpu_clock = (clk_freq / nr * nf / od)/2; + } else { + /* OSC selected */ + cpu_clock = clk_freq; + } + } + return cpu_clock; +} +#endif + void bsp_start(void) { riscv_find_harts(); diff --git a/bsps/riscv/riscv/start/linkcmds.in b/bsps/riscv/riscv/start/linkcmds.in deleted file mode 100644 index 80e2f5ef90..0000000000 --- a/bsps/riscv/riscv/start/linkcmds.in +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -MEMORY -{ - RAM : ORIGIN = @RISCV_RAM_REGION_BEGIN@, LENGTH = @RISCV_RAM_REGION_SIZE@ -} - -REGION_ALIAS ("REGION_START", RAM); -REGION_ALIAS ("REGION_TEXT", RAM); -REGION_ALIAS ("REGION_TEXT_LOAD", RAM); -REGION_ALIAS ("REGION_FAST_TEXT", RAM); -REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM); -REGION_ALIAS ("REGION_RODATA", RAM); -REGION_ALIAS ("REGION_RODATA_LOAD", RAM); -REGION_ALIAS ("REGION_DATA", RAM); -REGION_ALIAS ("REGION_DATA_LOAD", RAM); -REGION_ALIAS ("REGION_FAST_DATA", RAM); -REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); -REGION_ALIAS ("REGION_RTEMSSTACK", RAM); -REGION_ALIAS ("REGION_WORK", RAM); - -INCLUDE linkcmds.base |