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-rw-r--r--bsps/include/dev/serial/arm-pl011-regs.h27
-rw-r--r--bsps/include/dev/serial/arm-pl011.h27
-rw-r--r--bsps/include/dev/serial/zynq-uart-regs.h22
-rw-r--r--bsps/include/dev/serial/zynq-uart-zynq.h66
-rw-r--r--bsps/include/dev/serial/zynq-uart-zynqmp.h66
-rw-r--r--bsps/include/dev/serial/zynq-uart.h27
6 files changed, 201 insertions, 34 deletions
diff --git a/bsps/include/dev/serial/arm-pl011-regs.h b/bsps/include/dev/serial/arm-pl011-regs.h
index eaf560ed8b..d6ea9ae11a 100644
--- a/bsps/include/dev/serial/arm-pl011-regs.h
+++ b/bsps/include/dev/serial/arm-pl011-regs.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
@@ -7,11 +9,28 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H
diff --git a/bsps/include/dev/serial/arm-pl011.h b/bsps/include/dev/serial/arm-pl011.h
index 75ceb676a8..a22fa1ac06 100644
--- a/bsps/include/dev/serial/arm-pl011.h
+++ b/bsps/include/dev/serial/arm-pl011.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
/**
* @file
*
@@ -7,11 +9,28 @@
*/
/*
- * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
*
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_SHARED_ARM_PL011_H
diff --git a/bsps/include/dev/serial/zynq-uart-regs.h b/bsps/include/dev/serial/zynq-uart-regs.h
index 8b6e7d513b..5e872d16c3 100644
--- a/bsps/include/dev/serial/zynq-uart-regs.h
+++ b/bsps/include/dev/serial/zynq-uart-regs.h
@@ -7,7 +7,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2013 embedded brains GmbH
+ * Copyright (C) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,6 +43,8 @@
#include <bsp/utility.h>
+#define ZYNQ_UART_DEFAULT_BAUD 115200
+
#define ZYNQ_UART_FIFO_DEPTH 64
typedef struct zynq_uart {
@@ -158,6 +160,24 @@ typedef struct zynq_uart {
#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
} zynq_uart;
+void zynq_uart_initialize(volatile zynq_uart *regs);
+
+int zynq_uart_read_char_polled(volatile zynq_uart *regs);
+
+void zynq_uart_write_char_polled(volatile zynq_uart *regs, char c);
+
+/**
+ * Flush TX FIFO and wait until it is empty. Used in bsp_reset.
+ */
+void zynq_uart_reset_tx_flush(volatile zynq_uart *regs);
+
+int zynq_cal_baud_rate(
+ uint32_t baudrate,
+ uint32_t* brgr,
+ uint32_t* bauddiv,
+ uint32_t modereg
+);
+
/** @} */
#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */
diff --git a/bsps/include/dev/serial/zynq-uart-zynq.h b/bsps/include/dev/serial/zynq-uart-zynq.h
new file mode 100644
index 0000000000..169037b33a
--- /dev/null
+++ b/bsps/include/dev/serial/zynq-uart-zynq.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup zynq_uart
+ *
+ * @brief This header file provides interfaces with respect to the Zynq
+ * platform.
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_SERIAL_ZYNQ_UART_ZYNQ_H
+#define _DEV_SERIAL_ZYNQ_UART_ZYNQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @addtogroup zynq_uart
+ *
+ * @{
+ */
+
+/**
+ * @brief This constant defines the Xilinx Zynq UART 0 base address.
+ */
+#define ZYNQ_UART_0_BASE_ADDR 0xe0000000
+
+/**
+ * @brief This constant defines the Xilinx Zynq UART 1 base address.
+ */
+#define ZYNQ_UART_1_BASE_ADDR 0xe0001000
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DEV_SERIAL_ZYNQ_UART_ZYNQ_H */
diff --git a/bsps/include/dev/serial/zynq-uart-zynqmp.h b/bsps/include/dev/serial/zynq-uart-zynqmp.h
new file mode 100644
index 0000000000..9f29003053
--- /dev/null
+++ b/bsps/include/dev/serial/zynq-uart-zynqmp.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup zynq_uart
+ *
+ * @brief This header file provides interfaces with respect to the Zynq
+ * UltraScale+ MPSoC and RFSoC platforms.
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H
+#define _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @addtogroup zynq_uart
+ *
+ * @{
+ */
+
+/**
+ * @brief This constant defines the Xilinx Zynq UART 0 base address.
+ */
+#define ZYNQ_UART_0_BASE_ADDR 0xff000000
+
+/**
+ * @brief This constant defines the Xilinx Zynq UART 1 base address.
+ */
+#define ZYNQ_UART_1_BASE_ADDR 0xff010000
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H */
diff --git a/bsps/include/dev/serial/zynq-uart.h b/bsps/include/dev/serial/zynq-uart.h
index b21e16f6de..002adcdbd6 100644
--- a/bsps/include/dev/serial/zynq-uart.h
+++ b/bsps/include/dev/serial/zynq-uart.h
@@ -7,7 +7,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (C) 2013, XXX embedded brains GmbH
+ * Copyright (C) 2013, XXX embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -34,7 +34,7 @@
#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_H
#define LIBBSP_ARM_XILINX_ZYNQ_UART_H
-#include <rtems/termiostypes.h>
+#include <rtems/termiosdevice.h>
#ifdef __cplusplus
extern "C" {
@@ -59,29 +59,6 @@ typedef struct {
extern const rtems_termios_device_handler zynq_uart_handler;
-#define ZYNQ_UART_DEFAULT_BAUD 115200
-
-void zynq_uart_initialize(rtems_termios_device_context *base);
-
-int zynq_uart_read_polled(rtems_termios_device_context *base);
-
-void zynq_uart_write_polled(
- rtems_termios_device_context *base,
- char c
-);
-
-/**
- * Flush TX FIFO and wait until it is empty. Used in bsp_reset.
- */
-void zynq_uart_reset_tx_flush(zynq_uart_context *ctx);
-
-int zynq_cal_baud_rate(
- uint32_t baudrate,
- uint32_t* brgr,
- uint32_t* bauddiv,
- uint32_t modereg
-);
-
#ifdef __cplusplus
}
#endif /* __cplusplus */