diff options
Diffstat (limited to 'bsps/arm/imxrt/start')
| -rw-r--r-- | bsps/arm/imxrt/start/bspstart.c | 29 | ||||
| -rw-r--r-- | bsps/arm/imxrt/start/bspstarthooks.c | 38 | ||||
| -rw-r--r-- | bsps/arm/imxrt/start/clock-arm-pll-config.c | 33 | ||||
| -rw-r--r-- | bsps/arm/imxrt/start/flash-boot-data.c | 4 | ||||
| -rw-r--r-- | bsps/arm/imxrt/start/flash-dcd.c | 283 | ||||
| -rw-r--r-- | bsps/arm/imxrt/start/flash-flexspi-config.c | 60 | ||||
| -rw-r--r-- | bsps/arm/imxrt/start/flash-ivt.c | 2 | ||||
| -rw-r--r-- | bsps/arm/imxrt/start/imxrt-ffec-init.c | 8 | ||||
| -rw-r--r-- | bsps/arm/imxrt/start/mpu-config.c | 10 |
9 files changed, 67 insertions, 400 deletions
diff --git a/bsps/arm/imxrt/start/bspstart.c b/bsps/arm/imxrt/start/bspstart.c index 445af04563..1d583d7ca4 100644 --- a/bsps/arm/imxrt/start/bspstart.c +++ b/bsps/arm/imxrt/start/bspstart.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -47,6 +47,7 @@ uint32_t imxrt_systick_frequency(void) static void imxrt_disable_wait_mode(void) { +#if IMXRT_IS_MIMXRT10xx /* * Prevent processor from entering WAIT or SLEEP mode when a WFI is executed. * This would switch off the normal interrupt controller and activate an @@ -58,6 +59,16 @@ static void imxrt_disable_wait_mode(void) * every WFI. */ CLOCK_SetMode(kCLOCK_ModeRun); +#elif IMXRT_IS_MIMXRT11xx + /* + * i.MX RT11xx doesn't support disabling power saving for WFI. On the other + * hand it doesn't have a separate interrupt controller like the i.MX RT1050. + * So a power save during WFI is only annoying during debugging but doesn't + * hurt otherwise. + */ +#else + #error Disabling wait mode not implemented for this chip. +#endif } void bsp_start(void) @@ -125,6 +136,22 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells) return intr[0]; } +/* + * Clock frequencies for peripherals like SD card. These are used by libbsd + * drivers. + */ +#if IMXRT_IS_MIMXRT11xx +uint32_t +imx_ccm_sdhci_hz(void) +{ + /* + * We don't know which SDHCI is used. So just return the clock frequency + * of the first SDHCI and hope the best. + */ + return CLOCK_GetRootClockFreq(kCLOCK_Root_Usdhc1); +} +#endif + /* Make sure to pull in the flash headers */ __attribute__((used)) static const void *hdr_dcd = &imxrt_dcd_data; __attribute__((used)) static const void *hdr_ivt = &imxrt_image_vector_table; diff --git a/bsps/arm/imxrt/start/bspstarthooks.c b/bsps/arm/imxrt/start/bspstarthooks.c index b8149691e7..c10d0dbcfe 100644 --- a/bsps/arm/imxrt/start/bspstarthooks.c +++ b/bsps/arm/imxrt/start/bspstarthooks.c @@ -1,15 +1,28 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* - * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2023 embedded brains GmbH & Co. KG * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <rtems/score/armv7m.h> @@ -18,13 +31,10 @@ #include <imxrt/mpu-config.h> #include <chip.h> -#include <fsl_pin_mux.h> #include <fsl_clock_config.h> BSP_START_TEXT_SECTION void bsp_start_hook_0(void) { - /* FIXME: Initializing SDRAM is currently done by DCD. It would be more user - * friendly if that would be done here with a readable structure. */ if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) { SCB_EnableICache(); } @@ -33,7 +43,7 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void) SCB_EnableDCache(); } - _ARMV7M_MPU_Setup(imxrt_config_mpu_region, imxrt_config_mpu_region_count); + _ARMV7M_MPU_Setup(ARMV7M_MPU_CTRL_DEFAULT, imxrt_config_mpu_region, imxrt_config_mpu_region_count); } BSP_START_TEXT_SECTION void bsp_start_hook_1(void) @@ -46,9 +56,11 @@ BSP_START_TEXT_SECTION void bsp_start_hook_1(void) BOARD_BootClockRUN(); BOARD_InitDEBUG_UARTPins(); +#if IMXRT_IS_MIMXRT10xx /* Reduce frequency for I2C */ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); /* Enable EDMA clock. We initialize the EDMA so we need the clock. */ CLOCK_EnableClock(kCLOCK_Dma); +#endif } diff --git a/bsps/arm/imxrt/start/clock-arm-pll-config.c b/bsps/arm/imxrt/start/clock-arm-pll-config.c deleted file mode 100644 index 12ad1867eb..0000000000 --- a/bsps/arm/imxrt/start/clock-arm-pll-config.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_clock_config.h" - -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { - .loopDivider = 100, - .src = 0, -}; diff --git a/bsps/arm/imxrt/start/flash-boot-data.c b/bsps/arm/imxrt/start/flash-boot-data.c index a1877f4d26..2186fc08bf 100644 --- a/bsps/arm/imxrt/start/flash-boot-data.c +++ b/bsps/arm/imxrt/start/flash-boot-data.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -30,7 +30,7 @@ #include <bspopts.h> const BOOT_DATA_T imxrt_boot_data = { - .start = (uint32_t) imxrt_memory_flash_config_begin, + .start = (uint32_t) imxrt_memory_flash_raw_begin, .size = IMXRT_MEMORY_FLASH_SIZE, .plugin = PLUGIN_FLAG, .placeholder = 0xFFFFFFFF, diff --git a/bsps/arm/imxrt/start/flash-dcd.c b/bsps/arm/imxrt/start/flash-dcd.c deleted file mode 100644 index a53e5bda39..0000000000 --- a/bsps/arm/imxrt/start/flash-dcd.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <bsp/flash-headers.h> -#include <stdint.h> - -__attribute__((section(".boot_hdr.dcd_data"))) -const uint8_t imxrt_dcd_data[] = { - /* HEADER */ - /* Tag */ - 0xD2, - /* Image Length */ - 0x04, 0x10, - /* Version */ - 0x41, - - /* COMMANDS */ - - /* group: 'Imported Commands' */ - /* #1.1-113, command header bytes for merged 'Write - value' command */ - 0xCC, 0x03, 0x8C, 0x04, - /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ - 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, - /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */ - 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, - /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ - 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, - /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, - /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, - /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, - /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, - /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, - /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, - /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, - /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, - /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, - /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, - /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, - /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, - /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, - /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, - /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, - /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, - /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, - /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, - /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, - /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, - /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, - /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, - /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, - /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, - /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, - /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, - /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, - /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, - /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, - /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, - /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, - /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, - /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, - /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, - /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, - /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, - /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, - /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, - /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ - 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, - /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, - /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, - /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, - /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, - /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, - /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, - /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, - /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, - /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, - /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, - /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, - /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, - /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, - /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, - /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, - /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, - /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, - /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, - /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, - /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, - /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, - /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, - /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, - /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, - /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, - /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, - /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, - /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, - /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, - /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, - /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, - /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, - /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, - /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, - /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, - /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, - /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, - /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, - /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, - /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, - /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ - 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, - /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */ - 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, - /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */ - 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, - /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, - /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, - /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, - /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, - /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ - 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, - /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ - 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, - /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ - 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, - /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, - /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, - /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ - 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, - /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ - 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, - /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ - 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, - /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ - 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, - /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ - 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, - /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, - /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ - 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, - /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ - 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, - /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ - 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, - /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #3.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #5.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #7.1-3, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x1C, 0x04, - /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ - 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, - /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, - /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ - 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 - }; -/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ diff --git a/bsps/arm/imxrt/start/flash-flexspi-config.c b/bsps/arm/imxrt/start/flash-flexspi-config.c deleted file mode 100644 index 50eca19b20..0000000000 --- a/bsps/arm/imxrt/start/flash-flexspi-config.c +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <bsp/flash-headers.h> -#include <bspopts.h> - -const flexspi_nor_config_t imxrt_flexspi_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .columnAddressWidth = 3u, - .controllerMiscOption = (1 << kFlexSpiMiscOffset_DdrModeEnable) | - (1 << kFlexSpiMiscOffset_WordAddressableEnable) | - (1 << kFlexSpiMiscOffset_SafeConfigFreqEnable) | - (1 << kFlexSpiMiscOffset_DiffClkEnable), - .deviceType = kFlexSpiDeviceType_SerialRAM, - .sflashPadType = kSerialFlash_8Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = IMXRT_MEMORY_FLASH_SIZE, - .dataValidTime = {16u, 16u}, - .lookupTable = { - FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), - FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), - FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), - }, - .lutCustomSeq = {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, - {0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}, - }, - .pageSize = 0x200, - .sectorSize = 0x40000, - .blockSize = 0x40000, - .isUniformBlockSize = 1, -}; diff --git a/bsps/arm/imxrt/start/flash-ivt.c b/bsps/arm/imxrt/start/flash-ivt.c index fd396d5e1a..be3ec402a8 100644 --- a/bsps/arm/imxrt/start/flash-ivt.c +++ b/bsps/arm/imxrt/start/flash-ivt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/arm/imxrt/start/imxrt-ffec-init.c b/bsps/arm/imxrt/start/imxrt-ffec-init.c index 4b71944c00..c0a8e168e3 100644 --- a/bsps/arm/imxrt/start/imxrt-ffec-init.c +++ b/bsps/arm/imxrt/start/imxrt-ffec-init.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -41,6 +41,7 @@ void imxrt_ffec_init(void) fdt = bsp_fdt_get(); +#if IMXRT_IS_MIMXRT10xx const clock_enet_pll_config_t config = { .enableClkOutput = true, .enableClkOutput25M = false, @@ -49,7 +50,10 @@ void imxrt_ffec_init(void) CLOCK_InitEnetPll(&config); - iomuxc_gpr->GPR1 |= IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + iomuxc_gpr->GPR1 |= IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#else + iomuxc_gpr->GPR4 |= IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK; +#endif node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imxrt-fec"); if (node >= 0) { diff --git a/bsps/arm/imxrt/start/mpu-config.c b/bsps/arm/imxrt/start/mpu-config.c index 79800ac431..93a4cb08e4 100644 --- a/bsps/arm/imxrt/start/mpu-config.c +++ b/bsps/arm/imxrt/start/mpu-config.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Copyright (C) 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -44,8 +44,8 @@ BSP_START_DATA_SECTION const ARMV7M_MPU_Region_config | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B | ARMV7M_MPU_RASR_ENABLE, }, { - .begin = imxrt_memory_flash_config_begin, - .end = imxrt_memory_flash_end, + .begin = imxrt_memory_flash_raw_begin, + .end = imxrt_memory_flash_raw_end, .rasr = ARMV7M_MPU_RASR_AP(0x3) | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B | ARMV7M_MPU_RASR_ENABLE, @@ -53,13 +53,13 @@ BSP_START_DATA_SECTION const ARMV7M_MPU_Region_config .begin = imxrt_memory_extram_nocache_begin, .end = imxrt_memory_extram_nocache_end, .rasr = ARMV7M_MPU_RASR_AP(0x3) - | ARMV7M_MPU_RASR_TEX(0x2) + | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_ENABLE, }, { .begin = imxrt_memory_ocram_nocache_begin, .end = imxrt_memory_ocram_nocache_end, .rasr = ARMV7M_MPU_RASR_AP(0x3) - | ARMV7M_MPU_RASR_TEX(0x2) + | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_ENABLE, }, { .begin = imxrt_memory_peripheral_begin, |