diff options
Diffstat (limited to 'bsps/arm/beagle/dcan')
| -rw-r--r-- | bsps/arm/beagle/dcan/am335x-dcan.c | 104 | ||||
| -rw-r--r-- | bsps/arm/beagle/dcan/dcan.c | 646 | ||||
| -rwxr-xr-x | bsps/arm/beagle/dcan/hw_cm_per.h | 1407 | ||||
| -rwxr-xr-x | bsps/arm/beagle/dcan/hw_dcan.h | 1289 |
4 files changed, 3446 insertions, 0 deletions
diff --git a/bsps/arm/beagle/dcan/am335x-dcan.c b/bsps/arm/beagle/dcan/am335x-dcan.c new file mode 100644 index 0000000000..f4bb717e1d --- /dev/null +++ b/bsps/arm/beagle/dcan/am335x-dcan.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup CANBus + * + * @brief Controller Area Network (CAN) Bus Implementation + * + */ + +/* + * Copyright (C) 2022 Prashanth S (fishesprashanth@gmail.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dev/can/can.h> + +#include <bsp/am335x_dcan.h> +#include <bsp/soc_AM335x.h> + +#define IF_NAME_SIZE_MAX (12) + +void beagle_can_init(void *node) +{ + /* FIXME: Remove this method, Check if the device node belongs to CAN + * Will be removed once device tree support is added + */ + static int init = 0; + + if (init != 0) { + return; + } + + init = 1; + + CAN_DEBUG("beagle_can_init\n"); + + char if_name[IF_NAME_SIZE_MAX]; + + struct am335x_dcan_priv *priv = NULL; + + /* FIXME: Get hardware specific information from device tree */ + struct am335x_dcan_irq dcan_irq_nums[2] = {{52, 53, 54}, {55, 56, 57}}; + uint32_t dcan_base_reg_addr[] = {SOC_DCAN_0_REGS, SOC_DCAN_1_REGS}; + + for (int i = 0; i < CAN_NODES; i++) { + priv = (struct am335x_dcan_priv *)calloc(1, sizeof(struct am335x_dcan_priv)); + + if (priv == NULL) { + CAN_ERR("beagle_can_init: calloc failed: cannot allocate memory\n"); + return; + } + + /* FIXME: Get hardware specific information from device tree */ + priv->node = i; + priv->base_reg = dcan_base_reg_addr[i]; + priv->irq = dcan_irq_nums[i]; + priv->baudrate = 1000000; + + if (dcan_init(priv) < 0) { + CAN_ERR("beagle_can_init: CAN controller %d initialization failed\n", priv->node); + free(priv); + continue; + } + + struct can_bus *bus = can_bus_alloc_and_init(sizeof(struct can_bus)); + + priv->bus = bus; + + snprintf(if_name, IF_NAME_SIZE_MAX, "/dev/can%d", i); + + bus->priv = priv; + dcan_init_ops(priv); + + if (can_bus_register(bus, if_name) != 0) { + CAN_ERR("beagle_can_init: bus register failed\n"); + free(priv); + return; + } + + CAN_DEBUG("beagle_can_init: can_bus_registered %s\n", if_name); + } +} diff --git a/bsps/arm/beagle/dcan/dcan.c b/bsps/arm/beagle/dcan/dcan.c new file mode 100644 index 0000000000..9fee40a340 --- /dev/null +++ b/bsps/arm/beagle/dcan/dcan.c @@ -0,0 +1,646 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup CANBus + * + * @brief Controller Area Network (DCAN) Controller Implementation + * + */ + +/* + * Copyright (C) 2022 Prashanth S (fishesprashanth@gmail.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/am335x_dcan.h> +#include <bsp/soc_AM335x.h> +#include <bsp/hw_control_AM335x.h> + +#include <bsp/irq.h> +#include <bsp/irq-generic.h> + +#include <dev/can/can.h> + +#include "hw_dcan.h" +#include "hw_cm_per.h" + +/* + * Pin configurations. + */ +#define AM335x_PIN_IN_OFFSET (0x138) +#define AM335x_PIN_SLEW_FAST (0 << 6) +#define AM335x_PIN_SLEW_SLOW (1 << 6) +#define AM335x_PIN_RX_DISABLE (0 << 5) +#define AM335x_PIN_RX_ENABLE (1 << 5) +#define AM335x_PIN_PULL_DIS (1 << 3) +#define AM335x_PIN_PULL_EN (0 << 3) +#define AM335x_PIN_PULL_UP ((1 << 4) | AM335x_PIN_PULL_EN) +#define AM335x_PIN_PULL_DOWN ((0 << 4) | AM335x_PIN_PULL_EN) + +#define AM335x_PIN_MODE_0 (0) +#define AM335x_PIN_MODE_1 (1) +#define AM335x_PIN_MODE_2 (2) + +static int dcan_tx(void *, struct can_msg *); +static bool dcan_tx_ready(void *); +static void dcan_int_enable(struct am335x_dcan_priv *); +static void dcan_int_disable(struct am335x_dcan_priv *); +static void dcan_reset(struct am335x_dcan_priv *priv); +static void dcan_clk_config(uint32_t node); +static void dcan_isr(void *data); +static void dcan_int(void *, bool); +static int dcan_intr_init(struct am335x_dcan_priv *priv); +static void dcan_inval_obj(struct am335x_dcan_priv *priv, uint32_t index); +static void dcan_init_rxobj(struct am335x_dcan_priv *priv); +static void dcan_save_msg(struct am335x_dcan_priv *priv, struct can_msg *msg); +static void dcan_read_obj(struct am335x_dcan_priv *priv, uint32_t index); +static void dcan_bittiming(struct am335x_dcan_priv *priv); +static void am335x_dcan_pinmux(uint32_t index); + +/* FIXME: Should be moved to shared beagle */ +uint32_t am335x_get_sysclk(void); + +static struct can_dev_ops dev_ops = { + .dev_tx = dcan_tx, + .dev_tx_ready = dcan_tx_ready, + .dev_int = dcan_int, +}; + +void dcan_init_ops(struct am335x_dcan_priv *priv) +{ + CAN_DEBUG("dcan_init_ops\n"); + priv->bus->can_dev_ops = &dev_ops; +} + +/** + * @brief Convert Data Length Code (CAN specific) to length + * of the CAN message. + * + * @param[in] Data Length Code for the CAN message. + * + * @retval Corresponding length for the DLC. + */ +static uint16_t can_dlc_to_len(uint16_t dlc) +{ + if (dlc > 8) { + switch(dlc) { + case 9: + dlc = 12; + case 10: + dlc = 16; + case 11: + dlc = 20; + case 12: + dlc = 24; + case 13: + dlc = 32; + case 14: + dlc = 48; + default: + dlc = 64; + } + } + return dlc; +} + +/** + * @brief Convert Length to Data Length Code (CAN specific). + * + * @param[in] Length of the CAN message. + * + * @retval Corresponding DLC for the length. + */ +static uint16_t can_len_to_dlc(uint16_t len) +{ + if (len > 8) { + switch(len) { + case 12: + len = 9; + case 16: + len = 10; + case 20: + len = 11; + case 24: + len = 12; + case 32: + len = 13; + case 48: + len = 14; + default: + len = 64; + } + } + return len; +} + +/* FIXME: Make DCAN_TXRQ dynamic */ +static bool dcan_tx_ready(void *data) +{ + struct am335x_dcan_priv *priv = (struct am335x_dcan_priv *)data; + + CAN_DEBUG("dcan_tx_ready %08x = %08x\n", priv->base_reg + DCAN_TXRQ(1), + can_getreg(priv, DCAN_TXRQ(1))); + + if (can_getreg(priv, DCAN_TXRQ(1)) == 0xffffffff) + { + return false; + } + + return true; +} + +static void dcan_inval_obj(struct am335x_dcan_priv *priv, uint32_t index) +{ + while (can_getreg(priv, DCAN_IFCMD(2)) & DCAN_IFCMD_BUSY) { + /* busy wait */ + } + + can_putreg(priv, DCAN_IFARB(2), 0); + + /* Disable rx and tx interrupts, clear transmit request */ + + can_putreg(priv, DCAN_IFMCTL(2), DCAN_IFMCTL_EOB & (~DCAN_IFMCTL_INTPND)); + can_putreg(priv, DCAN_IFCMD(2), DCAN_IFCMD_WR_RD | + DCAN_IFCMD_CLRINTPND | DCAN_IFCMD_CONTROL | DCAN_IFCMD_ARB | + DCAN_IFCMD_MSG_NUM(index)); +} + +static void dcan_init_rxobj(struct am335x_dcan_priv *priv) +{ + while (can_getreg(priv, DCAN_IFCMD(2)) & DCAN_IFCMD_BUSY) { + /* busy wait */ + } + + can_putreg(priv, DCAN_IFMSK(2), DCAN_IFMSK_MXTD | DCAN_IFMSK_MDIR); + can_putreg(priv, DCAN_IFMCTL(2), DCAN_IFMCTL_DATALENGTHCODE | + DCAN_IFMCTL_EOB | DCAN_IFMCTL_RXIE | DCAN_IFMCTL_UMASK); + +#ifdef CONFIG_CAN_EXTID + can_putreg(priv, DCAN_IFARB(2), + DCAN_IFARB_MSGVAL | DCAN_IFARB_XTD); +#else + can_putreg(priv, DCAN_IFARB(2), DCAN_IFARB_MSGVAL); +#endif + + for (int i = CAN_RX_MSG_OBJ_START_NUM; i <= CAN_RX_MSG_OBJ_END_NUM; i++) + { + while (can_getreg(priv, DCAN_IFCMD(2)) & DCAN_IFCMD_BUSY) { + /* busy wait */ + } + can_putreg(priv, DCAN_IFCMD(2), + DCAN_IFCMD_WR_RD | DCAN_IFCMD_MASK | + DCAN_IFCMD_ARB | DCAN_IFCMD_CONTROL | + DCAN_IFCMD_CLRINTPND | + DCAN_IFCMD_DATAA | DCAN_IFCMD_DATAB | + DCAN_IFCMD_MSG_NUM(i)); + } +} + +static void dcan_save_msg(struct am335x_dcan_priv *priv, struct can_msg *msg) +{ + uint32_t regval; + + regval = can_getreg(priv, DCAN_IFARB(2)); + CAN_DEBUG("IFARB = %08X\n", regval); + + /* FIXME: Add extid support in ifdefs */ + msg->id = (regval >> 18) & DCAN_IFARB_MSK; + + /* FIXME: This is to handle RTR feature not implemented yet */ + /* msg->rtr = ((regval & DCAN_IFARB_DIR) != 0); */ + +#ifdef CONFIG_CAN_EXTID + msg->flags |= ((regval & DCAN_IFARB_XTD) != 0) ? DCAN_XTD : 0; +#endif + + regval = can_getreg(priv, DCAN_IFMCTL(2)); + msg->len = can_dlc_to_len((regval >> DCAN_IFMCTL_DATALENGTHCODE_SHIFT) & DCAN_IFMCTL_DATALENGTHCODE); + + ((uint32_t *)msg->data)[0] = can_getreg(priv, DCAN_IFDATA(2)); + ((uint32_t *)msg->data)[1] = can_getreg(priv, DCAN_IFDATB(2)); +} + +static void dcan_read_obj(struct am335x_dcan_priv *priv, uint32_t index) +{ + while (can_getreg(priv, DCAN_IFCMD(2)) & DCAN_IFCMD_BUSY) { + /* busy wait */ + } + + can_putreg(priv, DCAN_IFCMD(2), + DCAN_IFCMD_MASK | DCAN_IFCMD_ARB | + DCAN_IFCMD_CONTROL | DCAN_IFCMD_CLRINTPND | DCAN_IFCMD_DATAA | + DCAN_IFCMD_DATAB | DCAN_IFCMD_MSG_NUM(index)); +} + +static void dcan_isr(void *data) +{ + struct am335x_dcan_priv *priv = data; + CAN_DEBUG(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> dcan_isr entry node = %d\n", priv->node); + + uint32_t interrupt = can_getreg(priv, DCAN_INT) & DCAN_INT_INT0ID; + uint32_t stat = can_getreg(priv, DCAN_ES); + uint32_t regval; + + CAN_DEBUG("DCAN_INT = %08x DCAN_ES = %08x\n", interrupt, stat); + + if (interrupt & 0x8000) { + /* Clear all warning/error states except RXOK/TXOK */ + + regval = can_getreg(priv, DCAN_ES); + regval &= DCAN_ES_RXOK | DCAN_ES_TXOK; + can_putreg(priv, DCAN_ES, regval); + + if (stat & (DCAN_ES_BOFF | DCAN_ES_EPASS | DCAN_ES_EWARN)) { + CAN_ERR("CAN: dcan_isr: Error state\n"); + REG(priv->base_reg + DCAN_CTL) |= (DCAN_CTL_ABO); + dcan_reset(priv); + } + } + + do { + if (interrupt != 0 && (interrupt & 0x8000) == 0) { + uint32_t msgindex = interrupt & 0x7fff; + CAN_DEBUG("msgindex %d\n", msgindex); + + /* if no error detected */ + + if (((stat & DCAN_ES_LEC) == 0) || + ((stat & DCAN_ES_LEC) == DCAN_ES_LEC)) { + if (msgindex <= CAN_RX_MSG_OBJ_END_NUM) { + CAN_DEBUG("rx interrupt msgobj = %u\n", msgindex); + struct can_msg msg; + + regval = can_getreg(priv, DCAN_ES); + regval &= ~DCAN_ES_RXOK; + can_putreg(priv, DCAN_ES, regval); + + dcan_read_obj(priv, msgindex); + dcan_save_msg(priv, &msg); +#ifdef CAN_DEBUG_ISR + can_print_msg(&msg); +#endif /* CAN_DEBUG_ISR */ + dcan_inval_obj(priv, msgindex); + + can_receive(priv->bus, &msg); + } else { + CAN_DEBUG("tx interrupt msgobj = %u\n", msgindex); + + regval = can_getreg(priv, DCAN_ES); + regval &= ~DCAN_ES_TXOK; + can_putreg(priv, DCAN_ES, regval); + + dcan_inval_obj(priv, msgindex); + } + } else { + dcan_inval_obj(priv, msgindex); + } + + can_putreg(priv, DCAN_ES, 0); + + if (msgindex == CAN_RX_MSG_OBJ_END_NUM) { + dcan_init_rxobj(priv); + } + } + + interrupt = can_getreg(priv, DCAN_INT); + CAN_DEBUG("DCAN_INT = %08x\n", interrupt); + } while (interrupt != 0); + + can_tx_done(priv->bus); + + CAN_DEBUG(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> dcan_isr exit\n"); +} + +static void dcan_int_enable(struct am335x_dcan_priv *priv) +{ + CAN_DEBUG("dcan_int_enable\n"); + bsp_interrupt_vector_enable(priv->irq.dcan_intr0); + bsp_interrupt_vector_enable(priv->irq.dcan_intr1); + bsp_interrupt_vector_enable(priv->irq.dcan_parity); + + REG(priv->base_reg + DCAN_CTL) |= DCAN_CTL_EIE | DCAN_CTL_SIE; + REG(priv->base_reg + DCAN_CTL) |= DCAN_CTL_IE1 | DCAN_CTL_IE0; + + CAN_DEBUG("DCAN_CTL = 0x%08X\n", can_getreg(priv, DCAN_CTL)); +} + +static void dcan_int_disable(struct am335x_dcan_priv *priv) +{ + CAN_DEBUG("dcan_int_disable\n"); + bsp_interrupt_vector_disable(priv->irq.dcan_intr0); + bsp_interrupt_vector_disable(priv->irq.dcan_intr1); + bsp_interrupt_vector_disable(priv->irq.dcan_parity); + + REG(priv->base_reg + DCAN_CTL) &= (~(DCAN_CTL_EIE | DCAN_CTL_SIE)); + REG(priv->base_reg + DCAN_CTL) &= (~(DCAN_CTL_IE1 | DCAN_CTL_IE0)); + + CAN_DEBUG("DCAN_CTL = 0x%08X\n", can_getreg(priv, DCAN_CTL)); +} + +static void dcan_int(void *data, bool flag) +{ + if (flag == true) { + dcan_int_enable(data); + } else { + dcan_int_disable(data); + } +} + +static int dcan_tx(void *data, struct can_msg *msg) +{ + uint32_t regval; + uint32_t num; + uint32_t id; + uint32_t dlc; + uint8_t txobj; + + struct am335x_dcan_priv *priv = (struct am335x_dcan_priv *)data; + + CAN_DEBUG("dcan_tx Entry\n"); + + regval = can_getreg(priv, DCAN_TXRQ(1)); + CAN_DEBUG("DCAN_TXRQ = 0x%08X\n", regval); + + for (num = 0; num < 32; num++) { + if ((regval & (1 << num)) == 0) { + break; + } + } + + if (num == 32) { + return RTEMS_NO_MEMORY; + } + + txobj = CAN_TX_MSG_OBJ_START_NUM + num; + if (txobj > CAN_TX_MSG_OBJ_END_NUM) { + CAN_DEBUG("dcan_tx Calculated txobj num exceeds the CAN_TX_MSG_OBJ_END_NUM\n") + return RTEMS_INTERNAL_ERROR; + } + CAN_DEBUG("msgobj num = %u\n", txobj); + + id = msg->id; + dlc = can_len_to_dlc(msg->len); + + CAN_DEBUG("CAN-%d ID: %d LEN: %d\n", + priv->node, msg->id, msg->len); + + /* FIXME: Add support for EXT ID */ + can_putreg(priv, DCAN_IFMSK(1), 0xffff); + + regval = ((dlc & DCAN_IFMCTL_DATALENGTHCODE) | + DCAN_IFMCTL_EOB | DCAN_IFMCTL_TXRQST | + DCAN_IFMCTL_TXIE); + can_putreg(priv, DCAN_IFMCTL(1), regval); + + /* Write data to IF1 data registers */ + regval = msg->data[0] + (msg->data[1] << 8) + + (msg->data[2] << 16) + (msg->data[3] << 24); + can_putreg(priv, DCAN_IFDATA(1), regval); + + regval = msg->data[4] + (msg->data[5] << 8) + + (msg->data[6] << 16) + (msg->data[7] << 24); + can_putreg(priv, DCAN_IFDATB(1), regval); + +#ifdef CONFIG_CAN_EXTID + can_putreg(priv, + DCAN_IFARB(1), + DCAN_IFARB_DIR | DCAN_IFARB_MSGVAL | + DCAN_IFARB_XTD | (id << DCAN_IFARB_MSK_SHIFT)); +#else + can_putreg(priv, + DCAN_IFARB(1), + DCAN_IFARB_DIR | DCAN_IFARB_MSGVAL | + (id << 18)); +#endif + + /* Write to Message RAM */ + regval = (DCAN_IFCMD_WR_RD | DCAN_IFCMD_MASK | + DCAN_IFCMD_ARB | DCAN_IFCMD_CONTROL | + DCAN_IFCMD_CLRINTPND | DCAN_IFCMD_TXRQST_NEWDAT | + DCAN_IFCMD_DATAA | DCAN_IFCMD_DATAB | + DCAN_IFCMD_MSG_NUM(txobj)); + can_putreg(priv, DCAN_IFCMD(1), regval); + + regval = can_getreg(priv, DCAN_TXRQ(1)); + + CAN_DEBUG("msgobj = %u DCAN_TXRQ(1) = 0x%08X\n", txobj, regval); + + CAN_DEBUG("dcan_tx Exit\n"); + + return RTEMS_SUCCESSFUL; +} + +static void am335x_dcan_pinmux(uint32_t index) +{ + CAN_DEBUG("am335x_dcan_pinmux for node = 0x%08X\n", index); + + /* FIXME: Add a common way of configuring control module */ + if (index == 1) { + REG(AM335X_PADCONF_BASE + AM335X_CONF_UART1_RXD) = AM335x_PIN_PULL_UP + | AM335x_PIN_RX_DISABLE | AM335x_PIN_MODE_2; + REG(AM335X_PADCONF_BASE + AM335X_CONF_UART1_TXD) = AM335x_PIN_PULL_UP + | AM335x_PIN_RX_ENABLE | AM335x_PIN_MODE_2; + } else if (index == 0) { + REG(AM335X_PADCONF_BASE + AM335X_CONF_UART1_CTSN) = AM335x_PIN_PULL_UP + | AM335x_PIN_RX_DISABLE | AM335x_PIN_MODE_2; + REG(AM335X_PADCONF_BASE + AM335X_CONF_UART1_RTSN) = AM335x_PIN_PULL_UP + | AM335x_PIN_RX_ENABLE | AM335x_PIN_MODE_2; + } +} + +uint32_t am335x_get_sysclk(void) +{ + uint32_t reg_val = REG(SOC_CONTROL_REGS + CONTROL_STATUS); + + switch(reg_val & CONTROL_STATUS_SYSBOOT1_MASK) { + case CONTROL_STATUS_SYSBOOT1_19p2MHZ: + return 19200000; + case CONTROL_STATUS_SYSBOOT1_24MHZ: + return 24000000; + case CONTROL_STATUS_SYSBOOT1_25MHZ: + return 25000000; + case CONTROL_STATUS_SYSBOOT1_26MHZ: + return 26000000; + default: + CAN_ERR("DCANGetSysCLK: failed\n"); + } + return 0; +} + +static void dcan_bittiming(struct am335x_dcan_priv *priv) +{ + uint32_t ts1 = CONFIG_AM335X_CAN_TSEG1; + uint32_t ts2 = CONFIG_AM335X_CAN_TSEG2; + uint32_t sjw = 1; + uint32_t brp = CAN_CLOCK_FREQUENCY / (priv->baudrate * CAN_BIT_QUANTA); + + uint32_t regval; + + CAN_DEBUG("CAN%d PCLK: %d baud: %d\n", + priv->node, CAN_CLOCK_FREQUENCY, priv->baudrate); + CAN_DEBUG("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw); + /* Start configuring bit timing */ + + regval = REG(priv->base_reg + DCAN_CTL); + regval |= DCAN_CTL_CCE; + can_putreg(priv, DCAN_CTL, regval); + + regval = (((brp - 1) << DCAN_BTR_BRP_SHIFT) + | ((ts1 - 1) << DCAN_BTR_TSEG1_SHIFT) + | ((ts2 - 1) << DCAN_BTR_TSEG2_SHIFT) + | ((sjw - 1) << DCAN_BTR_SJW_SHIFT)); + + CAN_DEBUG("Setting CANxBTR= 0x%08x\n", regval); + + /* Set bit timing */ + can_putreg(priv, DCAN_BTR, regval); + + /* Stop configuring bit timing */ + regval = can_getreg(priv, DCAN_CTL); + regval &= ~DCAN_CTL_CCE; + can_putreg(priv, DCAN_CTL, regval); +} + +static int dcan_intr_init(struct am335x_dcan_priv *priv) +{ + int ret; + + if ((ret = rtems_interrupt_handler_install(priv->irq.dcan_intr0, "can-intr-0", + RTEMS_INTERRUPT_UNIQUE, dcan_isr, (void *)priv)) != RTEMS_SUCCESSFUL) { + CAN_ERR("interrupt registration failed irq = %u\n", priv->irq.dcan_intr0); + return ret; + } + + CAN_DEBUG("Interrupt registration successful intr 0 = %u\n", priv->irq.dcan_intr0); + + if ((ret = rtems_interrupt_handler_install(priv->irq.dcan_intr1, "can-intr-1", + RTEMS_INTERRUPT_UNIQUE, dcan_isr, (void *)priv)) != RTEMS_SUCCESSFUL) { + CAN_ERR("interrupt registration failed irq = %u\n", priv->irq.dcan_intr1); + return ret; + } + + CAN_DEBUG("Interrupt registration successful intr 1 = %u\n", priv->irq.dcan_intr1); + + if ((ret = rtems_interrupt_handler_install(priv->irq.dcan_parity, "can-intr-parity", + RTEMS_INTERRUPT_UNIQUE, dcan_isr, (void *)priv)) != RTEMS_SUCCESSFUL) { + CAN_ERR("interrupt registration failed irq = %u\n", priv->irq.dcan_parity); + return ret; + } + + CAN_DEBUG("Interrupt registration successful intr parity = %u\n", priv->irq.dcan_parity); + + return ret; +} + +static void dcan_clk_config(uint32_t node) +{ + if (node == 1) { + CAN_DEBUG("CLK for DCAN1\n"); + REG(SOC_CM_PER_REGS + CM_PER_DCAN1_CLKCTRL) = + CM_PER_DCAN1_CLKCTRL_MODULEMODE_ENABLE; + + while((REG(SOC_CM_PER_REGS + CM_PER_DCAN1_CLKCTRL) & + CM_PER_DCAN1_CLKCTRL_MODULEMODE) != + CM_PER_DCAN1_CLKCTRL_MODULEMODE_ENABLE); + } else if (node == 0) { + CAN_DEBUG("CLK for DCAN0\n"); + REG(SOC_CM_PER_REGS + CM_PER_DCAN0_CLKCTRL) = + CM_PER_DCAN0_CLKCTRL_MODULEMODE_ENABLE; + + while((REG(SOC_CM_PER_REGS + CM_PER_DCAN0_CLKCTRL) & + CM_PER_DCAN0_CLKCTRL_MODULEMODE) != + CM_PER_DCAN0_CLKCTRL_MODULEMODE_ENABLE); + } else { + CAN_ERR("dcan_clk_config: unsupported node\n"); + } +} + +int dcan_init(struct am335x_dcan_priv *priv) +{ + uint32_t regval; + int ret; + + CAN_DEBUG("DCAN Node %d\n", priv->node); + + dcan_clk_config(priv->node); + + am335x_dcan_pinmux(priv->node); + + REG(SOC_CONTROL_REGS + CONTROL_DCAN_RAMINIT) |= + CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START; + while ((REG(SOC_CONTROL_REGS + CONTROL_DCAN_RAMINIT) & + CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START) == 0); + + dcan_reset(priv); + + dcan_bittiming(priv); + +#ifdef CAN_DEBUG + dcan_tx_ready(priv); +#endif /* CAN_DEBUG */ + + for (int i = 0; i < CAN_NUM_OF_MSG_OBJS; i++) { + dcan_inval_obj(priv, i); + } + +#ifdef CAN_DEBUG + dcan_tx_ready(priv); + + /* FIXME: This is for Enabling loopback and ABO, configure it from ioctl. */ + REG(priv->base_reg + DCAN_CTL) |= DCAN_CTL_ABO | DCAN_CTL_TEST; +#endif /* CAN_DEBUG */ + + regval = can_getreg(priv, DCAN_CTL); + regval &= ~DCAN_CTL_INIT; + can_putreg(priv, DCAN_CTL, regval); + + while (can_getreg(priv, DCAN_CTL) & DCAN_CTL_INIT); + +/* FIXME: This is for enabling Loopback, should be configured from ioctl */ +/* + CAN_DEBUG("Enabling Loopback\n"); + REG(priv->base_reg + DCAN_CTL) |= DCAN_CTL_TEST; + REG(priv->base_reg + DCAN_TEST) |= DCAN_TEST_LBACK; +*/ + + dcan_init_rxobj(priv); + + if ((ret = dcan_intr_init(priv)) != RTEMS_SUCCESSFUL) { + return ret; + } + + regval = can_getreg(priv, DCAN_CTL); + regval |= (DCAN_CTL_IE0 | DCAN_CTL_SIE | DCAN_CTL_EIE); + can_putreg(priv, DCAN_CTL, regval); + + return ret; +} + +static void dcan_reset(struct am335x_dcan_priv *priv) +{ + can_putreg(priv, DCAN_CTL, DCAN_CTL_INIT | DCAN_CTL_SWR); + while (can_getreg(priv, DCAN_CTL) & DCAN_CTL_SWR); +} diff --git a/bsps/arm/beagle/dcan/hw_cm_per.h b/bsps/arm/beagle/dcan/hw_cm_per.h new file mode 100755 index 0000000000..bb23fa3d4f --- /dev/null +++ b/bsps/arm/beagle/dcan/hw_cm_per.h @@ -0,0 +1,1407 @@ + + +/** + * @Component: CM + * + * @Filename: ../../CredDataBase/prcmCRED/cm_per_cred.h + * + ============================================================================ */ +/* +* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ +*/ +/* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +#ifndef _HW_CM_PER_H_ +#define _HW_CM_PER_H_ + + +/***********************************************************************\ + * Register arrays Definition +\***********************************************************************/ + + +/***********************************************************************\ + * Bundle arrays Definition +\***********************************************************************/ + + +/***********************************************************************\ + * Bundles Definition +\***********************************************************************/ + + + +/*************************************************************************\ + * Registers Definition +\*************************************************************************/ + +#define CM_PER_L4LS_CLKSTCTRL (0x0) +#define CM_PER_L3S_CLKSTCTRL (0x4) +#define CM_PER_L4FW_CLKSTCTRL (0x8) +#define CM_PER_L3_CLKSTCTRL (0xc) +#define CM_PER_CPGMAC0_CLKCTRL (0x14) +#define CM_PER_LCDC_CLKCTRL (0x18) +#define CM_PER_USB0_CLKCTRL (0x1c) +#define CM_PER_MLB_CLKCTRL (0x20) +#define CM_PER_TPTC0_CLKCTRL (0x24) +#define CM_PER_EMIF_CLKCTRL (0x28) +#define CM_PER_OCMCRAM_CLKCTRL (0x2c) +#define CM_PER_GPMC_CLKCTRL (0x30) +#define CM_PER_MCASP0_CLKCTRL (0x34) +#define CM_PER_UART5_CLKCTRL (0x38) +#define CM_PER_MMC0_CLKCTRL (0x3c) +#define CM_PER_ELM_CLKCTRL (0x40) +#define CM_PER_I2C2_CLKCTRL (0x44) +#define CM_PER_I2C1_CLKCTRL (0x48) +#define CM_PER_SPI0_CLKCTRL (0x4c) +#define CM_PER_SPI1_CLKCTRL (0x50) +#define CM_PER_L4LS_CLKCTRL (0x60) +#define CM_PER_L4FW_CLKCTRL (0x64) +#define CM_PER_MCASP1_CLKCTRL (0x68) +#define CM_PER_UART1_CLKCTRL (0x6c) +#define CM_PER_UART2_CLKCTRL (0x70) +#define CM_PER_UART3_CLKCTRL (0x74) +#define CM_PER_UART4_CLKCTRL (0x78) +//#define CM_PER_TIMER7_CLKCTRL (0x7c) +#define CM_PER_TIMER2_CLKCTRL (0x80) +#define CM_PER_TIMER3_CLKCTRL (0x84) +#define CM_PER_TIMER4_CLKCTRL (0x88) +#define CM_PER_RNG_CLKCTRL (0x90) +#define CM_PER_AES0_CLKCTRL (0x94) +#define CM_PER_SHA0_CLKCTRL (0xa0) +#define CM_PER_PKA_CLKCTRL (0xa4) +#define CM_PER_GPIO6_CLKCTRL (0xa8) +#define CM_PER_GPIO1_CLKCTRL (0xac) +#define CM_PER_GPIO2_CLKCTRL (0xb0) +#define CM_PER_GPIO3_CLKCTRL (0xb4) +#define CM_PER_TPCC_CLKCTRL (0xbc) +#define CM_PER_DCAN0_CLKCTRL (0xc0) +#define CM_PER_DCAN1_CLKCTRL (0xc4) +#define CM_PER_EPWMSS1_CLKCTRL (0xcc) +#define CM_PER_EMIF_FW_CLKCTRL (0xd0) +#define CM_PER_EPWMSS0_CLKCTRL (0xd4) +#define CM_PER_EPWMSS2_CLKCTRL (0xd8) +#define CM_PER_L3_INSTR_CLKCTRL (0xdc) +#define CM_PER_L3_CLKCTRL (0xe0) +#define CM_PER_IEEE5000_CLKCTRL (0xe4) +#define CM_PER_ICSS_CLKCTRL (0xe8) +#define CM_PER_TIMER5_CLKCTRL (0xec) +#define CM_PER_TIMER6_CLKCTRL (0xf0) +#define CM_PER_MMC1_CLKCTRL (0xf4) +#define CM_PER_MMC2_CLKCTRL (0xf8) +#define CM_PER_TPTC1_CLKCTRL (0xfc) +#define CM_PER_TPTC2_CLKCTRL (0x100) +#define CM_PER_SPINLOCK_CLKCTRL (0x10c) +#define CM_PER_MAILBOX0_CLKCTRL (0x110) +#define CM_PER_L4HS_CLKSTCTRL (0x11c) +#define CM_PER_L4HS_CLKCTRL (0x120) +#define CM_PER_MSTR_EXPS_CLKCTRL (0x124) +#define CM_PER_SLV_EXPS_CLKCTRL (0x128) +#define CM_PER_OCPWP_L3_CLKSTCTRL (0x12c) +#define CM_PER_OCPWP_CLKCTRL (0x130) +#define CM_PER_ICSS_CLKSTCTRL (0x140) +#define CM_PER_CPSW_CLKSTCTRL (0x144) +#define CM_PER_LCDC_CLKSTCTRL (0x148) +#define CM_PER_CLKDIV32K_CLKCTRL (0x14c) +#define CM_PER_CLK_24MHZ_CLKSTCTRL (0x150) + +/**************************************************************************\ + * Field Definition Macros +\**************************************************************************/ + +/* L4LS_CLKSTCTRL */ +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK (0x00000800u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_SHIFT (0x0000000Bu) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK (0x00080000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT (0x00000013u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK (0x00100000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT (0x00000014u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK (0x00200000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT (0x00000015u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_SHIFT (0x00000018u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_SHIFT (0x00000008u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK (0x00020000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_SHIFT (0x00000011u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK (0x02000000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_SHIFT (0x00000019u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK (0x00004000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_SHIFT (0x0000000Eu) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK (0x00008000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_SHIFT (0x0000000Fu) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK (0x00010000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_SHIFT (0x00000010u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK (0x08000000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_SHIFT (0x0000001Bu) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK (0x10000000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_SHIFT (0x0000001Cu) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK (0x00002000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_SHIFT (0x0000000Du) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK (0x00000400u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_SHIFT (0x0000000Au) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_ACT (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_INACT (0x0u) + +#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + +/* L3S_CLKSTCTRL */ +#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK (0x00000008u) +#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_SHIFT (0x00000003u) +#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_ACT (0x1u) +#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_INACT (0x0u) + +#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + +/* L4FW_CLKSTCTRL */ +#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK (0x00000100u) +#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK_SHIFT (0x00000008u) +#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK_ACT (0x1u) +#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK_INACT (0x0u) + +#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + +/* L3_CLKSTCTRL */ +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK (0x00000040u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT (0x00000006u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_ACT (0x1u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_INACT (0x0u) + +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK (0x00000004u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_SHIFT (0x00000002u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_ACT (0x1u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_INACT (0x0u) + +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK (0x00000010u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_SHIFT (0x00000004u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_ACT (0x1u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_INACT (0x0u) + +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK (0x00000080u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_SHIFT (0x00000007u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_ACT (0x1u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_INACT (0x0u) + +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK (0x00000008u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_SHIFT (0x00000003u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_ACT (0x1u) +#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_INACT (0x0u) + +#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + +/* CPGMAC0_CLKCTRL */ +#define CM_PER_CPGMAC0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_CPGMAC0_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_CPGMAC0_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_CPGMAC0_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_CPGMAC0_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* LCDC_CLKCTRL */ +#define CM_PER_LCDC_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_LCDC_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_LCDC_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_LCDC_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_LCDC_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_LCDC_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_LCDC_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_LCDC_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_LCDC_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_LCDC_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_LCDC_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_LCDC_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_LCDC_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_LCDC_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_LCDC_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_LCDC_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* USB0_CLKCTRL */ +#define CM_PER_USB0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_USB0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_USB0_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_USB0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_USB0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_USB0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_USB0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_USB0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_USB0_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_USB0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_USB0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_USB0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_USB0_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_USB0_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_USB0_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_USB0_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* MLB_CLKCTRL */ +#define CM_PER_MLB_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_MLB_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_MLB_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_MLB_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_MLB_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_MLB_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_MLB_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_MLB_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_MLB_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_MLB_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_MLB_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_MLB_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_MLB_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_MLB_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_MLB_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_MLB_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* TPTC0_CLKCTRL */ +#define CM_PER_TPTC0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TPTC0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TPTC0_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_TPTC0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TPTC0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TPTC0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TPTC0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_TPTC0_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_TPTC0_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_TPTC0_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_TPTC0_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* EMIF_CLKCTRL */ +#define CM_PER_EMIF_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_EMIF_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_EMIF_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_EMIF_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_EMIF_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_EMIF_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_EMIF_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_EMIF_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_EMIF_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_EMIF_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_EMIF_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_EMIF_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* OCMCRAM_CLKCTRL */ +#define CM_PER_OCMCRAM_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* GPMC_CLKCTRL */ +#define CM_PER_GPMC_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_GPMC_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_GPMC_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_GPMC_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_GPMC_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_GPMC_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_GPMC_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_GPMC_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_GPMC_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_GPMC_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* MCASP0_CLKCTRL */ +#define CM_PER_MCASP0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_MCASP0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_MCASP0_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_MCASP0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_MCASP0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_MCASP0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_MCASP0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* UART5_CLKCTRL */ +#define CM_PER_UART5_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_UART5_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_UART5_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_UART5_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_UART5_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_UART5_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_UART5_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_UART5_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_UART5_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_UART5_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_UART5_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_UART5_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* MMC0_CLKCTRL */ +#define CM_PER_MMC0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_MMC0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_MMC0_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_MMC0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_MMC0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_MMC0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_MMC0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_MMC0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_MMC0_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_MMC0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_MMC0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* ELM_CLKCTRL */ +#define CM_PER_ELM_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_ELM_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_ELM_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_ELM_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_ELM_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_ELM_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_ELM_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_ELM_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_ELM_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_ELM_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_ELM_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_ELM_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* I2C2_CLKCTRL */ +#define CM_PER_I2C2_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_I2C2_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_I2C2_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_I2C2_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_I2C2_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_I2C2_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_I2C2_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_I2C2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_I2C2_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_I2C2_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_I2C2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* I2C1_CLKCTRL */ +#define CM_PER_I2C1_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_I2C1_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_I2C1_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_I2C1_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_I2C1_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_I2C1_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_I2C1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_I2C1_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_I2C1_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_I2C1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* SPI0_CLKCTRL */ +#define CM_PER_SPI0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_SPI0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_SPI0_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_SPI0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_SPI0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_SPI0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_SPI0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_SPI0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_SPI0_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_SPI0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_SPI0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_SPI0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* SPI1_CLKCTRL */ +#define CM_PER_SPI1_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_SPI1_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_SPI1_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_SPI1_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_SPI1_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_SPI1_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_SPI1_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_SPI1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_SPI1_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_SPI1_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_SPI1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* L4LS_CLKCTRL */ +#define CM_PER_L4LS_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_L4LS_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_L4LS_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_L4LS_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_L4LS_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_L4LS_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_L4LS_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_L4LS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_L4LS_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_L4LS_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_L4LS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* L4FW_CLKCTRL */ +#define CM_PER_L4FW_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_L4FW_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_L4FW_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_L4FW_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_L4FW_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_L4FW_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_L4FW_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_L4FW_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_L4FW_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_L4FW_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_L4FW_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_L4FW_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* MCASP1_CLKCTRL */ +#define CM_PER_MCASP1_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_MCASP1_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_MCASP1_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_MCASP1_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_MCASP1_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_MCASP1_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_MCASP1_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* UART1_CLKCTRL */ +#define CM_PER_UART1_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_UART1_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_UART1_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_UART1_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_UART1_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_UART1_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_UART1_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_UART1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_UART1_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_UART1_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_UART1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* UART2_CLKCTRL */ +#define CM_PER_UART2_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_UART2_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_UART2_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_UART2_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_UART2_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_UART2_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_UART2_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_UART2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_UART2_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_UART2_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_UART2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* UART3_CLKCTRL */ +#define CM_PER_UART3_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_UART3_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_UART3_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_UART3_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_UART3_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_UART3_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_UART3_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_UART3_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_UART3_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_UART3_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_UART3_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_UART3_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* UART4_CLKCTRL */ +#define CM_PER_UART4_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_UART4_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_UART4_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_UART4_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_UART4_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_UART4_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_UART4_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_UART4_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_UART4_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_UART4_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_UART4_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_UART4_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* TIMER7_CLKCTRL */ +#define CM_PER_TIMER7_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TIMER7_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TIMER7_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_TIMER7_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TIMER7_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TIMER7_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TIMER7_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* TIMER2_CLKCTRL */ +#define CM_PER_TIMER2_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TIMER2_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TIMER2_CLKCTRL_IDLEST_DISABLDED (0x3u) +#define CM_PER_TIMER2_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TIMER2_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TIMER2_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TIMER2_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* TIMER3_CLKCTRL */ +#define CM_PER_TIMER3_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TIMER3_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TIMER3_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_TIMER3_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TIMER3_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TIMER3_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TIMER3_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* TIMER4_CLKCTRL */ +#define CM_PER_TIMER4_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TIMER4_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TIMER4_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_TIMER4_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TIMER4_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TIMER4_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TIMER4_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* RNG_CLKCTRL */ +#define CM_PER_RNG_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_RNG_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_RNG_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_RNG_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_RNG_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_RNG_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_RNG_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_RNG_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_RNG_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_RNG_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_RNG_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_RNG_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* AES0_CLKCTRL */ +#define CM_PER_AES0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_AES0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_AES0_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_AES0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_AES0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_AES0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_AES0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_AES0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_AES0_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_AES0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_AES0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_AES0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* SHA0_CLKCTRL */ +#define CM_PER_SHA0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_SHA0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_SHA0_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_SHA0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_SHA0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_SHA0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_SHA0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_SHA0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_SHA0_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_SHA0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_SHA0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_SHA0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* PKA_CLKCTRL */ +#define CM_PER_PKA_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_PKA_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_PKA_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_PKA_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_PKA_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_PKA_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_PKA_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_PKA_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_PKA_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_PKA_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_PKA_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_PKA_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* GPIO1_CLKCTRL */ +#define CM_PER_GPIO1_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_GPIO1_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_GPIO1_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_GPIO1_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_GPIO1_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_GPIO1_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_GPIO1_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK (0x00040000u) +#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT (0x00000012u) +#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK_FCLK_DIS (0x0u) +#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK_FCLK_EN (0x1u) + + +/* GPIO2_CLKCTRL */ +#define CM_PER_GPIO2_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_GPIO2_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_GPIO2_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_GPIO2_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_GPIO2_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_GPIO2_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_GPIO2_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK (0x00040000u) +#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT (0x00000012u) +#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK_FCLK_DIS (0x0u) +#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK_FCLK_EN (0x1u) + + +/* GPIO3_CLKCTRL */ +#define CM_PER_GPIO3_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_GPIO3_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_GPIO3_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_GPIO3_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_GPIO3_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_GPIO3_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_GPIO3_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK (0x00040000u) +#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT (0x00000012u) +#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK_FCLK_DIS (0x0u) +#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK_FCLK_EN (0x1u) + + +/* TPCC_CLKCTRL */ +#define CM_PER_TPCC_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TPCC_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TPCC_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_TPCC_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TPCC_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TPCC_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TPCC_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TPCC_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TPCC_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_TPCC_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TPCC_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TPCC_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* DCAN0_CLKCTRL */ +#define CM_PER_DCAN0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_DCAN0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_DCAN0_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_DCAN0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_DCAN0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_DCAN0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_DCAN0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* DCAN1_CLKCTRL */ +#define CM_PER_DCAN1_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_DCAN1_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_DCAN1_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_DCAN1_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_DCAN1_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_DCAN1_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_DCAN1_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* EPWMSS1_CLKCTRL */ +#define CM_PER_EPWMSS1_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* EMIF_FW_CLKCTRL */ +#define CM_PER_EMIF_FW_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* EPWMSS0_CLKCTRL */ +#define CM_PER_EPWMSS0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* EPWMSS2_CLKCTRL */ +#define CM_PER_EPWMSS2_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* L3_INSTR_CLKCTRL */ +#define CM_PER_L3_INSTR_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* L3_CLKCTRL */ +#define CM_PER_L3_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_L3_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_L3_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_L3_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_L3_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_L3_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_L3_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_L3_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_L3_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_L3_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_L3_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* IEEE5000_CLKCTRL */ +#define CM_PER_IEEE5000_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_IEEE5000_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_IEEE5000_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_IEEE5000_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_IEEE5000_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_IEEE5000_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_IEEE5000_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_IEEE5000_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_IEEE5000_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_IEEE5000_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* ICSS_CLKCTRL */ +#define CM_PER_ICSS_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_ICSS_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_ICSS_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_ICSS_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_ICSS_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_ICSS_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_ICSS_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_ICSS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_ICSS_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_ICSS_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_ICSS_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_ICSS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_ICSS_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_ICSS_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_ICSS_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_ICSS_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* TIMER5_CLKCTRL */ +#define CM_PER_TIMER5_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TIMER5_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TIMER5_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_TIMER5_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TIMER5_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TIMER5_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TIMER5_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* TIMER6_CLKCTRL */ +#define CM_PER_TIMER6_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TIMER6_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TIMER6_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_TIMER6_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TIMER6_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TIMER6_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TIMER6_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* MMC1_CLKCTRL */ +#define CM_PER_MMC1_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_MMC1_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_MMC1_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_MMC1_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_MMC1_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_MMC1_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_MMC1_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_MMC1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_MMC1_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_MMC1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_MMC1_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_MMC1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* MMC2_CLKCTRL */ +#define CM_PER_MMC2_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_MMC2_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_MMC2_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_MMC2_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_MMC2_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_MMC2_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_MMC2_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_MMC2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_MMC2_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_MMC2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_MMC2_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_MMC2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* TPTC1_CLKCTRL */ +#define CM_PER_TPTC1_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TPTC1_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TPTC1_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_TPTC1_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TPTC1_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TPTC1_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TPTC1_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_TPTC1_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_TPTC1_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_TPTC1_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_TPTC1_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* TPTC2_CLKCTRL */ +#define CM_PER_TPTC2_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_TPTC2_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_TPTC2_CLKCTRL_IDLEST_DISABLED (0x3u) +#define CM_PER_TPTC2_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_TPTC2_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_TPTC2_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_TPTC2_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_DISABLE (0x0u) +#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_TPTC2_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_TPTC2_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_TPTC2_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_TPTC2_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* SPINLOCK_CLKCTRL */ +#define CM_PER_SPINLOCK_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* MAILBOX0_CLKCTRL */ +#define CM_PER_MAILBOX0_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* L4HS_CLKSTCTRL */ +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK (0x00000010u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT (0x00000004u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK_ACT (0x1u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK_INACT (0x0u) + +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK (0x00000020u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT (0x00000005u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK_ACT (0x1u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK_INACT (0x0u) + +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK (0x00000040u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT (0x00000006u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK_ACT (0x1u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK_INACT (0x0u) + +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK (0x00000008u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK_SHIFT (0x00000003u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK_ACT (0x1u) +#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK_INACT (0x0u) + +#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + +/* L4HS_CLKCTRL */ +#define CM_PER_L4HS_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_L4HS_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_L4HS_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_L4HS_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_L4HS_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_L4HS_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_L4HS_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_L4HS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_L4HS_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_L4HS_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_L4HS_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_L4HS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* MSTR_EXPS_CLKCTRL */ +#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* SLV_EXPS_CLKCTRL */ +#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* OCPWP_L3_CLKSTCTRL */ +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK (0x00000010u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT (0x00000004u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK_ACT (0x1u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK_INACT (0x0u) + +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT (0x00000005u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK_ACT (0x1u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK_INACT (0x0u) + +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + +/* OCPWP_CLKCTRL */ +#define CM_PER_OCPWP_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_OCPWP_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_OCPWP_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_OCPWP_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_OCPWP_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_OCPWP_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_OCPWP_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + +#define CM_PER_OCPWP_CLKCTRL_STBYST (0x00040000u) +#define CM_PER_OCPWP_CLKCTRL_STBYST_SHIFT (0x00000012u) +#define CM_PER_OCPWP_CLKCTRL_STBYST_FUNC (0x0u) +#define CM_PER_OCPWP_CLKCTRL_STBYST_STANDBY (0x1u) + + +/* ICSS_CLKSTCTRL */ +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK (0x00000020u) +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK_SHIFT (0x00000005u) +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK_ACT (0x1u) +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK_INACT (0x0u) + +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK (0x00000010u) +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK_SHIFT (0x00000004u) +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK_ACT (0x1u) +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK_INACT (0x0u) + +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK (0x00000040u) +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK_SHIFT (0x00000006u) +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK_ACT (0x1u) +#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK_INACT (0x0u) + +#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + +/* CPSW_CLKSTCTRL */ +#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK (0x00000010u) +#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT (0x00000004u) +#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK_ACT (0x1u) +#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK_INACT (0x0u) + +#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + +/* LCDC_CLKSTCTRL */ +#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK (0x00000010u) +#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT (0x00000004u) +#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK_ACT (0x1u) +#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK_INACT (0x0u) + +#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK (0x00000020u) +#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT (0x00000005u) +#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK_ACT (0x1u) +#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK_INACT (0x0u) + +#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + +/* CLKDIV32K_CLKCTRL */ +#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST (0x00030000u) +#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_DISABLE (0x3u) +#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_FUNC (0x0u) +#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_IDLE (0x2u) +#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_TRANS (0x1u) + +#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE (0x00000003u) +#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_SHIFT (0x00000000u) +#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_DISABLED (0x0u) +#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_RESERVED (0x3u) +#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u) + + +/* CLK_24MHZ_CLKSTCTRL */ +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK (0x00000010u) +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT (0x00000004u) +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK_ACT (0x1u) +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK_INACT (0x0u) + +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL (0x00000003u) +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u) +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u) +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u) +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u) +#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u) + + + +#endif diff --git a/bsps/arm/beagle/dcan/hw_dcan.h b/bsps/arm/beagle/dcan/hw_dcan.h new file mode 100755 index 0000000000..24a8b7aed5 --- /dev/null +++ b/bsps/arm/beagle/dcan/hw_dcan.h @@ -0,0 +1,1289 @@ + + +/** + * @Component: DCAN + * + * @Filename: ../../CredDataBase/dcan_cred.h + * + ============================================================================ */ +/* +* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ +*/ +/* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +#ifndef _HW_DCAN_H_ +#define _HW_DCAN_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***********************************************************************\ + * Register arrays Definition +\***********************************************************************/ + + +/***********************************************************************\ + * Bundle arrays Definition +\***********************************************************************/ + + +/***********************************************************************\ + * Bundles Definition +\***********************************************************************/ + + + +/*************************************************************************\ + * Registers Definition +\*************************************************************************/ + +#define DCAN_CTL (0x0) +#define DCAN_PARITYERR_EOI (0x04) +#define DCAN_ES (0x4) +#define DCAN_ERRC (0x8) +#define DCAN_BTR (0xc) +#define DCAN_INT (0x10) +#define DCAN_TEST (0x14) +#define DCAN_PERR (0x1c) +#define DCAN_ABOTR (0x80) +#define DCAN_TXRQ_X (0x84) +#define DCAN_TXRQ(n) (0x88 + (n * 4)) +#define DCAN_NWDAT_X (0x98) +#define DCAN_NWDAT(n) (0x9c + (n * 4)) +#define DCAN_INTPND_X (0xac) +#define DCAN_INTPND(n) (0xB0 + (n * 4)) +#define DCAN_MSGVAL_X (0xc0) +#define DCAN_MSGVAL(n) (0xC4 + (n * 4)) +#define DCAN_INTMUX(n) (0xD8 + (n * 4)) +#define DCAN_IFCMD(n) (0x100 + (((n) - 1) * 0x20)) +#define DCAN_IFMSK(n) (0x104 + (((n) - 1) * 0x20)) +#define DCAN_IFARB(n) (0x108 + (((n) - 1) * 0x20)) +#define DCAN_IFMCTL(n) (0x10c + (((n) - 1) * 0x20)) +#define DCAN_IFDATA(n) (0x110 + (((n) - 1) * 0x20)) +#define DCAN_IFDATB(n) (0x114 + (((n) - 1) * 0x20)) +#define DCAN_IF3OBS (0x140) +#define DCAN_IF3UPD(n) (0x160 + (n * 4)) +#define DCAN_TIOC (0x1e0) +#define DCAN_RIOC (0x1e4) + +/**************************************************************************\ + * Field Definition Macros +\**************************************************************************/ + +/* CTL */ +#define DCAN_CTL_ABO (0x00000200u) +#define DCAN_CTL_ABO_SHIFT (0x00000009u) +#define DCAN_CTL_ABO_DISABLED (0x0u) +#define DCAN_CTL_ABO_ENABLED (0x1u) + +#define DCAN_CTL_CCE (0x00000040u) +#define DCAN_CTL_CCE_SHIFT (0x00000006u) +#define DCAN_CTL_CCE_ACCESS (0x1u) +#define DCAN_CTL_CCE_NOACCESS (0x0u) + +#define DCAN_CTL_DAR (0x00000020u) +#define DCAN_CTL_DAR_SHIFT (0x00000005u) +#define DCAN_CTL_DAR_DISABLED (0x1u) +#define DCAN_CTL_DAR_ENABLED (0x0u) + +#define DCAN_CTL_DE1 (0x00040000u) +#define DCAN_CTL_DE1_SHIFT (0x00000012u) +#define DCAN_CTL_DE1_DISABLED (0x0u) +#define DCAN_CTL_DE1_ENABLED (0x1u) + +#define DCAN_CTL_DE2 (0x00080000u) +#define DCAN_CTL_DE2_SHIFT (0x00000013u) +#define DCAN_CTL_DE2_DISABLED (0x0u) +#define DCAN_CTL_DE2_ENABLED (0x1u) + +#define DCAN_CTL_DE3 (0x00100000u) +#define DCAN_CTL_DE3_SHIFT (0x00000014u) +#define DCAN_CTL_DE3_DISABLED (0x0u) +#define DCAN_CTL_DE3_ENABLED (0x1u) + +#define DCAN_CTL_EIE (0x00000008u) +#define DCAN_CTL_EIE_SHIFT (0x00000003u) +#define DCAN_CTL_EIE_DISABLED (0x0u) +#define DCAN_CTL_EIE_ENABLED (0x1u) + +#define DCAN_CTL_IDS (0x00000100u) +#define DCAN_CTL_IDS_SHIFT (0x00000008u) +#define DCAN_CTL_IDS_INTERRUPT (0x1u) +#define DCAN_CTL_IDS_WAIT (0x0u) + +#define DCAN_CTL_IE0 (0x00000002u) +#define DCAN_CTL_IE0_SHIFT (0x00000001u) +#define DCAN_CTL_IE0_DISABLED (0x0u) +#define DCAN_CTL_IE0_ENABLED (0x1u) + +#define DCAN_CTL_IE1 (0x00020000u) +#define DCAN_CTL_IE1_SHIFT (0x00000011u) +#define DCAN_CTL_IE1_DISABLED (0x0u) +#define DCAN_CTL_IE1_ENABLED (0x1u) + +#define DCAN_CTL_INIT (0x00000001u) +#define DCAN_CTL_INIT_SHIFT (0x00000000u) +#define DCAN_CTL_INIT_INITMODE (0x1u) +#define DCAN_CTL_INIT_NORMAL (0x0u) + +#define DCAN_CTL_INITDBG (0x00010000u) +#define DCAN_CTL_INITDBG_SHIFT (0x00000010u) +#define DCAN_CTL_INITDBG_DISABLED (0x0u) +#define DCAN_CTL_INITDBG_ENABLED (0x1u) + +#define DCAN_CTL_PDR (0x01000000u) +#define DCAN_CTL_PDR_SHIFT (0x00000018u) +#define DCAN_CTL_PDR_NOTPOWERDOWN (0x0u) +#define DCAN_CTL_PDR_POWERDOWN (0x1u) + +#define DCAN_CTL_PMD (0x00003C00u) +#define DCAN_CTL_PMD_SHIFT (0x0000000Au) +#define DCAN_CTL_PMD_DISABLED (0x5u) +#define DCAN_CTL_PMD_ENABLED (0x1u) + +#define DCAN_CTL_SIE (0x00000004u) +#define DCAN_CTL_SIE_SHIFT (0x00000002u) +#define DCAN_CTL_SIE_DISABLED (0x0u) +#define DCAN_CTL_SIE_ENABLED (0x1u) + +#define DCAN_CTL_SWR (0x00008000u) +#define DCAN_CTL_SWR_SHIFT (0x0000000Fu) +#define DCAN_CTL_SWR_NORMAL (0x0u) +#define DCAN_CTL_SWR_RESET (0x1u) + +#define DCAN_CTL_TEST (0x00000080u) +#define DCAN_CTL_TEST_SHIFT (0x00000007u) +#define DCAN_CTL_TEST_NORMALMODE (0x0u) +#define DCAN_CTL_TEST_TESTMODE (0x1u) + +#define DCAN_CTL_WUBA (0x02000000u) +#define DCAN_CTL_WUBA_SHIFT (0x00000019u) +#define DCAN_CTL_WUBA_DETECTION (0x1u) +#define DCAN_CTL_WUBA_NODETECTION (0x0u) + + +/* PARITYERR_EOI */ +#define DCAN_PARITYERR_EOI_PARITYERR_EOI (0x00000100u) +#define DCAN_PARITYERR_EOI_PARITYERR_EOI_SHIFT (0x00000008u) +#define DCAN_PARITYERR_EOI_PARITYERR_EOI_ENDOFINTERRUPT (0x1u) +#define DCAN_PARITYERR_EOI_PARITYERR_EOI_NOEFFECT (0x0u) + + +/* ES */ +#define DCAN_ES_BOFF (0x00000080u) +#define DCAN_ES_BOFF_SHIFT (0x00000007u) +#define DCAN_ES_BOFF_ERROR (0x1u) +#define DCAN_ES_BOFF_NOERROR (0x0u) + +#define DCAN_ES_EPASS (0x00000020u) +#define DCAN_ES_EPASS_SHIFT (0x00000005u) +#define DCAN_ES_EPASS_NOPASSIVE (0x0u) +#define DCAN_ES_EPASS_PASSIVEERROR (0x1u) + +#define DCAN_ES_EWARN (0x00000040u) +#define DCAN_ES_EWARN_SHIFT (0x00000006u) +#define DCAN_ES_EWARN_ATLEAST1ERRORABOVE_96 (0x1u) +#define DCAN_ES_EWARN_ERRENCOUNTERBELOW_96 (0x0u) + +#define DCAN_ES_LEC (0x00000007u) +#define DCAN_ES_LEC_SHIFT (0x00000000u) +#define DCAN_ES_LEC_ACKERROR (0x3u) +#define DCAN_ES_LEC_BIT0ERROR (0x5u) +#define DCAN_ES_LEC_BIT1ERROR (0x4u) +#define DCAN_ES_LEC_CRCERROR (0x6u) +#define DCAN_ES_LEC_FORMERROR (0x2u) +#define DCAN_ES_LEC_NOERROR (0x0u) +#define DCAN_ES_LEC_NOEVENT (0x7u) +#define DCAN_ES_LEC_STUFFERROR (0x1u) + +#define DCAN_ES_PDA (0x00000400u) +#define DCAN_ES_PDA_SHIFT (0x0000000Au) +#define DCAN_ES_PDA_NOTPOWERDOWN (0x0u) +#define DCAN_ES_PDA_POWERDOWN (0x1u) + +#define DCAN_ES_PER (0x00000100u) +#define DCAN_ES_PER_SHIFT (0x00000008u) +#define DCAN_ES_PER_ERROR (0x1u) +#define DCAN_ES_PER_NOERROR (0x0u) + +#define DCAN_ES_RXOK (0x00000010u) +#define DCAN_ES_RXOK_SHIFT (0x00000004u) +#define DCAN_ES_RXOK_MESSAGERECIEVED (0x1u) +#define DCAN_ES_RXOK_NOMESSAGE (0x0u) + +#define DCAN_ES_TXOK (0x00000008u) +#define DCAN_ES_TXOK_SHIFT (0x00000003u) +#define DCAN_ES_TXOK_MESSAGETRANSMITTED (0x1u) +#define DCAN_ES_TXOK_NOMESSAGE (0x0u) + +#define DCAN_ES_WAKEUPPND (0x00000200u) +#define DCAN_ES_WAKEUPPND_SHIFT (0x00000009u) +#define DCAN_ES_WAKEUPPND_INITWAKEUP (0x1u) +#define DCAN_ES_WAKEUPPND_NOWAKEUP (0x0u) + + +/* ERRC */ +#define DCAN_ERRC_REC (0x00007F00u) +#define DCAN_ERRC_REC_SHIFT (0x00000008u) + +#define DCAN_ERRC_RP (0x00008000u) +#define DCAN_ERRC_RP_SHIFT (0x0000000Fu) +#define DCAN_ERRC_RP_BELOWERRORPASSIVELEVEL (0x0u) +#define DCAN_ERRC_RP_REACHEDERRORPASSIVELEVEL (0x1u) + +#define DCAN_ERRC_TEC (0x000000FFu) +#define DCAN_ERRC_TEC_SHIFT (0x00000000u) + + +/* BTR */ +#define DCAN_BTR_BRP (0x0000003Fu) +#define DCAN_BTR_BRP_SHIFT (0x00000000u) + +#define DCAN_BTR_BRPE (0x000F0000u) +#define DCAN_BTR_BRPE_SHIFT (0x00000010u) + +#define DCAN_BTR_DCAN_BTR (0xFFFFFFFFu) +#define DCAN_BTR_DCAN_BTR_SHIFT (0x00000000u) + +#define DCAN_BTR_SJW (0x000000C0u) +#define DCAN_BTR_SJW_SHIFT (0x00000006u) + +#define DCAN_BTR_TSEG1 (0x00000F00u) +#define DCAN_BTR_TSEG1_SHIFT (0x00000008u) + +#define DCAN_BTR_TSEG2 (0x00007000u) +#define DCAN_BTR_TSEG2_SHIFT (0x0000000Cu) + + +/* INT */ +#define DCAN_INT_INT0ID (0x0000FFFFu) +#define DCAN_INT_INT0ID_SHIFT (0x00000000u) + +#define DCAN_INT_INT1ID (0x00FF0000u) +#define DCAN_INT_INT1ID_SHIFT (0x00000010u) + + +/* TEST */ +#define DCAN_TEST_EXL (0x00000100u) +#define DCAN_TEST_EXL_SHIFT (0x00000008u) +#define DCAN_TEST_EXL_DISABLED (0x0u) +#define DCAN_TEST_EXL_ENABLED (0x1u) + +#define DCAN_TEST_LBACK (0x00000010u) +#define DCAN_TEST_LBACK_SHIFT (0x00000004u) +#define DCAN_TEST_LBACK_DISABLED (0x0u) +#define DCAN_TEST_LBACK_ENABLED (0x1u) + +#define DCAN_TEST_RDA (0x00000200u) +#define DCAN_TEST_RDA_SHIFT (0x00000009u) +#define DCAN_TEST_RDA_ACCESS (0x1u) +#define DCAN_TEST_RDA_NORMAL (0x0u) + +#define DCAN_TEST_RX (0x00000080u) +#define DCAN_TEST_RX_SHIFT (0x00000007u) +#define DCAN_TEST_RX_DOMINANT (0x0u) +#define DCAN_TEST_RX_RECESSIVE (0x1u) + +#define DCAN_TEST_TX (0x00000060u) +#define DCAN_TEST_TX_SHIFT (0x00000005u) +#define DCAN_TEST_TX_DOMINANT (0x2u) +#define DCAN_TEST_TX_NORMAL (0x0u) +#define DCAN_TEST_TX_RECESSIVE (0x3u) +#define DCAN_TEST_TX_SAMPLEPOINT (0x1u) + +#define DCAN_TEST_SILENT (0x00000008u) +#define DCAN_TEST_SILENT_SHIFT (0x00000003u) +#define DCAN_TEST_SILENT_DISABLED (0x0u) +#define DCAN_TEST_SILENT_ENABLED (0x1u) + + +/* PERR */ +#define DCAN_PERR_MESSAGE_NUMBER (0x000000FFu) +#define DCAN_PERR_MESSAGE_NUMBER_SHIFT (0x00000000u) + +#define DCAN_PERR_WORD_NUMBER (0x00000700u) +#define DCAN_PERR_WORD_NUMBER_SHIFT (0x00000008u) + + +/* ABOTR */ +#define DCAN_ABOTR_ABOTIME (0xFFFFFFFFu) +#define DCAN_ABOTR_ABOTIME_SHIFT (0x00000000u) + + +/* TXRQ_X */ +#define DCAN_TXRQ_X_TXRQSTREG1 (0x00000003u) +#define DCAN_TXRQ_X_TXRQSTREG1_SHIFT (0x00000000u) + +#define DCAN_TXRQ_X_TXRQSTREG2 (0x0000000Cu) +#define DCAN_TXRQ_X_TXRQSTREG2_SHIFT (0x00000002u) + +#define DCAN_TXRQ_X_TXRQSTREG3 (0x00000030u) +#define DCAN_TXRQ_X_TXRQSTREG3_SHIFT (0x00000004u) + +#define DCAN_TXRQ_X_TXRQSTREG4 (0x000000C0u) +#define DCAN_TXRQ_X_TXRQSTREG4_SHIFT (0x00000006u) + +#define DCAN_TXRQ_X_TXRQSTREG5 (0x00000300u) +#define DCAN_TXRQ_X_TXRQSTREG5_SHIFT (0x00000008u) + +#define DCAN_TXRQ_X_TXRQSTREG6 (0x00000C00u) +#define DCAN_TXRQ_X_TXRQSTREG6_SHIFT (0x0000000Au) + +#define DCAN_TXRQ_X_TXRQSTREG7 (0x00003000u) +#define DCAN_TXRQ_X_TXRQSTREG7_SHIFT (0x0000000Cu) + +#define DCAN_TXRQ_X_TXRQSTREG8 (0x0000C000u) +#define DCAN_TXRQ_X_TXRQSTREG8_SHIFT (0x0000000Eu) + + +/* TXRQ12 */ +#define DCAN_TXRQ12_TXRQST_16_1 (0x0000FFFFu) +#define DCAN_TXRQ12_TXRQST_16_1_SHIFT (0x00000000u) + +#define DCAN_TXRQ12_TXRQST_32_17 (0xFFFF0000u) +#define DCAN_TXRQ12_TXRQST_32_17_SHIFT (0x00000010u) + + +/* TXRQ34 */ +#define DCAN_TXRQ34_TXRQST_48_33 (0x0000FFFFu) +#define DCAN_TXRQ34_TXRQST_48_33_SHIFT (0x00000000u) + +#define DCAN_TXRQ34_TXRQST_64_49 (0xFFFF0000u) +#define DCAN_TXRQ34_TXRQST_64_49_SHIFT (0x00000010u) + + +/* TXRQ56 */ +#define DCAN_TXRQ56_TXRQST_80_65 (0x0000FFFFu) +#define DCAN_TXRQ56_TXRQST_80_65_SHIFT (0x00000000u) + +#define DCAN_TXRQ56_TXRQST_96_81 (0xFFFF0000u) +#define DCAN_TXRQ56_TXRQST_96_81_SHIFT (0x00000010u) + + +/* TXRQ78 */ +#define DCAN_TXRQ78_TXRQST_112_97 (0x0000FFFFu) +#define DCAN_TXRQ78_TXRQST_112_97_SHIFT (0x00000000u) + +#define DCAN_TXRQ78_TXRQST_128_113 (0xFFFF0000u) +#define DCAN_TXRQ78_TXRQST_128_113_SHIFT (0x00000010u) + + +/* NWDAT_X */ +#define DCAN_NWDAT_X_NEWDATREG1 (0x00000003u) +#define DCAN_NWDAT_X_NEWDATREG1_SHIFT (0x00000000u) + +#define DCAN_NWDAT_X_NEWDATREG2 (0x0000000Cu) +#define DCAN_NWDAT_X_NEWDATREG2_SHIFT (0x00000002u) + +#define DCAN_NWDAT_X_NEWDATREG3 (0x00000030u) +#define DCAN_NWDAT_X_NEWDATREG3_SHIFT (0x00000004u) + +#define DCAN_NWDAT_X_NEWDATREG4 (0x000000C0u) +#define DCAN_NWDAT_X_NEWDATREG4_SHIFT (0x00000006u) + +#define DCAN_NWDAT_X_NEWDATREG5 (0x00000300u) +#define DCAN_NWDAT_X_NEWDATREG5_SHIFT (0x00000008u) + +#define DCAN_NWDAT_X_NEWDATREG6 (0x00000C00u) +#define DCAN_NWDAT_X_NEWDATREG6_SHIFT (0x0000000Au) + +#define DCAN_NWDAT_X_NEWDATREG7 (0x00003000u) +#define DCAN_NWDAT_X_NEWDATREG7_SHIFT (0x0000000Cu) + +#define DCAN_NWDAT_X_NEWDATREG8 (0x0000C000u) +#define DCAN_NWDAT_X_NEWDATREG8_SHIFT (0x0000000Eu) + + +/* NWDAT12 */ +#define DCAN_NWDAT12_NEWDAT_16_1 (0x0000FFFFu) +#define DCAN_NWDAT12_NEWDAT_16_1_SHIFT (0x00000000u) + +#define DCAN_NWDAT12_NEWDAT_32_17 (0xFFFF0000u) +#define DCAN_NWDAT12_NEWDAT_32_17_SHIFT (0x00000010u) + +#define DCAN_NWDAT12_NEWDAT_80_65 (0x0000FFFFu) +#define DCAN_NWDAT12_NEWDAT_80_65_SHIFT (0x00000000u) + + +/* NWDAT34 */ +#define DCAN_NWDAT34_NEWDAT_48_33 (0x0000FFFFu) +#define DCAN_NWDAT34_NEWDAT_48_33_SHIFT (0x00000000u) + +#define DCAN_NWDAT34_NEWDAT_64_49 (0xFFFF0000u) +#define DCAN_NWDAT34_NEWDAT_64_49_SHIFT (0x00000010u) + + +/* NWDAT56 */ + +#define DCAN_NWDAT56_NEWDAT_96_81 (0xFFFF0000u) +#define DCAN_NWDAT56_NEWDAT_96_81_SHIFT (0x00000000u) + + +/* NWDAT78 */ +#define DCAN_NWDAT78_NEWDAT_112_97 (0x0000FFFFu) +#define DCAN_NWDAT78_NEWDAT_112_97_SHIFT (0x00000000u) + +#define DCAN_NWDAT78_NEWDAT_128_113 (0xFFFF0000u) +#define DCAN_NWDAT78_NEWDAT_128_113_SHIFT (0x00000010u) + + +/* INTPND_X */ +#define DCAN_INTPND_X_INTPNDREG1 (0x00000003u) +#define DCAN_INTPND_X_INTPNDREG1_SHIFT (0x00000000u) + +#define DCAN_INTPND_X_INTPNDREG2 (0x0000000Cu) +#define DCAN_INTPND_X_INTPNDREG2_SHIFT (0x00000002u) + +#define DCAN_INTPND_X_INTPNDREG3 (0x00000030u) +#define DCAN_INTPND_X_INTPNDREG3_SHIFT (0x00000004u) + +#define DCAN_INTPND_X_INTPNDREG4 (0x000000C0u) +#define DCAN_INTPND_X_INTPNDREG4_SHIFT (0x00000006u) + +#define DCAN_INTPND_X_INTPNDREG5 (0x00000300u) +#define DCAN_INTPND_X_INTPNDREG5_SHIFT (0x00000008u) + +#define DCAN_INTPND_X_INTPNDREG6 (0x00000C00u) +#define DCAN_INTPND_X_INTPNDREG6_SHIFT (0x0000000Au) + +#define DCAN_INTPND_X_INTPNDREG7 (0x00003000u) +#define DCAN_INTPND_X_INTPNDREG7_SHIFT (0x0000000Cu) + +#define DCAN_INTPND_X_INTPNDREG8 (0x0000C000u) +#define DCAN_INTPND_X_INTPNDREG8_SHIFT (0x0000000Eu) + + +/* INTPND12 */ +#define DCAN_INTPND12_INTPND_16_1 (0x0000FFFFu) +#define DCAN_INTPND12_INTPND_16_1_SHIFT (0x00000001u) + +#define DCAN_INTPND12_INTPND_32_17 (0xFFFF0000u) +#define DCAN_INTPND12_INTPND_32_17_SHIFT (0x00000010u) + + +/* INTPND34 */ +#define DCAN_INTPND34_INTPND_48_33 (0x0000FFFFu) +#define DCAN_INTPND34_INTPND_48_33_SHIFT (0x00000001u) + +#define DCAN_INTPND34_INTPND_64_49 (0xFFFF0000u) +#define DCAN_INTPND34_INTPND_64_49_SHIFT (0x00000010u) + + +/* INTPND56 */ +#define DCAN_INTPND56_INTPND_80_65 (0x0000FFFFu) +#define DCAN_INTPND56_INTPND_80_65_SHIFT (0x00000001u) + +#define DCAN_INTPND56_INTPND_96_81 (0xFFFF0000u) +#define DCAN_INTPND56_INTPND_96_81_SHIFT (0x00000000u) + + + +/* INTPND78 */ + +#define DCAN_INTPND78_INTPND_128_113 (0xFFFF0000u) +#define DCAN_INTPND78_INTPND_128_113_SHIFT (0x00000010u) + + +/* MSGVAL_X */ +#define DCAN_MSGVAL_X_MSGVALREG1 (0x00000003u) +#define DCAN_MSGVAL_X_MSGVALREG1_SHIFT (0x00000000u) + +#define DCAN_MSGVAL_X_MSGVALREG2 (0x0000000Cu) +#define DCAN_MSGVAL_X_MSGVALREG2_SHIFT (0x00000002u) + +#define DCAN_MSGVAL_X_MSGVALREG3 (0x00000030u) +#define DCAN_MSGVAL_X_MSGVALREG3_SHIFT (0x00000004u) + +#define DCAN_MSGVAL_X_MSGVALREG4 (0x000000C0u) +#define DCAN_MSGVAL_X_MSGVALREG4_SHIFT (0x00000006u) + +#define DCAN_MSGVAL_X_MSGVALREG5 (0x00000300u) +#define DCAN_MSGVAL_X_MSGVALREG5_SHIFT (0x00000008u) + +#define DCAN_MSGVAL_X_MSGVALREG6 (0x00000C00u) +#define DCAN_MSGVAL_X_MSGVALREG6_SHIFT (0x0000000Au) + +#define DCAN_MSGVAL_X_MSGVALREG7 (0x00003000u) +#define DCAN_MSGVAL_X_MSGVALREG7_SHIFT (0x0000000Cu) + +#define DCAN_MSGVAL_X_MSGVALREG8 (0x0000C000u) +#define DCAN_MSGVAL_X_MSGVALREG8_SHIFT (0x00000000u) + + +/* MSGVAL12 */ +#define DCAN_MSGVAL12_MSGVAL_16_1 (0x0000FFFFu) +#define DCAN_MSGVAL12_MSGVAL_16_1_SHIFT (0x00000001u) + +#define DCAN_MSGVAL12_MSGVAL_32_17 (0xFFFF0000u) +#define DCAN_MSGVAL12_MSGVAL_32_17_SHIFT (0x00000010u) + + +/* MSGVAL34 */ +#define DCAN_MSGVAL34_MSGVAL_48_33 (0x0000FFFFu) +#define DCAN_MSGVAL34_MSGVAL_48_33_SHIFT (0x00000001u) + +#define DCAN_MSGVAL34_MSGVAL_64_49 (0xFFFF0000u) +#define DCAN_MSGVAL34_MSGVAL_64_49_SHIFT (0x00000010u) + + +/* MSGVAL56 */ +#define DCAN_MSGVAL56_MSGVAL_80_65 (0x0000FFFFu) +#define DCAN_MSGVAL56_MSGVAL_80_65_SHIFT (0x00000001u) + +#define DCAN_MSGVAL56_MSGVAL_96_81 (0xFFFF0000u) +#define DCAN_MSGVAL56_MSGVAL_96_81_SHIFT (0x00000010u) + + +/* MSGVAL78 */ +#define DCAN_MSGVAL78_MSGVAL_112_97 (0x0000FFFFu) +#define DCAN_MSGVAL78_MSGVAL_112_97_SHIFT (0x00000001u) + +#define DCAN_MSGVAL78_MSGVAL_128_113 (0xFFFF0000u) +#define DCAN_MSGVAL78_MSGVAL_128_113_SHIFT (0x00000010u) + + +/* INTMUX12 */ +#define DCAN_INTMUX12_INTMUX_16_1 (0x0000FFFFu) +#define DCAN_INTMUX12_INTMUX_16_1_SHIFT (0x00000001u) + +#define DCAN_INTMUX12_INTMUX_32_17 (0xFFFF0000u) +#define DCAN_INTMUX12_INTMUX_32_17_SHIFT (0x00000010u) + + +/* INTMUX34 */ +#define DCAN_INTMUX34_INTMUX_48_33 (0x0000FFFFu) +#define DCAN_INTMUX34_INTMUX_48_33_SHIFT (0x00000001u) + +#define DCAN_INTMUX34_INTMUX_64_49 (0xFFFF0000u) +#define DCAN_INTMUX34_INTMUX_64_49_SHIFT (0x00000010u) + + +/* INTMUX56 */ +#define DCAN_INTMUX56_INTMUX_80_65 (0x0000FFFFu) +#define DCAN_INTMUX56_INTMUX_80_65_SHIFT (0x00000001u) + +#define DCAN_INTMUX56_INTMUX_96_81 (0xFFFF0000u) +#define DCAN_INTMUX56_INTMUX_96_81_SHIFT (0x00000010u) + + +/* INTMUX78 */ +#define DCAN_INTMUX78_INTMUX_112_95 (0x0000FFFFu) +#define DCAN_INTMUX78_INTMUX_112_95_SHIFT (0x00000001u) + +#define DCAN_INTMUX78_INTMUX_128_113 (0xFFFF0000u) +#define DCAN_INTMUX78_INTMUX_128_113_SHIFT (0x00000010u) + +/* IFxCMD mu */ +#define DCAN_IFCMD_ARB (0x00200000u) +#define DCAN_IFCMD_ARB_SHIFT (0x00000015u) +#define DCAN_IFCMD_ARB_NOCHANGE (0x0u) +#define DCAN_IFCMD_ARB_OBJTOREG (0x1u) +#define DCAN_IFCMD_ARB_REGTOOBJ (0x1u) + +#define DCAN_IFCMD_BUSY (0x00008000u) +#define DCAN_IFCMD_BUSY_SHIFT (0x0000000Fu) +#define DCAN_IFCMD_BUSY_NOTRANSFER (0x0u) +#define DCAN_IFCMD_BUSY_TRANSFER (0x1u) + +#define DCAN_IFCMD_CLRINTPND (0x00080000u) +#define DCAN_IFCMD_CLRINTPND_SHIFT (0x00000013u) +#define DCAN_IFCMD_CLRINTPND_CHANGE (0x1u) +#define DCAN_IFCMD_CLRINTPND_NOCHANGE (0x0u) + +#define DCAN_IFCMD_CONTROL (0x00100000u) +#define DCAN_IFCMD_CONTROL_SHIFT (0x00000014u) + +#define DCAN_IFCMD_DATAA (0x00020000u) +#define DCAN_IFCMD_DATAA_SHIFT (0x00000011u) + +#define DCAN_IFCMD_DATAB (0x00010000u) +#define DCAN_IFCMD_DATAB_SHIFT (0x00000010u) + +#define DCAN_IFCMD_DMAACTIVE (0x00004000u) +#define DCAN_IFCMD_DMAACTIVE_SHIFT (0x0000000Eu) +#define DCAN_IFCMD_DMAACTIVE_ACTIVE (0x1u) +#define DCAN_IFCMD_DMAACTIVE_INACTIVE (0x0u) + +#define DCAN_IFCMD_MASK (0x00400000u) +#define DCAN_IFCMD_MASK_SHIFT (0x00000016u) + +#define DCAN_IFCMD_MESSAGENUMBER (0x000000FFu) +#define DCAN_IFCMD_MESSAGENUMBER_SHIFT (0x00000000u) + +#define DCAN_IFCMD_TXRQST_NEWDAT (0x00040000u) +#define DCAN_IFCMD_TXRQST_NEWDAT_SHIFT (0x00000012u) + +#define DCAN_IFCMD_WR_RD (0x00800000u) +#define DCAN_IFCMD_WR_RD_SHIFT (0x00000017u) + + +/* IFxMSK mu */ +#define DCAN_IFMSK_MDIR (0x40000000u) +#define DCAN_IFMSK_MDIR_SHIFT (0x00000001Eu) +#define DCAN_IFMSK_MDIR_NOTUSED (0x0u) +#define DCAN_IFMSK_MDIR_USED (0x1u) + +#define DCAN_IFMSK_MSK (0x1FFFFFFFu) +#define DCAN_IFMSK_MSK_SHIFT (0x00000000u) +#define DCAN_IFMSK_MSK_NOTUSED (0x0u) +#define DCAN_IFMSK_MSK_USED (0x1u) + +#define DCAN_IFMSK_MXTD (0x80000000u) +#define DCAN_IFMSK_MXTD_SHIFT (0x00000001Fu) +#define DCAN_IFMSK_MXTD_NOTUSED (0x0u) +#define DCAN_IFMSK_MXTD_USED (0x1u) + + +/* IFxARB mu */ +#define DCAN_IFARB_DIR (0x20000000u) +#define DCAN_IFARB_DIR_SHIFT (0x0000001Du) +#define DCAN_IFARB_DIR_RECEIVE (0x0u) +#define DCAN_IFARB_DIR_TRANSMIT (0x1u) + +#define DCAN_IFARB_MSGVAL (0x80000000u) +#define DCAN_IFARB_MSGVAL_SHIFT (0x0000001Fu) +#define DCAN_IFARB_MSGVAL_IGNORED (0x0u) +#define DCAN_IFARB_MSGVAL_USED (0x1u) + +#define DCAN_IFARB_MSK (0x1FFFFFFFu) +#define DCAN_IFARB_MSK_SHIFT (0x000000000u) +#define DCAN_IFARB_MSK_RECEIVE (0x0u) +#define DCAN_IFARB_MSK_TRANSMIT (0x1u) + +#define DCAN_IFARB_XTD (0x40000000u) +#define DCAN_IFARB_XTD_SHIFT (0x0000001Eu) +#define DCAN_IFARB_XTD_11_BIT (0x0u) +#define DCAN_IFARB_XTD_29_BIT (0x1u) + +/* IFxMCTL mu */ +#define DCAN_IFMCTL_DATALENGTHCODE (0x0000000Fu) +#define DCAN_IFMCTL_DATALENGTHCODE_SHIFT (0x00000000u) + +#define DCAN_IFMCTL_EOB (0x00000080u) +#define DCAN_IFMCTL_EOB_SHIFT (0x00000007u) + +#define DCAN_IFMCTL_INTPND (0x00002000u) +#define DCAN_IFMCTL_INTPND_SHIFT (0x0000000Du) +#define DCAN_IFMCTL_INTPND_INTERRUPT (0x1u) +#define DCAN_IFMCTL_INTPND_NOINTERRUPT (0x0u) + +#define DCAN_IFMCTL_MSGLST (0x00004000u) +#define DCAN_IFMCTL_MSGLST_SHIFT (0x0000000Eu) +#define DCAN_IFMCTL_MSGLST_MSGLOST (0x1u) +#define DCAN_IFMCTL_MSGLST_NOMSGLOST (0x0u) + +#define DCAN_IFMCTL_NEWDAT (0x00008000u) +#define DCAN_IFMCTL_NEWDAT_SHIFT (0x0000000Fu) +#define DCAN_IFMCTL_NEWDAT_NEWDATA (0x1u) +#define DCAN_IFMCTL_NEWDAT_NONEWDATA (0x0u) + +#define DCAN_IFMCTL_RMTEN (0x00000200u) +#define DCAN_IFMCTL_RMTEN_SHIFT (0x00000009u) +#define DCAN_IFMCTL_RMTEN_DISABLE (0x0u) +#define DCAN_IFMCTL_RMTEN_ENABLE (0x1u) + +#define DCAN_IFMCTL_RXIE (0x00000400u) +#define DCAN_IFMCTL_RXIE_SHIFT (0x0000000Au) +#define DCAN_IFMCTL_RXIE_NOTRIGGER (0x0u) +#define DCAN_IFMCTL_RXIE_TRIGGER (0x1u) + +#define DCAN_IFMCTL_TXIE (0x00000800u) +#define DCAN_IFMCTL_TXIE_SHIFT (0x0000000Bu) +#define DCAN_IFMCTL_TXIE_NOTRIGGER (0x0u) +#define DCAN_IFMCTL_TXIE_TRIGGER (0x1u) + +#define DCAN_IFMCTL_TXRQST (0x00000100u) +#define DCAN_IFMCTL_TXRQST_SHIFT (0x00000008u) +#define DCAN_IFMCTL_TXRQST_NOREQUESTED (0x0u) +#define DCAN_IFMCTL_TXRQST_REQUESTED (0x1u) + +#define DCAN_IFMCTL_UMASK (0x00001000u) +#define DCAN_IFMCTL_UMASK_SHIFT (0x0000000Cu) +#define DCAN_IFMCTL_UMASK_IGNORED (0x0u) +#define DCAN_IFMCTL_UMASK_MASKED (0x1u) + +/* IFxDATA mu */ +#define DCAN_IFDATA_DCAN_IFDATA (0xFFFFFFFFu) +#define DCAN_IFDATA_DCAN_IFDATA_SHIFT (0x00000000u) + + +/* IFxDATB mu */ +#define DCAN_IFDATB_DCAN_IFDATB (0xFFFFFFFFu) +#define DCAN_IFDATB_DCAN_IFDATB_SHIFT (0x00000000u) + +/* IF1CMD */ +#define DCAN_IF1CMD_ARB (0x00200000u) +#define DCAN_IF1CMD_ARB_SHIFT (0x00000015u) + +#define DCAN_IF1CMD_BUSY (0x00008000u) +#define DCAN_IF1CMD_BUSY_SHIFT (0x0000000Fu) +#define DCAN_IF1CMD_BUSY_NOTRANSFER (0x0u) +#define DCAN_IF1CMD_BUSY_TRANSFER (0x1u) + +#define DCAN_IF1CMD_CLRINTPND (0x00080000u) +#define DCAN_IF1CMD_CLRINTPND_SHIFT (0x00000013u) +#define DCAN_IF1CMD_CLRINTPND_CHANGE (0x1u) +#define DCAN_IF1CMD_CLRINTPND_NOCHANGE (0x0u) + +#define DCAN_IF1CMD_CONTROL (0x00100000u) +#define DCAN_IF1CMD_CONTROL_SHIFT (0x00000014u) + +#define DCAN_IF1CMD_DATAA (0x00020000u) +#define DCAN_IF1CMD_DATAA_SHIFT (0x00000011u) + +#define DCAN_IF1CMD_DATAB (0x00010000u) +#define DCAN_IF1CMD_DATAB_SHIFT (0x00000010u) + +#define DCAN_IF1CMD_DMAACTIVE (0x00004000u) +#define DCAN_IF1CMD_DMAACTIVE_SHIFT (0x0000000Eu) +#define DCAN_IF1CMD_DMAACTIVE_ACTIVE (0x1u) +#define DCAN_IF1CMD_DMAACTIVE_INACTIVE (0x0u) + +#define DCAN_IF1CMD_MASK (0x00400000u) +#define DCAN_IF1CMD_MASK_SHIFT (0x00000016u) + +#define DCAN_IF1CMD_MESSAGENUMBER (0x0000000Fu) +#define DCAN_IF1CMD_MESSAGENUMBER_SHIFT (0x00000000u) + +#define DCAN_IF1CMD_TXRQST_NEWDAT (0x00040000u) +#define DCAN_IF1CMD_TXRQST_NEWDAT_SHIFT (0x00000012u) + +#define DCAN_IF1CMD_WR_RD (0x00800000u) +#define DCAN_IF1CMD_WR_RD_SHIFT (0x00000017u) + + +/* IF1MSK */ +#define DCAN_IF1MSK_MDIR (0x40000000u) +#define DCAN_IF1MSK_MDIR_SHIFT (0x00000001Eu) +#define DCAN_IF1MSK_MDIR_NOTUSED (0x0u) +#define DCAN_IF1MSK_MDIR_USED (0x1u) + +#define DCAN_IF1MSK_MSK (0x1FFFFFFFu) +#define DCAN_IF1MSK_MSK_SHIFT (0x00000000u) +#define DCAN_IF1MSK_MSK_NOTUSED (0x0u) +#define DCAN_IF1MSK_MSK_USED (0x1u) + +#define DCAN_IF1MSK_MXTD (0x80000000u) +#define DCAN_IF1MSK_MXTD_SHIFT (0x00000001Fu) +#define DCAN_IF1MSK_MXTD_NOTUSED (0x0u) +#define DCAN_IF1MSK_MXTD_USED (0x1u) + + +/* IF1ARB */ +#define DCAN_IF1ARB_DIR (0x20000000u) +#define DCAN_IF1ARB_DIR_SHIFT (0x0000001Du) +#define DCAN_IF1ARB_DIR_RECEIVE (0x0u) +#define DCAN_IF1ARB_DIR_TRANSMIT (0x1u) + +#define DCAN_IF1ARB_MSGVAL (0x80000000u) +#define DCAN_IF1ARB_MSGVAL_SHIFT (0x0000001Fu) +#define DCAN_IF1ARB_MSGVAL_IGNORED (0x0u) +#define DCAN_IF1ARB_MSGVAL_USED (0x1u) + +#define DCAN_IF1ARB_MSK (0x1FFFFFFFu) +#define DCAN_IF1ARB_MSK_SHIFT (0x000000000u) +#define DCAN_IF1ARB_MSK_RECEIVE (0x0u) +#define DCAN_IF1ARB_MSK_TRANSMIT (0x1u) + +#define DCAN_IF1ARB_XTD (0x40000000u) +#define DCAN_IF1ARB_XTD_SHIFT (0x0000001Eu) +#define DCAN_IF1ARB_XTD_11_BIT (0x0u) +#define DCAN_IF1ARB_XTD_29_BIT (0x1u) + + +/* IF1MCTL */ +#define DCAN_IF1MCTL_DATALENGTHCODE (0x0000000Fu) +#define DCAN_IF1MCTL_DATALENGTHCODE_SHIFT (0x00000000u) + +#define DCAN_IF1MCTL_EOB (0x00000080u) +#define DCAN_IF1MCTL_EOB_SHIFT (0x00000007u) + +#define DCAN_IF1MCTL_INTPND (0x00002000u) +#define DCAN_IF1MCTL_INTPND_SHIFT (0x0000000Du) +#define DCAN_IF1MCTL_INTPND_INTERRUPT (0x1u) +#define DCAN_IF1MCTL_INTPND_NOINTERRUPT (0x0u) + +#define DCAN_IF1MCTL_MSGLST (0x00004000u) +#define DCAN_IF1MCTL_MSGLST_SHIFT (0x0000000Eu) +#define DCAN_IF1MCTL_MSGLST_MSGLOST (0x1u) +#define DCAN_IF1MCTL_MSGLST_NOMSGLOST (0x0u) + +#define DCAN_IF1MCTL_NEWDAT (0x00008000u) +#define DCAN_IF1MCTL_NEWDAT_SHIFT (0x0000000Fu) +#define DCAN_IF1MCTL_NEWDAT_NEWDATA (0x1u) +#define DCAN_IF1MCTL_NEWDAT_NONEWDATA (0x0u) + +#define DCAN_IF1MCTL_RMTEN (0x00000200u) +#define DCAN_IF1MCTL_RMTEN_SHIFT (0x00000009u) +#define DCAN_IF1MCTL_RMTEN_DISABLE (0x0u) +#define DCAN_IF1MCTL_RMTEN_ENABLE (0x1u) + +#define DCAN_IF1MCTL_RXIE (0x00000400u) +#define DCAN_IF1MCTL_RXIE_SHIFT (0x0000000Au) +#define DCAN_IF1MCTL_RXIE_NOTRIGGER (0x0u) +#define DCAN_IF1MCTL_RXIE_TRIGGER (0x1u) + +#define DCAN_IF1MCTL_TXIE (0x00000800u) +#define DCAN_IF1MCTL_TXIE_SHIFT (0x0000000Bu) +#define DCAN_IF1MCTL_TXIE_NOTRIGGER (0x0u) +#define DCAN_IF1MCTL_TXIE_TRIGGER (0x1u) + +#define DCAN_IF1MCTL_TXRQST (0x00000100u) +#define DCAN_IF1MCTL_TXRQST_SHIFT (0x00000008u) +#define DCAN_IF1MCTL_TXRQST_NOREQUESTED (0x0u) +#define DCAN_IF1MCTL_TXRQST_REQUESTED (0x1u) + +#define DCAN_IF1MCTL_UMASK (0x00001000u) +#define DCAN_IF1MCTL_UMASK_SHIFT (0x0000000Cu) +#define DCAN_IF1MCTL_UMASK_IGNORED (0x0u) +#define DCAN_IF1MCTL_UMASK_MASKED (0x1u) + + +/* IF1DATA */ +#define DCAN_IF1DATA_DCAN_IF1DATA (0xFFFFFFFFu) +#define DCAN_IF1DATA_DCAN_IF1DATA_SHIFT (0x00000000u) + + +/* IF1DATB */ +#define DCAN_IF1DATB_DCAN_IF1DATB (0xFFFFFFFFu) +#define DCAN_IF1DATB_DCAN_IF1DATB_SHIFT (0x00000000u) + + +/* IF2CMD */ +#define DCAN_IF2CMD_ARB (0x00200000u) +#define DCAN_IF2CMD_ARB_SHIFT (0x00000015u) + +#define DCAN_IF2CMD_BUSY (0x00008000u) +#define DCAN_IF2CMD_BUSY_SHIFT (0x0000000Fu) +#define DCAN_IF2CMD_BUSY_NOTRANSFER (0x0u) +#define DCAN_IF2CMD_BUSY_TRANSFER (0x1u) + +#define DCAN_IF2CMD_CLRINTPND (0x00080000u) +#define DCAN_IF2CMD_CLRINTPND_SHIFT (0x00000013u) +#define DCAN_IF2CMD_CLRINTPND_CHANGE (0x1u) +#define DCAN_IF2CMD_CLRINTPND_NOCHANGE (0x0u) + +#define DCAN_IF2CMD_CONTROL (0x00100000u) +#define DCAN_IF2CMD_CONTROL_SHIFT (0x00000014u) + +#define DCAN_IF2CMD_DATAA (0x00020000u) +#define DCAN_IF2CMD_DATAA_SHIFT (0x00000011u) + +#define DCAN_IF2CMD_DATAB (0x00010000u) +#define DCAN_IF2CMD_DATAB_SHIFT (0x00000010u) + +#define DCAN_IF2CMD_DMAACTIVE (0x00004000u) +#define DCAN_IF2CMD_DMAACTIVE_SHIFT (0x0000000Eu) +#define DCAN_IF2CMD_DMAACTIVE_ACTIVE (0x1u) +#define DCAN_IF2CMD_DMAACTIVE_INACTIVE (0x0u) + +#define DCAN_IF2CMD_MASK (0x00400000u) +#define DCAN_IF2CMD_MASK_SHIFT (0x00000016u) + +#define DCAN_IF2CMD_MESSAGENUMBER (0x000000FFu) +#define DCAN_IF2CMD_MESSAGENUMBER_SHIFT (0x00000000u) + +#define DCAN_IF2CMD_TXRQST_NEWDAT (0x00040000u) +#define DCAN_IF2CMD_TXRQST_NEWDAT_SHIFT (0x00000012u) + +#define DCAN_IF2CMD_WR_RD (0x00800000u) +#define DCAN_IF2CMD_WR_RD_SHIFT (0x00000017u) + + +/* IF2MSK */ +#define DCAN_IF2MSK_MDIR (0x40000000u) +#define DCAN_IF2MSK_MDIR_SHIFT (0x00000001Eu) +#define DCAN_IF2MSK_MDIR_NOTUSED (0x0u) +#define DCAN_IF2MSK_MDIR_USED (0x1u) + +#define DCAN_IF2MSK_MSK (0x1FFFFFFFu) +#define DCAN_IF2MSK_MSK_SHIFT (0x00000000u) +#define DCAN_IF2MSK_MSK_NOTUSED (0x0u) +#define DCAN_IF2MSK_MSK_USED (0x1u) + +#define DCAN_IF2MSK_MXTD (0x80000000u) +#define DCAN_IF2MSK_MXTD_SHIFT (0x00000001Fu) +#define DCAN_IF2MSK_MXTD_NOTUSED (0x0u) +#define DCAN_IF2MSK_MXTD_USED (0x1u) + + +/* IF2ARB */ +#define DCAN_IF2ARB_DIR (0x20000000u) +#define DCAN_IF2ARB_DIR_SHIFT (0x0000001Du) +#define DCAN_IF2ARB_DIR_RECEIVE (0x0u) +#define DCAN_IF2ARB_DIR_TRANSMIT (0x1u) + +#define DCAN_IF2ARB_MSGVAL (0x80000000u) +#define DCAN_IF2ARB_MSGVAL_SHIFT (0x0000001Fu) +#define DCAN_IF2ARB_MSGVAL_IGNORED (0x0u) +#define DCAN_IF2ARB_MSGVAL_USED (0x1u) + +#define DCAN_IF2ARB_MSK (0x1FFFFFFFu) +#define DCAN_IF2ARB_MSK_SHIFT (0x000000000u) +#define DCAN_IF2ARB_MSK_RECEIVE (0x0u) +#define DCAN_IF2ARB_MSK_TRANSMIT (0x1u) + +#define DCAN_IF2ARB_XTD (0x40000000u) +#define DCAN_IF2ARB_XTD_SHIFT (0x0000001Eu) +#define DCAN_IF2ARB_XTD_11_BIT (0x0u) +#define DCAN_IF2ARB_XTD_29_BIT (0x1u) + + +/* IF2MCTL */ +#define DCAN_IF2MCTL_DATALENGTHCODE (0x0000000Fu) +#define DCAN_IF2MCTL_DATALENGTHCODE_SHIFT (0x00000000u) + +#define DCAN_IF2MCTL_EOB (0x00000080u) +#define DCAN_IF2MCTL_EOB_SHIFT (0x00000007u) + +#define DCAN_IF2MCTL_INTPND (0x00002000u) +#define DCAN_IF2MCTL_INTPND_SHIFT (0x0000000Du) +#define DCAN_IF2MCTL_INTPND_INTERRUPT (0x1u) +#define DCAN_IF2MCTL_INTPND_NOINTERRUPT (0x0u) + +#define DCAN_IF2MCTL_MSGLST (0x00004000u) +#define DCAN_IF2MCTL_MSGLST_SHIFT (0x0000000Eu) +#define DCAN_IF2MCTL_MSGLST_MSGLOST (0x1u) +#define DCAN_IF2MCTL_MSGLST_NOMSGLOST (0x0u) + +#define DCAN_IF2MCTL_NEWDAT (0x00008000u) +#define DCAN_IF2MCTL_NEWDAT_SHIFT (0x0000000Fu) +#define DCAN_IF2MCTL_NEWDAT_NEWDATA (0x1u) +#define DCAN_IF2MCTL_NEWDAT_NONEWDATA (0x0u) + +#define DCAN_IF2MCTL_RMTEN (0x00000200u) +#define DCAN_IF2MCTL_RMTEN_SHIFT (0x00000009u) +#define DCAN_IF2MCTL_RMTEN_DISABLE (0x0u) +#define DCAN_IF2MCTL_RMTEN_ENABLE (0x1u) + +#define DCAN_IF2MCTL_RXIE (0x00000400u) +#define DCAN_IF2MCTL_RXIE_SHIFT (0x0000000Au) +#define DCAN_IF2MCTL_RXIE_NOTRIGGER (0x0u) +#define DCAN_IF2MCTL_RXIE_TRIGGER (0x1u) + +#define DCAN_IF2MCTL_TXIE (0x00000800u) +#define DCAN_IF2MCTL_TXIE_SHIFT (0x0000000Bu) +#define DCAN_IF2MCTL_TXIE_NOTRIGGER (0x0u) +#define DCAN_IF2MCTL_TXIE_TRIGGER (0x1u) + +#define DCAN_IF2MCTL_TXRQST (0x00000100u) +#define DCAN_IF2MCTL_TXRQST_SHIFT (0x00000008u) +#define DCAN_IF2MCTL_TXRQST_NOREQUESTED (0x0u) +#define DCAN_IF2MCTL_TXRQST_REQUESTED (0x1u) + +#define DCAN_IF2MCTL_UMASK (0x00001000u) +#define DCAN_IF2MCTL_UMASK_SHIFT (0x0000000Cu) +#define DCAN_IF2MCTL_UMASK_IGNORED (0x0u) +#define DCAN_IF2MCTL_UMASK_MASKED (0x1u) + + +/* IF2DATA */ +#define DCAN_IF2DATA_DCAN_IF2DATA (0xFFFFFFFFu) +#define DCAN_IF2DATA_DCAN_IF2DATA_SHIFT (0x00000000u) + + +/* IF2DATB */ +#define DCAN_IF2DATB_DCAN_IF2DATB (0xFFFFFFFFu) +#define DCAN_IF2DATB_DCAN_IF2DATB_SHIFT (0x00000000u) + + +/* IF3OBS */ +#define DCAN_IF3OBS_ARB (0x00000002u) +#define DCAN_IF3OBS_ARB_SHIFT (0x00000001u) +#define DCAN_IF3OBS_ARB_DATATOBEREAD (0x1u) +#define DCAN_IF3OBS_ARB_NOTTOBEREAD (0x0u) + +#define DCAN_IF3OBS_CTRL (0x00000004u) +#define DCAN_IF3OBS_CTRL_SHIFT (0x00000002u) +#define DCAN_IF3OBS_CTRL_DATATOBEREAD (0x1u) +#define DCAN_IF3OBS_CTRL_NOTTOBEREAD (0x0u) + +#define DCAN_IF3OBS_DATAA (0x00000008u) +#define DCAN_IF3OBS_DATAA_SHIFT (0x00000003u) +#define DCAN_IF3OBS_DATAA_DATATOBEREAD (0x1u) +#define DCAN_IF3OBS_DATAA_NOTTOBEREAD (0x0u) + +#define DCAN_IF3OBS_DATAB (0x00000010u) +#define DCAN_IF3OBS_DATAB_SHIFT (0x00000004u) +#define DCAN_IF3OBS_DATAB_DATATOBEREAD (0x1u) +#define DCAN_IF3OBS_DATAB_NOTTOBEREAD (0x0u) + +#define DCAN_IF3OBS_IF3SA (0x00000200u) +#define DCAN_IF3OBS_IF3SA_SHIFT (0x00000009u) +#define DCAN_IF3OBS_IF3SA_ALREADYREADOUT (0x0u) +#define DCAN_IF3OBS_IF3SA_STILLTOBEREAD (0x1u) + +#define DCAN_IF3OBS_IF3SC (0x00000400u) +#define DCAN_IF3OBS_IF3SC_SHIFT (0x0000000Au) +#define DCAN_IF3OBS_IF3SC_ALREADYREADOUT (0x0u) +#define DCAN_IF3OBS_IF3SC_STILLTOBEREAD (0x1u) + +#define DCAN_IF3OBS_IF3SDA (0x00000800u) +#define DCAN_IF3OBS_IF3SDA_SHIFT (0x0000000Bu) +#define DCAN_IF3OBS_IF3SDA_ALREADYREADOUT (0x0u) +#define DCAN_IF3OBS_IF3SDA_STILLTOBEREAD (0x1u) + +#define DCAN_IF3OBS_IF3SDB (0x00001000u) +#define DCAN_IF3OBS_IF3SDB_SHIFT (0x0000000Cu) +#define DCAN_IF3OBS_IF3SDB_ALREADYREADOUT (0x0u) +#define DCAN_IF3OBS_IF3SDB_STILLTOBEREAD (0x1u) + +#define DCAN_IF3OBS_IF3SM (0x00000100u) +#define DCAN_IF3OBS_IF3SM_SHIFT (0x00000008u) +#define DCAN_IF3OBS_IF3SM_ALREADYREADOUT (0x0u) +#define DCAN_IF3OBS_IF3SM_STILLTOBEREAD (0x1u) + +#define DCAN_IF3OBS_IF3UPD (0x00008000u) +#define DCAN_IF3OBS_IF3UPD_SHIFT (0x0000000Fu) +#define DCAN_IF3OBS_IF3UPD_NEWDATALOAD (0x1u) +#define DCAN_IF3OBS_IF3UPD_NONEWDATALOAD (0x0u) + +#define DCAN_IF3OBS_MASK (0x00000001u) +#define DCAN_IF3OBS_MASK_SHIFT (0x00000000u) +#define DCAN_IF3OBS_MASK_DATATOBEREAD (0x1u) +#define DCAN_IF3OBS_MASK_NOTTOBEREAD (0x0u) + + +/* IF3MSK */ +#define DCAN_IF3MSK_MDIR (0x40000000u) +#define DCAN_IF3MSK_MDIR_SHIFT (0x00000001Eu) +#define DCAN_IF3MSK_MDIR_NOTUSED (0x0u) +#define DCAN_IF3MSK_MDIR_USED (0x1u) + +#define DCAN_IF3MSK_MSK (0x1FFFFFFFu) +#define DCAN_IF3MSK_MSK_SHIFT (0x00000000u) +#define DCAN_IF3MSK_MSK_NOTUSED (0x0u) +#define DCAN_IF3MSK_MSK_USED (0x1u) + +#define DCAN_IF3MSK_MXTD (0x80000000u) +#define DCAN_IF3MSK_MXTD_SHIFT (0x00000001Fu) +#define DCAN_IF3MSK_MXTD_NOTUSED (0x0u) +#define DCAN_IF3MSK_MXTD_USED (0x1u) + + +/* IF3ARB */ +#define DCAN_IF3ARB_DIR (0x20000000u) +#define DCAN_IF3ARB_DIR_SHIFT (0x0000001Du) +#define DCAN_IF3ARB_DIR_RECEIVE (0x0u) +#define DCAN_IF3ARB_DIR_TRANSMIT (0x1u) + +#define DCAN_IF3ARB_MSGVAL (0x80000000u) +#define DCAN_IF3ARB_MSGVAL_SHIFT (0x0000001Fu) +#define DCAN_IF3ARB_MSGVAL_IGNORED (0x0u) +#define DCAN_IF3ARB_MSGVAL_USED (0x1u) + +#define DCAN_IF3ARB_MSK (0x1FFFFFFFu) +#define DCAN_IF3ARB_MSK_SHIFT (0x000000000u) +#define DCAN_IF3ARB_MSK_RECEIVE (0x0u) +#define DCAN_IF3ARB_MSK_TRANSMIT (0x1u) + +#define DCAN_IF3ARB_XTD (0x40000000u) +#define DCAN_IF3ARB_XTD_SHIFT (0x0000001Eu) +#define DCAN_IF3ARB_XTD_11_BIT (0x0u) +#define DCAN_IF3ARB_XTD_29_BIT (0x1u) + + +/* IF3MCTL */ +#define DCAN_IF3MCTL_DATALENGTHCODE (0x0000000Fu) +#define DCAN_IF3MCTL_DATALENGTHCODE_SHIFT (0x00000000u) + +#define DCAN_IF3MCTL_EOB (0x00000080u) +#define DCAN_IF3MCTL_EOB_SHIFT (0x00000007u) + +#define DCAN_IF3MCTL_INTPND (0x00002000u) +#define DCAN_IF3MCTL_INTPND_SHIFT (0x0000000Du) +#define DCAN_IF3MCTL_INTPND_INTERRUPT (0x1u) +#define DCAN_IF3MCTL_INTPND_NOINTERRUPT (0x0u) + +#define DCAN_IF3MCTL_MSGLST (0x00004000u) +#define DCAN_IF3MCTL_MSGLST_SHIFT (0x0000000Eu) +#define DCAN_IF3MCTL_MSGLST_MSGLOST (0x1u) +#define DCAN_IF3MCTL_MSGLST_NOMSGLOST (0x0u) + +#define DCAN_IF3MCTL_NEWDAT (0x00008000u) +#define DCAN_IF3MCTL_NEWDAT_SHIFT (0x0000000Fu) +#define DCAN_IF3MCTL_NEWDAT_NEWDATA (0x1u) +#define DCAN_IF3MCTL_NEWDAT_NONEWDATA (0x0u) + +#define DCAN_IF3MCTL_RMTEN (0x00000200u) +#define DCAN_IF3MCTL_RMTEN_SHIFT (0x00000009u) +#define DCAN_IF3MCTL_RMTEN_DISABLE (0x0u) +#define DCAN_IF3MCTL_RMTEN_ENABLE (0x1u) + +#define DCAN_IF3MCTL_RXIE (0x00000400u) +#define DCAN_IF3MCTL_RXIE_SHIFT (0x0000000Au) +#define DCAN_IF3MCTL_RXIE_NOTRIGGER (0x0u) +#define DCAN_IF3MCTL_RXIE_TRIGGER (0x1u) + +#define DCAN_IF3MCTL_TXIE (0x00000800u) +#define DCAN_IF3MCTL_TXIE_SHIFT (0x0000000Bu) +#define DCAN_IF3MCTL_TXIE_NOTRIGGER (0x0u) +#define DCAN_IF3MCTL_TXIE_TRIGGER (0x1u) + +#define DCAN_IF3MCTL_TXRQST (0x00000100u) +#define DCAN_IF3MCTL_TXRQST_SHIFT (0x00000008u) +#define DCAN_IF3MCTL_TXRQST_NOREQUESTED (0x0u) +#define DCAN_IF3MCTL_TXRQST_REQUESTED (0x1u) + +#define DCAN_IF3MCTL_UMASK (0x00001000u) +#define DCAN_IF3MCTL_UMASK_SHIFT (0x0000000Cu) +#define DCAN_IF3MCTL_UMASK_IGNORED (0x0u) +#define DCAN_IF3MCTL_UMASK_MASKED (0x1u) + + +/* IF3DATA */ +#define DCAN_IF3DATA_DCAN_IF3DATA (0xFFFFFFFFu) +#define DCAN_IF3DATA_DCAN_IF3DATA_SHIFT (0x00000000u) + + +/* IF3DATB */ +#define DCAN_IF3DATB_DCAN_IF3DATB (0xFFFFFFFFu) +#define DCAN_IF3DATB_DCAN_IF3DATB_SHIFT (0x00000000u) + + +/* IF3UPD12 */ +#define DCAN_IF3UPD12_IF3UPDEN_16_1 (0x0000FFFFu) +#define DCAN_IF3UPD12_IF3UPDEN_16_1_SHIFT (0x00000001u) + +#define DCAN_IF3UPD12_IF3UPDEN_32_17 (0xFFFF0000u) +#define DCAN_IF3UPD12_IF3UPDEN_32_17_SHIFT (0x00000010u) + + +/* IF3UPD34 */ +#define DCAN_IF3UPD34_IF3UPDEN_48_33 (0x0000FFFFu) +#define DCAN_IF3UPD34_IF3UPDEN_48_33_SHIFT (0x00000001u) + +#define DCAN_IF3UPD34_IF3UPDEN_64_49 (0xFFFF0000u) +#define DCAN_IF3UPD34_IF3UPDEN_64_49_SHIFT (0x00000010u) + + +/* IF3UPD56 */ +#define DCAN_IF3UPD56_IF3UPDEN_80_65 (0x0000FFFFu) +#define DCAN_IF3UPD56_IF3UPDEN_80_65_SHIFT (0x00000001u) + +#define DCAN_IF3UPD56_IF3UPDEN_96_81 (0xFFFF0000u) +#define DCAN_IF3UPD56_IF3UPDEN_96_81_SHIFT (0x00000010u) + + +/* IF3UPD78 */ +#define DCAN_IF3UPD78_IF3UPDEN_112_97 (0x0000FFFFu) +#define DCAN_IF3UPD78_IF3UPDEN_112_97_SHIFT (0x00000001u) + +#define DCAN_IF3UPD78_IF3UPDEN_128_113 (0xFFFF0000u) +#define DCAN_IF3UPD78_IF3UPDEN_128_113_SHIFT (0x00000010u) + + +/* TIOC */ +#define DCAN_TIOC_DIR (0x00000004u) +#define DCAN_TIOC_DIR_SHIFT (0x00000002u) +#define DCAN_TIOC_DIR_INPUT (0x0u) +#define DCAN_TIOC_DIR_OUTPUT (0x1u) + +#define DCAN_TIOC_FUNC (0x00000008u) +#define DCAN_TIOC_FUNC_SHIFT (0x00000003u) +#define DCAN_TIOC_FUNC_FUNCTIONAL (0x1u) +#define DCAN_TIOC_FUNC_GIO (0x0u) + +#define DCAN_TIOC_IN (0x00000001u) +#define DCAN_TIOC_IN_SHIFT (0x00000000u) +#define DCAN_TIOC_IN_HIGH (0x1u) +#define DCAN_TIOC_IN_LOW (0x0u) + +#define DCAN_TIOC_OD (0x00010000u) +#define DCAN_TIOC_OD_SHIFT (0x00000010u) +#define DCAN_TIOC_OD_OPEN_DRAIN (0x1u) +#define DCAN_TIOC_OD_PUSH_PULL (0x0u) + +#define DCAN_TIOC_OUT (0x00000002u) +#define DCAN_TIOC_OUT_SHIFT (0x00000001u) +#define DCAN_TIOC_OUT_HIGH (0x1u) +#define DCAN_TIOC_OUT_LOW (0x0u) + +#define DCAN_TIOC_PD (0x00020000u) +#define DCAN_TIOC_PD_SHIFT (0x00000011u) +#define DCAN_TIOC_PD_ACTIVE (0x0u) +#define DCAN_TIOC_PD_DISABLED (0x1u) + +#define DCAN_TIOC_PU (0x00040000u) +#define DCAN_TIOC_PU_SHIFT (0x00000011u) +#define DCAN_TIOC_PU_PULL_DOWN (0x0u) +#define DCAN_TIOC_PU_PULL_UP (0x1u) + + +/* RIOC */ +#define DCAN_RIOC_DIR (0x00000004u) +#define DCAN_RIOC_DIR_SHIFT (0x00000002u) +#define DCAN_RIOC_DIR_INPUT (0x0u) +#define DCAN_RIOC_DIR_OUTPUT (0x1u) + +#define DCAN_RIOC_FUNC (0x00000008u) +#define DCAN_RIOC_FUNC_SHIFT (0x00000003u) +#define DCAN_RIOC_FUNC_FUNCTIONAL (0x1u) +#define DCAN_RIOC_FUNC_GIO (0x0u) + +#define DCAN_RIOC_IN (0x00000001u) +#define DCAN_RIOC_IN_SHIFT (0x00000000u) +#define DCAN_RIOC_IN_HIGH (0x1u) +#define DCAN_RIOC_IN_LOW (0x0u) + +#define DCAN_RIOC_OD (0x00010000u) +#define DCAN_RIOC_OD_SHIFT (0x00000010u) +#define DCAN_RIOC_OD_OPEN_DRAIN (0x1u) +#define DCAN_RIOC_OD_PUSH_PULL (0x0u) + +#define DCAN_RIOC_OUT (0x00000002u) +#define DCAN_RIOC_OUT_SHIFT (0x00000001u) +#define DCAN_RIOC_OUT_HIGH (0x1u) +#define DCAN_RIOC_OUT_LOW (0x0u) + +#define DCAN_RIOC_PD (0x00020000u) +#define DCAN_RIOC_PD_SHIFT (0x00000011u) +#define DCAN_RIOC_PD_ACTIVE (0x0u) +#define DCAN_RIOC_PD_DISABLED (0x1u) + +#define DCAN_RIOC_PU (0x00020000u) +#define DCAN_RIOC_PU_SHIFT (0x00000011u) +#define DCAN_RIOC_PU_PULL_DOWN (0x0u) +#define DCAN_RIOC_PU_PULL_UP (0x1u) + + + +#ifdef __cplusplus +} +#endif + +#endif + |